WO2021083155A1 - 像素驱动电路及其驱动方法、显示面板、显示装置 - Google Patents

像素驱动电路及其驱动方法、显示面板、显示装置 Download PDF

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Publication number
WO2021083155A1
WO2021083155A1 PCT/CN2020/124069 CN2020124069W WO2021083155A1 WO 2021083155 A1 WO2021083155 A1 WO 2021083155A1 CN 2020124069 W CN2020124069 W CN 2020124069W WO 2021083155 A1 WO2021083155 A1 WO 2021083155A1
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Prior art keywords
transistor
circuit
driving
sub
signal terminal
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PCT/CN2020/124069
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English (en)
French (fr)
Inventor
岳晗
张粲
玄明花
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京东方科技集团股份有限公司
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Priority to US17/609,238 priority Critical patent/US11620939B2/en
Publication of WO2021083155A1 publication Critical patent/WO2021083155A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0204—Compensation of DC component across the pixels in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, a display panel, and a display device.
  • Self-luminous devices have received widespread attention due to their high brightness and wide color gamut.
  • the turn-on voltage of the self-luminous device will be inconsistent, and the photoelectric conversion characteristics of the self-luminous device (including photoelectric conversion efficiency, uniformity and color coordinates, etc.) will flow through the self-luminous device. Therefore, when the self-luminous device is applied to the display panel, the display effect of the display panel will be affected to a certain extent.
  • a pixel driving circuit including: a driving control sub-circuit and a time control sub-circuit.
  • the driving control sub-circuit is connected to at least a first scan signal terminal, a first data signal terminal, a first power supply voltage signal terminal, an enable signal terminal, and a first pole of the element to be driven;
  • the driving control sub-circuit includes a first A driving sub-circuit, the first driving sub-circuit includes a driving transistor;
  • the driving control sub-circuit is configured to respond to the received first scan signal from the first scan signal terminal, at least from the first data
  • the first data signal at the signal terminal is written into the first driving sub-circuit; and in response to the received enable signal from the enable signal terminal, the driving transistor is made to respond to the first data signal and from the first driving sub-circuit.
  • a first power supply voltage signal at a power supply voltage signal terminal outputs a driving signal to the first pole of the component to be driven.
  • the time control sub-circuit is connected to at least a second scan signal terminal, a second data signal terminal, a second power supply voltage signal terminal, an enable signal terminal, a common voltage signal terminal, and the second pole of the component to be driven;
  • the time control sub-circuit includes a second driving sub-circuit; the time control sub-circuit is configured to respond to the received second scan signal from the second scan signal terminal, at least the second data signal terminal from the second Data signals are written into the second driving sub-circuit; and in response to the received enable signal from the enable signal terminal, the second driving sub-circuit is connected to the second power supply voltage signal terminal and the standby signal
  • the second pole of the driving element is connected; the second driving sub-circuit responds to the second data signal and the common voltage signal in which the voltage from the common voltage signal terminal changes within a set voltage range, to the element to be driven The second pole of which outputs a second power supply voltage signal from the second power supply voltage signal terminal, so that the component to be driven starts to work in response to the received driving
  • the first driving sub-circuit further includes a first capacitor; a first pole of the first capacitor is connected to the first power supply voltage signal terminal, and a second pole of the first capacitor is connected to The first node; the gate of the driving transistor is connected to the first node.
  • the drive control sub-circuit further includes a first data writing sub-circuit and a first control sub-circuit; the first data writing sub-circuit is connected to the first scan signal terminal and the first A data signal terminal, the first node, and the driving transistor; the first data writing sub-circuit is configured to combine the first data signal with the first scan signal in response to the received first scan signal
  • the threshold voltage of the driving transistor is written into the first node; the first control sub-circuit is connected to the enable signal terminal, the first power supply voltage signal terminal, the driving transistor, and the first node of the element to be driven.
  • One pole the first control sub-circuit is configured to connect the driving transistor to the first power supply voltage signal terminal and the first pole of the element to be driven in response to the received enable signal.
  • the first data writing sub-circuit includes a second transistor and a third transistor; the gate of the second transistor is connected to the first scan signal terminal, and the first transistor of the second transistor The second electrode of the second transistor is connected to the first node; the gate of the third transistor is connected to the first scan signal terminal, and the second electrode of the second transistor is connected to the first scan signal terminal.
  • the first electrode of the three transistor is connected to the first data signal terminal, and the second electrode of the third transistor is connected to the first electrode of the driving transistor.
  • the first control sub-circuit includes a fourth transistor and a fifth transistor; the gate of the fourth transistor is connected to the enable signal terminal, and the first electrode of the fourth transistor is connected to The first power supply voltage signal terminal, the second pole of the fourth transistor is connected to the first pole of the driving transistor; the gate of the fifth transistor is connected to the enable signal terminal, the fifth The first electrode of the transistor is connected to the second electrode of the driving transistor, and the second electrode of the fifth transistor is connected to the first electrode of the element to be driven.
  • the driving control sub-circuit further includes a first reset sub-circuit; the first reset sub-circuit is connected to the first initial signal terminal, the first reset signal terminal and the gate of the driving transistor; The first reset sub-circuit is configured to transmit the first initial signal from the first initial signal terminal to the gate of the driving transistor in response to the received first reset signal from the first reset signal terminal, The gate of the driving transistor is reset.
  • the first reset sub-circuit includes a sixth transistor; the gate of the sixth transistor is connected to the first reset signal terminal, and the first electrode of the sixth transistor is connected to the first reset signal terminal. An initial signal terminal, the second electrode of the sixth transistor is connected to the gate of the driving transistor.
  • the second driving sub-circuit includes a first transistor and a second capacitor; the first pole of the second capacitor is connected to the second node, and the second pole of the second capacitor is connected to the Common voltage signal terminal; the gate of the first transistor is connected to the second node.
  • the time control sub-circuit further includes a second data writing sub-circuit and a second control sub-circuit; the second data writing sub-circuit is connected to the second scan signal terminal, the first Two data signal terminals, the second node, and the first pole and the second pole of the first transistor; the second data writing sub-circuit is configured to respond to the received second scan signal, The second data signal and the threshold voltage of the first transistor are written into the second node; the second control sub-circuit is connected to the enable signal terminal, the second power supply voltage signal terminal, and the The first pole and the second pole of the first transistor, and the second pole of the element to be driven; the second control sub-circuit is configured to enable the first transistor in response to the received enable signal It is connected to the second power supply voltage signal terminal and the second pole of the component to be driven.
  • the second data writing sub-circuit includes a seventh transistor and an eighth transistor; the gate of the seventh transistor is connected to the second scan signal terminal, and the first transistor of the seventh transistor The electrode is connected to the first electrode of the first transistor, the second electrode of the seventh transistor is electrically connected to the second data signal terminal; the gate of the eighth transistor is connected to the second scan signal The first electrode of the eighth transistor is connected to the second electrode of the first transistor, and the second electrode of the eighth transistor is connected to the second node.
  • the second control sub-circuit includes a ninth transistor and a tenth transistor; the gate of the ninth transistor is connected to the enable signal terminal, and the first electrode of the ninth transistor is connected to For the second power supply voltage signal terminal, the second electrode of the ninth transistor is connected to the first electrode of the first transistor; the gate of the tenth transistor is connected to the enable signal terminal, and the first electrode of the tenth transistor is connected to the enable signal terminal.
  • the first electrode of the tenth transistor is connected to the second electrode of the element to be driven, and the second electrode of the tenth transistor is connected to the second electrode of the first transistor.
  • the first transistor is an N-type transistor, and the driving transistor is a P-type transistor; or, the first transistor is a P-type transistor, and the driving transistor is an N-type transistor.
  • the time control sub-circuit further includes a second reset sub-circuit; the second reset sub-circuit is connected to the second initial signal terminal, the second reset signal terminal and the second node; the first The second reset sub-circuit is configured to transmit a second initial signal from the second initial signal terminal to the second node in response to the received second reset signal from the second reset signal terminal, and to the second node. The second node is reset.
  • the second reset sub-circuit includes an eleventh transistor; the gate of the eleventh transistor is connected to the second reset signal terminal, and the first electrode of the eleventh transistor is connected to For the second initial signal terminal, the second electrode of the eleventh transistor is connected to the second node.
  • a display panel including a plurality of the aforementioned pixel driving circuits and a plurality of elements to be driven, one of the plurality of elements to be driven is connected to a corresponding pixel driving circuit.
  • the display panel has a plurality of sub-pixel regions, and each pixel driving circuit is disposed in one sub-pixel region; the display panel further includes: a plurality of first scan signal lines, a plurality of first data A signal line, a plurality of second scan signal lines, and a plurality of second data signal lines; the first scan signal terminal connected to each pixel driving circuit in the sub-pixel area of the same row is connected to a corresponding first scan signal line; The first data signal terminal connected to each pixel driving circuit in the sub-pixel area of the same column is connected to a corresponding first data signal line; the second scanning signal terminal connected to each pixel driving circuit in the sub-pixel area of the same row is connected to the corresponding one A second scan signal line connected to a second scan signal line; a second data signal terminal connected to each pixel drive circuit located in the sub-pixel area of the same column is connected to a corresponding second data signal line.
  • the component to be driven is a current-type light emitting diode.
  • a display device including the above-mentioned display panel.
  • One frame period includes a scanning phase and a working phase, and the scanning phase includes a plurality of row scanning phases.
  • the driving method includes:
  • the drive control sub-circuit responds to the received first scan signal from the first scan signal terminal, and at least transfers data from the first data signal terminal The first data signal is written into the first driving sub-circuit; the time control sub-circuit responds to the received second scan signal from the second scan signal terminal, at least the second data signal from the second data signal terminal The data signal is written into the second driving sub-circuit.
  • the driving control sub-circuit in response to the received enable signal from the enable signal terminal, causes the driving transistor in the first driving sub-circuit to respond according to the first data signal from the first data signal terminal.
  • a data signal and a first power supply voltage signal from the first power supply voltage signal terminal output a driving signal to the first pole of the component to be driven.
  • the time control sub-circuit connects the second driving sub-circuit with the second power supply voltage signal terminal and the second pole of the component to be driven in response to the received enable signal from the enable signal terminal
  • the second driving sub-circuit responds to the second data signal from the second data signal terminal and the common voltage signal in which the voltage from the common voltage signal terminal changes within a set voltage range, to the component to be driven
  • the second pole outputs a second power supply voltage signal from the second power supply voltage signal terminal, so that the component to be driven starts to work in response to the received driving signal and the second power supply voltage signal.
  • the driving control sub-circuit further includes a first data writing sub-circuit and a first control sub-circuit; in each of the plurality of row scanning stages, the driving control sub-circuit In response to the received first scan signal from the first scan signal terminal, at least the first data signal from the first data signal terminal is written into the first driving sub-circuit; in the working phase, the In response to the enable signal received from the enable signal terminal, the driving control sub-circuit causes the driving transistor in the first driving sub-circuit to transmit the signal to the power source according to the first data signal and the first power supply voltage signal.
  • the output driving signal of the first pole of the component to be driven includes:
  • the first data writing sub-circuit responds to the received first scan signal from the first scan signal terminal, and transfers the data from the first data signal The first data signal at the terminal and the threshold voltage of the driving transistor are written into the first node.
  • the first control sub-circuit responds to the received enable signal from the enable signal terminal, causing the driving transistor to interact with the first power supply voltage signal terminal and the component to be driven.
  • the first electrode is connected so that the driving transistor outputs a driving signal to the first electrode of the element to be driven according to the first data signal and the first power supply voltage signal.
  • the time control sub-circuit further includes a second data writing sub-circuit and a second control sub-circuit; in each of the plurality of row scanning stages, the time control sub-circuit In response to the second scan signal received from the second scan signal terminal, at least the second data signal from the second data signal terminal is written into the second driving sub-circuit; in the working phase, the The time control sub-circuit connects the second driving sub-circuit with the second power supply voltage signal terminal and the second pole of the component to be driven in response to the received enable signal from the enable signal terminal, including :
  • the second data writing sub-circuit responds to the received second scan signal from the second scan signal terminal, and transfers the second data from the second scan signal.
  • the second data signal at the signal terminal and the threshold voltage of the first transistor in the second driving sub-circuit are written into the second node to perform threshold compensation on the first transistor.
  • the second control sub-circuit responds to the enable signal received from the enable signal terminal to make the first transistor and the second power supply voltage signal terminal and the component to be driven The second pole is connected.
  • FIG. 1 is a structural diagram of a display panel according to some embodiments
  • FIG. 2 is a structural block diagram of a pixel driving circuit according to some embodiments.
  • FIG. 3 is a structural block diagram of another pixel driving circuit according to some embodiments.
  • FIG. 4 is a structural block diagram of still another pixel driving circuit according to some embodiments.
  • FIG. 5 is a circuit diagram of a pixel driving circuit according to some embodiments.
  • FIG. 6 is a structural block diagram of still another pixel driving circuit according to some embodiments.
  • FIG. 7 is a circuit diagram of another pixel driving circuit according to some embodiments.
  • FIG. 8 is a signal timing diagram of a pixel driving circuit according to some embodiments.
  • FIG. 9 is another signal timing diagram of the pixel driving circuit according to some embodiments.
  • FIG. 10 is a circuit diagram of still another pixel driving circuit according to some embodiments.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • connection may be used to indicate that two or more components are in direct physical or electrical contact with each other.
  • terms such as “connected” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • the first node and the second node do not represent actual components, but represent the junction of related electrical connections in the circuit diagram, that is, these nodes are related electrical connections in the circuit diagram.
  • the junction point is equivalent to a node.
  • Some embodiments of the present disclosure provide a display device including a display panel. As shown in FIG. 1, the display panel has a plurality of sub-pixel regions P.
  • FIG. 1 takes the above-mentioned multiple sub-pixel regions P arranged in an array of N rows and M columns as an example for illustration, but the embodiment of the present disclosure is not limited to this, and the above-mentioned multiple sub-pixel regions P may also be arranged in other ways. Way to arrange.
  • the above-mentioned display device is a product with a display function such as a TV, a mobile phone, a tablet computer, a notebook computer, a display, a digital photo frame, or a navigator, which is not limited in the embodiment of the present disclosure.
  • the display panel includes a plurality of pixel driving circuits and a plurality of elements to be driven, and one of the plurality of elements to be driven is connected to a corresponding pixel driving circuit.
  • a to-be-driven element and a pixel drive circuit connected to the to-be-driven element are correspondingly provided, and the pixel drive circuit is configured to drive the to-be-driven element to work.
  • the component to be driven is a current-type driving device.
  • the element to be driven is a current-type light emitting diode.
  • the current-type light emitting diode is a Micro Light Emitting Diode (Micro LED), a Mini Light Emitting Diode (Mini LED), or an Organic Light Emitting Diode (OLED).
  • Micro LED Micro Light Emitting Diode
  • Mini LED Mini Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • the above-mentioned work of the component to be driven can be understood as the current-type light-emitting diode emitting light.
  • Some embodiments of the present disclosure provide a pixel driving circuit, as shown in FIG. 2, including: a driving control sub-circuit 10 and a time control sub-circuit 20.
  • the driving control sub-circuit 10 is connected to at least the first scan signal terminal G1, the first data signal terminal D1, the first power voltage signal terminal S1, the enable signal terminal EM, and the first pole of the element L to be driven.
  • the driving control sub-circuit 10 includes a first driving sub-circuit 101, and the first driving sub-circuit 101 includes a driving transistor Td.
  • the driving control sub-circuit 10 is configured to: in response to receiving the first scan signal from the first scan signal terminal G1, at least write the first data signal from the first data signal terminal D1 into the first driving sub-circuit 101; And in response to the received enable signal from the enable signal terminal EM, the driving transistor Td is enabled according to the first data signal from the first data signal terminal D1 and the first power supply voltage signal from the first power supply voltage signal terminal S1, The drive signal is output to the first pole of the element L to be driven.
  • the time control sub-circuit 20 is connected to at least the second scan signal terminal G2, the second data signal terminal D2, the second power voltage signal terminal S2, the enable signal terminal EM, the common voltage signal terminal V1, and the second pole of the element L to be driven. ;
  • the time control sub-circuit 20 includes a second driving sub-circuit 201.
  • the time control sub-circuit 20 is configured to: in response to the received second scan signal from the second scan signal terminal G2, write the second data signal from the second data signal terminal D2 into the second driving sub-circuit 201; and In response to the received enable signal from the enable signal terminal EM, the second driving sub-circuit 201 is connected to the second power supply voltage signal terminal S2 and the second pole of the element L to be driven.
  • the second driving sub-circuit 201 responds to the received second data signal from the second data signal terminal D2 and the common voltage signal in which the voltage from the common voltage signal terminal V1 changes within the set voltage range, and sends the signal to the element L to be driven
  • the second pole outputs the second power supply voltage signal from the second power supply voltage signal terminal S2, so that the component L to be driven starts to work in response to the received driving signal and the second power supply voltage signal.
  • the driving transistor Td outputs a driving signal to the first electrode of the element L to be driven can be understood as: the driving transistor Td outputs a driving current to the first electrode of the current-type light emitting diode.
  • the second driving sub-circuit 201 outputting the second power supply voltage signal to the second pole of the element L to be driven can be understood as: the second driving sub-circuit 201 outputs the second power supply voltage signal to the second pole of the current-type light emitting diode.
  • the element to be driven L starts to work in response to the received drive signal and the second power supply voltage signal, which can be understood as: the current-type light emitting diode responds to the drive signal received by its first pole and its second pole Upon receiving the second power supply voltage signal, the current-type LED is turned on, and the driving transistor Td outputs a driving current to the first pole of the current-type LED to drive the current-type LED to start emitting light.
  • the first pole and the second pole of the element L to be driven are the anode and the cathode of the current-type light emitting diode, respectively.
  • the first power supply voltage signal from the first power supply voltage signal terminal S1 is a high-level signal
  • the second power supply voltage signal from the second power supply voltage signal terminal S2 is a low-level signal.
  • the first pole of the element L to be driven is the anode of the current-type light-emitting diode
  • the second pole of the element L to be driven is the cathode of the current-type light-emitting diode.
  • the first power supply voltage signal from the first power supply voltage signal terminal S1 is a low-level signal
  • the second power supply voltage signal from the second power supply voltage signal terminal S2 is a high-level signal.
  • the first pole of the element L to be driven is the cathode of the current-type light-emitting diode
  • the second pole of the element L to be driven is the anode of the current-type light-emitting diode.
  • the first power supply voltage signal from the first power supply voltage signal terminal S1 and the second power supply voltage signal from the second power supply voltage signal terminal S2 are both fixed voltage signals within one frame time.
  • Those skilled in the art can set the voltage levels of the first power supply voltage signal and the second power supply voltage signal under the condition that the pixel driving circuit is guaranteed to work normally.
  • the first data signal from the first data signal terminal D1 is a fixed high voltage signal, so that the element L to be driven can have a higher luminous efficiency.
  • the pixel driving circuit controls the gray scale through the time control sub-circuit 20.
  • the voltage of the first data signal from the first data signal terminal D1 changes within a certain voltage interval, and the first data signal within the voltage interval can ensure that the element L to be driven has a higher value. Luminous efficiency.
  • the pixel driving circuit controls the gray scale through the driving control sub-circuit 10 and the time control sub-circuit 20 together.
  • the drive control sub-circuit 10 controls the voltage levels of the first data signal from the first data signal terminal D1 and the first power supply voltage signal from the first power supply voltage signal terminal S1.
  • the magnitude of the driving signal (for example, the amplitude of the driving current) transmitted from the driving transistor Td to the element L to be driven.
  • the second power voltage signal is controlled to be transmitted to the element L to be driven by controlling the voltage levels of the second data signal from the second data signal terminal D2 and the common voltage signal from the common voltage signal terminal V1.
  • the duration of the second pole is used to control the working duration of the element L to be driven.
  • the element L to be driven is turned on and starts to work.
  • the above-mentioned working time length of the to-be-driven element L can be understood as: the light-emitting time length of the current-type light-emitting diode.
  • the driving control sub-circuit 10 writes at least the first data signal from the first data signal terminal D1 in response to the received first scan signal from the first scan signal terminal G1 Into the first driving sub-circuit 101; and in response to the received enable signal from the enable signal terminal EM, the driving transistor Td according to the first data signal from the first data signal terminal D1 and from the first power voltage signal terminal
  • the first power supply voltage signal of S1 outputs a driving signal to the first pole of the element L to be driven.
  • the time control sub-circuit 20 writes the second data signal from the second data signal terminal D2 into the second driving sub-circuit 201 in response to the received second scan signal from the second scan signal terminal G2; and in response to receiving the second scan signal
  • the enable signal from the enable signal terminal EM makes the second driving sub-circuit 201 respond to the received second data signal from the second data signal terminal D2 and the voltage from the common voltage signal terminal V1 within the set voltage range
  • the internally changed common voltage signal outputs the second power supply voltage signal from the second power supply voltage signal terminal S2 to the second pole of the component L to be driven, so that the component L to be driven responds to the received driving signal and the second power supply voltage. Signal to start working.
  • the drive control sub-circuit 10 controls the magnitude of the drive signal transmitted to the first pole of the component to be driven
  • the time control sub-circuit 20 controls the transmission of the second power voltage signal from the second power voltage signal terminal S2 to the component to be driven.
  • the time of the second pole of L In this way, when the element L to be driven displays different gray scales, by controlling the size of the driving signal input to the element L to be driven and the working time of the element to be driven, the brightness of the element to be driven L can be changed, and the corresponding gray scale can be realized. Order display.
  • the pixel driving circuit When the element L to be driven is a current-driven light-emitting device, when the element L to be driven performs higher grayscale display, the pixel driving circuit outputs a larger driving current to the element L to be driven, and can control the element L to be driven
  • the light-emitting duration of is the longer light-emitting duration.
  • the driving current output by the pixel driving circuit to the element to be driven can be a larger value (for example, the driving current corresponding to a certain high gray scale). The light-emitting time of, the brightness of the element L to be driven is reduced.
  • the driving current output by the pixel driving circuit to the element to be driven L is maintained in a higher value range (for example, the driving current in the higher value range is close to the higher gray scale.
  • the driving current in the step display by shortening the light-emitting time of the element L to be driven, the brightness of the element L to be driven is reduced. Therefore, regardless of whether the element L to be driven performs high-gray-scale display or low-gray-scale display, the driving current is always large, so that the element L to be driven is always at a higher current density, and the luminous efficiency and brightness of the element L to be driven are higher. Stable, low power consumption, and better display effect.
  • the first driving sub-circuit 101 includes a driving transistor Td and a first capacitor C1.
  • the first pole of the first capacitor C1 is connected to the first power supply voltage signal terminal S1, and the second pole of the first capacitor C1 is connected to the first node A.
  • the gate of the driving transistor Td is connected to the first node A.
  • the driving transistor Td is configured to be turned on in response to the first data signal from the first data signal terminal D1 and the first power supply voltage signal from the first power supply voltage signal terminal S1, and to output a driving signal to the first electrode of the element L to be driven .
  • the driving control sub-circuit further includes a first data writing sub-circuit and a first control sub-circuit 103.
  • the first data writing sub-circuit 102 is connected to the first scan signal terminal G1, the first data signal terminal D1, the first node A, and the first pole and the second pole of the driving transistor Td.
  • the first data writing sub-circuit 102 is configured to: in response to receiving the first scan signal from the first scan signal terminal G1, combine the first data signal from the first data signal terminal D1 and the threshold voltage of the driving transistor Td
  • the first node A is written to perform threshold voltage compensation for the driving transistor Td.
  • the first control sub-circuit 103 is connected to the enable signal terminal EM, the first power supply voltage signal terminal S1, the first pole and the second pole of the driving transistor Td, and the first pole of the element L to be driven.
  • the first control sub-circuit 103 is configured to connect the driving transistor Td with the first power supply voltage signal terminal S1 and the first pole of the element L to be driven in response to a received enable signal from the enable signal terminal EM.
  • the first data writing sub-circuit 102 includes a second transistor T2 and a third transistor T3.
  • the gate of the second transistor T2 is connected to the first scan signal terminal G1, the first electrode of the second transistor T2 is connected to the second electrode of the driving transistor Td, and the second electrode of the second transistor T2 is connected to the first node A.
  • the gate of the third transistor T3 is connected to the first scan signal terminal G1, the first electrode of the third transistor T3 is connected to the first data signal terminal D1, and the second electrode of the third transistor T3 is connected to the first electrode of the driving transistor Td.
  • the first control sub-circuit 103 includes a fourth transistor T4 and a fifth transistor T5.
  • the gate of the fourth transistor T4 is connected to the enable signal terminal EM
  • the first electrode of the fourth transistor T4 is connected to the first power supply voltage signal terminal S1
  • the second electrode of the fourth transistor T4 is connected to the first electrode of the driving transistor Td .
  • the gate of the fifth transistor T5 is connected to the enable signal terminal EM
  • the first electrode of the fifth transistor T5 is connected to the second electrode of the driving transistor Td
  • the second electrode of the fifth transistor Td is connected to the first electrode of the element L to be driven. pole.
  • the driving control sub-circuit 10 further includes a first reset sub-circuit 104.
  • the first reset sub-circuit 104 is connected to the first initial signal terminal INI1, the first reset signal terminal RST1, and the gate of the driving transistor Td.
  • the first reset sub-circuit 104 is configured to transmit the first initial signal from the first initial signal terminal INI1 to the gate of the driving transistor Td in response to the received first reset signal from the first reset signal terminal RST1, The gate of the driving transistor Td is reset.
  • the first reset sub-circuit 104 includes a sixth transistor T6.
  • the gate of the sixth transistor T6 is connected to the first reset signal terminal RST1, the second electrode of the sixth transistor T6 is connected to the first initial signal terminal INI1, and the first electrode of the sixth transistor T6 is connected to the gate of the driving transistor Td.
  • the second driving sub-circuit 201 includes a first transistor T1 and a second capacitor C2.
  • the first pole of the second capacitor C2 is connected to the second node B, the second pole of the second capacitor C2 is connected to the common voltage signal terminal V1, and the gate of the first transistor T1 is connected to the second node B; the first transistor T1 is connected to the second node B.
  • the configuration is: in response to the common voltage signal whose voltage from the common voltage signal terminal V1 changes within a set voltage range and the second data signal from the second data signal terminal D2, output the second pole to the second pole of the element L to be driven. Power supply voltage signal.
  • the time control sub-circuit 20 further includes a second driving sub-circuit 201, a second data writing sub-circuit 202, and a second control sub-circuit 203.
  • the second data writing sub-circuit 202 is connected to the second scan signal terminal G2, the second data signal terminal D2, the second node B, and the first pole and the second pole of the first transistor T1.
  • the second data writing sub-circuit 202 is configured to: in response to the received second scan signal from the second scan signal terminal G2, combine the second data signal from the second data signal terminal D2 and the threshold value of the first transistor T1 The voltage is written into the second node B to perform threshold voltage compensation for the first transistor T1.
  • the second control sub-circuit 203 is connected to the enable signal terminal EM, the second power supply voltage signal terminal S2, the first pole and the second pole of the first transistor T1, and the second pole of the element L to be driven.
  • the second control sub-circuit 203 is configured to connect the first transistor T1 with the second power supply voltage signal terminal S2 and the second pole of the element L to be driven in response to the received enable signal from the enable signal terminal EM, So that the first transistor T1 is turned on in response to the common voltage signal whose voltage from the common voltage signal terminal V1 changes within the set voltage range and the second data signal from the second data signal terminal D2, and turns on the second power voltage signal from the second power supply voltage signal.
  • the second power supply voltage signal at the terminal S2 is transmitted to the second pole of the element L to be driven, so as to control the working time of the element L to be driven.
  • the voltage of the common voltage signal changes with time within the set voltage range, and the set voltage range is determined according to the light-emitting duration of the element L to be driven. Therefore, by changing the voltage of the common voltage signal that changes within the set voltage range, it is possible to realize the control of the light-emitting duration of the element L to be driven, thereby realizing the control of the gray scale.
  • the second data writing sub-circuit 202 writes the second data signal from the second data signal terminal D2 and the threshold voltage of the first transistor T1 into the second node B
  • the voltage of the second node B is the sum of the voltage of the second data signal (denoted as V data2 ) and the threshold voltage of the first transistor T1 (denoted as V th1 ). Since the first pole of the second capacitor C2 is connected to the second node B, the voltage of the first pole of the second capacitor C2 is the voltage of the second node B, that is, V data2 +V th1 .
  • the voltage of the second pole of the second capacitor C2 is the voltage of the common voltage signal from the common voltage signal terminal V1. According to the capacitor charge retention law, the voltage difference between the two ends of the second capacitor C2 remains unchanged.
  • the voltage of the common voltage signal changes within the set voltage range, the voltage of the first pole of the second capacitor C2 will follow the common voltage.
  • the voltage of the signal changes, that is, the voltage of the second node B changes with the voltage of the common voltage signal.
  • the first transistor T1 Turn on. At this time, the first transistor T1 is connected to the second power supply voltage signal terminal S2 and the second pole of the element to be driven L, and the second power supply voltage signal from the second power supply voltage signal terminal S2 is transmitted to the element to be driven through the first transistor T1
  • the second pole of L enables the element L to be driven to start working in response to the received driving signal from the driving transistor Td and the second power supply voltage signal.
  • the variable common voltage signal can be used to control whether the first transistor T1 is turned on or not to realize the element to be driven. Control of L's working hours.
  • the second data writing sub-circuit 202 includes a seventh transistor T7 and an eighth transistor T8.
  • the gate of the seventh transistor T7 is connected to the second scan signal terminal G2, the first electrode of the seventh transistor T7 is connected to the first electrode of the first transistor T1, and the second electrode of the seventh transistor T7 is connected to the second data signal terminal D2.
  • the gate of the eighth transistor T8 is connected to the second scan signal terminal G2, the first electrode of the eighth transistor T8 is connected to the second electrode of the first transistor T1, and the second electrode of the eighth transistor T8 is connected to the second node B.
  • the second control sub-circuit 203 includes a ninth transistor T9 and a tenth transistor T10.
  • the gate of the ninth transistor T9 is connected to the enable signal terminal EM
  • the first electrode of the ninth transistor T9 is connected to the second power supply voltage signal terminal S2
  • the second electrode of the ninth transistor T9 is connected to the first transistor T1.
  • the gate of the tenth transistor T10 is connected to the enable signal terminal EM
  • the second electrode of the tenth transistor T10 is connected to the second electrode of the first transistor T1
  • the first electrode of the tenth transistor T10 is connected to the first electrode of the element L to be driven. Two poles.
  • the first pole is one of the source and drain of the transistor
  • the second pole is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable. That is to say, the first pole and the second pole of the transistor in the embodiment of the present disclosure may be indistinguishable in structure.
  • the second electrode is called the drain
  • the first electrode is called the source.
  • the first electrode is referred to as the drain
  • the second electrode is referred to as the source.
  • the present disclosure does not limit the types of other transistors in the pixel driving circuit. These transistors may be P-type transistors or N-type transistors.
  • the transistor can be divided into an enhancement transistor and a depletion transistor.
  • Each transistor in the embodiments of the present disclosure may be an enhancement type transistor or a depletion type transistor, which is not limited.
  • the driving transistor Td is a P-type transistor
  • the first transistor T1 is an N-type transistor.
  • the component L to be driven In the case that the first power supply voltage signal from the first power supply voltage signal terminal S1 is a high-level signal, and the second power supply voltage signal provided from the second power supply voltage signal terminal S2 is a low-level signal, the component L to be driven
  • the first pole is the anode and the second pole is the cathode. Therefore, in the working state of the element L to be driven, the driving current flows from the first pole to the second pole of the element L to be driven. That is, the driving current flowing through the driving transistor Td flows from the first electrode of the driving transistor Td to the second electrode of the driving transistor Td, and the driving current flowing through the first transistor T1 flows from the second electrode of the first transistor T1 to the second electrode.
  • the driving transistor Td is a P-type transistor
  • the first electrode of the driving transistor Td is referred to as a source. In this way, the first power supply voltage signal from the first power supply voltage signal terminal S1 is transmitted to the first pole of the driving transistor Td, that is, the source of the driving transistor Td receives the first power supply voltage signal.
  • the second electrode of the first transistor T1 is called a source.
  • the second pole of the first transistor T1 can be understood as the first pole of the first transistor T1
  • the first transistor T1 The first pole of T1 can be understood as the second pole of the first transistor T1.
  • the second power supply voltage signal from the second power supply voltage signal terminal S2 is transmitted to the first pole of the first transistor T1, that is, the second pole (ie, the source) of the first transistor T1 receives the second power supply voltage signal.
  • the first power supply voltage signal and the second power supply voltage signal are both fixed voltage signals. Therefore, by controlling the source of the driving transistor Td and the source of the first transistor T1 under a fixed voltage signal, the operation of the driving element L can be controlled more finely, and the turn-on voltage of the driving element L can be prevented from affecting the display panel.
  • the display effect has an impact.
  • the driving transistor Td is an N-type transistor
  • the first transistor T1 is a P-type transistor.
  • the component L to be driven When the first power supply voltage signal from the first power supply voltage signal terminal S1 is a low-level signal, and the second power supply voltage signal provided from the second power supply voltage signal terminal S2 is a high-level signal, the component L to be driven
  • the first pole is the cathode and the second pole is the anode. Therefore, in the working state of the element L to be driven, the driving current flows from the second pole to the first pole of the element L to be driven. That is, the driving current flowing through the driving transistor Td flows from the second electrode of the driving transistor Td to the first electrode of the driving transistor Td, and the driving current flowing through the first transistor T1 flows from the first electrode of the first transistor T1 to the first electrode.
  • the second electrode of the driving transistor Td is sourced.
  • the second electrode of the driving transistor Td can be understood as the first electrode of the driving transistor Td
  • the first electrode of the driving transistor Td It can be understood as the second pole of the driving transistor Td.
  • the first power voltage signal from the first power voltage signal terminal S1 is transmitted to the first electrode of the driving transistor Td, that is, the second electrode (ie, the source) of the driving transistor Td receives the first power voltage signal.
  • the first transistor T1 is a P-type transistor
  • the first electrode of the first transistor T1 is called a source
  • the second power voltage signal from the second power voltage signal terminal S2 is transmitted to the first electrode of the first transistor T1
  • the source of the first transistor T1 receives the second power supply voltage signal.
  • the first power supply voltage signal and the second power supply voltage signal are both fixed voltage signals. Therefore, by controlling the source of the driving transistor Td and the source of the first transistor T1 under a fixed voltage signal, the operation of the driving element L can be controlled more finely, and the turn-on voltage of the driving element L can be prevented from affecting the display panel.
  • the display effect has an impact.
  • the time control sub-circuit 20 further includes a second reset sub-circuit 204.
  • the second reset sub-circuit 204 is connected to the second initial signal terminal INI2, the second reset signal terminal RST2, and the second node B.
  • the second reset sub-circuit 204 is configured to: in response to the second reset signal from the second reset signal terminal RST2, transmit the second initial signal from the second initial signal terminal INI2 to the second node B, to the second node B Perform a reset.
  • the second reset sub-circuit 204 includes an eleventh transistor T11.
  • the gate of the eleventh transistor T11 is connected to the second reset signal terminal RST2, the first electrode of the eleventh transistor T11 is connected to the second initial signal terminal INI2, and the second electrode of the eleventh transistor T11 is connected to the second node B .
  • each transistor in the drive control sub-circuit 10 is a P-type transistor; in the time control sub-circuit 20, except for the first transistor T1, the seventh transistor T7, the eighth transistor T8, and the eleventh transistor T11, they are N-type transistors.
  • the other transistors are all P-type transistors as an example for description.
  • the first power supply voltage signal from the first power supply voltage signal terminal S1 is a high-level signal
  • the second power supply voltage signal from the second power supply voltage signal terminal S2 is a low-level signal.
  • the first pole is the anode and the second pole is the cathode.
  • a frame period includes a scanning phase (P1 to P6) and a working phase (P6 to P7).
  • the scanning stage (P1 to P6) includes multiple line scanning stages.
  • the plurality of row scanning stages are N row scanning stages, and the N row scanning stages are ts1 to tsN,
  • the first line scanning stage is ts1
  • the Nth line scanning stage is tsN
  • N is an integer not less than 2.
  • the pixel driving circuits in the sub-pixel regions P of each row are scanned row by row. That is, starting from the pixel driving circuit in the first row of sub-pixel area P, the pixel driving circuit in each row of sub-pixel area P sequentially input the first data signal and the second data signal, until the first data signal And the second data signal is input to each pixel driving circuit located in the sub-pixel area P of the Nth row.
  • the pixel driving circuits in each row of the sub-pixel regions P may enter the working phase sequentially. That is, the pixel driving circuit in the first row of sub-pixel area P first enters the working phase, and then the pixel driving circuit in the second row of sub-pixel area P enters the working phase, until the pixel driving circuit in the Nth row of sub-pixel area P enters Work Phase.
  • the effective duration of the enable signal of the pixel driving circuit in each row of the sub-pixel area P in the working phase is the same.
  • the pixel driving circuits in the sub-pixel regions P of each row enter the working phase synchronously.
  • the pixel driving circuit in each row of the sub-pixel area P enters the working phase after the corresponding row scanning phase ends.
  • the pixel driving circuits in the M sub-pixel regions P in the same row are synchronously written with different or the same first data signals.
  • the first data signal is a group of signals.
  • the pixel driving circuits located in the M sub-pixel regions P in the same row are synchronously written with different or the same second data signals.
  • the second data signal is a group of signals.
  • the pixel driving circuit located in the first sub-pixel area P of the first row and the to-be-driven element L connected to the pixel driving circuit is a current-type light emitting diode as an example for description.
  • the pixel driving circuit located in the first sub-pixel area P of the first row includes the following driving process:
  • the sixth transistor T6 In the first stage (P1 ⁇ P2), in response to the received first reset signal input from the first reset signal terminal RST1, the sixth transistor T6 is turned on to transmit the first initial signal from the first initial signal terminal INI1 to The first node A realizes the reset of the first node A. At this time, the voltage of the first node A is the voltage of the first initial signal (denoted as V init1 ). In this case, the second pole of the first capacitor C1 connected to the first node A and the gate of the driving transistor Td are also reset to V init1 .
  • the first initial signal from the first initial signal terminal INI1 can eliminate the influence of the signal of the previous frame on the first node A.
  • the first initial signal is a high-level signal.
  • the first initial signal resets the first node A and ensures that the driving transistor Td is in the off state.
  • the second reset signal from the second reset signal terminal RST2 and the second scan signal from the second scan signal terminal G2 are both low-level signals in the first stage (P1 to P2). Therefore, the seventh transistor T7, the eighth transistor T8, and the eleventh transistor T11 are all in the off state.
  • the first scan signal from the first scan signal terminal G1 and the enable signal from the enable signal terminal EM are both high-level signals in the first stage (P1 to P2). Therefore, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the tenth transistor T10 are all in the off state.
  • the element L to be driven does not work.
  • the second transistor T2 In response to the first scan signal received from the first scan signal terminal G1, the second transistor T2 is turned on to short-circuit the gate and the second pole of the driving transistor Td, so that the driving transistor Td is in a saturated state.
  • the voltage of the gate of the driving transistor Td is the sum of the voltage of the first electrode and its threshold voltage.
  • the third transistor T3 In response to receiving the first scan signal from the first scan signal terminal G1, the third transistor T3 is turned on, and the first data signal from the first data signal terminal D1 is written into the first pole of the driving transistor Td. Therefore, the voltage of the first electrode of the driving transistor Td is the voltage of the first data signal from the first data signal terminal D1 (denoted as V data1 ). In this case, the voltage of the gate of the driving transistor Td is the sum of the voltage V data1 of the first data signal and the threshold voltage (denoted as V thd ) of the driving transistor Td, that is, V data1 +V thd . At this time, the voltage of the first node A connected to the gate of the driving transistor Td is also V data1 +V thd .
  • the voltage of the second pole of the first capacitor C1 connected to the first node A is V data1 +V thd . Since the first pole of the first capacitor C1 is connected to the first power supply voltage signal terminal S1, the voltage of the first pole of the first capacitor C1 is the voltage of the first power supply voltage signal (denoted as V S1 ). The two poles of the first capacitor C1 are charged respectively, and there is a potential difference V S1 -V data1 -V thd .
  • the enable signal from the enable signal terminal EM is still a high level signal in the second stage (P2 to P3), and the fifth transistor T5 is still in the off state. Therefore, the element L to be driven is disconnected from the driving transistor Td, and the element L to be driven does not work.
  • the fourth transistor T4, the ninth transistor T9, and the tenth transistor T10 are also in the off state.
  • the first reset signal is a high-level signal in the second stage (P2 to P3), and therefore, the sixth transistor T6 is in the off state.
  • the second reset signal and the second scan signal are both low-level signals in the second stage (P2 to P3), and the seventh transistor T7, the eighth transistor T8 and the eleventh transistor T11 are all in the off state.
  • the element L to be driven does not work.
  • the eleventh transistor T11 is turned on to transmit the second initial signal from the second initial signal terminal INI2 to The second node B realizes the reset of the second node B.
  • the voltage of the second node B is the voltage of the second initial signal (denoted as V init2 ).
  • the voltages of the first pole of the second capacitor C2 connected to the second node B and the gate of the first transistor T1 are also reset to V init2 .
  • the second initial signal provided by the second initial signal terminal INI2 can eliminate the influence of the signal of the previous frame on the second node B.
  • the second initial signal is a low-level signal.
  • the second reset sub-circuit 204 works, the second node B is reset, and the first transistor T1 is ensured to be in the off state.
  • the second scan signal is a low-level signal in the third stage (P3 to P4). Therefore, the seventh transistor T7 and the eighth transistor T8 are both in the off state.
  • the first scan signal, the first reset signal, and the enable signal are all high-level signals in the third stage (P3 to P4), the second transistor T2, the third transistor T3, the fourth transistor T4, and the The fifth transistor T5 and the sixth transistor T6 are both in the off state. In this case, the element L to be driven does not work.
  • the seventh transistor T7 in response to the second scan signal received from the second scan signal terminal G2, the seventh transistor T7 is turned on to transmit the second data signal from the second data signal terminal D2 to the first The second pole of a transistor T1.
  • the voltage of the second electrode of the first transistor T1 is the voltage of the second data signal (denoted as V data2 ).
  • the eighth transistor T8 is turned on, so that the gate of the first transistor T1 and the first electrode are short-circuited, so that the first transistor T1 is in a saturated state .
  • the voltage of the gate of the first transistor T1 is the sum of the voltage of the second electrode and its threshold voltage. That is, the voltage of the gate of the first transistor T1 is the sum of the voltage V data2 of the second data signal and its threshold voltage (denoted as V th1 ), namely: V data2 +V th1 .
  • the voltage of the second node B connected to the gate of the first transistor T1 is also V data2 +V th1 .
  • the voltage of the first pole of the second capacitor C2 connected to the second node B is also V data2 +V th1 .
  • the voltage of the second pole of the second capacitor C2 is the voltage V V1 of the common voltage signal of the common voltage signal terminal V1. That is, the two poles of the second capacitor C2 are charged respectively, and there is a voltage difference V data2 +V th1 -V V1 .
  • the first scan signal, the first reset signal, and the enable signal are all high-level signals in the fourth stage (P4 to P5)
  • the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor are all high-level signals.
  • the transistor T5, the sixth transistor T6, the ninth transistor T9, and the tenth transistor T10 are all in the off state.
  • the second reset signal is a low-level signal in the fourth stage (P4 to P5), and the eleventh transistor T11 is also in the off state. In this case, the element L to be driven does not work.
  • the above-mentioned first stage (P1 ⁇ P2) and third stage (P3 ⁇ P4) can be Synchronization.
  • the second stage (P2 to P3) and the fourth stage (P4 to P5) can be performed simultaneously.
  • the fourth transistor T4 the fifth transistor Both the transistor T5 and the tenth transistor T10 are in the off state, which can avoid charging the element L to be driven during the charging of the first capacitor C1 and the second capacitor C2; thereby, it can prevent the element L to be driven from writing data to the pixel drive circuit Input and threshold compensation have an impact.
  • the pixel driving circuit in the second row sub-pixel area P is scanned until in the Nth row scanning stage tsN, the Nth row
  • the pixel driving circuit in the sub-pixel area P performs scanning. As shown in FIG. 8, starting from the end time (P5) of the first row scanning stage ts1, during the time period P5 to P6, the pixel drive circuits located in the sub-pixel area P from the second row to the Nth row are gradually Line to scan.
  • the driving process of the pixel driving circuit in the sub-pixel area P from the second row to the Nth row in the corresponding row scanning phase is the same as that of the pixel driving circuit in the sub-pixel area P of the first row in the first row scanning phase ts1
  • the driving process is the same, so I won’t repeat it here. That is to say, in the entire scanning phase (P1 to P6), the above-mentioned driving process of the first phase to the fourth phase needs to be executed N times.
  • each of the N row scanning stages includes the first to fourth stages mentioned above, so that the pixels in the N rows of sub-pixel regions P can be driven
  • the circuit writes the first data signal and the second data signal, and stores the first data signal and the second data signal to prepare for the working phase (P6 to P7).
  • the pixel driving circuits in the N rows of sub-pixel regions are scanned row by row, the pixel driving circuits in each row of the sub-pixel regions P enter the working phase (P6 to P7).
  • the working phase of the pixel driving circuit located in the first sub-pixel area P in the first row includes the following processes:
  • the fourth transistor T4 and the fifth transistor T5 are turned on.
  • the first power supply voltage signal from the first power supply voltage signal terminal S1 is transmitted to the first pole of the driving transistor Td through the fourth transistor T4.
  • the voltage of the first electrode of the driving transistor Td is the voltage of the first power supply voltage signal (denoted as V S1 ). That is, the voltage of the source of the driving transistor Td is V S1 .
  • the voltage difference between the first pole and the second pole of the first capacitor C1 remains unchanged. Therefore, when the voltage of the first pole of the first capacitor C1 is maintained at the voltage V S1 of the first power supply voltage signal, the voltage of the second pole of the first capacitor C1 is still V data1 +V thd . At this time, the voltage of the gate of the driving transistor Td still remains V data1 +V thd .
  • the gate-source voltage difference V gs of the driving transistor Td V data1 +V thd -V S1 .
  • the gate-source voltage difference V gs of the driving transistor Td is smaller than its threshold voltage, it turns on, that is: when V data1 +V thd ⁇ V S1 ⁇ V thd , the driving transistor Td turns on and outputs a driving current.
  • the second pole output of Td is transmitted to the element L to be driven via the turned-on fifth transistor T5.
  • K 1/2 ⁇ W/L ⁇ C ⁇ u
  • W/L is the width-to-length ratio of the driving transistor Td
  • C is the capacitance of the channel insulating layer
  • u is the channel carrier mobility.
  • the above parameters are only related to the structure of the driving transistor Td. Therefore, the driving current flowing through the driving transistor Td is only related to the voltage V data1 of the first data signal from the first data signal terminal D1 and the voltage V data1 from the first power supply voltage signal terminal.
  • the voltage V S1 of the first power supply voltage signal of S1 is related to the threshold voltage V thd of the driving transistor Td.
  • the amplitude of the driving current flowing through the driving transistor Td can be controlled by controlling the voltage V data1 of the first data signal. That is, the magnitude of the driving signal output by the driving transistor Td to the element L to be driven can be controlled by controlling the voltage V data1 of the first data signal.
  • the ninth transistor T9 and the tenth transistor T10 are turned on.
  • the second power supply voltage signal from the second power supply voltage signal terminal S2 is transmitted to the first pole of the first transistor T1 through the turned-on ninth transistor T9, so that the voltage of the first pole of the first transistor T1 is equal to that of the second power supply voltage signal Voltage (denoted as V S2 ).
  • the voltage of the second pole of the second capacitor C2 connected to the common voltage signal terminal V1 changes with the voltage V V1 of the common voltage signal.
  • the voltage difference between the first pole and the second pole of the second capacitor C2 remains unchanged. Therefore, the voltage of the second node B connected to the first pole of the second capacitor C2 also changes with the voltage V V1 of the common voltage signal, and the voltage of the second node B changes at the same speed as the voltage of the common voltage signal.
  • the voltage of the common voltage signal is denoted as V V1 (0), and the voltage of the second node B is denoted as V B (0).
  • V V1 (t) the voltage of the common voltage signal
  • V B (t) the voltage of the second node B
  • the voltage of the gate of the first transistor T1 connected to the second node B is V data2 +V th1 + ⁇ V V1 .
  • the changing speed of the voltage of the second node B and the gate of the first transistor T1 is determined by the common voltage signal.
  • the first electrode of the ninth transistor T9 is connected to the second power supply voltage signal terminal S2; the first electrode of the first transistor T1 is connected to the tenth transistor T9.
  • the first pole of the transistor T10 and the second pole of the tenth transistor T10 are connected to the second pole of the element L to be driven; therefore, the opening of the ninth transistor T9 makes the second pole of the first transistor T1 and the second power voltage signal terminal S2 is connected, and the tenth transistor T10 is turned on so that the first pole of the first transistor T1 is connected to the second pole of the element L to be driven.
  • the second power supply voltage signal from the second power supply voltage signal terminal S2 is transmitted to the first transistor T1 through the turned-on ninth transistor T9, and is transmitted to the second electrode of the element L to be driven through the turned-on tenth transistor T10.
  • the enable signal from the enable signal terminal EM changes from a low level signal to a high level signal
  • the ten transistor T10 changes from the on state to the off state, so that the driving transistor Td and the first transistor T1 are disconnected from the element L to be driven, and the element L to be driven stops working.
  • the driving element L Since the first power voltage signal from the first power voltage signal terminal S1 is transmitted to the first pole of the element L to be driven, and the second power voltage signal from the second power voltage signal terminal S2 is transmitted to the first pole of the element L to be driven In the case of two poles, the driving element L will not work. Therefore, by controlling the turn-on time of the first transistor T1, control of the operating time of the element L to be driven can be achieved.
  • control of the operating time of the drive element L is independent of the turn-on voltage of the drive element L itself, so that the Mura phenomenon can be avoided due to the different turn-on voltages of the drive elements L in the display panel, resulting in uneven display brightness.
  • the voltage V of the second data signal from the second data signal terminal D2 can be controlled.
  • the voltage change of the second node B makes the first transistor T1 turn on at a different time, so that the second power supply voltage signal from the second power supply voltage signal terminal S2 is transmitted to the second pole of the to-be-driven element L at a different time, so that The turn-on time of the element L to be driven is different.
  • the turn-on time of the element L to be driven can be controlled to make the element L to be driven display different gray scales, thereby improving the luminous efficiency of the element L to be driven.
  • B(1) in Fig. 8 represents the signal timing of the second node B in an image frame period.
  • B(2) in FIG. 9 represents the signal timing of the second node B in another image frame period.
  • V B2 V V1 - ⁇ V B2 .
  • the voltage V B2 of the second node B changes to the time that the first transistor T1 is turned on less than the voltage V B1 of the second node B changes to make the first transistor
  • the time T1 is turned on, so that the element to be driven L under one frame of image shown in FIG. 9 is turned on earlier than the element to be driven L in FIG. 8, so that the element to be driven L under one frame of image shown in FIG. 9
  • the light-emitting duration of is longer than that of the component L to be driven in another frame of image.
  • the signal timing and waiting time of the second node B can also refer to FIG. 8 and FIG. 9, which will not be repeated here.
  • the drive control sub-circuit 10 controls the amplitude of the drive current transmitted to the element L to be driven
  • the time control sub-circuit 20 controls The working time of the element L to be driven realizes the display of different gray scales of the element L to be driven.
  • the operating time of the element L to be driven can be shortened to enable the element L to be driven to perform low-gray display, so as to improve the luminescence of the element L to be driven. Efficiency, avoiding the problem of low luminous efficiency and high power consumption of the element L to be driven at a lower current, thereby improving the display effect of the display panel.
  • each The pixel driving circuit outputs a driving signal and controls the time during which the second power supply voltage signal is transmitted to the element L to be driven. In this way, the control of the light emission brightness of the element L to be driven is realized.
  • the amplitude of the driving current input to the element L to be driven and the light-emitting duration the light-emitting intensity of the element L to be driven is changed, and display of different gray scales is realized.
  • the element L to be driven can work in a relatively stable current density range, which avoids the problem of unstable light emission of the element L to be driven at low current densities, improves the luminous efficiency of the element L to be driven, and reduces the display panel Power consumption.
  • the driving transistor Td, the seventh transistor T7, the eighth transistor T8, and the eleventh transistor T11 are all N-type transistors, the other transistors are all P-type transistors.
  • the first power supply voltage signal from the first power supply voltage signal terminal S1 is a low-level signal
  • the second power supply voltage signal from the second power supply voltage signal terminal S2 is a high-level signal.
  • the first pole is the cathode and the second pole is the anode.
  • a frame period includes a scanning phase (P1 to P6) and a working phase (P6 to P7).
  • the scanning phases (P1 to P6) include multiple line scanning phases (ts1 to tsN).
  • Each line scan stage includes S10 to S20, and the work stage includes S30 to S40.
  • the driving method is as follows.
  • the driving control sub-circuit 10 In response to the first scan signal received from the first scan signal terminal G1, the driving control sub-circuit 10 writes at least the first data signal from the first data signal terminal D1 into the first driving sub-circuit 101.
  • the time control sub-circuit 20 receives the second scan signal from the second scan signal terminal G2, and writes at least the second data signal from the second data signal terminal D2 into the second driving sub-circuit.
  • the driving control sub-circuit 10 causes the driving transistor Td to respond to the first data signal from the first data signal terminal D1 and the signal from the first power voltage signal terminal S1.
  • the first power supply voltage signal outputs a driving signal to the first pole of the element L to be driven.
  • the time control sub-circuit 20 connects the second driving sub-circuit 201 with the second power supply voltage signal terminal S2 and the second pole of the element L to be driven in response to the received enable signal from the enable signal terminal EM.
  • the second driving sub-circuit 201 responds to the second data signal from the second data signal terminal D2 and the common voltage signal in which the voltage from the common voltage signal terminal V1 changes within a set voltage range, and sends the signal to the second electrode of the element L to be driven.
  • the second power supply voltage signal from the second power supply voltage signal terminal S2 is output, so that the component L to be driven starts to work in response to the received driving signal and the second power supply voltage signal.
  • the driving control sub-circuit 10 includes a first driving sub-circuit 101, a first data writing sub-circuit 102, and a first control sub-circuit 103.
  • the above S10 includes S101
  • the above S30 includes S301.
  • the first data writing sub-circuit 102 writes the first data signal from the first data signal terminal D1 and the threshold voltage of the driving transistor Td into The first node A is used for threshold voltage compensation of the driving transistor Td.
  • the first control sub-circuit 103 connects the driving transistor Td with the first power supply voltage signal terminal S1 and the first pole of the element L to be driven, so as to drive
  • the transistor Td outputs a driving signal to the first electrode of the element L to be driven according to the first data signal from the first data signal terminal D1 and the first voltage signal from the first power supply voltage signal terminal S1.
  • the time control sub-circuit 20 includes a second driving sub-circuit 201, a second data writing sub-circuit 202, and a second control sub-circuit 203.
  • the foregoing S20 includes S201
  • the foregoing S40 includes S401.
  • the second data writing sub-circuit 202 In response to the second scan signal received from the second scan signal terminal G2, the second data writing sub-circuit 202 combines the second data signal from the second data signal terminal D2 with the second data signal in the second driving sub-circuit 201 The threshold voltage of the first transistor T1 is written into the second node B to perform threshold compensation for the first transistor T1.
  • the second control sub-circuit 203 In response to the received enable signal from the enable signal terminal EM, the second control sub-circuit 203 connects the first transistor T1 with the second power supply voltage signal terminal S2 and the second pole of the element L to be driven, so that The first transistor T1 is turned on in response to the common voltage signal whose voltage from the common voltage signal terminal V1 changes within a set voltage range and the second data signal from the second data signal terminal D2, and turns on the signal from the second power supply voltage signal terminal S2. The second power supply voltage signal is transmitted to the second pole of the element L to be driven.
  • the above-mentioned driving method of the pixel driving circuit has the same beneficial effects as the above-mentioned pixel driving circuit, and will not be repeated here.
  • the driving control sub-circuit 10 further includes a first reset sub-circuit 104.
  • the above S10 further includes S102.
  • the first reset sub-circuit 104 transmits the first initial signal from the first initial signal terminal INI1 to the first node A, for the first node A A to reset.
  • the first reset sub-circuit 104 includes a sixth transistor T6.
  • the sixth transistor T6 is turned on to transmit the first initial signal from the first initial signal terminal INI1 to the first node A, Reset the first node A.
  • the voltage of the first node A is the voltage V init1 of the first initial signal.
  • the second electrode of the first capacitor C1 connected to the first node A and the gate of the driving transistor Td are also reset.
  • the time control sub-circuit 20 further includes a second reset sub-circuit 204.
  • S20 further includes S202.
  • the second reset sub-circuit 204 transmits the second initial signal from the second initial signal terminal INI2 to the second node B. B to reset.
  • the second reset sub-circuit 204 includes an eleventh transistor T11.
  • the second reset sub-circuit 204 turns on the eleventh transistor T11, and transmits the second initial signal from the second initial signal terminal INI2 to the second node B , To reset the second node B.
  • the voltage of the second node B is the voltage V init2 of the second initial signal.
  • the first pole of the second capacitor C2 connected to the second node B and the gate of the first transistor T1 are also reset.
  • the voltage of the first driving sub-circuit 101 is reset by the first reset sub-circuit 104, and the voltage of the second driving sub-circuit 201 is reset by the second reset sub-circuit 204, so that the first reset sub-circuit
  • the noise reduction of the driving sub-circuit 101 and the second driving sub-circuit 201 avoids affecting the first data signal and the second data signal written in the subsequent driving process.
  • the display panel further includes a plurality of first scan signal lines G1(1) to G1(N), and a plurality of first data signal lines D1(1) to D1.
  • M multiple second scan signal lines G2(1) ⁇ G2(N), multiple second data signal lines D2(1) ⁇ D2(M), multiple enable signal lines E(1) ⁇ E (N).
  • the first scan signal line is configured to provide a first scan signal to the pixel driving circuit.
  • the second scan signal line is configured to provide a second scan signal to the pixel driving circuit.
  • the enable signal line is configured to provide an enable signal to the pixel driving circuit.
  • the first data signal line is configured to provide a first data signal to the pixel driving circuit.
  • the second data signal line is configured to provide a second data signal to the pixel driving circuit.
  • the first power supply voltage signal line is configured to provide a first power supply voltage signal to the pixel driving circuit.
  • the second power supply voltage signal line is configured to provide a second power supply voltage signal to the pixel driving circuit.
  • the common voltage signal line is configured to provide a common voltage signal to the pixel driving circuit.
  • the pixel driving circuits located in the same row of sub-pixel regions P are connected to the same first scan signal line and the plurality of second scan signal lines G1(1) to G1(N).
  • Each pixel driving circuit located in the sub-pixel area P of the same column is connected to the same first data signal line and the second data signal lines D2 ( 1) The same second data signal line in D2(M), the same first power supply voltage signal line in the plurality of first power supply voltage signal lines L S1 , and the same first power supply voltage signal line in the plurality of second power supply voltage signal lines L S2 The same second power supply voltage signal line and the same common voltage signal line among the plurality of common voltage signal lines LV1.
  • each pixel driving circuit located in the first row of sub-pixel regions P is connected to the first scan signal line G1(1), the second scan signal line G2(1), and the enable signal line E(1).
  • the pixel driving circuits located in the second row of sub-pixel regions P are connected to the first scan signal line G1(2), the second scan signal line G2(2), and the enable signal line E(2).
  • Each pixel driving circuit located in the sub-pixel area P in the Nth row is connected to the first scan signal line G1 (N), the second scan signal line G2 (N), and the enable signal line E (N).
  • Each pixel driving circuit located in the first column sub-pixel area P is connected to the first data signal line D1 (1), the second data signal line D2 (1), the first power supply voltage signal line L S1 , and the second power supply voltage signal The line L S2 and the common voltage signal line L V1 .
  • Each pixel driving circuit located in the second column sub-pixel area P is connected to the first data signal line D1 (2), the second data signal line D2 (2), the first power supply voltage signal line L S1 , and the second power supply voltage signal The line L S2 and the common voltage signal line L V1 .
  • Each pixel driving circuit located in the sub-pixel area P of the M-th column is connected to the first data signal line D1 (M), the second data signal line D2 (M), the first power supply voltage signal line L S1 and the second power supply voltage signal The line L S2 and the common voltage signal line L V1 .
  • the first scan signal terminal G1 can be understood as an equivalent connection point after the first scan signal line is connected to the pixel driving circuit.
  • the first data signal terminal D1 can be understood as an equivalent connection point after the first data signal line is connected to the pixel driving circuit.
  • the enable signal terminal EM can be understood as an equivalent connection point after the enable signal line is connected to the pixel driving circuit.
  • the first power supply voltage signal terminal S1 can be understood as an equivalent connection point after the first power supply voltage signal line L S1 is connected to the pixel driving circuit.
  • the second power supply voltage signal terminal S2 can be understood as an equivalent connection point after the second voltage signal line L S2 is connected to the pixel driving circuit.
  • the common voltage signal terminal V1 can be understood as an equivalent connection point after the common voltage signal line L V1 is connected to the pixel driving circuit.
  • FIG. 1 illustrates that the pixel driving circuits located in any two columns of sub-pixel regions P are connected to different first power supply voltage signal lines L S1 , second power supply voltage signal lines L S2 and common voltage signal lines L V1 , but the present disclosure
  • the embodiment is not limited to this, and the pixel driving circuits located in multiple columns (for example, 2 columns or 3 columns or 4 columns) in the sub-pixel area P are connected to the same first power supply voltage signal line L S1 and the second power supply voltage.
  • the signal line L S2 and the common voltage signal line L V1 are examples of the first power supply voltage signal line L S1 , the second power supply voltage signal line L V1 .
  • the display panel further includes a plurality of first reset signal lines R1(1) to R1(N) and a plurality of first initial signal lines (not shown in FIG. 1).
  • the first reset signal line is configured to provide a first reset signal to the pixel driving circuit.
  • the first initial signal line is configured to provide a first initial signal to the pixel driving circuit.
  • the pixel driving circuits located in the same row of sub-pixel regions P are connected to the same first reset signal line among the plurality of first reset signal lines R1(1) to R1(N), and are located in the same column sub-pixel area.
  • Each pixel driving circuit in the pixel area P is connected to the same first initial signal line among the plurality of first initial signal lines.
  • each pixel driving circuit located in the first row of sub-pixel regions P is connected to the first reset signal line R1 (1).
  • Each pixel driving circuit located in the second row sub-pixel area P is connected to the first reset signal line R1 (2).
  • Each pixel driving circuit located in the sub-pixel area P of the Nth row is connected to the first reset signal line R1 (N).
  • the first reset signal terminal RST1 can be understood as: an equivalent connection point after the first reset signal line is connected to the pixel driving circuit.
  • the first initial signal terminal INI1 can be understood as an equivalent connection point after the first initial signal line is connected to the pixel driving circuit.
  • the display panel further includes a plurality of second reset signal lines R2(1)-R2(N) and a plurality of second initial signal lines (not shown in FIG. 1).
  • the second reset signal line is configured to provide a second reset signal to the pixel driving circuit.
  • the second initial signal line is configured to provide a second initial signal to the pixel driving circuit.
  • the pixel drive circuits located in the same row of sub-pixel regions P are connected to the same second reset signal line among the plurality of second reset signal lines R2(1) to R2(N), and are located in the same column sub-pixel area.
  • Each pixel driving circuit in the pixel area P is connected to the same second initial signal line among the plurality of second initial signal lines.
  • each pixel driving circuit located in the first row of sub-pixel regions P is connected to the second reset signal line R2(1).
  • Each pixel driving circuit located in the second row sub-pixel area P is connected to the second reset signal line R2(2).
  • Each pixel driving circuit located in the sub-pixel area P of the Nth row is connected to the second reset signal line R2(N).
  • the second reset signal terminal RST2 can be understood as: an equivalent connection point after the second reset signal line is connected to the pixel driving circuit.
  • the second initial signal terminal INI2 can be understood as an equivalent connection point after the second initial signal line is connected to the pixel driving circuit.

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Abstract

一种像素驱动电路，包括驱动控制子电路（10）和时间控制子电路（20）。驱动控制子电路（10）被配置为响应于来自第一扫描信号端（G1）的第一扫描信号，至少将来自第一数据信号端（D1）的第一数据信号写入第一驱动子电路（101）；以及响应于来自使能信号端（EM）的使能信号，使驱动晶体管（Td）根据第一数据信号和来自第一电源电压信号端（S1）的第一电源电压信号，向待驱动元件（L）的第一极输出驱动信号；时间控制子电路（20）被配置为响应于来自第二扫描信号端（G2）的第二扫描信号，至少将来自第二数据信号端（D2）的第二数据信号写入第二驱动子电路（201）；以及响应于使能信号，使第二驱动子电路（201）与第二电源电压信号端（S2）和待驱动元件（L）的第二极连接；第二驱动子电路（201）被配置为响应于第二数据信号和来自公共电压信号端（V1）的电压在设定电压范围内变化的公共电压信号，向待驱动元件（L）的第二极输出来自第二电源电压信号端（S2）的第二电源电压信号，以使待驱动元件（L）响应于驱动信号和第二电源电压信号开始工作。

Description

像素驱动电路及其驱动方法、显示面板、显示装置
本申请要求于2019年10月30日提交的、申请号为201911047859.7的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路及其驱动方法、显示面板、显示装置。
背景技术
自发光器件因其亮度高、色域广的特点受到广泛关注。然而，由于制作工艺均一性的问题，会导致自发光器件的开启电压不一致，并且自发光器件的光电转换特性(包括光电转换效率、均一性和色坐标等)会随着流过该自发光器件的电流的变化而发生改变；因此，在将自发光器件应用在显示面板的情况下，会对显示面板的显示效果造成一定的影响。
发明内容
一方面，提供一种像素驱动电路，包括：驱动控制子电路和时间控制子电路。所述驱动控制子电路至少连接到第一扫描信号端、第一数据信号端、第一电源电压信号端、使能信号端以及待驱动元件的第一极；所述驱动控制子电路包括第一驱动子电路，所述第一驱动子电路包括驱动晶体管；所述驱动控制子电路被配置为响应于接收到的来自所述第一扫描信号端的第一扫描信号，至少将来自所述第一数据信号端的第一数据信号写入所述第一驱动子电路；以及响应于接收到的来自所述使能信号端的使能信号，使所述驱动晶体管根据所述第一数据信号和来自所述第一电源电压信号端的第一电源电压信号，向所述待驱动元件的第一极输出驱动信号。
所述时间控制子电路至少连接到第二扫描信号端、第二数据信号端、第二电源电压信号端、使能信号端、公共电压信号端以及所述待驱动元件的第二极；所述时间控制子电路包括第二驱动子电路；所述时间控制子电路被配置为响应于接收到的来自所述第二扫描信号端的第二扫描信号，至少将来自所述第二数据信号端的第二数据信号写入所述第二驱动子电路；以及响应于接收到的来自所述使能信号端的使能信号，使所述第二驱动子电路与所述第二电源电压信号端和所述待驱动元件的第二极连接；所述第二驱动子电路响应于所述第二数据信号和来自所述公共电压信号端的电压在设定电压范围内变化的公共电压信号，向所述待驱动元件的第二极输出来自所 述第二电源电压信号端的第二电源电压信号，以使所述待驱动元件响应于接收到的所述驱动信号和所述第二电源电压信号，开始工作。
在一些实施例中，所述第一驱动子电路还包括第一电容器；所述第一电容器的第一极连接到所述第一电源电压信号端，所述第一电容器的第二极连接到第一节点；所述驱动晶体管的栅极连接到所述第一节点。
在一些实施例中，所述驱动控制子电路还包括第一数据写入子电路以及第一控制子电路；所述第一数据写入子电路连接到所述第一扫描信号端、所述第一数据信号端、所述第一节点以及所述驱动晶体管；所述第一数据写入子电路被配置为响应于接收到的所述第一扫描信号，将所述第一数据信号和所述驱动晶体管的阈值电压写入所述第一节点；所述第一控制子电路连接到所述使能信号端、所述第一电源电压信号端、所述驱动晶体管以及所述待驱动元件的第一极；所述第一控制子电路被配置为响应于接收到的所述使能信号，使所述驱动晶体管与所述第一电源电压信号端和所述待驱动元件的第一极连接。
在一些实施例中，所述第一数据写入子电路包括第二晶体管和第三晶体管；所述第二晶体管的栅极连接到所述第一扫描信号端，所述第二晶体管的第一极连接到所述驱动晶体管的第二极，所述第二晶体管的第二极连接到所述第一节点；所述第三晶体管的栅极连接到所述第一扫描信号端，所述第三晶体管的第一极连接到所述第一数据信号端，所述第三晶体管的第二极连接到所述驱动晶体管的第一极。
在一些实施例中，所述第一控制子电路包括第四晶体管和第五晶体管；所述第四晶体管的栅极连接到所述使能信号端，所述第四晶体管的第一极连接到所述第一电源电压信号端，所述第四晶体管的第二极连接到所述驱动晶体管的第一极；所述第五晶体管的栅极连接到所述使能信号端，所述第五晶体管的第一极连接到所述驱动晶体管的第二极，所述第五晶体管的第二极连接到所述待驱动元件的第一极。
在一些实施例中，所述驱动控制子电路还包括第一复位子电路；所述第一复位子电路连接到第一初始信号端、第一复位信号端以及所述驱动晶体管的栅极；所述第一复位子电路被配置为响应于接收到的来自所述第一复位信号端的第一复位信号，将来自所述第一初始信号端的第一初始信号传输至所述驱动晶体管的栅极，对所述驱动晶体管的栅极进行复位。
在一些实施例中，所述第一复位子电路包括第六晶体管；所述第六晶体 管的栅极连接到所述第一复位信号端，所述第六晶体管的第一极连接到所述第一初始信号端，所述第六晶体管的第二极连接到所述驱动晶体管的栅极。
在一些实施例中，所述第二驱动子电路包括第一晶体管和第二电容器；所述第二电容器的第一极连接到第二节点，所述第二电容器的第二极连接到所述公共电压信号端；所述第一晶体管的栅极连接到所述第二节点。
在一些实施例中，所述时间控制子电路还包括第二数据写入子电路以及第二控制子电路；所述第二数据写入子电路连接到所述第二扫描信号端、所述第二数据信号端、所述第二节点以及所述第一晶体管的第一极和第二极；所述第二数据写入子电路被配置为响应于接收到的所述第二扫描信号，将所述第二数据信号和所述第一晶体管的阈值电压写入所述第二节点；所述第二控制子电路连接到所述使能信号端、所述第二电源电压信号端、所述第一晶体管的第一极和第二极、以及所述待驱动元件的第二极；所述第二控制子电路被配置为响应于接收到的所述使能信号，使所述第一晶体管与所述第二电源电压信号端和所述待驱动元件的第二极连接。
在一些实施例中，所述第二数据写入子电路包括第七晶体管和第八晶体管；所述第七晶体管的栅极连接到所述第二扫描信号端，所述第七晶体管的第一极连接到所述第一晶体管的第一极，所述第七晶体管的第二极连接到所述第二数据信号端电连接；所述第八晶体管的栅极连接到所述第二扫描信号端，所述第八晶体管的第一极连接到所述第一晶体管的第二极，所述第八晶体管的第二极连接到所述第二节点。
在一些实施例中，所述第二控制子电路包括第九晶体管和第十晶体管；所述第九晶体管的栅极连接到所述使能信号端，所述第九晶体管的第一极连接到所述第二电源电压信号端，所述第九晶体管的第二极连接到所述第一晶体管的第一极；所述第十晶体管的栅极连接到所述使能信号端，所述第十晶体管的第一极连接到所述待驱动元件的第二极，所述第十晶体管的第二极连接到所述第一晶体管的第二极。
在一些实施例中，所述第一晶体管为N型晶体管，所述驱动晶体管为P型晶体管；或者，所述第一晶体管为P型晶体管，所述驱动晶体管为N型晶体管。
在一些实施例中，所述时间控制子电路还包括第二复位子电路；所述第二复位子电路连接到第二初始信号端、第二复位信号端以及所述第二节点；所述第二复位子电路被配置为响应于接收到的来自所述第二复位 信号端的第二复位信号，将来自所述第二初始信号端的第二初始信号传输至所述第二节点，对所述第二节点进行复位。
在一些实施例中，所述第二复位子电路包括第十一晶体管；所述第十一晶体管的栅极连接到所述第二复位信号端，所述第十一晶体管的第一极连接到所述第二初始信号端，所述第十一晶体管的第二极连接到所述第二节点。
第二方面，提供一种显示面板，包括多个上述的像素驱动电路以及多个待驱动元件，多个待驱动元件中的一个与对应的一个像素驱动电路连接。
在一些实施例中，所述显示面板具有多个亚像素区，每个像素驱动电路设置于一个亚像素区中；所述显示面板还包括：多条第一扫描信号线、多条第一数据信号线、多条第二扫描信号线及多条第二数据信号线；位于同一行亚像素区中的各像素驱动电路连接的第一扫描信号端与对应的一条第一扫描信号线连接；位于同一列亚像素区中的各像素驱动电路连接的第一数据信号端与对应的一条第一数据信号线连接；位于同一行亚像素区中的各像素驱动电路连接的第二扫描信号端与对应的一条第二扫描信号线连接；位于同一列亚像素区中的各像素驱动电路连接的第二数据信号端与对应的一条第二数据信号线连接。
在一些实施例中，所述待驱动元件为电流型发光二极管。
第三方面，提供一种显示装置，包括上述的显示面板。
第四方面，提供一种如上述的像素驱动电路的驱动方法，一个帧周期包括扫描阶段和工作阶段，所述扫描阶段包括多个行扫描阶段。
所述驱动方法，包括：
在所述多个行扫描阶段中的每个行扫描阶段：所述驱动控制子电路响应于接收到的来自所述第一扫描信号端的第一扫描信号，至少将来自所述第一数据信号端的第一数据信号写入所述第一驱动子电路；所述时间控制子电路响应于接收到的来自所述第二扫描信号端的第二扫描信号，至少将来自所述第二数据信号端的第二数据信号写入所述第二驱动子电路。
在所述工作阶段：所述驱动控制子电路响应于接收到的来自所述使能信号端的使能信号，使所述第一驱动子电路中的驱动晶体管根据来自所述第一数据信号端的第一数据信号和来自所述第一电源电压信号端的第一电源电压信号，向所述待驱动元件的第一极输出驱动信号。所述时间控制子电路响应于接收到的来自所述使能信号端的使能信号，使所述第二驱动子 电路与所述第二电源电压信号端和所述待驱动元件的第二极连接；所述第二驱动子电路响应于来自所述第二数据信号端的第二数据信号和来自所述公共电压信号端的电压在设定电压范围内变化的公共电压信号，向所述待驱动元件的第二极输出来自所述第二电源电压信号端的第二电源电压信号，以使所述待驱动元件响应于接收到的所述驱动信号和所述第二电源电压信号，开始工作。
在一些实施例中，所述驱动控制子电路还包括第一数据写入子电路以及第一控制子电路；在所述多个行扫描阶段中的每个行扫描阶段，所述驱动控制子电路响应于接收到的来自所述第一扫描信号端的第一扫描信号，至少将来自所述第一数据信号端的第一数据信号写入所述第一驱动子电路；在所述工作阶段，所述驱动控制子电路响应于接收到的来自所述使能信号端的使能信号，使所述第一驱动子电路中的驱动晶体管根据所述第一数据信号和所述第一电源电压信号，向所述待驱动元件的第一极输出驱动信号，包括：
在所述多个行扫描阶段中的每个行扫描阶段：所述第一数据写入子电路响应于接收到的所述第一扫描信号端的第一扫描信号，将来自所述第一数据信号端的第一数据信号和所述驱动晶体管的阈值电压写入第一节点。
在所述工作阶段：所述第一控制子电路响应于接收到的来自所述使能信号端的使能信号，使所述驱动晶体管与所述第一电源电压信号端和所述待驱动元件的第一极连接，以使所述驱动晶体管根据所述第一数据信号和所述第一电源电压信号，向所述待驱动元件的第一极输出驱动信号。
在一些实施例中，所述时间控制子电路还包括第二数据写入子电路以及第二控制子电路；在所述多个行扫描阶段中的每个行扫描阶段，所述时间控制子电路响应于接收到的来自所述第二扫描信号端的第二扫描信号，至少将来自所述第二数据信号端的第二数据信号写入所述第二驱动子电路；在所述工作阶段，所述时间控制子电路响应于接收到的来自所述使能信号端的使能信号，使所述第二驱动子电路与所述第二电源电压信号端和所述待驱动元件的第二极连接，包括：
在所述多个行扫描阶段中的每个行扫描阶段：所述第二数据写入子电路响应于接收到的来自所述第二扫描信号端的第二扫描信号，将来自所述第二数据信号端的第二数据信号和所述第二驱动子电路中的第一晶体管的阈值电压写入第二节点，以对所述第一晶体管进行阈值补偿。
在所述工作阶段：所述第二控制子电路响应于接收到的来自所述使能信号端的使能信号，使所述第一晶体管与所述第二电源电压信号端和所述待驱动元件的第二极连接。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的一种显示面板的结构图；
图2为根据的一些实施例的一种像素驱动电路的结构框图；
图3为根据一些实施例的另一种像素驱动电路的结构框图；
图4为根据一些实施例的又一种像素驱动电路的结构框图；
图5为根据的一些实施例的一种像素驱动电路的电路图；
图6为根据一些实施例的又一种像素驱动电路的结构框图；
图7为根据的一些实施例的另一种像素驱动电路的电路图；
图8为根据一些实施例的像素驱动电路的一种信号时序图；
图9为根据一些实施例的像素驱动电路的另一种信号时序图；
图10为根据一些实施例的又一种像素驱动电路的电路图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术 语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。但是，诸如“连接”这样的术语也可能意味着两个或多个组件彼此之间不直接接触，但仍然相互协作或交互。这里所公开的实施例并不必然限制于本文内容。
在本公开的实施例提供的电路中，第一节点和第二节点并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
在描述一些实施例时，术语“被配置为”的使用意味着开放和包容性的语言，其不排除被配置为执行额外任务或步骤的设备。
本公开一些实施例提供一种显示装置，该显示装置包括显示面板。如图1所示，该显示面板具有多个亚像素区P。
需要说明的是，图1以上述多个亚像素区P呈N行M列的阵列形式排列为例进行示意，但本公开实施例并不限于此，上述多个亚像素区P还可以以其他方式进行排布。
在一些实施例中，上述显示装置为电视机、手机、平板电脑、笔记本电脑、显示器、数码相框或导航仪等具有显示功能的产品，本公开实施例对此不做限定。
在一些实施例中，显示面板包括多个像素驱动电路和多个待驱动元件，多个待驱动元件中的一个与对应的一个像素驱动电路连接。
在一些示例中，在显示面板的一个亚像素区P中，对应设置一个待驱动元件和连接到该待驱动元件的一个像素驱动电路，该像素驱动电路被配置为驱动该待驱动元件工作。
在一些实施例中，该待驱动元件为电流型驱动器件。
在一些示例中，待驱动元件为电流型发光二极管。
示例的，电流型发光二极管为微型发光二极管(Micro Light Emitting Diode，Micro LED)、迷你发光二极管(Mini Light Emitting Diode，Mini LED) 或者有机电致发光二极管(Organic Light Emitting Diode，OLED)。
在此基础上，上述的待驱动元件工作可以被理解为电流型发光二极管发光。
本公开一些实施例提供一种像素驱动电路，如图2所示，包括：驱动控制子电路10和时间控制子电路20。
驱动控制子电路10至少连接到第一扫描信号端G1、第一数据信号端D1、第一电源电压信号端S1、使能信号端EM以及待驱动元件L的第一极。驱动控制子电路10包括第一驱动子电路101，第一驱动子电路101包括驱动晶体管Td。
驱动控制子电路10被配置为：响应于接收到的来自第一扫描信号端G1的第一扫描信号，至少将来自第一数据信号端D1的第一数据信号写入第一驱动子电路101；以及响应于接收到的来自使能信号端EM的使能信号，使驱动晶体管Td根据来自第一数据信号端D1的第一数据信号和来自第一电源电压信号端S1的第一电源电压信号，向待驱动元件L的第一极输出驱动信号。
时间控制子电路20至少连接到第二扫描信号端G2、第二数据信号端D2、第二电源电压信号端S2、使能信号端EM、公共电压信号端V1以及待驱动元件L的第二极；时间控制子电路20包括第二驱动子电路201。
时间控制子电路20被配置为：响应于接收到的来自第二扫描信号端G2的第二扫描信号，将来自第二数据信号端D2的第二数据信号写入第二驱动子电路201；以及响应于接收到的来自使能信号端EM的使能信号，使第二驱动子电路201与第二电源电压信号端S2和待驱动元件L的第二极连接。第二驱动子电路201响应于接收到的来自第二数据信号端D2的第二数据信号和来自公共电压信号端V1的电压在设定电压范围内变化的公共电压信号，向待驱动元件L的第二极输出来自第二电源电压信号端S2的第二电源电压信号，以使待驱动元件L响应于接收到的驱动信号和第二电源电压信号，开始工作。
在一些实施例中，驱动晶体管Td向待驱动元件L的第一极输出驱动信号可以被理解为：驱动晶体管Td向电流型发光二极管的第一极输出驱动电流。第二驱动子电路201向待驱动元件L的第二极输出第二电源电压信号可以被理解为：第二驱动子电路201向电流型发光二极管的第二极输出第二电源电压信号。在此基础上，待驱动元件L响应于接收到的驱动信号和第二电源电压信号开始工作，可以被理解为：电流型发光二极管响应于其第一极接收到的驱动信号和其第二极接收到的第二电源电压信号，电流型发光二极管导通，则驱动晶体管Td向电流型发光二极管的第一极输出驱动电流，以驱动电流型 发光二极管开始发光。
在一些实施例中，待驱动元件L的第一极和第二极分别为电流型发光二极管的阳极和阴极。
在一些示例中，来自第一电源电压信号端S1的第一电源电压信号为高电平信号，来自第二电源电压信号端S2的第二电源电压信号为低电平信号。在此基础上，如图2所示，待驱动元件L的第一极为电流型发光二极管的阳极，待驱动元件L的第二极为电流型发光二极管的阴极。
在另一些示例中，来自第一电源电压信号端S1的第一电源电压信号为低电平信号，来自第二电源电压信号端S2的第二电源电压信号为高电平信号。在此基础上，如图3所示，待驱动元件L的第一极为电流型发光二极管的阴极，待驱动元件L的第二极为电流型发光二极管的阳极。
在一些示例中，来自第一电源电压信号端S1的第一电源电压信号和来自第二电源电压信号端S2的第二电源电压信号在一帧时间内均为固定的电压信号。本领域技术人员可以在保证像素驱动电路正常工作的情况下，对第一电源电压信号和第二电源电压信号的电压大小进行设定。
在一些示例中，来自第一数据信号端D1的第一数据信号为固定的高电压信号，以使待驱动元件L能够具有较高的发光效率。在此情况下，像素驱动电路通过时间控制子电路20来控制灰阶。
在另一些示例中，来自第一数据信号端D1的第一数据信号的电压在一定的电压区间范围内变化，在该电压区间范围内的第一数据信号能够保证待驱动元件L具有较高的发光效率。在此情况下，像素驱动电路通过驱动控制子电路10和时间控制子电路20共同控制灰阶。
在上述的驱动控制子电路10中，驱动控制子电路10通过控制来自第一数据信号端D1的第一数据信号和来自第一电源电压信号端S1的第一电源电压信号的电压大小，来控制驱动晶体管Td传输至待驱动元件L的驱动信号的大小(例如驱动电流的幅值)。在时间控制子电路20中，通过控制来自第二数据信号端D2的第二数据信号和来自公共电压信号端V1的公共电压信号的电压大小，来控制第二电源电压信号传输至待驱动元件L的第二极的时长，以此来控制待驱动元件L的工作时长。这里，当第二电源电压信号传输至待驱动元件L的第二极时，待驱动元件L导通，开始工作。
在一些实施例中，上述的待驱动元件L的工作时长，可以被理解为：电流型发光二极管的发光时长。
在本公开一些实施例的像素驱动电路中，驱动控制子电路10响应于接收 到的来自第一扫描信号端G1的第一扫描信号，至少将来自第一数据信号端D1的第一数据信号写入第一驱动子电路101；以及响应于接收到的来自使能信号端EM的使能信号，使驱动晶体管Td根据来自第一数据信号端D1的第一数据信号和来自第一电源电压信号端S1的第一电源电压信号，向待驱动元件L的第一极输出驱动信号。时间控制子电路20响应于接收到的来自第二扫描信号端G2的第二扫描信号，将来自第二数据信号端D2的第二数据信号写入第二驱动子电路201；以及响应于接收到的来自使能信号端EM的使能信号，使第二驱动子电路201响应于接收到的来自第二数据信号端D2的第二数据信号和来自公共电压信号端V1的电压在设定电压范围内变化的公共电压信号，向待驱动元件L的第二极输出来自第二电源电压信号端S2的第二电源电压信号，以使待驱动元件L响应于接收到的驱动信号和第二电源电压信号，开始工作。由此可知，驱动控制子电路10控制传输至待驱动元件的第一极的驱动信号的大小，时间控制子电路20控制来自第二电源电压信号端S2的第二电源电压信号传输至待驱动元件L的第二极的时间。这样，在待驱动元件L进行不同灰阶的显示时，通过控制输入待驱动元件L的驱动信号的大小以及待驱动元件的工作时长，可实现待驱动元件L的亮度改变，进而实现对应的灰阶显示。
在待驱动元件L为电流驱动型发光器件的情况下，在待驱动元件L进行较高灰阶显示时，像素驱动电路向待驱动元件L输出较大的驱动电流，并且可以控制待驱动元件L的发光时长为较长的发光时长。在待驱动元件L进行较低灰阶显示时，像素驱动电路向待驱动元件L输出的驱动电流可以为一个较大值(例如某一高灰阶对应的驱动电流)，通过缩短待驱动元件L的发光时长，使待驱动元件L的亮度降低。或者，在待驱动元件L进行较低灰阶显示时，像素驱动电路向待驱动元件L输出的驱动电流维持在较高值范围内(例如，该较高值范围内的驱动电流接近较高灰阶显示时的驱动电流)，通过缩短待驱动元件L的发光时长，使待驱动元件L的亮度降低。由此，无论待驱动元件L进行高灰阶显示还是低灰阶显示，驱动电流始终较大，使得待驱动元件L始终处于较高电流密度下，待驱动元件L的发光效率较高、亮度较稳定、功耗较低，且显示效果较好。
在一些实施例中，如图4所示，第一驱动子电路101包括驱动晶体管Td和第一电容器C1。第一电容器C1的第一极连接到第一电源电压信号端S1，第一电容器C1的第二极连接到第一节点A。驱动晶体管Td的栅极连接到第一节点A。驱动晶体管Td被配置为响应于来自第一数据信号端D1的第一数 据信号和来自第一电源电压信号端S1的第一电源电压信号开启，并向待驱动元件L的第一极输出驱动信号。
在一些实施例中，如图4所示，驱动控制子电路还包括第一数据写入子电路和第一控制子电路103。第一数据写入子电路102连接到第一扫描信号端G1、第一数据信号端D1、第一节点A以及驱动晶体管Td的第一极和第二极。第一数据写入子电路102被配置为：响应于接收到的来自第一扫描信号端G1的第一扫描信号，将来自第一数据信号端D1的第一数据信号和驱动晶体管Td的阈值电压写入第一节点A，以对驱动晶体管Td进行阈值电压补偿。
第一控制子电路103连接到使能信号端EM、第一电源电压信号端S1、驱动晶体管Td的第一极和第二极、以及待驱动元件L的第一极。第一控制子电路103被配置为：响应于接收到的来自使能信号端EM的使能信号，使驱动晶体管Td与第一电源电压信号端S1和待驱动元件L的第一极连接。
在一些示例中，如图5所示，第一数据写入子电路102包括第二晶体管T2和第三晶体管T3。第二晶体管T2的栅极连接到第一扫描信号端G1，第二晶体管T2的第一极连接到驱动晶体管Td的第二极，第二晶体管T2的第二极连接到第一节点A。第三晶体管T3的栅极连接到第一扫描信号端G1，第三晶体管T3的第一极连接到第一数据信号端D1，第三晶体管T3的第二极连接到驱动晶体管Td的第一极。
在一些示例中，如图5所示，第一控制子电路103包括第四晶体管T4和第五晶体管T5。第四晶体管T4的栅极连接到使能信号端EM，第四晶体管T4的第一极连接到第一电源电压信号端S1，第四晶体管T4的第二极连接到驱动晶体管Td的第一极。第五晶体管T5的栅极连接到使能信号端EM，第五晶体管T5的第一极连接到驱动晶体管Td的第二极，第五晶体管Td的第二极连接到待驱动元件L的第一极。
在一些实施例中，如图6所示，驱动控制子电路10还包括第一复位子电路104。第一复位子电路104连接到第一初始信号端INI1、第一复位信号端RST1以及驱动晶体管Td的栅极。第一复位子电路104被配置为：响应于接收到的来自第一复位信号端RST1的第一复位信号，将来自第一初始信号端INI1的第一初始信号传输至驱动晶体管Td的栅极，对驱动晶体管Td的栅极进行复位。
在一些示例中，如图7所示，第一复位子电路104包括第六晶体管T6。第六晶体管T6的栅极连接到第一复位信号端RST1，第六晶体管T6的第二极连接到第一初始信号端INI1，第六晶体管T6的第一极连接到驱动晶体管Td 的栅极。
在此基础上，由于第一电容器C1的第二极和驱动晶体管Td的栅极均连接到第一节点A，因此，在第一复位子电路104对第一节点A进行复位的同时，第一电容器C1的第二极和驱动晶体管Td的栅极也均被复位，从而实现了对第一驱动子电路101的降噪。
在一些实施例中，如图4所示，第二驱动子电路201包括第一晶体管T1和第二电容器C2。第二电容器C2的第一极连接到第二节点B，第二电容器C2的第二极连接到公共电压信号端V1，第一晶体管T1的栅极连接到第二节点B；第一晶体管T1被配置为：响应于来自公共电压信号端V1的电压在设定电压范围内变化的公共电压信号和来自第二数据信号端D2的第二数据信号，向待驱动元件L的第二极输出第二电源电压信号。
在一些实施例中，时间控制子电路20还包括第二驱动子电路201、第二数据写入子电路202以及第二控制子电路203。
第二数据写入子电路202连接到第二扫描信号端G2、第二数据信号端D2、第二节点B以及第一晶体管T1的第一极和第二极。第二数据写入子电路202被配置为：响应于接收到的来自第二扫描信号端G2的第二扫描信号，将来自第二数据信号端D2的第二数据信号和第一晶体管T1的阈值电压写入第二节点B，以对第一晶体管T1进行阈值电压补偿。
第二控制子电路203连接到使能信号端EM、第二电源电压信号端S2、第一晶体管T1的第一极和第二极、以及待驱动元件L的第二极。第二控制子电路203被配置为：响应于接收到的来自使能信号端EM的使能信号，使第一晶体管T1与第二电源电压信号端S2和待驱动元件L的第二极连接，以使第一晶体管T1响应于来自公共电压信号端V1的电压在设定电压范围内变化的公共电压信号和来自第二数据信号端D2的第二数据信号开启，并将来自第二电源电压信号端S2的第二电源电压信号传输至待驱动元件L的第二极，从而控制待驱动元件L的工作时长。
公共电压信号的电压在设定电压范围内随时间发生变化，并且该设定电压范围根据待驱动元件L的发光时长确定。因此，通过改变在设定电压范围内变化的公共电压信号的电压，可以实现对待驱动元件L的发光时长的控制，从而实现对灰阶的控制。
在本公开一些实施例提供的时间控制子电路中，第二数据写入子电路202将来自第二数据信号端D2的第二数据信号与第一晶体管T1的阈值电压写入第二节点B，使得第二节点B的电压为第二数据信号的电压(记为V data2)与 第一晶体管T1的阈值电压(记为V th1)之和。由于第二电容器C2的第一极连接到第二节点B，则第二电容器C2的第一极的电压为第二节点B的电压，即为：V data2+V th1。并且，由于第二电容器C2的第二极连接到公共电压信号端V1，则第二电容器C2的第二极的电压为来自公共电压信号端V1的公共电压信号的电压。根据电容器的电荷保持定律，第二电容器C2的两端的电压差保持不变，当公共电压信号的电压在设定电压范围内变化时，第二电容器C2的第一极的电压会随着公共电压信号的电压变化而变化，即第二节点B的电压会随着公共电压信号的电压变化而变化。
由于公共电压信号的电压在设定电压范围内变化，且第一晶体管T1的栅极连接到第二节点B，因此，当第二节点B的电压变化到某一特定值时，第一晶体管T1开启。此时，第一晶体管T1与第二电源电压信号端S2和待驱动元件L的第二极连接，来自第二电源电压信号端S2的第二电源电压信号通过第一晶体管T1传输至待驱动元件L的第二极，使得待驱动元件L响应于接收到的来自驱动晶体管Td的驱动信号和该第二电源电压信号开始工作。由于第一晶体管T1的开启与否决定了第二电源电压信号能否传输到待驱动元件L的第二极，因而通过变化的公共电压信号控制第一晶体管T1开启与否，可实现对待驱动元件L的工作时长的控制。
在一些示例中，如图5所示，第二数据写入子电路202包括第七晶体管T7和第八晶体管T8。第七晶体管T7的栅极连接到第二扫描信号端G2，第七晶体管T7的第一极连接到第一晶体管T1的第一极，第七晶体管T7的第二极连接到第二数据信号端D2。第八晶体管T8的栅极连接到第二扫描信号端G2，第八晶体管T8的第一极连接到第一晶体管T1的第二极，第八晶体管T8的第二极连接到第二节点B。
在一些示例中，如图5所示，第二控制子电路203包括第九晶体管T9和第十晶体管T10。第九晶体管T9的栅极连接到使能信号端EM，第九晶体管T9的第一极连接到第二电源电压信号端S2，第九晶体管T9的第二极连接到第一晶体管T1的第一极。第十晶体管T10的栅极连接到使能信号端EM，第十晶体管T10的第二极连接到第一晶体管T1的第二极，第十晶体管T10的第一极连接到待驱动元件L的第二极。
在本公开的实施例中，第一极为晶体管的源极和漏极中的一者，第二极为晶体管的源极和漏极中的另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例 的，对于P型晶体管，将第二极称为漏极，将第一极称为源极。又示例的，对于N型晶体管，将第一极称为漏极，将第二极称为源极。
需要说明的是，除了驱动晶体管Td和第一晶体管T1之外，本公开对像素驱动电路中的其余晶体管的类型不作限制，这些晶体管可以是P型晶体管，也可以是N型晶体管。
此外，根据晶体管导电方式的不同，可以将晶体管分为增强型晶体管和耗尽型晶体管。本公开实施例中的各个晶体管可以为增强型晶体管，也可以为耗尽型晶体管，对此不作限制。
在一些实施例中，如图5和图7所示，驱动晶体管Td为P型晶体管，第一晶体管T1为N型晶体管。
在来自第一电源电压信号端S1的第一电源电压信号为高电平信号、来自第二电源电压信号端S2提供的第二电源电压信号为低电平信号的情况下，待驱动元件L的第一极为阳极，第二极为阴极。因此，在待驱动元件L的工作状态下，驱动电流由待驱动元件L的第一极流向第二极。即，流过驱动晶体管Td的驱动电流为由驱动晶体管Td的第一极流向驱动晶体管Td的第二极，且流过第一晶体管T1的驱动电流为由第一晶体管T1的第二极流向第一晶体管T1的第一极。
由于驱动晶体管Td为P型晶体管，则将驱动晶体管Td的第一极称为源极。这样，来自第一电源电压信号端S1的第一电源电压信号传输至驱动晶体管Td的第一极，即，驱动晶体管Td的源极接收第一电源电压信号。
由于第一晶体管T1为N型晶体管，则第一晶体管T1的第二极称为源极。这里，由于晶体管的第一极和第二极在结构上可以是没有区别的，因此，第一晶体管T1的第二极可以被理解为第一晶体管T1的第一极，相应地，第一晶体管T1的第一极可以被理解为第一晶体管T1的第二极。这样，来自第二电源电压信号端S2的第二电源电压信号传输至第一晶体管T1的第一极，即，第一晶体管T1的第二极(即，源极)接收第二电源电压信号。
在此基础上，由于第一电源电压信号和第二电源电压信号均为固定的电压信号。因此，将驱动晶体管Td的源极和第一晶体管T1的源极控制在固定的电压信号下，可对待驱动元件L的工作进行更精细的控制，避免待驱动元件L的开启电压对显示面板的显示效果产生影响。
在另一些实施例中，参考图10，驱动晶体管Td为N型晶体管，第一晶体管T1为P型晶体管。
在来自第一电源电压信号端S1的第一电源电压信号为低电平信号、来自 第二电源电压信号端S2提供的第二电源电压信号为高电平信号的情况下，待驱动元件L的第一极为阴极，第二极为阳极。因此，在待驱动元件L的工作状态下，驱动电流由待驱动元件L的第二极流向第一极。即，流过驱动晶体管Td的驱动电流为由驱动晶体管Td的第二极流向驱动晶体管Td的第一极，且流过第一晶体管T1的驱动电流为由第一晶体管T1的第一极流向第一晶体管T1的第二极。
由于驱动晶体管Td为N型晶体管，则将驱动晶体管Td的第二极为源极。这里，由于晶体管的第一极和第二极在结构上可以是没有区别的，因此，驱动晶体管Td的第二极可以被理解为驱动晶体管Td的第一极，而驱动晶体管Td的第一极则可以被理解为驱动晶体管Td的第二极。这样，来自第一电源电压信号端S1的第一电源电压信号传输至驱动晶体管Td的第一极，即，驱动晶体管Td的第二极(即，源极)接收第一电源电压信号。
由于第一晶体管T1为P型晶体管，则将第一晶体管T1的第一极称为源极，来自第二电源电压信号端S2的第二电源电压信号传输至第一晶体管T1的第一极，即，第一晶体管T1的源极接收第二电源电压信号。
在此基础上，由于第一电源电压信号和第二电源电压信号均为固定的电压信号。因此，将驱动晶体管Td的源极和第一晶体管T1的源极控制在固定的电压信号下，可对待驱动元件L的工作进行更精细的控制，避免待驱动元件L的开启电压对显示面板的显示效果产生影响。
在一些实施例中，如图6所示，时间控制子电路20还包括第二复位子电路204。第二复位子电路204连接到第二初始信号端INI2、第二复位信号端RST2以及第二节点B。第二复位子电路204被配置为：响应于来自第二复位信号端RST2的第二复位信号，将来自第二初始信号端INI2的第二初始信号传输至第二节点B，对第二节点B进行复位。
由于第二电容器C2的第一极和第一晶体管T1的栅极均与第二节点B连接，因此，在第二复位子电路204对第二节点B进行复位的同时，第二电容器C2的第一极和第一晶体管T1的栅极也均被复位，从而实现了对第二驱动子电路201的降噪。
在一些实施例中，如图7所示，第二复位子电路204包括第十一晶体管T11。第十一晶体管T11的栅极连接到第二复位信号端RST2，第十一晶体管T11的第一极连接到第二初始信号端INI2，第十一晶体管T11的第二极连接到第二节点B。
在此基础上，结合图8(图8示出了图7的像素驱动电路的信号时序图)， 对图7所示的像素驱动电路在不同阶段的工作情况进行举例说明。图7以驱动控制子电路10中的各晶体管均为P型晶体管；时间控制子电路20中，除第一晶体管T1、第七晶体管T7、第八晶体管T8和第十一晶体管T11为N型晶体管之外，其余各晶体管均为P型晶体管为例进行说明。
在此基础上，来自第一电源电压信号端S1的第一电源电压信号为高电平信号，来自第二电源电压信号端S2的第二电源电压信号为低电平信号，待驱动元件L的第一极为阳极，第二极为阴极。
如图8所示，一个帧周期包括扫描阶段(P1～P6)和工作阶段(P6～P7)。其中，扫描阶段(P1～P6)包括多个行扫描阶段。在显示面板中的多个像素驱动电路设置在N行M列的亚像素区P中的情况下，该多个行扫描阶段为N个行扫描阶段，该N个行扫描阶段为ts1～tsN，第一行扫描阶段为ts1，第N个行扫描阶段为tsN，且N为不小于2的整数。
在扫描阶段(P1～P6)，对各行亚像素区P中的像素驱动电路逐行进行扫描。即，从位于第一行亚像素区P中的像素驱动电路开始逐行扫描，依次向各行亚像素区P中的像素驱动电路输入第一数据信号和第二数据信号，直至将第一数据信号和第二数据信号输入位于第N行亚像素区P中的各像素驱动电路。
在一些实施例中，对各行亚像素区P中的像素驱动电路逐行进行扫描后，进入工作阶段(P6～P7)。
在一些示例中，各行亚像素区P中的像素驱动电路可以依次进入工作阶段。即，第一行亚像素区P中的像素驱动电路首先进入工作阶段，之后第二行亚像素区P中的像素驱动电路进入工作阶段，直至第N行亚像素区P中的像素驱动电路进入工作阶段。每行亚像素区P中的像素驱动电路在工作阶段的使能信号的有效时长相同。
在另一些示例中，各行亚像素区P中的像素驱动电路同步进入工作阶段。
在另一些实施例中，每行亚像素区P中的像素驱动电路在相应的行扫描阶段结束后，进入工作阶段。
在每个行扫描阶段，位于同一行的M个亚像素区P中的像素驱动电路被同步写入不同的或者相同的第一数据信号。也就是说，第一数据信号为一组信号。位于同一行M个亚像素区P中的像素驱动电路被同步写入不同的或者相同的第二数据信号。也就是说，第二数据信号为一组信号。
以下以位于第一行第一个亚像素区P中的像素驱动电路，且与该像素驱动电路连接的待驱动元件L为电流型发光二极管为例，进行说明。
如图7和图8所示，在扫描阶段(P1～P6)中的第一个行扫描阶段ts1，位于第一行的第一个亚像素区P中的像素驱动电路包括如下驱动过程：
在第一阶段(P1～P2)，响应于接收到的来自第一复位信号端RST1输入的第一复位信号，第六晶体管T6开启，将来自第一初始信号端INI1的第一初始信号传输至第一节点A，实现对第一节点A的复位。此时，第一节点A的电压为第一初始信号的电压(记为V init1)。在此情况下，与第一节点A连接的第一电容器C1的第二极、以及驱动晶体管Td的栅极也均被复位为V init1。
来自第一初始信号端INI1的第一初始信号能够消除上一帧的信号对第一节点A的影响。
在一些示例中，第一初始信号为高电平信号。在第一复位子电路104工作时，第一初始信号对第一节点A进行复位，且保证驱动晶体管Td处于关闭的状态。
此外，来自第二复位信号端RST2的第二复位信号和来自第二扫描信号端G2的第二扫描信号在第一阶段(P1～P2)均为低电平信号。因此，第七晶体管T7、第八晶体管T8和第十一晶体管T11均处于关闭状态。并且，来自第一扫描信号端G1的第一扫描信号和来自使能信号端EM的使能信号在第一阶段(P1～P2)均为高电平信号。因此，第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第十晶体管T10均处于关闭状态。待驱动元件L不工作。
在第二阶段(P2～P3)，
响应于接收到的来自第一扫描信号端G1的第一扫描信号，第二晶体管T2开启，使驱动晶体管Td的栅极和第二极短接，这样，驱动晶体管Td处于饱和状态。驱动晶体管Td的栅极的电压为其第一极的电压与其阈值电压之和。
响应于接收到的来自第一扫描信号端G1的第一扫描信号，第三晶体管T3开启，将来自第一数据信号端D1的第一数据信号写入驱动晶体管Td的第一极。因此，驱动晶体管Td的第一极的电压为来自第一数据信号端D1的第一数据信号的电压(记为V data1)。在此情况下，驱动晶体管Td的栅极的电压为第一数据信号的电压V data1与驱动晶体管Td的阈值电压(记为V thd)之和，即为V data1+V thd。此时，与驱动晶体管Td的栅极连接的第一节点A电压也为V data1+V thd。
在此基础上，与第一节点A连接的第一电容器C1的第二极的电压为V data1+V thd。由于第一电容器C1的第一极连接到第一电源电压信号端S1，因此，第一电容器C1的第一极的电压为第一电源电压信号的电压(记为V S1)。 第一电容器C1的两极分别被充电，且存在电位差V S1-V data1-V thd。
来自使能信号端EM的使能信号在第二阶段(P2～P3)仍为高电平信号，第五晶体管T5仍然处于关闭状态。因此，待驱动元件L与驱动晶体管Td断开，待驱动元件L不工作。当然，第四晶体管T4、第九晶体管T9和第十晶体管T10也处于关闭状态。
此外，第一复位信号在第二阶段(P2～P3)为高电平信号，因此，第六晶体管T6处于关闭状态。并且，第二复位信号和第二扫描信号在第二阶段(P2～P3)均为低电平信号，第七晶体管T7、第八晶体管T8和第十一晶体管T11均处于关闭状态。待驱动元件L不工作。
在第三阶段(P3～P4)，响应于接收到的来自第二复位信号端RST2的第二复位信号，第十一晶体管T11开启，将来自第二初始信号端INI2的第二初始信号传输至第二节点B，实现对第二节点B的复位。此时，第二节点B的电压为第二初始信号的电压(记为V init2)。在此情况下，与第二节点B连接的第二电容器C2的第一极、以及第一晶体管T1的栅极的电压也均被复位为V init2。
第二初始信号端INI2提供的第二初始信号能够消除上一帧的信号对第二节点B的影响。
在一些示例中，第二初始信号为低电平信号。在第二复位子电路204工作时，对第二节点B进行复位，且保证第一晶体管T1处于关闭状态。
此外，第二扫描信号在第三阶段(P3～P4)为低电平信号，因此，第七晶体管T7和第八晶体管T8均处于关闭状态。并且，由于第一扫描信号、第一复位信号和使能信号在第三阶段(P3～P4)均为高电平信号，因此，第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6均处于关闭状态。在此情况下，待驱动元件L不工作。
在第四阶段(P4～P5)，响应于接收到的来自第二扫描信号端G2的第二扫描信号，第七晶体管T7开启，将来自第二数据信号端D2的第二数据信号传输至第一晶体管T1的第二极。此时，第一晶体管T1的第二极的电压为第二数据信号的电压(记为V data2)。
同时，响应于接收到的来自第二扫描信号端G2的第二扫描信号，第八晶体管T8开启，使第一晶体管T1的栅极和第一极短接，这样，第一晶体管T1处于饱和状态。第一晶体管T1的栅极的电压为其第二极的电压与其阈值电压之和。即，第一晶体管T1的栅极的电压为第二数据信号的电压V data2与其阈值电压(记为V th1)之和，即为：V data2+V th1。相应地，与第一晶体管T1的栅 极连接的第二节点B的电压也为V data2+V th1。
在此情况下，与第二节点B连接的第二电容器C2的第一极的电压也为V data2+V th1。并且，由于第二电容器C2的第二极连接到公共电压信号端V1，因此，第二电容器C2的第二极的电压为公共电压信号端V1的公共电压信号的电压V V1。即，第二电容器C2的两极分别被充电，且存在电压差V data2+V th1-V V1。
此外，由于第一扫描信号、第一复位信号和使能信号在第四阶段(P4～P5)均为高电平信号，因此第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第九晶体管T9和第十晶体管T10均处于关闭状态。第二复位信号在第四阶段(P4～P5)为低电平信号，第十一晶体管T11也处于关闭状态。在此情况下，待驱动元件L不工作。
需要说明的是，在不考虑各信号之间可能会存在信号干扰的情况下，在本公开的一些实施例中，上述的第一阶段(P1～P2)和第三阶段(P3～P4)可以同步进行。在另一些实施例中，第二阶段(P2～P3)和第四阶段(P4～P5)可以同步进行。
在此基础上，由于待驱动元件L在不工作的情况下会表现为电容器特性，因此，在第二阶段(P2～P3)和第四阶段(P4～P5)，第四晶体管T4、第五晶体管T5和第十晶体管T10均处于关闭状态，可以避免在对第一电容器C1和第二电容器C2充电的过程中，对待驱动元件L充电；进而可避免待驱动元件L对像素驱动电路的数据写入和阈值补偿产生影响。
在第一个行扫描阶段ts1结束之后，在第二个行扫描阶段ts2，对第二行亚像素区P中的像素驱动电路进行扫描，直至在第N个行扫描阶段tsN，对第N行亚像素区P中的像素驱动电路进行扫描。如图8所示，从第一个行扫描阶段ts1的结束时刻(P5)开始，在P5～P6时间段内，对位于第二行至第N行的亚像素区P中的像素驱动电路逐行进行扫描。
位于第二行至第N行的亚像素区P中的像素驱动电路在相应的行扫描阶段的驱动过程与位于第一行的亚像素区P中的像素驱动电路在第一个行扫描阶段ts1的驱动过程一致，在此不再赘述。也就是说，在整个扫描阶段(P1～P6)，上述的第一阶段～第四阶段的驱动过程需执行N次。
综上，在整个扫描阶段(P1～P6)，N个行扫描阶段中的每个行扫描阶段均包括上述的第一阶段～第四阶段，从而可向N行亚像素区P中的像素驱动电路写入第一数据信号和第二数据信号，并对第一数据信号和第二数据信号进行存储，为工作阶段(P6～P7)做好准备。
在一些示例中，在对N行亚像素区中的像素驱动电路逐行进行扫描后，各行亚像素区P中的像素驱动电路进入工作阶段(P6～P7)。
在工作阶段(P6～P7)，位于第一行的第一个亚像素区P的像素驱动电路的工作阶段包括如下过程：
参考图7和图8，驱动控制子电路10中，响应于接收到的来自使能信号端EM的使能信号，第四晶体管T4和第五晶体管T5开启。来自第一电源电压信号端S1的第一电源电压信号通过第四晶体管T4传输至驱动晶体管Td的第一极。此时，驱动晶体管Td的第一极的电压为第一电源电压信号的电压(记为V S1)。即，驱动晶体管Td的源极的电压为V S1。
根据电容器的电荷保持定律，第一电容器C1的第一极和第二极的电压差保持不变。因此，在第一电容器C1的第一极的电压保持为第一电源电压信号的电压V S1的情况下，第一电容器C1的第二极的电压仍为V data1+V thd。此时，驱动晶体管Td的栅极的电压仍保持为V data1+V thd。
在此情况下，驱动晶体管Td的栅源电压差V gs＝V data1+V thd-V S1。在驱动晶体管Td的栅源电压差V gs小于其阈值电压时开启，即：在V data1+V thd-V S1＜V thd时，驱动晶体管Td开启，并输出驱动电流，该驱动电流从驱动晶体管Td的第二极输出，经开启的第五晶体管T5传输至待驱动元件L。
流过驱动晶体管Td的驱动电流I＝K×(V gs-V thd) 2＝K×(V data1+V thd-V S1-V thd) 2＝K×(V data1-V S1) 2。K＝1/2×W/L×C×u，W/L为驱动晶体管Td的宽长比，C为沟道绝缘层电容，u为沟道载流子迁移率。
由此可知，上述参数只与驱动晶体管Td结构有关，因此，流过驱动晶体管Td的驱动电流只与来自第一数据信号端D1的第一数据信号的电压V data1和来自第一电源电压信号端S1的第一电源电压信号的电压V S1有关，与驱动晶体管Td的阈值电压V thd无关。
在此基础上，当各亚像素区P中的待驱动元件L进行不同灰阶的显示时，由于可向各亚像素区P中的像素驱动电路输入相同的第一电源电压信号，并且可将第一电源电压信号设置为固定的电平信号，因此，可以通过控制第一数据信号的电压V data1，来控制流过驱动晶体管Td的驱动电流的幅值。即，可以通过控制第一数据信号的电压V data1，来控制驱动晶体管Td输出至待驱动元件L的驱动信号的大小。
参考图7和图8，在时间控制子电路20中，响应于接收到的来自使能信号端EM的使能信号，第九晶体管T9和第十晶体管T10开启。来自第二电源电压信号端S2的第二电源电压信号通过开启的第九晶体管T9传输至第一晶 体管T1的第一极，使得第一晶体管T1的第一极的电压为第二电源电压信号的电压(记为V S2)。
由于公共电压信号的电压V V1在设定电压范围内变化，因此，与公共电压信号端V1连接的第二电容器C2的第二极的电压随公共电压信号的电压V V1变化。根据电容器的电荷保持定律，第二电容器C2的第一极和第二极的电压差保持不变。因此，与第二电容器C2的第一极连接的第二节点B的电压也随公共电压信号的电压V V1变化，且第二节点B的电压与公共电压信号的电压的变化速度相同。
在工作阶段(P6～P7)的初始时刻，公共电压信号的电压记为V V1(0)，第二节点B的电压记为V B(0)。在工作阶段(P6～P7)的t时刻，公共电压信号的电压记为V V1(t)，第二节点B的电压记为V B(t)。根据电容器的电荷保持定律，第二电容器C2的两极的电压差保持不变。因此，在工作阶段(P6～P7)的初始时刻和t时刻，第二节点B与公共电压信号端V1的电压差ΔV相等，即，ΔV＝V B(0)-V V1(0)＝V B(t)-V V1(t)。
在此基础上，由于在工作阶段(P6～P7)的初始时刻，即上述扫描阶段的第四阶段(P4～P5)，第二节点B的电压V B(0)＝V data2+V th1。因此，第二节点B与第一电压信号端V1的电压差ΔV＝V data2+V th1-V V1(0)＝V B(t)-V V1(t)。那么，在工作阶段(P6～P7)的t时刻，第二节点B的电压V B(t)＝V data2+V th1+V V1(t)-V V1(0)＝V data2+V th1+ΔV V1，这里，ΔV V1为公共电压信号的电压V V1在工作阶段(P6～P7)的初始时刻和t时刻的电压差值。
因此，在工作阶段(P6～P7)的t时刻，与第二节点B连接的第一晶体管T1的栅极的电压为V data2+V th1+ΔV V1。并且，第二节点B和第一晶体管T1的栅极的电压的变化速度由公共电压信号决定。
在此基础上，由于第一晶体管T1的第一极可以被理解为第一晶体管T1的第二极，即，这里，可将第一晶体管T1的第一极称为源极，则第一晶体管T1的源极电压为V S2。因此，在第一晶体管T1的栅源电压差大于其阈值电压时，第一晶体管T1开启，且在第一晶体管T1的栅源电压差等于其阈值电压时，第一晶体管T1处于开启与关闭的临界状态。即，第一晶体管T1的栅源电压差V gs1＝V data2+V th1+ΔV V1-V S2＝V th1。因此，当来自公共电压信号端V1的在设定电压范围内变化的公共电压信号的电压V V1在工作阶段(P6～P7)的初始时刻和t时刻的电压差ΔV V1＝V S2-V data2时，第一晶体管T1开启。由此可知，第一晶体管T1的开启与其阈值电压V th1无关。
由于第一晶体管T1的第二极连接到第九晶体管T9的第二极，第九晶体 管T9的第一极连接到第二电源电压信号端S2；第一晶体管T1的第一极连接到第十晶体管T10的第一极，第十晶体管T10的第二极连接到待驱动元件L的第二极；因此，第九晶体管T9的开启使得第一晶体管T1的第二极与第二电源电压信号端S2连接，第十晶体管T10的开启使得第一晶体管T1的第一极与待驱动元件L的第二极连接。来自第二电源电压信号端S2的第二电源电压信号通过开启的第九晶体管T9传输至第一晶体管T1，并通过开启的第十晶体管T10传输至待驱动元件L的第二极。
在工作阶段(P6～P7)的结束时刻，来自使能信号端EM的使能信号由低电平信号变为高电平信号，第四晶体管T4、第五晶体管T5、第九晶体管T9和第十晶体管T10由开启状态变为关闭状态，从而使驱动晶体管Td和第一晶体管T1与待驱动元件L断开，使待驱动元件L停止工作。
由于在来自第一电源电压信号端S1的第一电源电压信号传输至待驱动元件L的第一极，且来自第二电源电压信号端S2的第二电源电压信号传输至待驱动元件L的第二极时，待驱动元件L才会工作。因此，可以通过控制第一晶体管T1的开启时间，实现对待驱动元件L的工作时长的控制。
此外，对待驱动元件L的工作时长的控制，与待驱动元件L自身的开启电压无关，从而可以避免因显示面板中各待驱动元件L的开启电压不同导致显示亮度不均一而出现Mura现象。
当待驱动元件L进行不同灰阶的显示，且驱动控制子电路10向待驱动元件L提供的驱动信号保持不变时，可以通过控制来自第二数据信号端D2的第二数据信号的电压V data2不同，使得在工作阶段(P6～P7)的t时刻，第二节点B的电压V B(t)＝V data2+V th1+ΔV V1随着公共电压信号的电压V V1在工作阶段(P6～P7)的初始时刻和t时刻的电压差值ΔV V1＝V S2-V data2的大小也不同。因此，第二节点B的电压变化使第一晶体管T1开启的时刻不同，从而使来自第二电源电压信号端S2的第二电源电压信号传输至待驱动元件L的第二极的时刻不同，使得待驱动元件L的开启时间不同。这样，在驱动信号的大小维持在较高值范围内的情况下，可通过控制待驱动元件L的开启时间，使得待驱动元件L显示不同的灰阶，从而提高待驱动元件L的发光效率避免在较低电流密度下实现低灰阶显示时待驱动元件L发光效率较低、功耗较高的问题。
图8和图9分别示意了同一个亚像素区P的待驱动元件L在显示不同灰阶下的时序图。图8中的B(1)表示在一图像帧周期内第二节点B的信号时序，第二节点B的电压记为V B1，V B1随着公共电压信号的电压V V1按变化量ΔV B1变化，第二节点B的电压V B1＝V V1-ΔV B1。图9中的B(2)表示另一图像帧周期 内第二节点B的信号时序，第二节点B的电压记为V B2，V B2随着公共电压信号的电压V V1按变化量ΔV B2变化，第二节点B的电压V B2＝V V1-ΔV B2。在上述的一图像帧周期内和另一图像帧周期内，在来自第二数据信号端D2的第二数据信号的电压V data2不同的情况下，ΔV B2的值与ΔV B1的值也不同，相应地，第二节点B的电压也不相同。
在此情况下，若ΔV B2的值大于ΔV B1的值，则第二节点B的电压V B2变化至使第一晶体管T1开启的时间小于第二节点B的电压V B1变化至使第一晶体管T1开启的时间，从而使图9所示的一帧图像下的待驱动元件L相对于图8中的待驱动元件L较早开启，使得图9所示的一帧图像下的待驱动元件L的发光时长相对于另一帧图像下待驱动元件L较长。
需要说明的是，对于不同的亚像素区P中的像素驱动电路在同一图像帧下，或者不同的亚像素区P中的像素驱动电路在不同图像帧下，第二节点B的信号时序和待驱动元件L的发光情况也可以参考图8和图9，在此不再赘述。
由此，可以在驱动控制子电路10和时间控制子电路20的共同作用下，即，通过驱动控制子电路10控制传输至待驱动元件L的驱动电流的幅值，通过时间控制子电路20控制待驱动元件L的工作时长，实现待驱动元件L不同灰阶的显示。并且，在驱动电流的幅值维持在较高值范围内的情况下，可通过缩短待驱动元件L的工作时长，来使待驱动元件L进行低灰阶显示，以提高待驱动元件L的发光效率，避免在较低电流下待驱动元件L发光效率较低、功耗较高的问题，从而提高显示面板的显示效果。
需要说明的是，对于第二行至第N行的亚像素区中的像素驱动电路在工作阶段(P6～P7)的驱动过程，可参见上述对第一行的亚像素区P中的像素驱动电路在工作阶段(P6～P7)的驱动过程的描述。
综上所述，一个帧周期内，在扫描阶段(P1～P6)，第一数据信号和第二数据信号被写入各像素驱动电路的每个中，在工作阶段(P6～P7)，各像素驱动电路输出驱动信号，并控制第二电源电压信号传输至待驱动元件L的时间。这样，实现了对待驱动元件L的发光亮度的控制。在此基础上，通过控制输入待驱动元件L的驱动电流的幅值以及发光时长，改变待驱动元件L的发光强度，实现了不同灰阶的显示。示例的，通过增大传输至待驱动元件L的驱动信号的强度，并控制待驱动元件L的发光时长为较长发光时长，可实现较高灰阶显示。又示例的，通过控制待驱动元件L的开启时间，即，通过控制第二电源电压信号传输至待驱动元件L的时长，可实现低灰阶显示。这样，待驱动元件L可以在较稳定的电流密度范围下工作，，避免了待驱动元件L 在低电流密度下发光不稳定的问题，提高了待驱动元件L的发光效率，降低了显示面板的功耗。
在另一些实施例中，如图10所示，除了驱动晶体管Td、第七晶体管T7、第八晶体管T8和第十一晶体管T11均为N型晶体管之外，其余各个晶体管均为P型晶体管。
在此基础上，来自第一电源电压信号端S1的第一电源电压信号为低电平信号，来自第二电源电压信号端S2的第二电源电压信号为高电平信号，待驱动元件L的第一极为阴极，第二极为阳极。
需要说明的是，图10所示的像素驱动电路在不同阶段的工作情况与上述图7所示的像素驱动电路在不同阶段的工作情况相同，且具有相同的技术效果，在此不再赘述。
本公开一些实施例提供一种像素驱动电路的驱动方法，如图8所示，一个帧周期包括扫描阶段(P1～P6)和工作阶段(P6～P7)。扫描阶段(P1～P6)包括多个行扫描阶段(ts1～tsN)。每个行扫描阶段包括S10～S20，工作阶段包括S30～S40。
参考图2和图8，该驱动方法如下所述。
S10、驱动控制子电路10响应于接收到的来自第一扫描信号端G1的第一扫描信号，至少将来自第一数据信号端D1的第一数据信号写入第一驱动子电路101。
S20、时间控制子电路20来自第二扫描信号端G2的第二扫描信号，至少将来自第二数据信号端D2的第二数据信号写入第二驱动子电路。
S30、驱动控制子电路10响应于接收到的来自使能信号端EM的使能信号，使驱动晶体管Td根据来自第一数据信号端D1的第一数据信号和来自第一电源电压信号端S1的第一电源电压信号，向待驱动元件L的第一极输出驱动信号。
S40、时间控制子电路20响应于接收到的来自使能信号端EM的使能信号，使第二驱动子电路201与第二电源电压信号端S2和待驱动元件L的第二极连接。第二驱动子电路201响应于来自第二数据信号端D2的第二数据信号和来自公共电压信号端V1的电压在设定电压范围内变化的公共电压信号，向待驱动元件L的第二极输出来自第二电源电压信号端S2的第二电源电压信号，以使待驱动元件L响应于接收到的驱动信号和第二电源电压信号，开始工作。
在一些实施例中，参考图4和图5，驱动控制子电路10包括第一驱动子 电路101、第一数据写入子电路102、以及第一控制子电路103。
参考图4、图5以及图8，上述S10包括S101，上述S30包括S301。
S101、第一数据写入子电路102响应于接收到的来自第一扫描信号端G1的第一扫描信号，将来自第一数据信号端D1的第一数据信号和驱动晶体管Td的阈值电压写入第一节点A，以对驱动晶体管Td进行阈值电压补偿。
S301、第一控制子电路103响应于接收到的来自使能信号端EM的使能信号，使驱动晶体管Td与第一电源电压信号端S1和待驱动元件L的第一极连接，以使驱动晶体管Td根据来自第一数据信号端D1的第一数据信号和来自第一电源电压信号端S1的第一电压信号，向待驱动元件L的第一极输出驱动信号。
在一些实施例中，参考图4和图5，时间控制子电路20包括第二驱动子电路201、第二数据写入子电路202、以及第二控制子电路203。
参考图4、图5以及图8，上述S20包括S201，上述S40包括S401。
S201、第二数据写入子电路202响应于接收到的来自第二扫描信号端G2的第二扫描信号，将来自第二数据信号端D2的第二数据信号和第二驱动子电路201中的第一晶体管T1的阈值电压写入第二节点B，以对第一晶体管T1进行阈值补偿。
S401：第二控制子电路203响应于接收到的来自使能信号端EM的使能信号，使第一晶体管T1与第二电源电压信号端S2和待驱动元件L的第二极连接，以使第一晶体管T1响应于来自公共电压信号端V1的电压在设定电压范围内变化的公共电压信号和来自第二数据信号端D2的第二数据信号开启，并将来自第二电源电压信号端S2的第二电源电压信号传输至待驱动元件L的第二极。
上述的像素驱动电路的驱动方法具有与上述的像素驱动电路相同的有益效果，在此不再赘述。
在一些实施例中，参考图6和图7，驱动控制子电路10还包括第一复位子电路104。
在多个行扫描阶段中的每个行扫描阶段，参考图6-图8，上述S10还包括S102。
S102、第一复位子电路104响应于接收到的来自第一复位信号端RST1的第一复位信号，将来自第一初始信号端INI1的第一初始信号传输至第一节点A，对第一节点A进行复位。
示例的，如图7和图8所示，第一复位子电路104包括第六晶体管T6。 第一复位子电路104响应于接收到的来自第一复位信号端RST1的第一复位信号，第六晶体管T6开启，将来自第一初始信号端INI1的第一初始信号传输至第一节点A，对第一节点A进行复位。此时，第一节点A的电压为第一初始信号的电压V init1。在此情况下，与第一节点A连接的第一电容器C1的第二极以及驱动晶体管Td的栅极也均被复位。
在一些实施例中，如图6和图7所示，时间控制子电路20还包括第二复位子电路204。
在多个行扫描阶段中的每个行扫描阶段，参考图6和图8，上述S20还包括S202。
S202、第二复位子电路204响应于接收到的来自第二复位信号端RST2的第二复位信号，将来自第二初始信号端INI2的第二初始信号传输至第二节点B，对第二节点B进行复位。
示例的，如图7和图8所示，第二复位子电路204包括第十一晶体管T11。第二复位子电路204响应于接收到的来自第二复位信号端RST2的第二复位信号，第十一晶体管T11开启，将来自第二初始信号端INI2的第二初始信号传输至第二节点B，对第二节点B进行复位。此时，第二节点B的电压为第二初始信号的电压V init2。在此情况下，与第二节点B连接的第二电容器C2的第一极、以及第一晶体管T1的栅极也均被复位。
在每个行扫描阶段，通过第一复位子电路104对第一驱动子电路101的电压进行复位，通过第二复位子电路204对第二驱动子电路201的电压进行复位，实现了对第一驱动子电路101和第二驱动子电路201的降噪，从而避免对后续驱动过程中写入的第一数据信号和第二数据信号造成影响。
在上述基础上，在一些实施例中，参考图1，该显示面板还包括多条第一扫描信号线G1(1)～G1(N)、多条第一数据信号线D1(1)～D1(M)、多条第二扫描信号线G2(1)～G2(N)、多条第二数据信号线D2(1)～D2(M)、多条使能信号线E(1)～E(N)、多条第一电源电压信号线L S1、多条第二电源电压信号线L S2以及多条公共电压信号线L V1。该第一扫描信号线被配置为向像素驱动电路提供第一扫描信号。该第二扫描信号线被配置为向像素驱动电路提供第二扫描信号。该使能信号线被配置为向像素驱动电路提供使能信号。该第一数据信号线被配置为向像素驱动电路提供第一数据信号。该第二数据信号线被配置为向像素驱动电路提供第二数据信号。该第一电源电压信号线被配置为向像素驱动电路提供第一电源电压信号。该第二电源电压信号线被配置为向像素驱动电路提供第二电源电压信号。该公共电压信号线被配置为向像素驱动电路提供 公共电压信号。
在一些示例中，位于同一行亚像素区P中的各像素驱动电路连接到多条第一扫描信号线G1(1)～G1(N)中的同一条第一扫描信号线、多条第二扫描信号线G2(1)～G2(N)中的同一条第二扫描信号线、多条使能信号线E(1)～E(N)中的同一条使能信号线。位于同一列亚像素区P中的各像素驱动电路连接到多条第一数据信号线D1(1)～D1(M)中的同一条第一数据信号线、多条第二数据信号线D2(1)～D2(M)中的同一条第二数据信号线、多条第一电源电压信号线L S1中的同一条第一电源电压信号线、多条第二电源电压信号线L S2中的同一条第二电源电压信号线以及多条公共电压信号线L V1中的同一条公共电压信号线。
示例的，如图1所示，位于第一行亚像素区P中的各像素驱动电路连接到第一扫描信号线G1(1)、第二扫描信号线G2(1)、以及使能信号线E(1)。位于第二行亚像素区P中的各像素驱动电路连接到第一扫描信号线G1(2)、第二扫描信号线G2(2)、以及使能信号线E(2)。位于第N行亚像素区P中的各像素驱动电路连接到第一扫描信号线G1(N)、第二扫描信号线G2(N)、以及使能信号线E(N)。位于第一列亚像素区P中的各像素驱动电路连接到第一数据信号线D1(1)、第二数据信号线D2(1)、第一电源电压信号线L S1、第二电源电压信号线L S2以及公共电压信号线L V1。位于第二列亚像素区P中的各像素驱动电路连接到第一数据信号线D1(2)、第二数据信号线D2(2)、第一电源电压信号线L S1、第二电源电压信号线L S2以及公共电压信号线L V1。位于第M列亚像素区P中的各像素驱动电路连接到第一数据信号线D1(M)、第二数据信号线D2(M)、第一电源电压信号线L S1、第二电源电压信号线L S2以及公共电压信号线L V1。
在此基础上，第一扫描信号端G1可以理解为：第一扫描信号线与像素驱动电路连接后等效的连接点。第二扫描信号端G2同理。第一数据信号端D1可以理解为：第一数据信号线与像素驱动电路连接后等效的连接点。第二数据信号端D2同理。使能信号端EM可以理解为：使能信号线与像素驱动电路连接后等效的连接点。第一电源电压信号端S1可以理解为：第一电源电压信号线L S1与像素驱动电路连接后等效的连接点。第二电源电压信号端S2可以理解为：第二电压信号线L S2与像素驱动电路连接后等效的连接点。公共电压信号端V1可以理解为：公共电压信号线L V1与像素驱动电路连接后等效的连接点。
需要说明的是，本领域技术人员可以根据显示面板的空间结构，设置第一电源电压信号线L S1、第二电源电压信号线L S2以及公共电压信号线L V1与 各亚像素区P中的各像素驱动电路的连接方式。图1以位于任意两列亚像素区P中的像素驱动电路连接到不同的第一电源电压信号线L S1、第二电源电压信号线L S2以及公共电压信号线L V1进行示意，但本公开实施例并不限于此，也可以是位于多列(例如2列或3列或4列)亚像素区P中的像素驱动电路连接到同一条第一电源电压信号线L S1、第二电源电压信号线L S2以及公共电压信号线L V1。
在一些实施例中，如图1所示，显示面板还包括多条第一复位信号线R1(1)～R1(N)以及多条第一初始信号线(图1中未示出)。该第一复位信号线被配置为向像素驱动电路提供第一复位信号。该第一初始信号线被配置为向像素驱动电路提供第一初始信号。
在一些示例中，位于同一行亚像素区P中的各像素驱动电路连接到多条第一复位信号线R1(1)～R1(N)中的同一条第一复位信号线，位于同一列亚像素区P中的各像素驱动电路连接到多条第一初始信号线中的同一条第一初始信号线。
示例的，如图1所示，位于第一行亚像素区P中的各像素驱动电路连接到第一复位信号线R1(1)。位于第二行亚像素区P中的各像素驱动电路连接到第一复位信号线R1(2)。位于第N行亚像素区P中的各像素驱动电路连接到第一复位信号线R1(N)。
第一复位信号端RST1可以理解为：第一复位信号线与像素驱动电路连接后等效的连接点。第一初始信号端INI1可以理解为：第一初始信号线与像素驱动电路连接后等效的连接点。
在一些实施例中，如图1所示，显示面板还包括多条第二复位信号线R2(1)～R2(N)以及多条第二初始信号线(图1中未示出)。该第二复位信号线被配置为向像素驱动电路提供第二复位信号。该第二初始信号线被配置为向像素驱动电路提供第二初始信号。
在一些示例中，位于同一行亚像素区P中的各像素驱动电路连接到多条第二复位信号线R2(1)～R2(N)中的同一条第二复位信号线，位于同一列亚像素区P中的各像素驱动电路连接到多条第二初始信号线中的同一条第二初始信号线。
示例的，如图1所示，位于第一行亚像素区P中的各像素驱动电路连接到第二复位信号线R2(1)。位于第二行亚像素区P中的各像素驱动电路连接到第二复位信号线R2(2)。位于第N行亚像素区P中的各像素驱动电路连接到第二复位信号线R2(N)。
第二复位信号端RST2可以理解为：第二复位信号线与像素驱动电路连接后等效的连接点。第二初始信号端INI2可以理解为：第二初始信号线与像素驱动电路连接后等效的连接点。
需要说明的是，以上实施例所述的显示面板所包括的多条信号线的排布，以及图1示出的显示面板的布线图仅是一些示例，本公开实施例不限于此。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种像素驱动电路，包括：
    驱动控制子电路，至少连接到第一扫描信号端、第一数据信号端、第一电源电压信号端、使能信号端以及待驱动元件的第一极；所述驱动控制子电路包括第一驱动子电路，所述第一驱动子电路包括驱动晶体管；所述驱动控制子电路被配置为响应于接收到的来自所述第一扫描信号端的第一扫描信号，至少将来自所述第一数据信号端的第一数据信号写入所述第一驱动子电路；以及响应于接收到的来自所述使能信号端的使能信号，使所述驱动晶体管根据所述第一数据信号和来自所述第一电源电压信号端的第一电源电压信号，向所述待驱动元件的第一极输出驱动信号；
    时间控制子电路，至少连接到第二扫描信号端、第二数据信号端、第二电源电压信号端、使能信号端、公共电压信号端以及所述待驱动元件的第二极；所述时间控制子电路包括第二驱动子电路；所述时间控制子电路被配置为响应于接收到的来自所述第二扫描信号端的第二扫描信号，至少将来自所述第二数据信号端的第二数据信号写入所述第二驱动子电路；以及响应于接收到的来自所述使能信号端的使能信号，使所述第二驱动子电路与所述第二电源电压信号端和所述待驱动元件的第二极连接；所述第二驱动子电路被配置为响应于所述第二数据信号和来自所述公共电压信号端的电压在设定电压范围内变化的公共电压信号，向所述待驱动元件的第二极输出来自所述第二电源电压信号端的第二电源电压信号，以使所述待驱动元件响应于接收到的所述驱动信号和所述第二电源电压信号，开始工作。
  2. 根据权利要求1所述的像素驱动电路，其中，所述第一驱动子电路还包括第一电容器；所述第一电容器的第一极连接到所述第一电源电压信号端，所述第一电容器的第二极连接到第一节点；所述驱动晶体管的栅极连接到所述第一节点。
  3. 根据权利要求2所述的像素驱动电路，其中，所述驱动控制子电路还包括第一数据写入子电路以及第一控制子电路；
    所述第一数据写入子电路连接到所述第一扫描信号端、所述第一数据信号端、所述第一节点以及所述驱动晶体管；所述第一数据写入子电路被配置为响应于接收到的所述第一扫描信号，将所述第一数据信号和所述驱动晶体管的阈值电压写入所述第一节点；
    所述第一控制子电路连接到所述使能信号端、所述第一电源电压信号端、所述驱动晶体管以及所述待驱动元件的第一极；所述第一控制子电路被配置为响应于接收到的所述使能信号，使所述驱动晶体管与所述第一电源电压信 号端和所述待驱动元件的第一极连接。
  4. 根据权利要求3所述的像素驱动电路，其中，所述第一数据写入子电路包括第二晶体管和第三晶体管；
    所述第二晶体管的栅极连接到所述第一扫描信号端，所述第二晶体管的第一极连接到所述驱动晶体管的第二极，所述第二晶体管的第二极连接到所述第一节点；
    所述第三晶体管的栅极连接到所述第一扫描信号端，所述第三晶体管的第一极连接到所述第一数据信号端，所述第三晶体管的第二极连接到所述驱动晶体管的第一极。
  5. 根据权利要求3或4所述的像素驱动电路，其中，所述第一控制子电路包括第四晶体管和第五晶体管；
    所述第四晶体管的栅极连接到所述使能信号端，所述第四晶体管的第一极连接到所述第一电源电压信号端，所述第四晶体管的第二极连接到所述驱动晶体管的第一极；
    所述第五晶体管的栅极连接到所述使能信号端，所述第五晶体管的第一极连接到所述驱动晶体管的第二极，所述第五晶体管的第二极连接到所述待驱动元件的第一极。
  6. 根据权利要求1-5任一项所述的像素驱动电路，其中，所述驱动控制子电路还包括第一复位子电路；
    所述第一复位子电路连接到第一初始信号端、第一复位信号端以及所述驱动晶体管的栅极；所述第一复位子电路被配置为响应于接收到的来自所述第一复位信号端的第一复位信号，将来自所述第一初始信号端的第一初始信号传输至所述驱动晶体管的栅极，对所述驱动晶体管的栅极进行复位。
  7. 根据权利要求6所述的像素驱动电路，其中，所述第一复位子电路包括第六晶体管；
    所述第六晶体管的栅极连接到所述第一复位信号端，所述第六晶体管的第一极连接到所述第一初始信号端，所述第六晶体管的第二极连接到所述驱动晶体管的栅极。
  8. 根据权利要求1-7任一项所述的像素驱动电路，其中，所述第二驱动子电路包括第一晶体管和第二电容器；所述第二电容器的第一极连接到第二节点，所述第二电容器的第二极连接到所述公共电压信号端；所述第一晶体管的栅极连接到所述第二节点；所述第一晶体管被配置为响应于来自公共电压信号端的电压在设定电压范围内变化的公共电压信号和所述第二数据信 号，向所述待驱动元件的第二极输出所述第二电源电压信号。
  9. 根据权利要求8所述的像素驱动电路，其中，所述时间控制子电路还包括第二数据写入子电路以及第二控制子电路；
    所述第二数据写入子电路连接到所述第二扫描信号端、所述第二数据信号端、所述第二节点以及所述第一晶体管的第一极和第二极；所述第二数据写入子电路被配置为响应于接收到的所述第二扫描信号，将所述第二数据信号和所述第一晶体管的阈值电压写入所述第二节点；
    所述第二控制子电路连接到所述使能信号端、所述第二电源电压信号端、所述第一晶体管的第一极和第二极、以及所述待驱动元件的第二极；所述第二控制子电路被配置为响应于接收到的所述使能信号，使所述第一晶体管与所述第二电源电压信号端和所述待驱动元件的第二极连接。
  10. 根据权利要求9所述的像素驱动电路，其中，所述第二数据写入子电路包括第七晶体管和第八晶体管；
    所述第七晶体管的栅极连接到所述第二扫描信号端，所述第七晶体管的第一极连接到所述第一晶体管的第一极，所述第七晶体管的第二极连接到所述第二数据信号端电连接；
    所述第八晶体管的栅极连接到所述第二扫描信号端，所述第八晶体管的第一极连接到所述第一晶体管的第二极，所述第八晶体管的第二极连接到所述第二节点；和/或
    所述第二控制子电路包括第九晶体管和第十晶体管；
    所述第九晶体管的栅极连接到所述使能信号端，所述第九晶体管的第一极连接到所述第二电源电压信号端，所述第九晶体管的第二极连接到所述第一晶体管的第一极；
    所述第十晶体管的栅极连接到所述使能信号端，所述第十晶体管的第一极连接到所述待驱动元件的第二极，所述第十晶体管的第二极连接到所述第一晶体管的第二极。
  11. 根据权利要求10所述的像素驱动电路，其中，所述第一晶体管为N型晶体管，所述驱动晶体管为P型晶体管；或者，所述第一晶体管为P型晶体管，所述驱动晶体管为N型晶体管。
  12. 根据权利要求9-11任一所述的像素驱动电路，其中，所述时间控制子电路还包括第二复位子电路；
    所述第二复位子电路连接到第二初始信号端、第二复位信号端以及所述第二节点；所述第二复位子电路被配置为响应于接收到的来自所述第二复位 信号端的第二复位信号，将来自所述第二初始信号端的第二初始信号传输至所述第二节点，对所述第二节点进行复位。
  13. 根据权利要求12所述的像素驱动电路，其中，所述第二复位子电路包括第十一晶体管；
    所述第十一晶体管的栅极连接到所述第二复位信号端，所述第十一晶体管的第一极连接到所述第二初始信号端，所述第十一晶体管的第二极连接到所述第二节点。
  14. 一种显示面板，包括：
    多个如权利要求1-13任一项所述的像素驱动电路；以及
    多个待驱动元件，多个待驱动元件中的一个与对应的一个像素驱动电路连接。
  15. 根据权利要求14所述的显示面板，其中，所述显示面板具有多个亚像素区，每个像素驱动电路设置于一个亚像素区中；
    所述显示面板还包括：
    多条第一扫描信号线，位于同一行亚像素区中的各像素驱动电路连接的第一扫描信号端与对应的一条第一扫描信号线连接；
    多条第一数据信号线，位于同一列亚像素区中的各像素驱动电路连接的第一数据信号端与对应的一条第一数据信号线连接；
    多条第二扫描信号线，位于同一行亚像素区中的各像素驱动电路连接的第二扫描信号端与对应的一条第二扫描信号线连接；以及
    多条第二数据信号线，位于同一列亚像素区中的各像素驱动电路连接的第二数据信号端与对应的一条第二数据信号线连接。
  16. 根据权利要求14所述的显示面板，其中，所述待驱动元件为电流型发光二极管。
  17. 一种显示装置，包括如权利要求14-16任一项所述的显示面板。
  18. 一种如权利要求1-13任一项所述的像素驱动电路的驱动方法，一个帧周期包括扫描阶段和工作阶段，所述扫描阶段包括多个行扫描阶段；
    所述驱动方法，包括：
    在所述多个行扫描阶阶段中的每个行扫描阶阶段：
    所述驱动控制子电路响应于接收到的来自所述第一扫描信号端的第一扫描信号，至少将来自所述第一数据信号端的第一数据信号写入所述第一驱动子电路；
    所述时间控制子电路响应于接收到的来自所述第二扫描信号端的第二扫 描信号，至少将来自所述第二数据信号端的第二数据信号写入所述第二驱动子电路；
    在所述工作阶段：
    所述驱动控制子电路响应于接收到的来自所述使能信号端的使能信号，使所述第一驱动子电路中的驱动晶体管根据所述第一数据信号和来自所述第一电源电压信号端的第一电源电压信号，向所述待驱动元件的第一极输出驱动信号；
    所述时间控制子电路响应于接收到的来自所述使能信号端的使能信号，使所述第二驱动子电路与所述第二电源电压信号端和所述待驱动元件的第二极连接；所述第二驱动子电路响应于所述第二数据信号和来自所述公共电压信号端的电压在设定电压范围内变化的公共电压信号，向所述待驱动元件的第二极输出来自所述第二电源电压信号端的第二电源电压信号，以使所述待驱动元件响应于接收到的所述驱动信号和所述第二电源电压信号，开始工作。
  19. 根据权利要求18所述的像素驱动电路的驱动方法，其中，所述驱动控制子电路还包括第一数据写入子电路以及第一控制子电路；
    在所述多个行扫描阶段中的每个行扫描阶段，所述驱动控制子电路响应于接收到的所述第一扫描信号，至少将来自所述第一数据信号写入所述第一驱动子电路；在所述工作阶段，所述驱动控制子电路响应于接收到的所述使能信号，使所述第一驱动子电路中的驱动晶体管根据所述第一数据信号和所述第一电源电压信号，向所述待驱动元件的第一极输出驱动信号，包括：
    在所述多个行扫描阶段中的每个行扫描阶阶段：
    所述第一数据写入子电路响应于接收到的所述第一扫描信号，将所述第一数据信号和所述驱动晶体管的阈值电压写入第一节点；
    在所述工作阶段：
    所述第一控制子电路响应于接收到的所述使能信号，使所述驱动晶体管与所述第一电源电压信号端和所述待驱动元件的第一极连接，以使所述驱动晶体管根据所述第一数据信号和所述第一电源电压信号，向所述待驱动元件的第一极输出驱动信号。
  20. 根据权利要求18或19所述的像素驱动电路的驱动方法，其中，所述时间控制子电路还包括第二数据写入子电路以及第二控制子电路；
    在所述多个行扫描阶段中的每个行扫描阶阶段，所述时间控制子电路响应于接收到的所述第二扫描信号，至少将所述第二数据信号写入所述第二驱动子电路；在所述工作阶段，所述时间控制子电路响应于接收到的所述使能 信号，使所述第二驱动子电路与所述第二电源电压信号端和所述待驱动元件的第二极连接，包括：
    在所述多个行扫描阶阶段中的每个行扫描阶阶段：
    所述第二数据写入子电路响应于接收到的所述第二扫描信号，将所述第二数据信号和所述第一晶体管的阈值电压写入第二节点；
    在所述工作阶段：
    所述第二控制子电路响应于接收到的所述使能信号，使所述第一晶体管与所述第二电源电压信号端和所述待驱动元件的第二极连接。
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