WO2021082989A1 - 显示基板及其制作方法、显示装置 - Google Patents
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- WO2021082989A1 WO2021082989A1 PCT/CN2020/122238 CN2020122238W WO2021082989A1 WO 2021082989 A1 WO2021082989 A1 WO 2021082989A1 CN 2020122238 W CN2020122238 W CN 2020122238W WO 2021082989 A1 WO2021082989 A1 WO 2021082989A1
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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- H10K59/1201—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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- H10K59/10—OLED displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
- H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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- H10K59/80—Constructional details
- H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
- H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/861—Repairing
Definitions
- the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device.
- OLED Organic Light Emitting Diode
- PM passive matrix
- AM active matrix
- AMOLED is a current-driven device that uses independent thin film transistors (Thin Film Transistor (TFT) controls each sub-pixel, and each sub-pixel can continuously and independently drive to emit light.
- TFT Thin Film Transistor
- the display area of the OLED display substrate includes: horizontally and vertically staggered gate lines and data lines.
- gate lines are made in the same layer of the gate electrode layer in the display area
- data lines are made in the same layer of the source and drain metal layers in the display area, so that In the display area, there is a large area where the gate line and the data line overlap.
- an embodiment of the present disclosure provides a display substrate including: a substrate, a gate line, a data line, a power connection line, and a plurality of sub-pixels defined by the intersection of the gate line and the data line provided on the substrate, each sub-pixel
- the pixel includes a driving circuit; the driving circuit includes a plurality of transistors and a storage capacitor, the display substrate has defective points formed by short-circuiting gate lines and data lines, and the gate lines forming the defective points are defective gate lines; forming The data line at the defective point is a defective data line; a plurality of transistors include: a switching transistor, a driving transistor, and a sensing transistor.
- the first electrode of the storage capacitor is respectively connected to the second electrode of the switching transistor and the gate electrode of the driving transistor, so The second electrode of the storage capacitor is respectively connected to the second electrode of the driving transistor and the second electrode of the sensing transistor;
- the first electrode of the driving transistor is connected to the power connection line;
- the power connection line is arranged in the same layer as the gate electrodes of the plurality of transistors;
- the defective gate line is connected to the first repair sub-pixel and the second repair sub-pixel, respectively.
- the gate electrode of the switching transistor in the pixel is connected; wherein, the first repair sub-pixel and the second repair sub-pixel are respectively located on both sides of the bad data line, and the power connection line connected to the first repair sub-pixel and the second repair sub-pixel is bad Power connection line;
- the display substrate further includes: a side of the source and drain electrodes of the plurality of transistors away from the substrate
- the repair line is respectively connected with the partially disconnected defective grid line and the partially disconnected defective power connection line, and is used to transmit scanning signals to repair the display substrate.
- the bad gate line includes: a first scanning part, a second scanning part, and a third scanning part that are arranged along the extending direction of the gate line and are disconnected from each other, wherein the second scanning Section is located between the first scanning section and the third scanning section;
- the first scanning part is located close to the first repair sub-pixel on the bad data line.
- the gate electrode of the switching transistor in the sub-pixel on one side is connected; the third scanning part is connected to the gate electrode of the switching transistor in the sub-pixel on the side of the bad data line close to the second repaired sub-pixel;
- the repair line is respectively connected with the first scanning part and the third scanning part.
- the poor power connection line includes a first connection part, a second connection part, and a third connection part that are arranged along the extending direction of the gate line and are disconnected from each other; wherein, the second connection ⁇ is located between the first connecting portion and the third connecting portion;
- the orthographic projection of the first connecting portion on the substrate has an overlapping area with the first electrode of the driving transistor in the first repair sub-pixel, and is connected to the first electrode of the driving transistor in the first repair sub-pixel.
- the orthographic projection of the three connecting parts on the substrate has an overlapping area with the first electrode of the driving transistor in the second repair sub-pixel, and is connected to the first electrode of the driving transistor in the second repair sub-pixel, the second connecting part There is an overlap area between the orthographic projection on the substrate and the second pole of the switching transistor in the first repair sub-pixel and the second repair sub-pixel, and the second connection part is connected to the repair line.
- the repair line includes: a first repair part and a second repair part;
- the first repairing part is respectively connected with the first scanning part and the second connecting part; the second repairing part is respectively connected with the third scanning part and the second connecting part.
- the material of the first repair part and the second repair part includes tungsten.
- both the first repair sub-pixel and the second repair sub-pixel include: a first groove and a second groove;
- the first groove penetrates the active layer of the switching transistor in the sub-pixel where the first groove is located, and the orthographic projection of the first groove on the substrate is located in the sub-pixel where the first groove is located Between the orthographic projection of the first electrode of the switching transistor on the substrate and the orthographic projection of the gate electrode of the switching transistor on the substrate in the sub-pixel where the first groove is located;
- the second groove penetrates the second pole of the switching transistor in the sub-pixel where the second groove is located, and the orthographic projection of the second groove on the substrate is located on the orthographic projection of the power connection line on the substrate and The gate electrode of the driving transistor of the sub-pixel where the second groove is located is between the orthographic projections on the substrate.
- both the first repair sub-pixel and the second repair sub-pixel further include: a first via hole and a second via hole;
- the first via hole in the first repair sub-pixel is used to expose the first scanning portion
- the first via hole in the second repair sub-pixel is used to expose the third scanning portion
- the second via hole is used to expose the first scanning portion.
- the first repairing portion is connected to the first scanning portion through a first via hole in the first repairing sub-pixel, and the first repairing portion is connected to the first scanning portion through a second via in the first repairing sub-pixel.
- the hole is connected to the second connecting portion; the second repairing portion is connected to the third scanning portion through the first via hole in the second repairing sub-pixel; the second repairing portion is connected to the third scanning portion through the second repairing sub-pixel
- the hole is connected with the second connecting part.
- the storage capacitor is a transparent capacitor
- the first electrode of the storage capacitor is arranged on the same layer as the active layer of the plurality of transistors
- the second electrode of the storage capacitor is arranged on the same layer of the active layer of the plurality of transistors. The side of the source and drain electrodes away from the substrate;
- the second electrode is made of a transparent conductive material, and the first electrode is made of the same material as the active layer of the plurality of transistors.
- each sub-pixel includes: a storage capacitor area provided with a storage capacitor and a non-storage capacitor area provided with a plurality of transistors;
- the non-storage capacitor area includes: a first non-storage capacitor area and a second non-storage capacitor area; the first non-storage capacitor area and the second non-storage capacitor area are respectively located on both sides of the storage capacitor area, and the switch transistor And the driving transistor is located in the first non-storage capacitor area, and the sensing transistor is located in the second non-storage capacitor area.
- the gate electrode of the switching transistor is connected to the gate line of the i-th row
- the gate electrode of the sensing transistor is connected to the gate line of the i+1-th row
- the gate line of the i-th row and the gate line of the (i+1)th row are respectively located on both sides of the storage capacitor area of the i-th row of sub-pixels.
- the display substrate further includes: power lines, sensing lines, and data lines arranged in the same layer as the source and drain electrodes of the plurality of transistors.
- the first electrode of the driving transistor is connected to the The power connection line is connected to the power line, and the first pole of the sensing transistor is connected to the sensing line;
- Each pixel includes four sub-pixels, each pixel is connected to four columns of data lines, one column of power lines, and two sensing lines, each sub-pixel corresponds to one column of data lines, and each pixel corresponds to one column of power lines and two columns of sensing line;
- the four sub-pixels are arranged in sequence along the extending direction of the gate line, the power line corresponding to each pixel is arranged between the second sub-pixel and the third sub-pixel, and the first column of sensing lines is arranged in the first sub-pixel away from the second sub-pixel.
- the second column of sensing lines is arranged on the side of the fourth sub-pixel away from the third sub-pixel;
- the data line corresponding to the first sub-pixel is located at a side of the first sub-pixel close to the second sub-pixel, and the data line corresponding to the second sub-pixel is located at a side of the second sub-pixel close to the first sub-pixel.
- Side the data line corresponding to the third sub-pixel is located on the side of the third sub-pixel close to the fourth sub-pixel, and the data line corresponding to the fourth sub-pixel is located in the fourth sub-pixel close to the third sub-pixel On the side.
- the display substrate further includes: a buffer layer and a light shielding layer disposed on a side of the active layer of the plurality of transistors close to the base; and a sensing connection line connected to the sensing line;
- the light-shielding layer is arranged on the side of the buffer layer close to the substrate, the sensing connection line and the light-shielding layer are arranged in the same layer, and the orthographic projection of the light-shielding layer on the substrate covers the effective of the active layer of the driving transistor. area;
- the first pole of the sensing transistor is connected to the sensing line through the sensing connection line.
- the display substrate further includes: a gate insulating layer provided between the active layers of the plurality of transistors and the gate electrodes of the plurality of transistors, and an active layer provided between the plurality of transistors and a plurality of The interlayer insulating layer between the source and drain electrodes of the transistor;
- the orthographic projection of the gate insulating layer on the substrate coincides with the orthographic projection of the gate electrodes of the plurality of transistors on the substrate, and the first via is provided on the interlayer insulating layer.
- embodiments of the present disclosure also provide a display device, including the above-mentioned display substrate.
- the embodiments of the present disclosure also provide a manufacturing method of a display substrate for manufacturing the above-mentioned display substrate, and the method includes:
- a gate line, a data line, a power connection line, and a plurality of sub-pixels defined by the intersection of the gate line and the data line are formed on the substrate; wherein each sub-pixel includes a driving circuit; the driving circuit includes: a plurality of transistors and storage capacitors; and A transistor includes: a switching transistor, a driving transistor, and a sensing transistor; the first electrode of the storage capacitor is connected to the second electrode of the switching transistor and the gate electrode of the driving transistor, and the second electrode of the storage capacitor is connected to the driving transistor.
- the second electrode of the driver transistor is connected to the second electrode of the sensing transistor, and for each sub-pixel, the first electrode of the driving transistor is connected to the power supply connection line; the power supply connection line is arranged in the same layer with the gate electrodes of the plurality of transistors;
- the gate lines forming the defective points are defective gate lines
- the data lines forming the defective points are defective data lines
- the first repair sub-pixel and the second repair sub-pixel They are respectively located on both sides of the bad data line and connected to the bad gate line
- the power connection lines connected to the first repair sub-pixel and the second repair sub-pixel are the bad power connection lines
- the defective gate line and the defective power connection line are disconnected, and a repair line is formed in the first repair sub-pixel and the second repair sub-pixel to repair the display substrate, and the repair line is arranged far away from the source and drain electrodes of the plurality of transistors.
- the repair lines are respectively connected to the partially disconnected gate lines and the partially disconnected defective power connection lines, and are used to transmit scanning signals to repair the display substrate.
- the formation of the gate line, the data line, the power connection line, and the plurality of sub-pixels defined by the intersection of the gate line and the data line on the substrate includes:
- Data lines, power lines, sensing lines, and source and drain electrodes of a plurality of transistors are formed on the interlayer insulating layer.
- the disconnecting the bad gate line and the bad power connection line includes:
- a laser process is used to cut the defective grid lines into a first scanning part, a second scanning part and a third scanning part which are disconnected from each other along the grid line arrangement direction; wherein, the orthographic projection of the second scanning part on the substrate and the The orthographic projection of the bad data line on the substrate has an overlapping area, and the first scanning part is connected to the gate electrode of the switching transistor in the sub-pixel on the side of the bad data line close to the first repaired sub-pixel; The third scanning part is connected to the gate electrode of the switching transistor in the sub-pixel on the side of the bad data line close to the second repaired sub-pixel;
- a laser process is used to cut the defective power supply connection line into a first connection part, a second connection part and a third connection part which are disconnected from each other along the grid line arrangement direction; wherein the orthographic projection of the first connection part on the substrate is the same as
- the first pole of the driving transistor in the first repairing sub-pixel has an overlapping area and is connected to the first pole of the driving transistor in the first repairing sub-pixel.
- the orthographic projection of the third connecting portion on the substrate is the same as that of the second repairing sub-pixel.
- the first pole of the driving transistor in the sub-pixel has an overlapping area, and is connected to the first pole of the driving transistor in the second repair sub-pixel.
- the orthographic projection of the second connection portion on the substrate and the first repair sub-pixel and The second pole of the switching transistor in the second sub-repair sub-pixel has an overlapping area, and the second connection part is connected to the repair line;
- a laser process is used to form a first groove, a second groove, a first via hole, and a second via hole in the first sub-pixel and the second sub-pixel; wherein the first groove penetrates the sub-pixel where the first groove is located.
- the active layer of the switching transistor in the pixel, and the orthographic projection of the first groove on the substrate is located on the substrate and the orthographic projection of the first pole of the switching transistor on the substrate in the sub-pixel where the first groove is located.
- the gate electrode of the switching transistor in the sub-pixel where the groove is located is between the orthographic projections on the substrate; the second groove penetrates the second electrode of the switching transistor in the sub-pixel where the second groove is located, and the second groove
- the orthographic projection of the groove on the substrate is located between the orthographic projection of the power connection line on the substrate and the orthographic projection of the gate electrode of the driving transistor of the sub-pixel where the second groove is located on the substrate; wherein, the first repairer The first via hole in the pixel is used to expose the first scanning portion, the first via hole in the second repair sub-pixel is used to expose the third scanning portion, and the second via hole is used to expose the second connecting portion.
- the forming a repair line in the first repair sub-pixel and the second repair sub-pixel to repair the display substrate includes:
- the first repairing part is connected to the first repairing part through a first via hole in the first repairing sub-pixel, and the first repairing part is connected to the second connecting part through a second via hole in the first repairing sub-pixel;
- the second repair part is connected to the third scanning part through the first via hole in the second repair sub-pixel;
- the second repair part is connected to the second connection part through the second via hole in the second repair sub-pixel.
- the method further includes:
- the second electrode of the storage capacitor is formed on the data line, the power line, the sensing line, and the source and drain electrodes of the plurality of transistors.
- Figure 1 is an equivalent circuit diagram of an OLED pixel drive circuit
- FIG. 2 is a schematic diagram of the structure of a display substrate provided by an embodiment of the disclosure.
- Figure 3 is a cross-sectional view of Figure 2 along the line A-A;
- FIG. 4 is a flowchart of a manufacturing method of a display substrate provided by an embodiment of the disclosure.
- 5A is a first schematic diagram of a manufacturing method of a display substrate provided by an embodiment of the disclosure.
- Figure 5B is a cross-sectional view of Figure 5A along the line A-A;
- 6A is a second schematic diagram of a manufacturing method of a display substrate provided by an embodiment of the disclosure.
- Fig. 6B is a cross-sectional view of Fig. 6A along the line A-A;
- FIG. 7A is a third schematic diagram of a manufacturing method of a display substrate provided by an embodiment of the disclosure.
- Figure 7B is a cross-sectional view of Figure 7A along the line A-A;
- FIG. 8A is a fourth schematic diagram of a manufacturing method of a display substrate provided by an embodiment of the disclosure.
- Figure 8B is a cross-sectional view of Figure 8A along the line A-A;
- FIG. 9A is a fifth schematic diagram of a manufacturing method of a display substrate provided by an embodiment of the disclosure.
- Figure 9B is a cross-sectional view of Figure 9A along the line A-A;
- 10A is a sixth schematic diagram of a manufacturing method of a display substrate provided by an embodiment of the disclosure.
- Fig. 10B is a cross-sectional view of Fig. 10A along the line A-A.
- the specification may have presented the method and/or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As those of ordinary skill in the art will understand, other sequence of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims for the method and/or process should not be limited to performing their steps in the written order. Those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present disclosure. Inside.
- the gate electrode layer and the source-drain metal layer are closer to each other, that is, the gate line and the data line are closer to each other.
- the insulating layer located in the overlapping area of the gate line and the data line is easily broken down, so that when driving the display, the electrostatic discharge will cause the gate line and the data line.
- Short-circuit causes the OLED display substrate to have defective points formed by short-circuiting the gate line and the data line, causing the OLED display substrate to produce horizontal and vertical or vertical stripes, which in turn leads to poor display effects of the OLED display substrate.
- the OLED display substrate includes a plurality of sub-pixels, and each sub-pixel includes an OLED pixel driving circuit and a light-emitting device OLED.
- Figure 1 is an equivalent circuit diagram of an OLED pixel drive circuit, which illustrates a 3T1C drive circuit.
- the OLED display substrate includes a plurality of sub-pixels, and each sub-pixel includes a drive circuit and a light-emitting element OLED.
- the pixel driving circuit is electrically connected to the gate line G_N, the compensation line Sense, the power line VDD, the data line Data, and the gate line G_N+1, and includes: a switching transistor T1, a driving transistor T2, a sensing transistor T3, and a storage capacitor C.
- the display substrate includes multiple rows of gate lines and multiple columns of data lines.
- the gate line G_N is the gate line of the Nth row
- the gate line G_N+1 is the gate line of the N+1th row.
- FIG. 1 is to illustrate the connection relationship. Take the OLED pixel driving circuit in two sub-pixels arranged along the column direction as an example for description.
- the gate electrode of the switching transistor T1 is connected to the gate line G_N
- the first electrode of the switching transistor T1 is connected to the data line Data
- the second electrode of the switching transistor T1 is connected to the node N1
- the gate electrode of the driving transistor T2 is connected to The node N1 is connected
- the first electrode of the driving transistor T2 is connected to the power supply line VDD
- the second electrode of the driving transistor T2 is connected to the node N2
- the gate electrode of the sensing transistor T3 is connected to the gate line G_N+1
- the first electrode of the sensing transistor T3 is connected to the gate line G_N+1.
- One electrode is connected to the sensing line Sense
- the second electrode of the sensing transistor T3 is connected to the node N2
- the anode of the OLED is connected to the node N2
- the cathode of the OLED is connected to the low voltage line VSS, and is configured to respond to the second electrode of the driving transistor.
- the current emits light of corresponding brightness.
- the sensing transistor T3 can respond to the compensation timing to extract the threshold voltage Vth and mobility of the driving transistor T2 to sense the threshold voltage Vth
- the storage capacitor C is used to keep emitting light for one frame
- FIG. 2 is a schematic diagram of the structure of the display substrate provided by the embodiment of the present disclosure.
- FIG. 3 is a cross-sectional view of FIG. 2 along the AA direction.
- the embodiment of the present disclosure is The provided display substrate includes: a substrate 10, a gate line G, a data line Data, a power connection line VL and a plurality of sub-pixels defined by the intersection of the gate line and the data line provided on the substrate 10, and each sub-pixel includes a driving circuit;
- the circuit includes multiple transistors and storage capacitors.
- the multiple transistors include: switching transistors, driving transistors, and sensing transistors.
- the storage capacitors are transparent capacitors.
- the display substrate has defective points formed by the short circuit of the gate line G and the data line Data ( Figure 2 The black dots in the middle), the grid lines that form the defective points are bad grid lines, and the data lines that form the bad points are bad data lines; the display substrate also includes: repair lines and located on both sides of the bad points and arranged along the extension direction of the grid lines The first sub-pixel P1 and the second sub-pixel P2.
- FIG. 2 illustrates the sub-pixels in the Nth row as an example.
- the first pole of the driving transistor is connected to the power connection line VL; the power connection line VL is arranged in the same layer as the gate electrodes of the plurality of transistors; the defective gate line G_N is respectively connected to the first repair sub-pixel and the second repair sub-pixel
- the gate electrode of the switching transistor in is connected; wherein, the first repair sub-pixel and the second repair sub-pixel are respectively located on both sides of the bad data line, and are connected to the bad gate line, and are connected to the first repair sub-pixel and the second repair sub-pixel
- the power cable is a bad power cable.
- the defective gate line and the defective power connection line are disconnected.
- the display substrate further includes: the source and drain electrodes of the plurality of transistors are arranged on the side away from the substrate The repair line is connected to the partially disconnected defective grid line and the partially disconnected defective power connection line, and is used to transmit scanning signals to repair the display substrate.
- the display substrate may be a large-size bottom emission OLED display substrate, wherein the data signal is provided by the data line, and the scan signal is provided by the gate line.
- FIG. 2 illustrates the existence of defective points on a display substrate as an example.
- the gate line G_N in the figure is the defective gate line in the present disclosure, and the other unillustrated gate lines are normal gate lines, that is, they are not disconnected.
- the display substrate provided by the embodiment of the present disclosure further includes: an active layer 21 of a switching transistor, a gate electrode 22, a first electrode 23 and a second electrode 24, a light shielding layer 11 of a driving transistor, and The source layer 31, the gate electrode 32, the first electrode 33 and the second electrode 34, the active layer 41 of the sensing transistor, the gate electrode (not shown in the figure), the first electrode 43 and the second electrode 44, the buffer layer 12 , The gate insulating layer 13, the interlayer insulating layer 14, the first electrode C1 and the second electrode C2 of the storage capacitor C, the compensation line Sense, and the compensation connection line SL.
- the first electrode C1 of the storage capacitor C is respectively connected to the second electrode 24 of the switching transistor and the gate electrode 32 of the driving transistor, and the second electrode C2 of the storage capacitor C is respectively connected to the second electrode 34 of the driving transistor and the second electrode 34 of the sensing transistor.
- the second pole 44 is connected.
- the compensation line Sense and the data line Data are provided in the same layer, and the compensation connection line SL and the light shielding layer 11 are provided in the same layer.
- the orthographic projection of the light shielding layer 11 on the substrate overlaps with the gate electrode of the driving transistor, and the orthographic projection of the gate insulating layer on the substrate coincides with the orthographic projection of the gate electrodes of the plurality of transistors on the substrate.
- the first via hole is arranged on the interlayer insulating layer.
- the base 10 may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be but not limited to one or more of glass and metal sheet; the flexible substrate may be but not limited to poly-p-phenylene Ethylene dicarboxylate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene , One or more of textile fibers.
- the rigid substrate may be but not limited to one or more of glass and metal sheet
- the flexible substrate may be but not limited to poly-p-phenylene Ethylene dicarboxylate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene , One or more of textile fibers.
- the light shielding layer 11 and the compensation connecting line SL are made of metal, for example, silver, aluminum, etc., which is not limited in the embodiment of the present disclosure.
- the function of the buffer layer 12 on the substrate 10 is to prevent the metal ions of the substrate from diffusing to the active layer, reducing defects and reducing the generation of leakage current.
- the buffer layer can be silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., or high-dielectric materials, such as aluminum oxide (AlOx), hafnium oxide (HfOx), oxide Tantalum (TaOx), etc., can be a single layer, a multilayer or a composite layer.
- the active layer is made of metal oxide, for example, indium gallium zinc oxide (IGZO), which is not limited in the embodiments of the present disclosure.
- IGZO indium gallium zinc oxide
- the material of the first electrode C1 and the second electrode C2 may be a transparent conductive material, which is not limited in the embodiment of the present disclosure.
- the buffer layer 12, the gate insulating layer 13 and the interlayer insulating layer 14 can be made of oxide, nitride, or oxynitride, which is not limited in the embodiment of the present disclosure.
- the gate line, the power connection line VL, and the gate electrode are formed by the same manufacturing process, and the manufacturing material can be silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), etc., or the above-mentioned metal Alloy materials, such as aluminum neodymium alloy (AlNd), molybdenum niobium alloy (MoNb), etc., can be multilayer metals, such as Mo/Cu/Mo, etc., or a stack structure formed by metal and transparent conductive materials, such as ITO/Ag /ITO etc.
- the data line Data, the compensation line Sense, the power supply line VDD, and the source and drain electrodes of the multiple transistors are formed by the same manufacturing process, and the manufacturing materials can be silver (Ag), copper (Cu), aluminum (Al), and molybdenum. (Mo), etc., or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd), molybdenum niobium alloy (MoNb), etc., can be multilayer metals, such as Mo/Cu/Mo, etc., or metal and transparent conductive materials
- the formed stack structure such as ITO/Ag/ITO, etc.
- the power connection line and the gate line in the present disclosure are arranged in the same layer. Since the gate line layer is closest to the source and drain electrode layer, the laser fuse range is reduced, which is high resolution. Technical support is provided for the rate of product maintenance.
- a repair line is used to replace a part of the gate line between the gate electrode of the switching transistor in the first repair sub-pixel and the gate electrode of the switching transistor in the second repair sub-pixel to provide scanning signals, which avoids being located in the second when driving the display.
- a part of the gate line between the gate electrode of the switching transistor in the repairing sub-pixel and the gate electrode of the switching transistor in the second repairing sub-pixel has a signal, which forms a short circuit with the bad data line.
- the display substrate of the embodiment of the present disclosure is ensuring that the data line is While functioning normally, it also guarantees the integrity of the scan signal provided by the gate line.
- the first repaired sub-pixel and the second repaired sub-pixel produce dark spots, the normal display of other sub-pixels is ensured to avoid horizontal or vertical stripes. , Realizes the repair of the display substrate with defective points, and then improves the display substrate, improves the product yield, and provides basic support for high-resolution bottom emission display products.
- the display substrate provided by the embodiment of the present disclosure includes a substrate, a gate line, a data line, a power connection line and a plurality of sub-pixels defined by the intersection of the gate line and the data line provided on the substrate, and each sub-pixel includes: a driving circuit; a driving circuit Including: multiple transistors and storage capacitors, the display substrate has defective points formed by short-circuiting gate lines and data lines, the gate lines forming the defective points are bad gate lines; the data lines forming the bad points are bad data lines; multiple transistors include : Switching transistor, driving transistor and sensing transistor; the first electrode of the storage capacitor is connected to the second electrode of the switching transistor and the gate electrode of the driving transistor, and the second electrode of the storage capacitor is connected to the second electrode of the driving transistor and the sensing transistor.
- the second pole of the transistor is connected.
- the first pole of the driving transistor is connected to the power connection line;
- the power connection line is arranged in the same layer with the gate electrodes of the plurality of transistors;
- the defective gate line is connected to the first repair sub-pixel and the second
- the gate electrode of the switching transistor in the second repair sub-pixel is connected; wherein, the first repair sub-pixel and the second repair sub-pixel are located on both sides of the bad data line, and are connected to the bad gate line, and are connected to the first repair sub-pixel and the second repair sub-pixel.
- the power connection line connected to the repair sub-pixel is a bad power connection line; the bad gate line and the bad power connection line are disconnected.
- the display substrate further includes: The source and drain electrodes are away from the repair line on the side of the substrate, and the repair lines are respectively connected to the partially disconnected bad grid lines and the partially disconnected bad power connection lines, and are used to transmit scanning signals to repair the display substrate.
- the technical solution provided by the present disclosure forms a partial grid line with a defective point by disconnecting a defective grid line and a defective power connection line, and setting a repair line connecting the partially disconnected defective grid line and the partially disconnected defective power connection line
- the scan signal is not transmitted, that is, part of the gate lines that form defective points cannot be short-circuited with the data lines, which realizes the repair of the display substrate with defective points, thereby ensuring the display effect of the display substrate, improving the product yield, and achieving high resolution
- the bottom launch display products provide basic support.
- the bad gate line provided by the embodiment of the present disclosure includes: a first scanning part G1, a second scanning part G2, and a third scanning part that are arranged along the extending direction of the gate line and are disconnected from each other G3, wherein the second scanning part G3 is located between the first scanning part G1 and the third scanning part G3.
- the orthographic projection of the second scanning part G2 on the substrate 10 and the orthographic projection of the bad data line on the substrate 10 have an overlapping area, and the first scanning part G1 and the bad data line are located close to the first restoration part.
- the gate electrode of the switching transistor in the sub-pixel on one side of the pixel is connected;
- the third scanning portion G3 is connected to the gate electrode of the switching transistor in the sub-pixel on the side of the bad data line close to the second repaired sub-pixel;
- the repair lines are respectively connected to the first A scanning part G1 and a third scanning part G3 are connected.
- the first scanning part G1 is connected to the gate electrodes of the switching transistors in all sub-pixels located on the side of the bad data line close to the first sub-pixel and arranged in line with the first sub-pixel; the third scan The part G3 is connected to the gate electrodes of the switching transistors in all the sub-pixels which are located on the side of the bad data line close to the second sub-pixel and arranged in parallel with the first sub-pixel.
- the first scanning part in this embodiment is connected to the output terminal of the gate driving circuit in the display substrate for transmitting scanning signals.
- the second scanning part since the second scanning part is connected to the first scanning Both the third scanning part and the third scanning part are disconnected, and the second scanning part has no signal when driving and displaying, so it will not form a short circuit with the bad data line.
- the poor power connection line provided by the embodiment of the present disclosure includes a first connection portion L1, a second connection portion L2, and a third connection portion L3 that are arranged along the extending direction of the gate line and are disconnected from each other;
- the second connecting portion L2 is located between the first connecting portion L1 and the third connecting portion L3.
- the orthographic projection of the first connecting portion L1 on the substrate 10 overlaps with the first electrode 33 of the driving transistor in the first repair sub-pixel, and overlaps with the first electrode of the driving transistor in the first repair sub-pixel. 33 is connected, the orthographic projection of the third connecting portion L3 on the substrate 10 overlaps with the first pole 33 of the driving transistor in the second repair sub-pixel, and overlaps with the first pole 33 of the driving transistor in the second repair sub-pixel. Connection, the orthographic projection of the second connection portion L2 on the substrate 10 overlaps with the second pole 24 of the switching transistor in the first repair sub-pixel and the second sub-repair sub-pixel, and the second connection portion L2 is connected to the repair line.
- the repair line provided by the embodiment of the present disclosure includes: a first repair part R1 and a second repair part R2; wherein the first repair part R1 is connected to the first scanning part G1 and the second connecting part L2, respectively. Connection;
- the second repair part R2 is connected to the third scanning part G3 and the second connection part L2 respectively.
- the material of the first repair part R1 and the second repair part R2 includes tungsten.
- both the first repair sub-pixel and the second repair sub-pixel include: a first groove D1 and a second groove D2.
- the first groove D1 penetrates the active layer 21 of the switching transistor in the sub-pixel where the first groove D1 is located, and the orthographic projection of the first groove D1 on the substrate is located on the sub-pixel where the first groove D1 is located.
- the second groove D2 penetrates the sub-pixel where the second groove D2 is located.
- the second pole 24 of the switching transistor in the pixel, and the orthographic projection of the second groove D2 on the substrate 10 is located on the orthographic projection of the power connection line VL on the substrate 10 and the gate electrode of the driving transistor of the sub-pixel where the second groove D2 is located 32 is between the orthographic projections on the substrate 10.
- both the first repair sub-pixel and the second repair sub-pixel further include: a first via V1 and a second via V2; wherein, the first repair sub-pixel in the first repair sub-pixel One via hole V1 is used to expose the first scanning portion G1, the first via hole V1 in the second repair sub-pixel is used to expose the third scanning portion G3, and the second via hole V2 is used to expose the second connection portion L2.
- the first repair part R1 is connected to the first scanning part G1 through the first via hole V1 in the first repair sub-pixel, and the first repair part R1 is connected to the second scan part G1 through the second via hole V2 in the first repair sub-pixel.
- Part L2 is connected; the second repair part R2 is connected to the third scanning part G3 through the first via hole V1 in the second repair sub-pixel; the second repair part R2 is connected to the third scanning part G3 through the second via hole V2 in the second repair sub-pixel
- the two connecting parts L2 are connected.
- the first repairing part R1 and the second repairing part R2 are formed by the same manufacturing process, and the manufacturing material is metal, such as tungsten, which is not limited in the embodiment of the present disclosure.
- the storage capacitor C is a transparent capacitor
- the first electrode C1 of the storage capacitor C is arranged in the same layer as the active layers of the multiple transistors
- the second electrode C2 of the storage capacitor is arranged on the source and drain of the multiple transistors. The side very far away from the substrate.
- the second electrode is made of a transparent conductive material
- the first electrode is made of the same material as the active layer of the plurality of transistors.
- each sub-pixel includes: a storage capacitor area provided with a storage capacitor and a non-storage capacitor area provided with a plurality of transistors.
- the non-storage capacitor area includes: a first non-storage capacitor area and a second non-storage capacitor area; the first non-storage capacitor area and the second non-storage capacitor area are located on both sides of the storage capacitor area, and the switching transistor and the driving transistor are located in the first non-storage capacitor area.
- the sensing transistor is located in the second non-storage capacitor area.
- the gate electrode of the switching transistor is connected to the gate line of the i-th row
- the gate electrode of the sensing transistor is connected to the gate line of the (i+1)th row
- the gate line of the i-th row is connected to the gate line of the i-th row.
- the i+1 row of gate lines are respectively located on both sides of the storage capacitor area of the i-th row of sub-pixels.
- the display substrate provided by the embodiment of the present disclosure further includes: a power line VDD, a sensing line Sense, and a data line Data arranged in the same layer as the source and drain electrodes of a plurality of transistors.
- the first pole 33 of the driving transistor is connected to the power supply line VDD through the power connection line VL, and the first pole 43 of the sensing transistor is connected to the sensing line Sense;
- Each pixel includes four sub-pixels, each pixel is connected to four columns of data lines, one column of power lines, and two sensing lines, each sub-pixel corresponds to one column of data lines, and each pixel corresponds to one column of power lines and two columns of sensing line.
- the four sub-pixels are arranged in sequence along the extending direction of the gate line, the power line corresponding to each pixel is arranged between the second sub-pixel and the third sub-pixel, and the sensing line of the first column is arranged in the first sub-pixel away from the second sub-pixel.
- the second column of sensing lines is arranged on the side of the fourth sub-pixel away from the third sub-pixel; the data line corresponding to the first sub-pixel is located at a side of the first sub-pixel close to the second sub-pixel.
- the data line corresponding to the second sub-pixel is located on the side of the second sub-pixel close to the first sub-pixel, and the data line corresponding to the third sub-pixel is located in the third sub-pixel close to the fourth sub-pixel On the side of the fourth sub-pixel, the data line corresponding to the fourth sub-pixel is located on the side of the fourth sub-pixel close to the third sub-pixel.
- the arrangement of the four sub-pixels in each pixel can be RWBG, but it is not limited to this arrangement.
- FIG. 2 uses four sub-pixels included between the two power supply lines as an example for illustration.
- the display substrate further includes: a sensing connection line connected to the sensing line; a light shielding layer is provided on the side of the buffer layer close to the substrate, the sensing connection line and the light shielding layer are provided in the same layer, and the light shielding layer is The orthographic projection on the substrate covers the effective area of the active layer of the driving transistor; for each sub-pixel, the first electrode of the sensing transistor is connected to the sensing line through the sensing connection line.
- the display substrate provided by the embodiment of the present disclosure disconnects the gate line between the gate electrode of the switching transistor in the first repairing sub-pixel and the gate electrode of the switching transistor in the second repairing sub-pixel, which is the channel for transmitting signals to the defective point.
- the new scan signal transmission channel forms a new scan signal signal line to ensure the integrity of the scan signal to ensure that the product can work normally, thereby improving the product yield.
- an embodiment of the present disclosure further provides a method for manufacturing a display substrate for manufacturing a display substrate.
- FIG. 4 is a flowchart of the method for manufacturing a display substrate provided by an embodiment of the disclosure, as shown in FIG. 4 As shown, the manufacturing method of the display substrate provided by the embodiment of the present disclosure includes steps S1 to S3. among them:
- Step S1 forming a gate line, a data line, a power connection line, and a plurality of sub-pixels defined by the intersection of the gate line and the data line on the substrate.
- Each sub-pixel includes a driving circuit; the driving circuit includes: a plurality of transistors and a storage capacitor; the storage capacitor is a transparent capacitor, and the plurality of transistors include: a switching transistor, a driving transistor, and a sensing transistor; The second electrode is connected to the gate electrode of the driving transistor. The second electrode of the storage capacitor is respectively connected to the second electrode of the driving transistor and the second electrode of the sensing transistor.
- the first electrode of the driving transistor is connected to the power supply connection line. Connection; The power connection line is arranged in the same layer with the gate electrodes of multiple transistors.
- step S1 includes: forming a light-shielding layer and a sensing connection line on the substrate; forming a buffer layer on the light-shielding layer and the sensing connection line; forming an active layer of a plurality of transistors and a second storage capacitor on the buffer layer An electrode; a gate insulating layer is formed on the active layer of the plurality of transistors and the first electrode of the storage capacitor; the gate line, the gate electrode of the plurality of transistors and the power connection line are formed on the gate insulating layer; An interlayer insulating layer is formed on the gate electrode of the transistor and the power connection line; the data line, the power line, the sensing line and the source and drain electrodes of a plurality of transistors are formed on the interlayer insulating layer.
- Step S2 find the defective point formed by the short circuit of the gate line and the data line.
- step S2 includes using a defective point search method in the related art to find defective points in the display substrate.
- the gate line forming the defective point is a defective gate line
- the data line forming the defective point is a defective data line.
- the first repair sub-pixel and the second repair sub-pixel are respectively located on both sides of the defective data line and are connected to the defective gate line.
- the power connection lines connected to the first repair sub-pixel and the second repair sub-pixel are defective power connection lines.
- Step S3 disconnect the bad gate line and the bad power connection line, and form a repair line in the first repair sub-pixel and the second repair sub-pixel to repair the display substrate.
- the repair line is arranged on the side of the source and drain electrodes of the plurality of transistors away from the substrate, and the repair line is respectively connected to the partially disconnected gate line and the partially disconnected bad power connection line, and is used to transmit scanning signals to The display substrate is repaired.
- disconnecting the bad grid line and the bad power connection line includes: cutting the bad grid line into the first scanning part, the second scanning part and the third scanning part which are disconnected from each other along the grid line arrangement direction by a laser process; The laser process cuts the defective power connection line into the first connection part, the second connection part and the third connection part which are disconnected from each other along the grid line arrangement direction; the laser process is used to form the first sub-pixel and the second sub-pixel.
- the orthographic projection of the second scanning part on the substrate and the orthographic projection of the bad data line on the substrate have an overlapping area, and the first scanning part and the switching transistor in the sub-pixel located on the side of the bad data line close to the first repaired sub-pixel
- the third scanning part is connected to the gate electrode of the switching transistor in the sub-pixel on the side of the bad data line close to the second repaired sub-pixel.
- the orthographic projection of the first connection part on the substrate has an overlap area with the first electrode of the driving transistor in the first repair sub-pixel, and is connected to the first electrode of the driving transistor in the first repair sub-pixel, and the third connection part is at
- the orthographic projection on the substrate has an overlapping area with the first pole of the driving transistor in the second repair sub-pixel, and is connected to the first pole of the driving transistor in the second repair sub-pixel.
- the orthographic projection of the second connection portion on the substrate There is an overlapping area with the second pole of the switching transistor in the first repair sub-pixel and the second sub-repair sub-pixel, and the second connection part is connected to the repair line; the first groove penetrates through the switching transistor in the sub-pixel where the first groove is located Active layer, and the orthographic projection of the first groove on the substrate is located in the sub-pixel where the first groove is located.
- forming a repair line in the first repair sub-pixel and the second repair sub-pixel to repair the display substrate includes: depositing a metal film on the first sub-pixel and the second sub-pixel; A first repair part is formed in the middle, and a second repair part is formed in the second sub-pixel to form a repair line.
- the first repairing part is connected to the first repairing part through a first via hole in the first repairing sub-pixel, and the first repairing part is connected to the second connecting part through a second via hole in the first repairing sub-pixel;
- the repairing part is connected to the third scanning part through the first via hole in the second repairing sub-pixel;
- the second repairing part is connected to the second connecting part through the second via hole in the second repairing sub-pixel.
- the manufacturing method of the display substrate provided by the embodiment of the present disclosure further includes: forming a second electrode of a storage capacitor on the data line, the power line, the sensing line, and the source and drain electrodes of the plurality of transistors.
- the display substrate is the display substrate provided in the foregoing embodiment, and its implementation principles and effects are similar, and will not be repeated here.
- the power connection line and the gate line in the present disclosure are arranged in the same layer. Since the gate line layer is closest to the source and drain electrode layer, the laser fuse range is reduced, which is high resolution. Technical support is provided for the rate of product maintenance.
- the technical solution of this embodiment will be described below through the preparation process of the display substrate of this embodiment.
- the "patterning process” referred to in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, developing, etching, and stripping photoresist.
- the deposition can be sputtering, vapor deposition, chemical vapor deposition and other processes, which are not limited here.
- “thin film” refers to a thin film made by depositing a certain material on a substrate or other processes. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be referred to as a "layer”. If the "thin film” needs a patterning process during the entire production process, it is called a "thin film” before the patterning process and a "layer” after the patterning process.
- the "layer” after the patterning process contains at least one "pattern”.
- FIG. 5A is a first schematic diagram of a manufacturing method of a display substrate provided by an embodiment of the disclosure
- FIG. 5B is a cross-sectional view along the AA direction of FIG. 5A
- FIG. 6A is a schematic diagram two of a manufacturing method of a display substrate provided by an embodiment of the disclosure
- FIG. 6B is FIG. 6A is a cross-sectional view along the AA direction
- FIG. 7A is a schematic diagram of the third of the manufacturing method of the display substrate provided by an embodiment of the disclosure
- FIG. 7B is a cross-sectional view along the AA direction of FIG. 7A
- FIG. Fig. 8B is a cross-sectional view taken along the line AA of Fig. 8A, Fig.
- FIG. 9A is a schematic view five of the manufacturing method of the display substrate provided by an embodiment of the present disclosure
- Fig. 9B is a cross-sectional view taken along the line AA of Fig. 9A
- Fig. 10A is the present disclosure
- FIG. 10B is a cross-sectional view along the AA direction of FIG. 10A.
- step 100 a substrate 10 is provided, and the light shielding layer 11 and the compensation connection line SL are formed on the substrate 10 using the same process, as shown in FIGS. 5A and 5B.
- Step 200 forming a buffer layer 12 covering the substrate 10, and forming an active layer 21 of a switching transistor, an active layer 31 of a driving transistor, an active layer 41 of a sensing transistor, and a first electrode of a storage capacitor on the buffer layer 12 C1, as shown in Figure 6A and Figure 6B.
- Step 300 forming a gate insulating layer 13, and using the same process to form a gate line G_N, a second gate line G_N+1, a power connection line VL, a gate electrode 22 of a switching transistor, and a gate electrode 32 of a driving transistor on the gate insulating layer 13 And the gate electrode of the sensing transistor (not shown in the figure), as shown in FIG. 7A and FIG. 7B.
- Step 400 forming an interlayer insulating layer 14, and forming the first electrode 23 and the second electrode 24 of the switching transistor, the first electrode 33 and the second electrode 34 of the driving transistor, and the first electrode of the sensing transistor on the interlayer insulating layer 14.
- the one pole 43 and the second pole 44, the data line Data, the power line VDD, the compensation line Sense, and the second electrode C2 of the storage capacitor are as shown in FIG. 8A and FIG. 8B.
- the source and drain electrodes, data lines, power lines, and compensation lines of multiple transistors can be formed by the same manufacturing process, which is not limited in the embodiment of the present disclosure.
- Step 500 Use a laser process to cut the bad grid lines along the grid line arrangement direction to form a first scanning part G1, a second scanning part G2, and a third scanning part G3 that are arranged along the extending direction of the grid lines and are disconnected from each other;
- the laser process forms the first groove D1 and the second groove D2 in the first repaired sub-pixel and the second repaired sub-pixel, and the power connection line VL is cut along the gate line arrangement direction by the laser process to be arranged along the extension direction of the gate line
- the first connecting portion L1, the second connecting portion L2, and the third connecting portion L3 that are disconnected from each other are shown in FIGS. 9A and 9B.
- Step 600 forming a first via V1 and a second via V2 in the first repair sub-pixel and the second repair sub-pixel, as shown in FIG. 10A and FIG. 10B.
- step 700 a first repair part R1 is formed in the first repair sub-pixel and a second repair part R2 is formed in the second repair sub-pixel to form a repair line, as shown in FIGS. 2 and 3.
- an embodiment of the present disclosure further provides a display device including: a display substrate.
- the display substrate is the display substrate provided in the foregoing embodiment, and its implementation principles and effects are similar, and will not be repeated here.
- the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
- a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
- Other indispensable components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, and should not be used as a limitation to the present disclosure.
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Abstract
Description
Claims (20)
- 一种显示基板,包括:基底以及设置在所述基底上的栅线、数据线、电源连接线以及由栅线和数据线交叉限定的多个子像素,每个子像素包括:驱动电路;所述驱动电路包括:多个晶体管和存储电容,所述显示基板存在由栅线和数据线短路形成的不良点,形成所述不良点的栅线为不良栅线;形成不良点的数据线为不良数据线;多个晶体管包括:开关晶体管、驱动晶体管和感测晶体管,所述存储电容的第一电极分别与开关晶体管的第二极和驱动晶体管的栅电极连接,所述存储电容的第二电极分别与驱动晶体管的第二极和感测晶体管的第二极连接;对于每个子像素,驱动晶体管的第一极与电源连接线连接;所述电源连接线与多个晶体管的栅电极同层设置;所述不良栅线分别与第一修复子像素和第二修复子像素中的开关晶体管的栅电极连接;其中,第一修复子像素和第二修复子像素分别位于不良数据线两侧,与第一修复子像素和第二修复子像素连接的电源连接线为不良电源连接线;所述不良栅线和所述不良电源连接线断开设置,对于第一修复子像素和第二修复子像素,所述显示基板还包括:设置在多个晶体管的源漏电极远离基底一侧的修复线,所述修复线分别与部分断开设置的不良栅线和部分断开设置的不良电源连接线连接,且用于传输扫描信号,以对显示基板进行修复。
- 根据权利要求1所述的显示基板,其中,所述不良栅线包括:沿栅线延伸方向设置的,且相互断开的第一扫描部、第二扫描部和第三扫描部,其中,所述第二扫描部位于所述第一扫描部和所述第三扫描部之间;所述第二扫描部在基底上的正投影与所述不良数据线在基底上的正投影存在重叠区域,所述第一扫描部与位于所述不良数据线靠近所述第一修复子像素的一侧的子像素中开关晶体管的栅电极连接;所述第三扫描部与位于不良数据线靠近所述第二修复子像素的一侧的子像素中开关晶体管的栅电极连接;所述修复线分别与第一扫描部和第三扫描部连接。
- 根据权利要求2所述的显示基板,其中,所述不良电源连接线包括沿 栅线延伸方向设置的,且相互断开的第一连接部、第二连接部和第三连接部;其中,所述第二连接部位于所述第一连接部和所述第三连接部之间;所述第一连接部在基底上的正投影与第一修复子像素中的驱动晶体管的第一极存在重叠区域,且与第一修复子像素中的驱动晶体管的第一极连接,所述第三连接部在基底上的正投影与第二修复子像素中的驱动晶体管的第一极存在重叠区域,且与第二修复子像素中的驱动晶体管的第一极连接,所述第二连接部在基底上的正投影与第一修复子像素和第二子修复子像素中的开关晶体管的第二极存在重叠区域,所述第二连接部与修复线连接。
- 根据权利要求3所述的显示基板,其中,所述修复线包括:第一修复部和第二修复部;其中,所述第一修复部分别与第一扫描部和第二连接部连接;所述第二修复部分别与第三扫描部和第二连接部连接。
- 根据权利要求4所述的显示基板,其中,所述第一修复部和所述第二修复部的制作材料包括:钨。
- 根据权利要求4所述的显示基板,其中,所述第一修复子像素和所述第二修复子像素均包括:第一凹槽和第二凹槽;其中,所述第一凹槽贯穿所述第一凹槽所在子像素中开关晶体管的有源层,且所述第一凹槽在基底上的正投影位于所述第一凹槽所在子像素中开关晶体管的第一极在基底上的正投影和所述第一凹槽所在子像素中开关晶体管的栅电极在基底上的正投影之间;所述第二凹槽贯穿所述第二凹槽所在子像素中开关晶体管的第二极,且所述第二凹槽在基底上的正投影位于所述电源连接线在基底上的正投影和所述第二凹槽所在子像素的驱动晶体管的栅电极在基底上的正投影之间。
- 根据权利要求4所述的显示基板,其中,所述第一修复子像素和第二修复子像素均还包括:第一过孔和第二过孔;其中,第一修复子像素中的第一过孔用于暴露第一扫描部,第二修复子像素中的第一过孔用于暴露第三扫描部,所述第二过孔用于暴露第二连接部。
- 根据权利要求7所述的显示基板,其中,所述第一修复部通过第一修 复子像素中的第一过孔与第一扫描部连接,所述第一修复部通过第一修复子像素中的第二过孔与第二连接部连接;所述第二修复部通过第二修复子像素中的第一过孔与第三扫描部连接;所述第二修复部通过第二修复子像素中的第二过孔与第二连接部连接。
- 根据权利要求1所述的显示基板,其中,所述存储电容为透明电容,所述存储电容的第一电极与多个晶体管的有源层同层设置,所述存储电容的第二电极设置在多个晶体管的源漏电极远离基底的一侧;所述第二电极的制作材料为透明导电材料,所述第一电极的制作材料与多个晶体管的有源层的制作材料相同。
- 根据权利要求1所述的显示基板,其中,每个子像素包括:设置有存储电容的存储电容区和设置有多个晶体管的非存储电容区;所述非存储电容区包括:第一非存储电容区和第二非存储电容区;所述第一非存储电容区和第二非存储电容区分别位于存储电容区的两侧,所述开关晶体管和所述驱动晶体管位于第一非存储电容区,所述感测晶体管位于第二非存储电容区。
- 根据权利要求1所述的显示基板,其中,对于第i行的每个子像素,所述开关晶体管的栅电极与第i行栅线连接,所述感测晶体管的栅电极与第i+1行栅线连接,第i行栅线和第i+1行栅线分别位于第i行子像素的存储电容区的两侧。
- 根据权利要求1所述的显示基板,还包括:与多个晶体管的源漏电极同层设置的电源线、感测线和数据线,对于每个子像素,驱动晶体管的第一极与通过电源连接线与电源线连接,感测晶体管的第一极与感测线连接;每个像素包括:四个子像素,每个像素分别与四列数据线、一列电源线和两个感测线连接,每个子像素对应一列数据线,每个像素对应一列电源线和两列感测线;所述四个子像素沿栅线延伸方向依次设置,每个像素对应的电源线设置在第二子像素和第三子像素之间,第一列感测线设置在第一子像素远离第二子像素的一侧,第二列感测线设置在第四子像素远离第三子像素的一侧;所述第一子像素对应的数据线位于所述第一子像素靠近第二子像素的一侧,所述第二子像素对应的数据线位于所述第二子像素靠近第一子像素的一侧,所述第三子像素对应的数据线位于所述第三子像素靠近第四子像素的一侧,所述第四子像素对应的数据线位于所述第四子像素靠近第三子像素的一侧。
- 根据权利要求11所述的显示基板,还包括:设置在多个晶体管的有源层靠近基底一侧的缓冲层和遮光层;以及与感测线连接的感测连接线;所述遮光层设置在缓冲层靠近基底的一侧,所述感测连接线与所述遮光层同层设置,所述遮光层在基底上的正投影覆盖所述驱动晶体管的有源层的有效区域;对于每个子像素,感测晶体管的第一极通过感测连接线与感测线连接。
- 根据权利要求13所述的显示基板,还包括:设置在多个晶体管的有源层和多个晶体管的栅电极之间的栅绝缘层以及设置在多个晶体管的有源层和多个晶体管的源漏电极之间的层间绝缘层;所述栅绝缘层在基底上的正投影与所述多个晶体管的栅电极在基底上的正投影重合,第一过孔设置在所述层间绝缘层上。
- 一种显示装置,其特征在于,包括如权利要求1至14任一项所述的显示基板。
- 一种显示基板的制作方法,用于制作如权利要求1至14任一项所述的显示基板,所述方法包括:在基底上形成栅线、数据线、电源连接线以及由栅线和数据线交叉限定的多个子像素;其中,每个子像素包括驱动电路;所述驱动电路包括:多个晶体管和存储电容;多个晶体管包括:开关晶体管、驱动晶体管和感测晶体管;所述存储电容的第一电极分别与开关晶体管的第二极和驱动晶体管的栅电极连接,所述存储电容的第二电极分别与驱动晶体管的第二极和感测晶体管的第二极连接,对于每个子像素,驱动晶体管的第一极与电源连接线连接;所述电源连接线与多个晶体管的栅电极同层设置;查找由栅线和数据线短路形成的不良点;其中,形成所述不良点的栅线 为不良栅线,形成不良点的数据线为不良数据线,第一修复子像素和第二修复子像素分别位于不良数据线两侧,且与不良栅线连接,与第一修复子像素和第二修复子像素连接的电源连接线为不良电源连接线;将不良栅线和不良电源连接线断开,在第一修复子像素和第二修复子像素中形成修复线,以对显示基板进行修复,所述修复线设置在多个晶体管的源漏电极远离基底一侧,所述修复线分别与部分断开设置的栅线和部分断开设置的不良电源连接线连接,且用于传输扫描信号,以对显示基板进行修复。
- 根据权利要求16所述的方法,其中,所述在基底上形成栅线、数据线、电源连接线以及由栅线和数据线交叉限定的多个子像素包括:在基底上形成遮光层和感测连接线;在遮光层和感测连接线上形成缓冲层;在缓冲层上形成多个晶体管的有源层和存储电容的第一电极;在多个晶体管的有源层和存储电容的第一电极上形成栅绝缘层;在栅绝缘层上形成栅线、多个晶体管的栅电极和电源连接线;在栅线、多个晶体管的栅电极和电源连接线上形成层间绝缘层;在层间绝缘层上形成数据线、电源线、感测线和多个晶体管的源漏电极。
- 根据权利要求17所述的方法,其中,所述将不良栅线和不良电源连接线断开包括:采用激光工艺沿栅线排布方向将不良栅线切割成相互断开的第一扫描部、第二扫描部和第三扫描部;其中,所述第二扫描部在基底上的正投影与所述不良数据线在基底上的正投影存在重叠区域,所述第一扫描部与位于所述不良数据线靠近所述第一修复子像素的一侧的子像素中开关晶体管的栅电极连接;所述第三扫描部与位于不良数据线靠近所述第二修复子像素的一侧的子像素中开关晶体管的栅电极连接;采用激光工艺沿栅线排布方向将不良电源连接线切割成相互断开的第一连接部、第二连接部和第三连接部;其中,所述第一连接部在基底上的正投影与第一修复子像素中的驱动晶体管的第一极存在重叠区域,且与第一修复 子像素中的驱动晶体管的第一极连接,所述第三连接部在基底上的正投影与第二修复子像素中的驱动晶体管的第一极存在重叠区域,且与第二修复子像素中的驱动晶体管的第一极连接,所述第二连接部在基底上的正投影与第一修复子像素和第二子修复子像素中的开关晶体管的第二极存在重叠区域,所述第二连接部与修复线连接;采用激光工艺在第一子像素和第二子像素中形成第一凹槽、第二凹槽、第一过孔和第二过孔;其中,第一凹槽贯穿所述第一凹槽所在子像素中开关晶体管的有源层,且所述第一凹槽在基底上的正投影位于所述第一凹槽所在子像素中开关晶体管的第一极在基底上的正投影和所述第一凹槽所在子像素中开关晶体管的栅电极在基底上的正投影之间;所述第二凹槽贯穿所述第二凹槽所在子像素中开关晶体管的第二极,且所述第二凹槽在基底上的正投影位于所述电源连接线在基底上的正投影和所述第二凹槽所在子像素的驱动晶体管的栅电极在基底上的正投影之间;其中,第一修复子像素中的第一过孔用于暴露第一扫描部,第二修复子像素中的第一过孔用于暴露第三扫描部,所述第二过孔用于暴露第二连接部。
- 根据权利要求18所述的方法,其中,所述在第一修复子像素和第二修复子像素中形成修复线,以对显示基板进行修复包括:在所述第一子像素和所述第二子像素上沉积金属薄膜;通过构图工艺在第一子像素中形成第一修复部,在第二子像素中形成第二修复部,以形成修复线;所述第一修复部通过第一修复子像素中的第一过孔与第一修复部连接,所述第一修复部通过第一修复子像素中的第二过孔与第二连接部连接;所述第二修复部通过第二修复子像素中的第一过孔与第三扫描部连接;所述第二修复部通过第二修复子像素中的第二过孔与第二连接部连接。
- 根据权利要求19所述的方法,还包括:在数据线、电源线、感测线和多个晶体管的源漏电极上形成存储电容的第二电极。
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