WO2021082159A1 - 半导体功率器件终端结构 - Google Patents

半导体功率器件终端结构 Download PDF

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WO2021082159A1
WO2021082159A1 PCT/CN2019/121675 CN2019121675W WO2021082159A1 WO 2021082159 A1 WO2021082159 A1 WO 2021082159A1 CN 2019121675 W CN2019121675 W CN 2019121675W WO 2021082159 A1 WO2021082159 A1 WO 2021082159A1
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Prior art keywords
trench
power device
semiconductor power
electrode
terminal structure
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PCT/CN2019/121675
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English (en)
French (fr)
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龚轶
刘磊
刘伟
王鑫
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苏州东微半导体有限公司
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Priority to US17/428,151 priority Critical patent/US20220254875A1/en
Publication of WO2021082159A1 publication Critical patent/WO2021082159A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Definitions

  • This application belongs to the technical field of semiconductor power devices, and for example relates to a terminal structure of a semiconductor power device.
  • High-voltage semiconductor devices IGBT, VDMOS, etc., as the third-generation power electronic products, are more and more widely used in the field of power electronics due to their high operating frequency, fast switching speed, and high control efficiency, such as automotive electronics, consumer electronics, and switching Power boxes are widely used in industrial control (such as relays, electronic ballasts for energy-saving lamps, motor frequency conversion speed regulation, high-frequency heating, motor drives, audio equipment for household appliances, switching power supplies, etc.).
  • the blocking capability of high-voltage power semiconductor devices is a very important indicator of the level of development. Depending on the application, the breakdown voltage can range from 25V to 6500V.
  • the semiconductor process uses a planar terminal structure, the junction depth is shallow and the junction edge Bending makes the withstand voltage lower, the withstand voltage stability is poor, the safe working area of the device is small, and the device is easy to be damaged. Therefore, in order to improve and stabilize the withstand voltage characteristics of the device, in addition to the coordination of the various parameters in the device body, it is more important to properly treat the surface-terminated pn junction to improve the electric field distribution at the edge of the device, reduce the surface electric field concentration, and improve The voltage resistance and stability of the device.
  • the present application provides a semiconductor power device terminal structure to improve the voltage resistance and stability of the semiconductor power device.
  • At least one groove comprising two parts: an upper part of the groove and a lower part of the groove;
  • the first electrode located in the upper part of the trench and the second electrode located at least in the lower part of the trench, the second electrode, the first electrode, and the n-type epitaxial layer are separated by an insulating medium Layer isolation
  • a first p-type doped region adjacent to the trench is adjacent to the trench.
  • the first p-type doped region described in the present application is externally connected to a source voltage.
  • the depth of the first p-type doped region in the present application is greater than the depth of the trench, and the first p-type doped region covers and surrounds all or part of the trench.
  • the thickness of the insulating dielectric layer between the second electrode and the n-type epitaxial layer of the present application is greater than or equal to the insulating layer between the first electrode and the n-type epitaxial layer The thickness of the dielectric layer.
  • the present application further includes a second p-type doped region located in the first p-type doped region, and the doping concentration of the second p-type doped region is greater than that of the first p-type doped region Doping concentration of the zone.
  • the width of the upper part of the groove in the present application is greater than the width of the lower part of the groove.
  • the second electrode of the present application extends upward into the upper part of the groove.
  • the second electrode of the present application divides the first electrode into two parts in the upper part of the trench.
  • the present application further includes an insulating layer covering the trench and a metal layer covering the insulating layer.
  • the metal layer described in this application is connected to an external source voltage.
  • FIG. 1 is a schematic cross-sectional structure diagram of a first embodiment of a semiconductor power device terminal structure provided by the present application
  • FIG. 2 is a schematic cross-sectional structure diagram of a second embodiment of a semiconductor power device terminal structure provided by the present application.
  • FIG. 3 is a schematic cross-sectional structure diagram of a third embodiment of a semiconductor power device terminal structure provided by the present application.
  • FIG. 1 is a schematic cross-sectional structure diagram of a first embodiment of a semiconductor power device terminal structure provided by the present application.
  • a semiconductor power device terminal structure provided by an embodiment of the present application includes an n-type epitaxial layer 20, and at least one trench 40 located in the n-type epitaxial layer 20.
  • FIG. 1 exemplarily shows four trenches 40.
  • the trench 40 includes a trench upper portion 41 and a trench lower portion 42, as shown in FIG.
  • the width of the upper part 41 of the trench 40 in the semiconductor power device terminal structure shown is greater than the width of the lower part 42 of the trench.
  • the second electrode 22, the first electrode 23, and the n-type epitaxial layer 20 are separated by an insulating dielectric layer 24.
  • the material of the insulating dielectric layer 24 is usually silicon oxide, and the material of the first electrode 23 and the second electrode 22 is usually polysilicon. Based on the selection of the manufacturing process of the semiconductor power device, the thickness of the insulating dielectric layer 24 between the second electrode 22 and the n-type epitaxial layer 20 is greater than or equal to the insulating dielectric layer 24 between the first electrode 23 and the n-type epitaxial layer 20 thickness of.
  • the thickness of the oxide layer between the second electrode 22 and the n-type epitaxial layer 20 may be greater than or equal to that between the first electrode 23 and the n-type epitaxial layer 20 The thickness of the oxide layer.
  • the second electrode 22 may extend upward into the upper portion 41 of the trench.
  • the first electrode 23 may still be a part of the connection in the upper portion 41 of the trench.
  • One electrode 23 can also be divided into two parts by the second electrode 22 in the upper part 41 of the trench (as shown in FIG. 1).
  • the depth of the first p-type doped region 21 is greater than the depth of the trench 40.
  • the first p-type doped region 21 may cover and surround the trench 40 .
  • the depth of the first p-type doped region 21 may also be equal to or less than the depth of the trench 40 (FIG. 2 is a schematic cross-sectional structure diagram of a second embodiment of a semiconductor power device terminal structure provided in this application, In this embodiment, the depth of the first p-type doped region 21 is smaller than the depth of the trench 40).
  • the doping concentration of the second p-type doped region 25 is greater than the doping concentration of the first p-type doped region 21.
  • the second p-type doped region 25 is externally connected to the source voltage through the metal layer 27.
  • the second p-type doped region 25 may not be formed in the first p-type doped region 21. In this case, the first p-type doped region 21 can directly connect to the source voltage through the metal layer 27.
  • an n-type doped region may also be formed in the second p-type doped region 25, which is not shown in the embodiment of the present application.
  • the terminal structure of the semiconductor power device can adjust the longitudinal electric field distribution near the trench, reduce the electric field at the bottom of the trench (that is, at the bottom of the trench), and improve the withstand voltage of the semiconductor power device.
  • the thick oxide capacitor between the second electrode and the n-type epitaxial layer can fix the movable charge in the terminal of the semiconductor power device, thereby improving the reliability of the semiconductor power device.
  • a semiconductor power device terminal structure provided in the present application may further include an insulating layer 26 covering the trench 40 and a metal layer 27 covering the insulating layer 26, and the metal layer 27 is externally connected to the source voltage.
  • the metal layer 27 and the insulating layer 26 simultaneously cover the trench 40 and the n-type epitaxial layer 20.
  • the insulating layer and the metal layer may only Covering the part of the trench 40, at this time, the metal layer can be externally connected to the source voltage, or floating without being connected to the source voltage.
  • FIG. 3 is a schematic cross-sectional structure diagram of a third embodiment of a semiconductor power device terminal structure provided by the present application.
  • a semiconductor power device terminal structure according to an embodiment of the present application includes four trenches 40 The depth of the first p-type doped region 21 is greater than the depth of the trench 40. At this time, the first p-type doped region 21 only covers a part of the trench 40.
  • the semiconductor power device terminal structure of the embodiment of the present application can adjust the longitudinal electric field distribution near the trench, so that the electric field distribution in the first p-type doped region is concentrated at the bottom position of the upper part of the trench and the bottom of the lower part of the trench In this way, the electric field at the bottom of the trench (ie the bottom position of the bottom of the trench) can be reduced, and the withstand voltage of the semiconductor power device can be improved.
  • the second An electric field distribution in the p-type doped region when the trench is all covered and surrounded by the first p-type doped region.
  • the thick oxide layer capacitance can fix the movable charge in the terminal of the semiconductor power device, and improve the reliability of the semiconductor power device; and
  • the thin oxide layer between the first electrode and the n-type epitaxial layer can alleviate the problem of the surface stress imbalance of the n-type epitaxial layer caused by the trench between the terminal of the semiconductor power device and the active region.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种半导体功率器件终端结构，包括：n型外延层（20）以及位于所述n型外延层（20）中的：至少一个沟槽（40），所述沟槽（40）包括沟槽上部（41）和沟槽下部（42）两部分；位于所述沟槽上部（41）中的第一电极（23）以及至少位于所述沟槽下部（42）中的第二电极（22），所述第二电极（22）、所述第一电极（23）、所述n型外延层（20）两两之间由绝缘介质层（24）隔离；与所述沟槽（40）相邻的第一p型掺杂区（21）。

Description

半导体功率器件终端结构
本申请要求在2019年10月28日提交中国专利局、申请号为201911030369.6的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请属于半导体功率器件技术领域，例如涉及一种半导体功率器件终端结构。
背景技术
高压半导体器件IGBT、VDMOS等作为第三代电力电子产品，由于其工作频率高、开关速度快、控制效率高而在电力电子领域得到越来越广泛的应用，例如在汽车电子、消费电子、开关电源盒工业控制中得到广泛应用(例如继电器、节能灯电子镇流器、电机变频调速、高频加热、马达驱动、家用电器音响装置、开关稳压电源等)。高压功率半导体器件的阻断能力是衡量发展水平的一个非常重要的标志，依据应用，击穿电压的范围可从25V到6500V，但是由于半导体工艺采用平面型终端结构，结深较浅，结边缘弯曲使得耐压降低、耐压稳定性差、器件的安全工作区较小，器件容易破坏。因此，为了提高和稳定器件的耐压特性，除了器件体内各参数的配合外，更重要的是对表面终止的pn结进行适当的处理，以改善器件边缘的电场分布，减弱表面电场集中，提高器件的耐压能力和稳定性。
发明内容
本申请提供一种半导体功率器件终端结构，以提高半导体功率器件的耐压能力和稳定性。
本申请实施例提供的一种半导体功率器件终端结构，包括：
n型外延层以及位于所述n型外延层中的：
至少一个沟槽，所述沟槽包括沟槽上部和沟槽下部两部分；
位于所述沟槽上部中的第一电极以及至少位于所述沟槽下部中的第二电极，所述第二电极、所述第一电极、所述n型外延层两两之间由绝缘介质层隔离；
与所述沟槽相邻的第一p型掺杂区。
可选的，本申请所述第一p型掺杂区外接源极电压。
可选的，本申请所述第一p型掺杂区的深度大于所述沟槽的深度，所述第一p型掺杂区覆盖包围所有或者部分所述沟槽。
可选的，本申请所述第二电极与所述n型外延层之间的所述绝缘介质层的厚度，大于或等于所述第一电极与所述n型外延层之间的所述绝缘介质层的厚度。
可选的，本申请还包括位于所述第一p型掺杂区中的第二p型掺杂区，所述第二p型掺杂区的掺杂浓度大于所述第一p型掺杂区的掺杂浓度。
可选的，本申请所述沟槽上部的宽度大于所述沟槽下部的宽度。
可选的，本申请所述第二电极向上延伸至所述沟槽上部中。
可选的，本申请所述第二电极在所述沟槽上部内将所述第一电极分割为两部分。
可选的，本申请还包括覆盖所述沟槽的绝缘层以及覆盖所述绝缘层的金属层。
可选的，本申请所述金属层外接源极电压。
附图说明
图1是本申请提供的一种半导体功率器件终端结构的第一个实施例的剖面结构示意图；
图2是本申请提供的一种半导体功率器件终端结构的第二个实施例的剖面结构示意图；
图3是本申请提供的一种半导体功率器件终端结构的第三个实施例的剖面结构示意图。
具体实施方式
以下将结合本申请实施例中的附图，通过实施方式，描述本申请的技术方案。所描述的实施例是本申请的一部分实施例，而不是全部的实施例。
本申请所使用的诸如“具有”、“包含”以及“包括”等术语并不配出一个或多个其它元件或其组合的存在或添加。说明书附图中所列图形大小并不代表实际尺寸，说明书附图是示意性的，不应限定本申请的范围。说明书中所列实施例不应仅限于说明书附图中所示区域的特定形状，而是包括所得到的形状 如制备引起的偏差等。
图1是本申请提供的一种半导体功率器件终端结构的第一个实施例的剖面结构示意图，如图1所示，本申请实施例提供的一种半导体功率器件终端结构，包括n型外延层20，以及位于n型外延层20中的至少一个沟槽40，图1中示例性的示出了4个沟槽40，沟槽40包括沟槽上部41和沟槽下部42，在图1所示的一种半导体功率器件终端结构中沟槽40的沟槽上部41的宽度大于沟槽下部42的宽度。
位于沟槽上部41中的第一电极23以及至少位于沟槽下部42中的第二电极22，第二电极22、第一电极23、n型外延层20两两之间由绝缘介质层24隔离，绝缘介质层24的材质通常为氧化硅，第一电极23和第二电极22的材质通常为多晶硅。基于半导体功率器件的制造工艺的选择，第二电极22与n型外延层20之间的绝缘介质层24的厚度，大于或等于第一电极23与n型外延层20之间的绝缘介质层24的厚度。示例性的，当绝缘介质层24为氧化硅等氧化层时，第二电极22与n型外延层20之间的氧化层的厚度可以大于或等于第一电极23与n型外延层20之间的氧化层的厚度。可选的，第二电极22可以向上延伸至沟槽上部41中，第二电极22向上延伸至沟槽上部41中时，第一电极23可以在沟槽上部41内仍为连接的一部分，第一电极23也可以在沟槽上部41内被第二电极22分割为两部分(如图1所示)。
与沟槽40相邻的第一p型掺杂区21，第一p型掺杂区21的深度大于沟槽40的深度，此时，第一p型掺杂区21可以覆盖包围沟槽40。可选的，第一p型掺杂区21的深度也可以等于或者小于沟槽40的深度(图2是本申请提供的一种半导体功率器件终端结构的第二个实施例的剖面结构示意图，在该实施例中，第一p型掺杂区21的深度小于沟槽40的深度)。
位于第一p型掺杂区21中的第二p型掺杂区25，第二p型掺杂区25的掺杂浓度大于第一p型掺杂区21的掺杂浓度。第二p型掺杂区25通过金属层27外接源极电压。第一p型掺杂区21中也可以不形成第二p型掺杂区25，此时第一p型掺杂区21可以直接通过金属层27外接源极电压。基于半导体功率器件制造工艺的选择，在第二p型掺杂区25中还可以形成有n型掺杂区，在本申请实施例中不在展示。
本申请实施例的一种半导体功率器件终端结构，可以调节沟槽附近的纵向电场分布，降低沟槽底部(即沟槽下部的底部位置处)的电场，提高半导体功率器件的耐压。同时，第二电极与n型外延层之间的厚氧化层电容可以固定半导体功率器件终端中的可动电荷，提高半导体功率器件的可靠性。
本申请提供的一种半导体功率器件终端结构还可以包括覆盖沟槽40的绝缘 层26以及覆盖绝缘层26的金属层27，金属层27外接源极电压。在图1所示的本申请提供的一种半导体功率器件终端结构中，金属层27和绝缘层26同时覆盖了沟槽40和n型外延层20，可选的，绝缘层和金属层可以仅覆盖沟槽40部分，此时金属层可以外接源极电压，也可以浮空不接源极电压。
图3是本申请提供的一种半导体功率器件终端结构的第三个实施例的剖面结构示意图，如图3所示，本申请实施例的一种半导体功率器件终端结构中包含4个沟槽40，第一p型掺杂区21的深度大于沟槽40的深度，此时，第一p型掺杂区21仅覆盖了部分沟槽40。
本申请实施例的一种半导体功率器件终端结构，可以调节沟槽附近的纵向电场分布，使得第一p型掺杂区中的电场分布集中在沟槽上部的底部位置处和沟槽下部的底部位置处，从而可以降低沟槽底部(即沟槽下部的底部位置处)的电场，提高半导体功率器件的耐压，例如当沟槽全部被第一p型掺杂区覆盖包围时，可以调整第一p型掺杂区内的电场分布。在一实施例中，当第二电极与n型外延层之间采用厚的氧化层时，厚的氧化层电容可以固定半导体功率器件终端中的可动电荷，提高半导体功率器件的可靠性；而第一电极与n型外延层之间的薄的氧化层可以缓解半导体功率器件的终端与有源区之间由于沟槽造成的n型外延层表面应力不平衡的问题。
以上实施方式及实施例是对本申请提出的一种半导体功率器件终端结构技术思想的支持，不能以此限定本申请的保护范围。

Claims (10)

  1. 一种半导体功率器件终端结构，包括：
    n型外延层以及位于所述n型外延层中的：
    至少一个沟槽，所述沟槽包括沟槽上部和沟槽下部两部分；
    位于所述沟槽上部中的第一电极以及至少位于所述沟槽下部中的第二电极，所述第二电极、所述第一电极、所述n型外延层两两之间由绝缘介质层隔离；
    与所述沟槽相邻的第一p型掺杂区。
  2. 如权利要求1所述的一种半导体功率器件终端结构，其中，所述第一p型掺杂区外接源极电压。
  3. 如权利要求1所述的一种半导体功率器件终端结构，其中，所述第一p型掺杂区的深度大于所述沟槽的深度，所述第一p型掺杂区覆盖包围所有或者部分所述沟槽。
  4. 如权利要求1所述的一种半导体功率器件终端结构，其中，所述第二电极与所述n型外延层之间的所述绝缘介质层的厚度，大于或等于所述第一电极与所述n型外延层之间的所述绝缘介质层的厚度。
  5. 如权利要求1所述的一种半导体功率器件终端结构，还包括：位于所述第一p型掺杂区中的第二p型掺杂区，所述第二p型掺杂区的掺杂浓度大于所述第一p型掺杂区的掺杂浓度。
  6. 如权利要求1所述的一种半导体功率器件终端结构，其中，所述沟槽上部的宽度大于所述沟槽下部的宽度。
  7. 如权利要求1所述的一种半导体功率器件终端结构，其中，所述第二电极向上延伸至所述沟槽上部中。
  8. 如权利要求7所述的一种半导体功率器件终端结构，其中，所述第二电极在所述沟槽上部内将所述第一电极分割为两部分。
  9. 如权利要求1所述的一种半导体功率器件终端结构，其中，还包括覆盖所述沟槽的绝缘层以及覆盖所述绝缘层的金属层。
  10. 如权利要求9所述的一种半导体功率器件终端结构，其中，所述金属层外接源极电压。
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