WO2021056141A1 - 显示驱动方法、显示驱动电路及显示装置 - Google Patents

显示驱动方法、显示驱动电路及显示装置 Download PDF

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Publication number
WO2021056141A1
WO2021056141A1 PCT/CN2019/107272 CN2019107272W WO2021056141A1 WO 2021056141 A1 WO2021056141 A1 WO 2021056141A1 CN 2019107272 W CN2019107272 W CN 2019107272W WO 2021056141 A1 WO2021056141 A1 WO 2021056141A1
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Prior art keywords
signal
effective pulse
row
start end
source driver
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PCT/CN2019/107272
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English (en)
French (fr)
Inventor
杨燕
洪青桦
刘蕊
孙伟
陈明
黄文杰
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/107272 priority Critical patent/WO2021056141A1/zh
Priority to US16/963,302 priority patent/US11450288B2/en
Priority to CN201980001771.3A priority patent/CN112997240A/zh
Publication of WO2021056141A1 publication Critical patent/WO2021056141A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display driving method, a display driving circuit, and a display device.
  • the purpose of the present disclosure is to provide a display driving method, a display driving circuit and a display device, which can alleviate the problem of insufficient charging time for remote sub-pixel data.
  • the first aspect of the present disclosure provides a display driving method, which includes:
  • the data signal includes a plurality of first effective pulse signals
  • the first effective pulse signal in the Nth row is used to drive the sub-pixel units in the Nth row
  • the start end of the first effective pulse signal in the Nth row The timing difference with the start end of the gate drive signal corresponding to it is smaller than the timing difference between the start end of the first valid pulse signal in the N+Mth row and the start end of the gate drive signal corresponding to it;
  • the sub-pixel units in the Nth row are closer to the source driver than the sub-pixel units in the N+M rows, and N and M are positive integers greater than or equal to 1.
  • controlling the source driver to output a data signal includes:
  • the data output control signal includes a plurality of second effective pulse signals, and each of the first effective pulse signals corresponds to one of the second effective pulse signals.
  • controlling the source driver to output a data signal includes:
  • the data output control signal includes a plurality of second effective pulse signals, and each of the first effective pulse signals corresponds to one of the second effective pulse signals.
  • the first effective pulse signal starts to be output at the start end of the second effective pulse signal
  • the timing difference between the start end of the second effective pulse signal in the Nth row and the start end of the corresponding gate drive signal is less than the difference between the start end of the second effective pulse signal in the N+M row and the corresponding gate drive signal The timing difference at the beginning.
  • the first effective pulse signal starts to be output at the terminal of the second effective pulse signal
  • the timing difference between the terminal of the second effective pulse signal in the Nth row and the start end of the corresponding gate drive signal is smaller than the terminal of the second effective pulse signal in the N+M row and the start end of the corresponding gate drive signal The timing difference.
  • M is greater than 1, where the start end of the first valid pulse signal in the Nth row, the N+1th row...the N+M-1th row and the corresponding gate The timing difference between the start ends of the pole drive signals is equal.
  • the timing difference is 0 to 0.5 ⁇ s.
  • the timing difference between the terminal of the first effective pulse signal in each row and the terminal of the corresponding gate driving signal is greater than or equal to zero.
  • a second aspect of the present disclosure provides a display driving circuit, which includes:
  • the data signal includes a plurality of first effective pulse signals, the first effective pulse signal in the Nth row is used to drive the sub-pixel units in the Nth row, the start end of the first effective pulse signal in the Nth row and the corresponding gate drive signal
  • the timing difference between the starting end of the N+M row is smaller than the timing difference between the starting end of the first valid pulse signal in the N+M row and the starting end of the corresponding gate drive signal;
  • the sub-pixel units in the Nth row are closer to the source driver than the sub-pixel units in the N+M rows, and N and M are positive integers greater than or equal to 1.
  • the controller is a timing controller, and the timing controller is configured to output a data output control signal to the source driver, and control the source based on the data output control signal.
  • the pole driver outputs the data signal;
  • the data output control signal includes a plurality of second effective pulse signals, and each of the first effective pulse signals corresponds to one of the second effective pulse signals.
  • the controller is a timing controller, and the timing controller is configured to output a control signal to the source driver; and control the source driver to generate data according to the control signal Output a control signal, and control the source driver to output a data signal based on the data output control signal;
  • the data output control signal includes a plurality of second effective pulse signals, and each of the first effective pulse signals corresponds to one of the second effective pulse signals.
  • the first effective pulse signal starts to be output at the start end of the second effective pulse signal
  • the timing difference between the start end of the second effective pulse signal in the Nth row and the start end of the corresponding gate drive signal is less than the difference between the start end of the second effective pulse signal in the N+M row and the corresponding gate drive signal The timing difference at the beginning.
  • the first effective pulse signal starts to be output at the terminal of the second effective pulse signal
  • the timing difference between the terminal of the second effective pulse signal in the Nth row and the start end of the corresponding gate drive signal is smaller than the terminal of the second effective pulse signal in the N+M row and the start end of the corresponding gate drive signal The timing difference.
  • a third aspect of the present disclosure provides a display device, which includes a display panel and the display drive circuit described in any one of the above, and the display drive circuit is used to drive the display panel.
  • the display driving method, display driving circuit, and display device provided by the present disclosure include: controlling a source driver to send a data signal.
  • the data signal may include a plurality of first valid pulse signals, and the first valid pulse signal in the Nth row is used for To drive the sub-pixel units in the Nth row, the timing difference between the start end of the first effective pulse signal in the Nth row and the start end of the corresponding gate drive signal is smaller than the start end of the first effective pulse signal in the N+Mth row and its corresponding The timing difference of the starting end of the gate drive signal; wherein, the sub-pixel unit of the Nth row is farther away from the source driver than the sub-pixel unit of the N+Mth row, and N and M are positive integers greater than or equal to 1, so the design It can compensate for the problem of poor data charging of the remote sub-pixel unit due to the data delay caused by the voltage drop, that is, the data charging time of the remote sub-pixel unit can be increased.
  • FIG. 1 shows a timing diagram of various signals in a display driving method in the prior art
  • FIG. 3 shows a simulation result diagram of the data fall time of the farthest sub-pixel unit and the near-terminal pixel unit in the prior art
  • FIG. 4 shows a simulation result diagram of various charging rates of a display panel in a display device in the prior art
  • FIG. 5 shows a timing diagram of various signals in the display driving method according to an embodiment of the present disclosure
  • FIG. 6 shows a timing diagram of various signals in a display driving method according to another embodiment of the present disclosure
  • FIG. 7 shows a block diagram of a display driving circuit according to an embodiment of the present disclosure
  • FIG. 8 shows a block diagram of a display driving circuit according to another embodiment of the present disclosure.
  • Fig. 9 shows a block diagram of a display device according to an embodiment of the present disclosure.
  • the problem of insufficient charging rate caused by this needs to be solved urgently.
  • the end closer to the source driver ie, the near-terminal pixel unit
  • the end farther from the source driver ie, the remote sub-pixel unit
  • the problem of insufficient time is that the charging rate gradually decreases from the near end to the far end of the source driver.
  • the data signal (ie: theoretical data signal) Data1 output by the source driver includes a plurality of data pulse signals, and the data pulse signal of the Nth row is used to drive the sub-pixel units of the Nth row (ie: near Terminal pixel unit), the N+M row data pulse signal is used to drive the N+M row sub-pixel unit (ie: remote sub-pixel unit), where the start end of the Nth row data pulse signal and the Nth row gate
  • the timing difference between the start end of the gate drive signal GateN and the start end of the data pulse signal of the N+M row and the timing difference between the start end of the gate drive signal GateN+M of the N+M row and the gate drive signal GateN+M are equal, and both are t.
  • the gate drive signal GateN(GateN+M) in the Nth row (N+M row) is used to drive the thin film transistor (TFT, Thin Film Transistor) of the sub-pixel unit in the Nth row (N+M row) to turn on , So that the Nth row (N+Mth row) sub-pixel unit receives the Nth row (N+Mth row) data pulse signal.
  • TFT Thin Film Transistor
  • the data signal actually received by a column of sub-pixel units is Data2.
  • the rising edge of the data pulse signal received by the sub-pixel units of the N+M row is compared with that of the sub-pixels of the Nth row.
  • the rising edge of the data pulse signal received by the unit is too wide. Therefore, the data delay of the sub-pixel unit of the N+M row is more serious than the data delay of the sub-pixel unit of the Nth row, which makes the charging time of the sub-pixel unit of the N+M row T2 is less than the charging duration T1 of the Nth row of sub-pixel units.
  • FIG. 2 shows the farthest sub-pixel unit (that is, the sub-pixel unit farthest from the source driver) and the near-terminal pixel unit (that is, the sub-pixel unit that is closer to the source driver than the farthest sub-pixel unit).
  • Figure 3 shows the simulation result of the data rising time (Falling Time) of the remote sub-pixel unit and the near-terminal pixel unit.
  • the dotted line in Figure 3 can be
  • the solid line may be the data rise time of the near-terminal pixel unit;
  • the dotted line in FIG. 3 is the data fall time of the farthest sub-pixel unit, and the solid line is the data fall time of the near-terminal pixel unit.
  • the position where the data of the farthest sub-pixel unit begins to climb and the position where the data of the farthest sub-pixel unit begins to fall are compared with the position where the data of the nearest pixel unit begins to climb.
  • the position where the data of the near-terminal pixel unit begins to fall is more serious.
  • the simulation results shown in Figures 2 and 3 show that the data delay time of the farthest sub-pixel unit is about 0.4 ⁇ s, but it is not limited to this. The specific value needs to be Determined according to the characteristics of the display panel.
  • the remote sub-pixel unit since the data delay of the remote sub-pixel unit is more serious than that of the near-terminal pixel unit, when the Thin Film Transistor (TFT) of the sub-pixel unit is turned on row by row, the remote sub-pixel unit The charging time of the pixel unit is shorter than that of the near-terminal pixel unit, so that the charging rate of the remote sub-pixel unit is smaller than the charging rate of the near-terminal pixel unit.
  • TFT Thin Film Transistor
  • the display panel 10 is divided into two columns, in which position 1, position 2, and position 3 are one column. From position 3 ⁇ position 2 ⁇ position 1, the corresponding charging rate From 87.36% ⁇ 79.85% ⁇ 79.48%; No. 4, No. 5 and No. 6 positions are in a row, from No. 6 position ⁇ No. 5 position ⁇ No. 4 position, the corresponding charging rate is from 90.10% ⁇ 84.49% ⁇ 84.22% That is, from the near end to the far end of the source driver 12, the charging rate gradually decreases.
  • this embodiment only intends to show that the charging rate gradually decreases from the near end to the far end of the source driver, but the value of the charging rate is not limited to this, and the specific value needs to be determined according to the characteristics of the display panel.
  • the charging rate of the sub-pixel unit will not only be affected by the positional relationship between it and the source driver, but also by other influences, such as the positional relationship between it and the gate driver. Therefore, although the distances between the positions marked 3 and 6 from the source driver in FIG. 4 are basically the same, the charging rate will still be different.
  • the display driving method may include:
  • the data signal Data1 output by the source driver may include a plurality of first valid pulse signals (ie: data pulse signals), the first valid pulse signal in the Nth row
  • the timing difference t1 between the start end of the first effective pulse signal in the Nth row and the start end of the corresponding gate drive signal GateN is smaller than that of the first effective pulse signal in the N+Mth row
  • the timing difference between the start end and the start end of the gate drive signal GateN+M corresponding to it is t2.
  • the sub-pixel unit in the Nth row is closer to the source driver than the sub-pixel unit in the N+M row, and N and M are positive integers greater than or equal to 1.
  • the sub-pixel unit of the Nth row may be the aforementioned near-terminal pixel unit.
  • the first effective pulse signal of the Nth row may be defined as the first effective pulse signal of the near-end;
  • the pixel unit may be the aforementioned remote sub-pixel unit.
  • the first effective pulse signal of the N+Mth row may be defined as the first effective pulse signal of the remote end.
  • the timing difference between the start end of the first effective pulse signal of the remote sub-pixel unit (ie, the sub-pixel unit of the N+M row) and the start end of the corresponding gate drive signal GateN+M is t2 It is greater than the timing difference t1 between the start end of the first effective pulse signal of the near-terminal pixel unit (ie: the sub-pixel unit in the Nth row) and the start end of the corresponding gate drive signal GateN.
  • This design makes the remote sub-pixel unit compare The near-terminal pixel unit enters the data charging stage earlier, so as to compensate for the problem of poor data charging of the remote sub-pixel unit due to the data delay caused by the voltage drop.
  • the data charging time of the remote sub-pixel unit can be increased to make the remote sub-pixel unit longer.
  • the data charging time of the terminal pixel unit is not much different from the data charging time of the near-terminal pixel.
  • the data charging time T4 of the N+M row sub-pixel unit in FIG. 5 is equal to the data charging time T3 of the Nth row sub-pixel unit. , Which can then improve the display effect.
  • the starting end of the gate drive signal when the gate drive signal is active at high level, the starting end of the gate drive signal is its rising edge, and its terminal is its falling edge; and when the gate drive signal is active at low level, The starting end of the gate drive signal is its falling edge, and the terminal is its rising edge; in the same way, when the first effective pulse signal is active at high level, the starting end of the first effective pulse signal is its rising edge. The terminal is its falling edge; and when the first effective pulse signal is active low, the start of the first effective pulse signal is its falling edge, and the terminal is its rising edge.
  • the present embodiment can use the data output
  • the control signal TP controls the source driver to output the data signal Data1, that is, the output position of the data signal Data1 is changed by modifying the position of the data output control signal TP, so that it is only the first effective pulse for the near and far ends without changing the total time of one frame. The position of the signal is shifted.
  • controlling the source driver to output the data signal through the data output control signal TP may specifically include the following two solutions:
  • controlling the source driver to output the data signal may include:
  • Step S100 using the timing controller to output a data output control signal TP to the source driver
  • Step S102 controlling the source driver to output the data signal Data1 based on the data output control signal TP.
  • the data output control signal TP ultimately used to control the source driver to output the aforementioned data signal Data1 is generated inside the timing controller, and the timing controller transmits the internally generated data output control signal TP.
  • the source driver In the source driver, the source driver generates a corresponding data signal Data1 according to the data output control signal TP, and outputs the data signal Data1.
  • controlling the output data signal of the source driver may include:
  • Step S200 using the timing controller to output a control signal to the source driver
  • Step S202 controlling the source driver to generate a data output control signal TP according to the control signal
  • Step S204 controlling the source driver to output the data signal Data1 based on the data output control signal TP.
  • control signal output by the timing controller to the source driver can be an initial data output control signal, and this initial data output control signal can be sent to a component of the source driver, which can control the initial data output
  • the signal is modified to generate the final data output control signal TP, and the component can send the final data output control signal TP to another component of the source driver, and this other component can be controlled by the final data output
  • the signal TP generates a corresponding data signal Data1, and outputs this data signal Data1.
  • the data output control signal TP includes a plurality of second effective pulse signals (ie, effective TP pulse signals), and each first effective pulse signal corresponds to a second effective pulse signal.
  • the second effective pulse signal may be a high-level effective signal.
  • the start end of the second effective pulse signal should be Its rising edge, the terminal of the second valid pulse signal should be its falling edge.
  • the second effective pulse signal can also be a low-level effective signal.
  • the second effective pulse signal can be a low-level effective signal, the starting end of the second effective pulse signal should be its falling edge.
  • the terminal of a valid pulse signal should be its rising edge.
  • the relationship between the transmission of the data signal Data1 and the data output control signal TP may specifically include the following two situations:
  • the first case the first effective pulse signal starts to be output at the beginning of the second effective pulse signal, which can be applied to high frame rate display products.
  • the start end of the second effective pulse signal in the Nth row and the corresponding gate drive signal GateN should be The timing difference t1 at the start end is smaller than the timing difference t2 between the start end of the second valid pulse signal in the N+M row and the start end of the corresponding gate drive signal GateN+M, so that the first valid pulse signal in the Nth row can be guaranteed
  • the timing difference t1 between the start end of the gate drive signal GateN and the start end of the corresponding gate drive signal GateN is smaller than the timing difference between the start end of the first valid pulse signal in the N+M row and the start end of the gate drive signal GateN+M corresponding to it t2.
  • the second case the first effective pulse signal starts to be output at the end of the second effective pulse signal.
  • the end of the second effective pulse signal in the Nth row and the start end of the corresponding gate drive signal GateN should be made
  • the timing difference t1 is smaller than the timing difference t2 between the end of the second valid pulse signal in the N+M row and the start end of the corresponding gate drive signal GateN+M, so as to ensure the start of the first valid pulse signal in the Nth row
  • the timing difference t1 with the start end of the gate drive signal GateN corresponding to it is smaller than the timing difference t2 between the start end of the first valid pulse signal in the N+M row and the start end of the gate drive signal GateN+M corresponding to it.
  • the data output control signal TP can be used as the trigger signal of the data signal Data1, that is, the data output control signal TP can be used to control the output of the data signal Data1.
  • the first effective pulse signal is in the second Whether the starting end of the effective pulse signal is output or the end of the second effective pulse signal is output, depending on the actual situation.
  • M may be equal to 1, so that from the near end to the far end of the source driver, the timing difference between the start end of the first effective pulse signal and the start end of the corresponding gate drive signal increases line by line , That is: the timing difference between the start end of the first effective pulse signal of the previous line (the line close to the source driver) and the start end of the corresponding gate drive signal in the two adjacent lines is smaller than that of the next line (far away from the source driver).
  • the start end (terminal) of the second effective pulse signal should be set The timing difference with the starting end of the gate drive signal corresponding to it increases row by row.
  • M may be greater than 1, where the start end of the first valid pulse signal in the Nth row, the N+1th row...the N+M-1th row and the corresponding gate drive signal The timing difference at the beginning is equal.
  • multiple rows ie, M rows
  • the display panel may include multiple groups of sub-pixel units, and each group of sub-pixel units is composed of M rows of sub-pixel units, wherein the starting end of the first effective pulse signal of each row in each group of sub-pixel units and the corresponding gate
  • the timing difference between the start ends of the driving signals is equal, and the first effective pulse signal of the first group (the group close to the source driver) in the adjacent two groups of sub-pixel units and the corresponding gate driving signal
  • the timing difference of the start end is smaller than the timing difference between the start end of the first effective pulse signal of the latter group (the group far from the source driver) and the start end of the corresponding gate drive signal.
  • the starting end of the first effective pulse signal from the first row, the second row...the 15th row and the corresponding The timing difference between the starting ends of the gate drive signals is equal; the timing difference between the starting end of the first valid pulse signal from the 16th row, the 17th row...the 30th row and the starting end of the corresponding gate drive signal is equal; And the timing difference between the start end of the first effective pulse signal in the 16th row and the start end of the corresponding gate drive signal is greater than the start end of the first effective pulse signal in the 15th row and the start end of the corresponding gate drive signal.
  • the timing difference at the beginning that is: each group of sub-pixel units is composed of 15 rows of sub-pixel units
  • M can be 15 to 1000, but is not limited to this, and the specific value needs to be determined according to the characteristics of the display panel.
  • each group The timing difference between the start end (terminal) of the second effective pulse signal of each row in the sub-pixel unit and the start end of the corresponding gate drive signal is equal, and the first group of the adjacent two groups of sub-pixel units (close to the source driver) The timing difference between the start end (terminal) of the second effective pulse signal and the start end of the corresponding gate drive signal is smaller than that of the second effective pulse signal of the latter group (the one far from the source driver) The timing difference between the start end (terminal) and the start end of the corresponding gate drive signal.
  • the timing difference between the start end of the first effective pulse signal and the start end of the corresponding gate driving signal may be 0 to 0.5 ⁇ s.
  • the data delay time of the farthest sub-pixel unit is about 0.4 ⁇ s. Therefore, in order to compensate for the problem of poor data charging of the farthest sub-pixel unit due to data delay , The time for the farthest sub-pixel unit to enter the data charging phase can be advanced by about 0.4 ⁇ s, but it is not limited to this, and the specific value needs to be determined according to the characteristics of the display panel.
  • the start end of the first effective pulse signal of each row is usually earlier than the start end of the corresponding gate drive signal, that is to say, the first effective pulse signal of each row is usually
  • the timing difference between the start end of an effective pulse signal and the start end of the corresponding gate drive signal is greater than 0. Therefore, in order to improve the charging effect of the farthest sub-pixel unit, the first effective pulse signal of the farthest sub-pixel unit
  • the timing difference between the starting end of the gate drive signal and the starting end of the corresponding gate drive signal should actually be greater than 0.4 ⁇ s.
  • the charging duration of the sub-pixel unit is related to the effective duration of the gate drive signal (the effective duration is the time difference between the terminal and the start of the gate drive signal), specifically, The starting end of the gate drive signal starts to charge the sub-pixel unit, and the charge ends at the terminal of the gate drive signal. Therefore, in order to further ensure the charging time of each sub-pixel unit, it is necessary to ensure that the terminal of the first effective pulse signal of each row and its corresponding The timing difference between the terminals of the gate drive signal is greater than or equal to zero.
  • the effective duration of the first effective pulse signal used to drive each sub-pixel unit can be the same, but is not limited to this, and can also be
  • the effective duration of the first effective pulse signal at the far end ie: the first effective pulse signal for driving the remote sub-pixel unit
  • the effective duration of the signal depends on the specific situation.
  • the display driving method of this embodiment can send instructions to the source driver through the timing controller, and the source driver receives the instructions to control the output position of the data signal.
  • the specific design can be: control signal settings between groups It should be completely independent. It should be understood that the group mentioned here includes multiple rows of sub-pixel units. The number of rows of sub-pixel units in each group can be 15 to 1000. The number of rows is adjustable. Specifically, it can be matched with MCU (micro-control Unit) design.
  • the data output control signal TP is moved to control the output position of the data signal Data1, so that the remote sub-pixel unit can get more charging time.
  • an embodiment of the present disclosure also provides a display driving circuit, which can use the display driving method described in any of the foregoing embodiments to drive a display panel. Therefore, the display of this embodiment
  • the beneficial effects of the driving circuit are the same as those of the display driving method of any of the foregoing embodiments, and the beneficial effects produced by the display driving circuit will not be described in detail herein.
  • the display driving circuit may include a controller 11 and a source driver communicatively connected with the controller 11.
  • the controller 11 is used to control the source driver to output a data signal, and the data signal includes multiple A first effective pulse signal, the first effective pulse signal in the Nth row is used to drive the sub-pixel units in the Nth row, and the timing of the start end of the first effective pulse signal in the Nth row and the start end of the corresponding gate drive signal GateN
  • the difference t1 is smaller than the timing difference t2 between the start end of the first valid pulse signal in the N+M row and the start end of the gate drive signal GateN+M corresponding to it.
  • the sub-pixel unit in the Nth row is closer to the source driver than the sub-pixel unit in the N+M row, and N and M are positive integers greater than or equal to 1.
  • the controller 11 is a timing controller, and the timing controller is used to control the source driver to output a data signal.
  • the timing controller can include the following two programs:
  • the timing controller is used to output a data output control signal to the source driver, and control the source driver to output a data signal based on the data output control signal.
  • the second solution the timing controller is used to output a control signal to the source driver; the source driver is controlled according to the control signal to generate a data output control signal, and the source driver is controlled to output a data signal based on the data output control signal.
  • the data output control signal in any of the solutions includes a plurality of second effective pulse signals, and each first effective pulse signal corresponds to a second effective pulse signal.
  • the first effective pulse signal starts to be output at the start end of the second effective pulse signal
  • the timing difference between the start end of the second effective pulse signal in the Nth row and the start end of the corresponding gate drive signal is less than the difference between the start end of the second effective pulse signal in the N+M row and the corresponding gate drive signal The timing difference at the beginning.
  • the first effective pulse signal starts to be output at the end of the second effective pulse signal
  • the timing difference between the terminal of the second effective pulse signal in the Nth row and the start end of the corresponding gate drive signal is smaller than the terminal of the second effective pulse signal in the N+M row and the start end of the corresponding gate drive signal The timing difference.
  • the timing controller 13 may include a first signal receiving unit (first Rx unit) 130, a color control unit (ACC unit) 131, a compensation unit (OD unit) 132, and a supplementary charging unit (VCC unit) 133.
  • first Rx unit first signal receiving unit
  • ACC unit color control unit
  • OD unit compensation unit
  • VCC unit supplementary charging unit
  • source driver 12 may include a second signal receiving unit (second Rx unit) 120, level conversion unit (LS unit) 121, digital-to-analog conversion The unit (DAC unit) 122 and the output unit (OP unit) 123, wherein the Tx unit 135 in the timing controller 13 sends a signal to the second Rx unit 120 of the source driver 12, and other units of the source driver 12 (for example: The LS unit 121, the DAC unit 122, etc.) can process the signal received by the second Rx unit 120 to convert it into a data signal, which can be output by the OP unit 123.
  • the units in the timing controller 13 and the units in the source driver 12 mentioned in this embodiment have conventional structures, which have the same functions as the conventional units. These unit structures are not disclosed in the present disclosure. The main improvement points, therefore, will not be explained in detail.
  • the display driving circuit may not only include the aforementioned timing controller 13 and the source driver 12, but also include a gate driver 14, which can interact with The timing controller 13 is communicatively connected, and the timing controller 13 can control the gate driver 14 to send the aforementioned gate signals.
  • the embodiment of the present disclosure also provides a display device, which includes: a display panel and the display driving circuit described in any of the foregoing embodiments.
  • the display driving circuit may include a timing controller 13 and a source driver. 12 and a gate driver 14.
  • the display driving circuit is used to drive a display panel.
  • the display panel can be a liquid crystal display panel, but is not limited to this.
  • the specific type of the display device is not particularly limited, and all types of display devices commonly used in the art can be used, such as liquid crystal displays or mobile devices with liquid crystal displays, wearable devices, VR devices, etc., Those skilled in the art can make a corresponding selection according to the specific purpose of the display device, which will not be repeated here.

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Abstract

一种显示驱动方法、显示驱动电路及显示装置。该显示驱动方法包括：控制源极驱动器（12）输出数据信号，数据信号包括多个第一有效脉冲信号，第N行第一有效脉冲信号用于驱动第N行子像素单元，第N行第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差小于第N+M行第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差；其中，第N行子像素单元相比于第N+M行子像素单元靠近源极驱动器（12），N、M为大于或等于1的正整数。能够改善远端子像素数据充电时间不够的问题。

Description

显示驱动方法、显示驱动电路及显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示驱动方法、显示驱动电路及显示装置。
背景技术
当显示面板的帧频越来越高时，使得一帧的时间越来越短，从而使得分配到每个子像素单元的充电时间越来越短，为了实现更好的充电效果，合理的分配每个子像素单元的充电时间，使其达到更好的充电效果变得越来越重要。
发明内容
本公开的目的在于提供一种显示驱动方法、显示驱动电路及显示装置，能够改善远端子像素数据充电时间不够的问题。
本公开第一方面提供了一种显示驱动方法，其包括：
控制源极驱动器输出数据信号，所述数据信号包括多个第一有效脉冲信号，第N行第一有效脉冲信号用于驱动第N行子像素单元，第N行第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差小于第N+M行第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差；
其中，第N行子像素单元相比于第N+M行子像素单元靠近所述源极驱动器，N、M为大于或等于1的正整数。
在本公开的一种示例性实施例中，所述控制源极驱动器输出数据信号，包括：
利用时序控制器向所述源极驱动器输出数据输出控制信号；
基于所述数据输出控制信号控制所述源极驱动器输出数据信号；
其中，所述数据输出控制信号包括多个第二有效脉冲信号，且每一所述第一有效脉冲信号对应一所述第二有效脉冲信号。
在本公开的一种示例性实施例中，所述控制源极驱动器输出数据信号，包括：
利用时序控制器向所述源极驱动器输出控制信号；
根据所述控制信号控制所述源极驱动器生成数据输出控制信号；
基于所述数据输出控制信号控制所述源极驱动器输出数据信号；
其中，所述数据输出控制信号包括多个第二有效脉冲信号，且每一所述第一有效脉冲信号对应一所述第二有效脉冲信号。
在本公开的一种示例性实施例中，所述第一有效脉冲信号在所述第二有效脉冲信号的起始端开始输出，
其中，第N行第二有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差 小于第N+M行第二有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差。
在本公开的一种示例性实施例中，所述第一有效脉冲信号在所述第二有效脉冲信号的终端开始输出，
其中，第N行第二有效脉冲信号的终端和与其对应的栅极驱动信号的起始端的时序差小于第N+M行第二有效脉冲信号的终端和与其对应的栅极驱动信号的起始端的时序差。
在本公开的一种示例性实施例中，M大于1，其中，第N行、第N+1行……第N+M－1行的第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差相等。
在本公开的一种示例性实施例中，所述时序差为0至0.5μs。
在本公开的一种示例性实施例中，各行所述第一有效脉冲信号的终端和与其对应的栅极驱动信号的终端的时序差均大于或等于零。
本公开第二方面提供了一种显示驱动电路，其包括：
控制器和与所述控制器通信连接的源极驱动器，所述控制器用于控制所述源极驱动器输出数据信号，
所述数据信号包括多个第一有效脉冲信号，第N行第一有效脉冲信号用于驱动第N行子像素单元，第N行第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差小于第N+M行第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差；
其中，第N行子像素单元相比于第N+M行子像素单元靠近所述源极驱动器，N、M为大于或等于1的正整数。
在本公开的一种示例性实施例中，所述控制器为时序控制器，所述时序控制器用于向所述源极驱动器输出数据输出控制信号，基于所述数据输出控制信号控制所述源极驱动器输出所述数据信号；
其中，所述数据输出控制信号包括多个第二有效脉冲信号，且每一所述第一有效脉冲信号对应一所述第二有效脉冲信号。
在本公开的一种示例性实施例中，所述控制器为时序控制器，所述时序控制器用于向所述源极驱动器输出控制信号；根据所述控制信号控制所述源极驱动器生成数据输出控制信号，基于所述数据输出控制信号控制所述源极驱动器输出数据信号；
其中，所述数据输出控制信号包括多个第二有效脉冲信号，且每一所述第一有效脉冲信号对应一所述第二有效脉冲信号。
在本公开的一种示例性实施例中，所述第一有效脉冲信号在所述第二有效脉冲信号的起始端开始输出，
其中，第N行第二有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差小于第N+M行第二有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差。
在本公开的一种示例性实施例中，所述第一有效脉冲信号在所述第二有效脉冲信号的终端开始输出，
其中，第N行第二有效脉冲信号的终端和与其对应的栅极驱动信号的起始端的时序差小于第N+M行第二有效脉冲信号的终端和与其对应的栅极驱动信号的起始端的时序差。
本公开第三方面提供了一种显示装置，其包括：显示面板及上述任一项所述的显示驱动电路，所述显示驱动电路用于驱动所述显示面板。
本公开提供的技术方案可以达到以下有益效果：
本公开所提供的显示驱动方法、显示驱动电路及显示装置，其包括：控制源极驱动器发送数据信号，该数据信号可包括多个第一有效脉冲信号，第N行第一有效脉冲信号用于驱动第N行子像素单元，第N行第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差小于第N+M行第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差；其中，第N行子像素单元相比于第N+M行子像素单元远离源极驱动器，N、M为大于或等于1的正整数，这样设计可补偿由于压降导致数据延迟而引起远端子像素单元数据充电不良的问题，即：可增大远端子像素单元数据充电时间。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了现有技术中的显示驱动方法中各信号的时序关系图；
图2示出了现有技术中的最远端子像素单元与近端子像素单元的数据上升时间的仿真结果图；
图3示出了现有技术中的最远端子像素单元与近端子像素单元的数据下降时间的仿真结果图；
图4示出了现有技术中的显示装置中显示面板各处充电率的仿真结果图；
图5示出了本公开一实施例所述的显示驱动方法中各信号的时序关系图；
图6示出了本公开另一实施例所述的显示驱动方法中各信号的时序关系图；
图7示出了本公开一实施例所述的显示驱动电路的框图；
图8示出了本公开另一实施例所述的显示驱动电路的框图；
图9示出了本公开一实施例所述的显示装置的框图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
随着用户对显示产品的要求越来越高，高穿透率、高解析度、高帧频的显示产品得到更多的重视，但由此而带来的充电率不足问题急需要解决。其中，离源极驱动器较近的一端(即：近端子像素单元)充电时间充足，而离源极驱动器较远的一端(即：远端子像素单元)由于压降导致数据延迟，因此会出现充电时间不足的问题，即：从源极驱动器的近端至远端，充电率逐渐减少。
具体地，如图1所示，源极驱动器输出的数据信号(即：理论数据信号)Data1包括多个数据脉冲信号，第N行数据脉冲信号用于驱动第N行子像素单元(即：近端子像素单元)，第N+M行数据脉冲信号用于驱动第N+M行子像素单元(即：远端子像素单元)，其中，第N行数据脉冲信号的起始端和与第N行栅极驱动信号GateN的起始端的时序差与第N+M行数据脉冲信号的起始端和与第N+M行栅极驱动信号GateN+M的起始端的时序差相等，均为t，应当理解的是，第N行(第N+M行)栅极驱动信号GateN(GateN+M)用于驱动第N行(第N+M行)子像素单元的薄膜晶体管(TFT，Thin Film Transistor)打开，以使第N行(第N+M行)子像素单元接收第N行(第N+M行)数据脉冲信号。
但由于压降原因，一列子像素单元实际接收到的数据信号为Data2，如图1所示，第N+M行子像素单元接收到的数据脉冲信号的上升沿相较于第N行子像素单元接收到的数据脉冲信号的上升沿过宽，因此，第N+M行子像素单元数据延迟比第N行子像素单元数据延迟更加严重，从而使得第N+M行子像素单元的充电时长T2小于第N行子像素单元的充电时长T1。
举例而言，图2示出了最远端子像素单元(即：离源极驱动器最远的子像素单元)与近端子像素单元(即：与最远端子像素单元相比更靠近源极驱动器的子像素单元)的数据上升时间(Rising Time)的仿真结果图，图3示出了远端子像素单元与近端子像素单元的数据下降时间(Falling Time)的仿真结果图，图3中虚线可为最远端子像素单元的数据上升时间，实线可为近端子像素单元的数据上升时间；图3中虚线为最远端子像素单元的数据下降时间， 实线为近端子像素单元的数据下降时间。
根据图2和图3中的仿真数据可知，其中，最远端子像素单元的数据开始爬升的位置、最远端子像素单元的数据开始下降的位置相较于近端子像素单元的数据开始爬升的位置、近端子像素单元的数据开始下降的位置延迟较严重，如图2和图3所示出的仿真结果，最远端子像素单元的数据延迟时间约为0.4μs，但不限于此，具体数值需根据显示面板特性来决定。
基于前述可知，由于远端子像素单元的数据延迟相较于近端子像素单元的数据延迟较严重，因此，在逐行打开子像素单元的薄膜晶体管(TFT，Thin Film Transistor)时，远端子像素单元的充电时长小于近端子像素单元的充电时长，因此，使得远端子像素单元的充电率小于近端子像素单元的充电率。
具体地，在图4中，将显示面板10分为两列，其中，1号位置、2号位置及3号位置为一列，从3号位置→2号位置→1号位置，对应的充电率从87.36％→79.85％→79.48％；4号位置、5号位置及6号位置为一列，从6号位置→5号位置→4号位置，对应的充电率从90.10％→84.49％→84.22％，即：从源极驱动器12的近端至远端，充电率逐渐减少。
应当理解的是，本实施例仅仅是想表示从源极驱动器的近端至远端，充电率逐渐减少，但充电率的数值不限于此，具体数值需根据显示面板特性来决定。
此外，还需要说明的是，子像素单元的充电率不仅会受到其与源极驱动器之间位置关系的影响，还会受到其他的影响，例如：其与栅极驱动器之间位置关系的影响，因此，图4中虽然标号3位置与标号6位置距源极驱动器的距离基本相同，但充电率仍然会有所不同。
为解决上述提到的问题，本公开实施例提供了一种显示驱动方法，用于驱动显示面板显示，该显示驱动方法可包括：
控制源极驱动器输出数据信号，如图5和图6所示，源极驱动器输出的数据信号Data1可包括多个第一有效脉冲信号(即：数据脉冲信号)，第N行第一有效脉冲信号用于驱动第N行子像素单元，此第N行第一有效脉冲信号的起始端和与其对应的栅极驱动信号GateN的起始端的时序差t1小于第N+M行第一有效脉冲信号的起始端和与其对应的栅极驱动信号GateN+M的起始端的时序差t2。
其中，第N行子像素单元相比于第N+M行子像素单元靠近源极驱动器，N、M为大于或等于1的正整数。应当理解的是，第N行子像素单元可为前述提到的近端子像素单元，此时，第N行第一有效脉冲信号可定义为近端第一有效脉冲信号；第N+M行子像素单元可为前述提到的远端子像素单元，此时，第N+M行第一有效脉冲信号可定义为远端第一有效脉冲信号。
本实施例中，通过使得远端子像素单元(即：第N+M行子像素单元)的第一有效脉冲信号的起始端和与其对应的栅极驱动信号GateN+M的起始端的时序差t2大于近端子像素单元(即：第N行子像素单元)的第一有效脉冲信号的起始端和与其对应的栅极驱动信号GateN的起始端的时序差t1，这样设计使得远端子像素单元相比于近端子像素单元更早的进入数据充电阶段，从而可补偿由于压降导致数据延迟而引起远端子像素单元数据充电不良的问题， 即：可增大远端子像素单元数据充电时间，以使远端子像素单元的数据充电时间与近端子像素的数据充电时间相差不大，例如，图5中第N+M行子像素单元的数据充电时间T4与第N行子像素单元的数据充电时间T3相等，继而可提高显示效果。
应当理解的是，在栅极驱动信号为高电平有效时，栅极驱动信号的起始端则为其上升沿，终端则为其下降沿；而在栅极驱动信号为低电平有效时，栅极驱动信号的起始端则为其下降沿，终端则为其上升沿；同理，在第一有效脉冲信号为高电平有效时，第一有效脉冲信号的起始端则为其上升沿，终端则为其下降沿；而在第一有效脉冲信号为低电平有效时，第一有效脉冲信号的起始端则为其下降沿，终端则为其上升沿。
如图5和图6所示，由于数据信号Data1的传输与数据输出控制信号TP相关，即：数据信号Data1的输出位置与数据输出控制信号TP的位置相关，因此，本实施例可通过数据输出控制信号TP控制源极驱动器输出数据信号Data1，即：通过修改数据输出控制信号TP的位置来改变数据信号Data1的输出位置，这样不用改变一帧总用时，仅仅是对近远端第一有效脉冲信号的位置做平移。
本实施例中，通过数据输出控制信号TP控制源极驱动器输出数据信号，具体可包括以下两种方案：
第一种方案：控制源极驱动器输出数据信号可包括：
步骤S100，利用时序控制器向源极驱动器输出数据输出控制信号TP；
步骤S102，基于数据输出控制信号TP控制源极驱动器输出数据信号Data1。
应当理解的是，此方案中最终用于控制源极驱动器输出前述数据信号Data1的数据输出控制信号TP为时序控制器内部所生成的，该时序控制器将其内部生成的数据输出控制信号TP输送至源极驱动器中，该源极驱动器根据此数据输出控制信号TP生成与之对应的数据信号Data1，并将此数据信号Data1输出。
第二种方案：控制源极驱动器输出数据信号可包括：
步骤S200，利用时序控制器向源极驱动器输出控制信号；
步骤S202，根据控制信号控制源极驱动器生成数据输出控制信号TP；
步骤S204，基于数据输出控制信号TP控制源极驱动器输出数据信号Data1。
应当理解的是，时序控制器向源极驱动器输出的控制信号可为初始数据输出控制信号，此初始数据输出控制信号可输送到源极驱动器的一元器件内，该元器件可对初始数据输出控制信号进行修改，以生成最终的数据输出控制信号TP，且该元器件可将最终生成的数据输出控制信号TP发送到源极驱动器的另一元器件内，此另一元器件可通过最终的数据输出控制信号TP生成与之对应的数据信号Data1，并将此数据信号Data1输出。
其中，前述任一种方案中数据输出控制信号TP均包括多个第二有效脉冲信号(即：有效TP脉冲信号)，每一第一有效脉冲信号对应一第二有效脉冲信号。
可选地，如图5和图6所示，第二有效脉冲信号可为高电平有效信号，在第二有效脉冲信号为高电平有效信号时，第二有效脉冲信号的起始端应为其上升沿，第二有效脉冲信号的 终端应为其下降沿。但不限于此，第二有效脉冲信号也可为低电平有效信号，在第二有效脉冲信号可为低电平有效信号时，第二有效脉冲信号的起始端应为其下降沿，第二有效脉冲信号的终端应为其上升沿。
举例而言，数据信号Data1的传输与数据输出控制信号TP的关系具体可包括以下两种情况：
第一种情况：第一有效脉冲信号在第二有效脉冲信号的起始端开始输出，这样可应用于高帧频的显示产品中。
其中，当第一有效脉冲信号在第二有效脉冲信号的起始端开始输出时，如图5所示，应使第N行第二有效脉冲信号的起始端和与其对应的栅极驱动信号GateN的起始端的时序差t1小于第N+M行第二有效脉冲信号的起始端和与其对应的栅极驱动信号GateN+M的起始端的时序差t2，这样可保证第N行第一有效脉冲信号的起始端和与其对应的栅极驱动信号GateN的起始端的时序差t1小于第N+M行第一有效脉冲信号的起始端和与其对应的栅极驱动信号GateN+M的起始端的时序差t2。
第二种情况：第一有效脉冲信号在第二有效脉冲信号的终端开始输出。
其中，在第一有效脉冲信号在第二有效脉冲信号的终端开始输出时，如图6所示，应使第N行第二有效脉冲信号的终端和与其对应的栅极驱动信号GateN的起始端的时序差t1小于第N+M行第二有效脉冲信号的终端和与其对应的栅极驱动信号GateN+M的起始端的时序差t2，这样可保证第N行第一有效脉冲信号的起始端和与其对应的栅极驱动信号GateN的起始端的时序差t1小于第N+M行第一有效脉冲信号的起始端和与其对应的栅极驱动信号GateN+M的起始端的时序差t2。
基于前述两种情况可知，该数据输出控制信号TP可作为数据信号Data1的触发信号，也就是说，数据输出控制信号TP可用于控制数据信号Data1的输出，具体第一有效脉冲信号是在第二有效脉冲信号的起始端输出，还是在第二有效脉冲信号的终端输出，可根据实际情况而定。
在一实施例中，M可等于1，这样使得从源极驱动器的近端至远端，第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差逐行增大，即：相邻两行中前一行(靠近源极驱动器的一行)的第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差小于后一行(远离源极驱动器的一行)的第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差；这样设计可提高各行子像素单元的充电效果，从而可提高显示效果。
应当理解的是，由于前述提到第一有效脉冲信号在第二有效脉冲信号的起始端(终端)开始输出，因此，当M等于1时，应使第二有效脉冲信号的起始端(终端)和与其对应的栅极驱动信号的起始端的时序差逐行增大。
在另一实施例中，M可大于1，其中，第N行、第N+1行……第N+M－1行的第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差相等。也就是说，本实施 例可以多行(即：M行)为一组进行调整，这样在补偿由于压降导致数据延迟而引起远端子像素单元数据充电不良的问题的同时，可降低调整难度。
具体地，显示面板中可包括多组子像素单元，每组子像素单元由M行子像素单元组成，其中，每组子像素单元中各行的第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差相等，而相邻两组子像素单元中前一组(靠近源极驱动器的一组)的第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差小于后一组(远离源极驱动器的一组)的第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差。
例如，在M等于15(即：每组子像素单元由15行子像素单元组成)时，从第1行、第2行……第15行的第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差相等；从第16行、第17行……第30行的第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差相等；且第16行的第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差大于第15行的第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差。
可选地，M可为15至1000，但不限于此，具体数值需根据显示面板特性来决定。
应当理解的是，由于前述提到第一有效脉冲信号在第二有效脉冲信号的起始端(终端)开始输出，因此，当M大于1时，即：以M行为一组进行调整时，每组子像素单元中各行的第二有效脉冲信号的起始端(终端)和与其对应的栅极驱动信号的起始端的时序差相等，而相邻两组子像素单元中前一组(靠近源极驱动器的一组)的第二有效脉冲信号的起始端(终端)和与其对应的栅极驱动信号的起始端的时序差小于后一组(远离源极驱动器的一组)的第二有效脉冲信号的起始端(终端)和与其对应的栅极驱动信号的起始端的时序差。
在前述提到的任一实施例中，第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差可为0至0.5μs。可选地，根据图2和图3所示的仿真结果可知，最远端子像素单元的数据延迟时间约为0.4μs，因此，为了补偿由于数据延迟而导致最远端子像素单元数据充电不良的问题，可将最远端子像素单元进入数据充电阶段的时间提前约0.4μs，但不限于此，具体数值需根据显示面板特性来决定。
理应了解的是，由于为了保证整个显示面板的数据充电良率，各行的第一有效脉冲信号的起始端通常早于与其对应的栅极驱动信号的起始端，也就是说，通常情况下各行第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差均大于0，因此，为了提高最远端子像素单元的充电效果，该最远端子像素单元的第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差实际应大于0.4μs。
此外，还应当理解的是，由于子像素单元的充电时长与栅极驱动信号的有效时长(该有效时长为栅极驱动信号的终端与起始端之间的时间差值)相关，具体地，在栅极驱动信号的起始端向子像素单元开始充电，在栅极驱动信号的终端充电结束，因此，为了进一步保证各子像素单元的充电时长，应保证各行第一有效脉冲信号的终端和与其对应的栅极驱动信号的终端的时序差均大于或等于零。
其中，用于驱动各子像素单元的第一有效脉冲信号的有效时长(该有效时长为第一有效脉冲信号的终端与起始端之间的时间差值)可相同，但不限于此，也可远端第一有效脉冲信号(即：用于驱动远端子像素单元的第一有效脉冲信号)的有效时长大于近端第一有效脉冲信号(即：用于驱动近端子像素单元的第一有效脉冲信号)的有效时长，视具体情况而定。
基于前述可知，本实施例的显示驱动方法可通过时序控制器输送指令给源极驱动器，源极驱动器接受指令，以控制数据信号的输出位置，具体设计可为：组与组间的控制信号设定完全独立，理应了解的是，此处提到的组包括多行子像素单元，每组中子像素单元的行数可为15至1000，该行数可调，具体可搭配MCU(微控制单元)设计，本实施例中通过移动数据输出控制信号TP以控制数据信号Data1输出的位置，使得远端子像素单元可以得到更多的充电时间。
针对前述提到的显示驱动方法，本公开实施例还提供了一种显示驱动电路，该显示驱动电路可使用前述任一实施例所描述的显示驱动方法驱动显示面板，因此，本实施例的显示驱动电路的有益效果与前述任一实施例的显示驱动方法的有益效果相同，在此不再对该显示驱动电路所产生的有益效果进行详细描述。
本实施例中，如图7所示，该显示驱动电路可包括控制器11和与控制器11通信连接的源极驱动器，控制器11用于控制源极驱动器输出数据信号，该数据信号包括多个第一有效脉冲信号，第N行第一有效脉冲信号用于驱动第N行子像素单元，第N行第一有效脉冲信号的起始端和与其对应的栅极驱动信号GateN的起始端的时序差t1小于第N+M行第一有效脉冲信号的起始端和与其对应的栅极驱动信号GateN+M的起始端的时序差t2。
其中，第N行子像素单元相比于第N+M行子像素单元靠近源极驱动器，N、M为大于或等于1的正整数。
可选地，该控制器11为时序控制器，该时序控制器用于控制源极驱动器输出数据信号。具体可包括以下两种方案：
第一种方案：时序控制器用于向源极驱动器输出数据输出控制信号，基于数据输出控制信号控制源极驱动器输出数据信号。
第二种方案：时序控制器用于向源极驱动器输出控制信号；根据控制信号控制源极驱动器生成数据输出控制信号，基于数据输出控制信号控制源极驱动器输出数据信号。
其中，任一种方案中的数据输出控制信号均包括多个第二有效脉冲信号，且每一第一有效脉冲信号对应一第二有效脉冲信号。
在一可选实施例中，第一有效脉冲信号在第二有效脉冲信号的起始端开始输出，
其中，第N行第二有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差小于第N+M行第二有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差。
在另一可选实施例中，第一有效脉冲信号在第二有效脉冲信号的终端开始输出，
其中，第N行第二有效脉冲信号的终端和与其对应的栅极驱动信号的起始端的时序差小于第N+M行第二有效脉冲信号的终端和与其对应的栅极驱动信号的起始端的时序差。
如图8所示，时序控制器13可包括第一信号接收单元(第一Rx单元)130、色彩控制单元(ACC单元)131、补偿单元(OD单元)132、补充充电单元(VCC单元)133、固件单元(FW单元)134及信号发送单元(Tx单元)135；源极驱动器12可包括第二信号接收单元(第二Rx单元)120、电平转换单元(LS单元)121、数模转换单元(DAC单元)122及输出单元(OP单元)123，其中，时序控制器13中的Tx单元135发送信号至源极驱动器12的第二Rx单元120，源极驱动器12的其他单元(例如：LS单元121、DAC单元122等)可对第二Rx单元120接收到的信号进行处理以转化成数据信号，此数据信号可通过OP单元123输出。
理应了解的是，本实施例中提到的时序控制器13中的各单元及源极驱动器12中的各单元为常规结构，与传统中各单元的作用相同，这些单元结构并不是本公开的主要改进点，因此，不作详细说明。
此外，还需要说明的是，如图9所示，该显示驱动电路不仅可包括前述提到的时序控制器13和源极驱动器12，还可包括栅极驱动器14，该栅极驱动器14可与时序控制器13通信连接，该时序控制器13可控制栅极驱动器14发送前述提到的栅极信号。
本公开实施例还提供了一种显示装置，其包括：显示面板及前述任一实施例所描述的显示驱动电路，如图9所示，该显示驱动电路可包括时序控制器13、源极驱动器12及栅极驱动器14，此显示驱动电路用于驱动显示面板，此显示面板可为液晶显示面板，但不限于此。根据本公开的实施例，该显示装置的具体类型不受特别的限制，本领域常用的显示装置类型均可，具体例如液晶显示器或具有液晶显示器的移动装置、可穿戴设备、VR装置等等，本领域技术人员可根据该显示设备的具体用途进行相应地选择，在此不再赘述。
用语“一个”、“一”、“该”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”等仅作为标记使用，不是对其对象的数量限制。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (14)

  1. 一种显示驱动方法，包括：
    控制源极驱动器输出数据信号，所述数据信号包括多个第一有效脉冲信号，第N行第一有效脉冲信号用于驱动第N行子像素单元，第N行第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差小于第N+M行第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差；
    其中，第N行子像素单元相比于第N+M行子像素单元靠近所述源极驱动器，N、M为大于或等于1的正整数。
  2. 根据权利要求1所述的显示驱动方法，所述控制源极驱动器输出数据信号，包括：
    利用时序控制器向所述源极驱动器输出数据输出控制信号；
    基于所述数据输出控制信号控制所述源极驱动器输出数据信号；
    其中，所述数据输出控制信号包括多个第二有效脉冲信号，且每一所述第一有效脉冲信号对应一所述第二有效脉冲信号。
  3. 根据权利要求1所述的显示驱动方法，所述控制源极驱动器输出数据信号，包括：
    利用时序控制器向所述源极驱动器输出控制信号；
    根据所述控制信号控制所述源极驱动器生成数据输出控制信号；
    基于所述数据输出控制信号控制所述源极驱动器输出数据信号；
    其中，所述数据输出控制信号包括多个第二有效脉冲信号，且每一所述第一有效脉冲信号对应一所述第二有效脉冲信号。
  4. 根据权利要求2或3所述的显示驱动方法，所述第一有效脉冲信号在所述第二有效脉冲信号的起始端开始输出，
    其中，第N行第二有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差小于第N+M行第二有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差。
  5. 根据权利要求2或3所述的显示驱动方法，所述第一有效脉冲信号在所述第二有效脉冲信号的终端开始输出，
    其中，第N行第二有效脉冲信号的终端和与其对应的栅极驱动信号的起始端的时序差小于第N+M行第二有效脉冲信号的终端和与其对应的栅极驱动信号的起始端的时序差。
  6. 根据权利要求1所述的显示驱动方法，M大于1，其中，第N行、第N+1行……第N+M－1行的第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差相等。
  7. 根据权利要求1所述的显示驱动方法，所述时序差为0至0.5μs。
  8. 根据权利要求1所述的显示驱动方法，各行所述第一有效脉冲信号的终端和与其对应的栅极驱动信号的终端的时序差均大于或等于零。
  9. 一种显示驱动电路，包括：
    控制器和与所述控制器通信连接的源极驱动器，所述控制器用于控制所述源极驱动器输出数据信号，
    所述数据信号包括多个第一有效脉冲信号，第N行第一有效脉冲信号用于驱动第N行子像素单元，第N行第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差小于第N+M行第一有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差；
    其中，第N行子像素单元相比于第N+M行子像素单元靠近所述源极驱动器，N、M为大于或等于1的正整数。
  10. 根据权利要求9所述的显示驱动电路，
    所述控制器为时序控制器，所述时序控制器用于向所述源极驱动器输出数据输出控制信号，基于所述数据输出控制信号控制所述源极驱动器输出所述数据信号；
    其中，所述数据输出控制信号包括多个第二有效脉冲信号，且每一所述第一有效脉冲信号对应一所述第二有效脉冲信号。
  11. 根据权利要求9所述的显示驱动电路，
    所述控制器为时序控制器，所述时序控制器用于向所述源极驱动器输出控制信号；根据所述控制信号控制所述源极驱动器生成数据输出控制信号，基于所述数据输出控制信号控制所述源极驱动器输出数据信号；
    其中，所述数据输出控制信号包括多个第二有效脉冲信号，且每一所述第一有效脉冲信号对应一所述第二有效脉冲信号。
  12. 根据权利要求10或11所述的显示驱动电路，所述第一有效脉冲信号在所述第二有效脉冲信号的起始端开始输出，
    其中，第N行第二有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差小于第N+M行第二有效脉冲信号的起始端和与其对应的栅极驱动信号的起始端的时序差。
  13. 根据权利要求10或11所述的显示驱动电路，所述第一有效脉冲信号在所述第二有效脉冲信号的终端开始输出，
    其中，第N行第二有效脉冲信号的终端和与其对应的栅极驱动信号的起始端的时序差小于第N+M行第二有效脉冲信号的终端和与其对应的栅极驱动信号的起始端的时序差。
  14. 一种显示装置，包括：显示面板及权利要求9至13所述的显示驱动电路，所述显示驱动电路用于驱动所述显示面板。
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