WO2020077892A1 - 液晶显示面板及其驱动电路 - Google Patents

液晶显示面板及其驱动电路 Download PDF

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Publication number
WO2020077892A1
WO2020077892A1 PCT/CN2019/070558 CN2019070558W WO2020077892A1 WO 2020077892 A1 WO2020077892 A1 WO 2020077892A1 CN 2019070558 W CN2019070558 W CN 2019070558W WO 2020077892 A1 WO2020077892 A1 WO 2020077892A1
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Prior art keywords
circuit
voltage
clock control
row
gate
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PCT/CN2019/070558
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English (en)
French (fr)
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张先明
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020077892A1 publication Critical patent/WO2020077892A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers

Definitions

  • the invention relates to the field of display, in particular to a liquid crystal display panel and its driving circuit.
  • GOA Gate Driver on Array
  • Figure 1 is an existing COF (Chip on Film, flip chip) module 90 and the liquid crystal display panel 9 of the GOA circuit 91
  • the GOA circuit 91 is made on the adjacent side of the COF module 90
  • the COF module 90 includes a clock control circuit for output
  • a clock control signal is transmitted to the GOA circuit 91, so that the GOA circuit 91 drives the scan line of the liquid crystal display panel row by row. Since the size of the liquid crystal display panel is becoming larger and larger, and it is required to meet the needs of narrow borders, the RC product value caused by the wiring distribution of the GOA circuit 91 at this time is relatively large, resulting in ,
  • the clock signal transmitted by the trace relatively close to the COF module 90 (as shown in FIG.
  • the main object of the present invention is to provide a liquid crystal display panel and its driving circuit, which can select a suitable initial gate voltage (VGH and VGL) according to different row partitions of the pixel array of the liquid crystal display panel Output to the GOA circuit, to ensure that the gate voltage of the GOA circuit is finally used to operate the pixels of each row is similar, to ensure that the charging of each row is equivalent.
  • VGH and VGL initial gate voltage
  • the present invention provides a driving circuit, which is applied to a liquid crystal display panel including a pixel array, a flip-chip thin film circuit module and a GOA circuit, wherein the driving circuit includes: a power management circuit, It is used to provide a plurality of different gate driving voltages through a voltage dividing circuit; a clock control circuit to output a clock control signal corresponding to each row partition based on the distribution relationship of the plurality of row partitions of the pixel array, wherein the pixel array
  • the distribution relationship of the plurality of row partitions is the distance relationship between each of the row partitions and the flip-chip thin film circuit module; and a level conversion circuit that connects the clock control circuit, the power management circuit and all
  • the GOA circuit is used to select the corresponding gate driving voltage controlled by the clock control signal corresponding to each row partition, and output the level to the GOA circuit after level shifting the selected gate driving voltage;
  • the clock control signal of the row partition far away from the flip chip circuit module is to control the level conversion circuit to select
  • the level conversion circuit includes an amplifier circuit for performing level conversion on the selected gate driving voltage and gate off voltage.
  • the present invention also provides another driving circuit, which is applied to a liquid crystal display panel including a pixel array, a chip on film (COF) circuit module and a GOA circuit.
  • the driving circuit includes: a power management circuit for dividing The voltage circuit provides a plurality of different gate driving voltages; a clock control circuit for outputting clock control signals corresponding to each row partition based on the distribution relationship of the row partitions of the pixel array; and a level conversion circuit connected to the The clock control circuit, the power management circuit, and the GOA circuit are used to select the corresponding gate drive voltage controlled by the clock control signal corresponding to each row partition, and perform level conversion on the selected gate drive voltage Then output to the GOA circuit.
  • the distribution relationship of the row partitions of the pixel array is the distance relationship between each row partition and the flip-chip thin film circuit module.
  • the clock control signal corresponding to the row partition farther away from the flip chip circuit module is to control the level shifting circuit to select a larger gate drive voltage;
  • the clock control signal of the row partition of the flip-chip thin film circuit module is to control the level conversion circuit to select a smaller gate driving voltage.
  • the level conversion circuit includes an amplifier circuit for performing level conversion on the selected gate driving voltage.
  • the power management circuit is further used to provide a plurality of different gate-off voltages through a voltage divider circuit; the level conversion circuit is controlled by the clock control signal corresponding to each row partition The corresponding gate-off voltage is selected, and the selected gate-off voltage is level-converted and output to the GOA circuit.
  • the clock control signal corresponding to the row partition farther away from the flip chip circuit module is to control the level shifting circuit to select a smaller gate-off voltage;
  • the clock control signal of the row division of the flip-chip thin film circuit module is to control the level conversion circuit to select a larger gate-off voltage.
  • the level conversion circuit includes an amplifier circuit for performing level conversion on the selected gate-off voltage.
  • the level conversion circuit is integrated in the flip-chip thin film circuit module.
  • the flip-chip thin film circuit module is disposed on one side of the liquid crystal display panel, and the side is parallel to the row partition of the pixel array.
  • the present invention also provides a liquid crystal display panel, which includes a pixel array, a flip-chip thin film circuit module, a GOA circuit, and a driving circuit, wherein the pixel array includes a plurality of pixel rows and is divided into a plurality of row partition , Each row partition includes more than one pixel row, wherein the driving circuit includes: a power management circuit for providing a plurality of different gate driving voltages through a voltage dividing circuit; and a clock control circuit for based on the The distribution relationship of a plurality of row partitions of the pixel array outputs clock control signals corresponding to each row partition; and a level conversion circuit connected to the clock control circuit, the power management circuit and the GOA circuit to be controlled by all The clock control signal corresponding to each row partition selects the corresponding gate drive voltage, and the selected gate drive voltage is level-converted and output to the GOA circuit.
  • the driving circuit includes: a power management circuit for providing a plurality of different gate driving voltages through a voltage dividing circuit; and a clock
  • the distribution relationship of the row partitions of the pixel array is the distance relationship between each row partition and the flip-chip thin film circuit module.
  • the clock control signal corresponding to the row partition farther away from the flip chip circuit module is to control the level shifting circuit to select a larger gate drive voltage;
  • the clock control signal of the row partition of the flip-chip thin film circuit module is to control the level conversion circuit to select a smaller gate driving voltage.
  • the level conversion circuit includes an amplifier circuit for performing level conversion on the selected gate driving voltage.
  • the power management circuit is further used to provide a plurality of different gate-off voltages through a voltage divider circuit; the level conversion circuit is controlled by the clock control signal corresponding to each row partition The corresponding gate-off voltage is selected, and the selected gate-off voltage is level-converted and output to the GOA circuit.
  • the clock control signal corresponding to the row partition farther away from the flip chip circuit module is to control the level shifting circuit to select a smaller gate-off voltage;
  • the clock control signal of the row division of the flip-chip thin film circuit module is to control the level conversion circuit to select a larger gate-off voltage.
  • the level conversion circuit includes an amplifier circuit for performing level conversion on the selected gate-off voltage.
  • the level conversion circuit is integrated in the flip-chip thin film circuit module.
  • the flip-chip thin film circuit module is disposed on one side of the liquid crystal display panel, and the side is parallel to the row partition of the pixel array.
  • the invention mainly changes the output method of the traditional Level Shifter IC, and selects the appropriate VGH and VGL voltage output to the GOA circuit according to the relative position of each row partition of the pixel array and the COF module to ensure that the voltage that can be reached in each row is close It is ensured that the charging of each row is equivalent, and in the prior art, the situation in which the influence of the gate driving voltage VGH on the capacitive coupling (Coupling) when charging each pixel row is different can be improved.
  • the present invention mainly changes the output method of the traditional Level Shifter IC, and selects the appropriate VGH and VGL voltage output to the GOA circuit according to the relative position of each row partition of the pixel array and the COF module to ensure that the voltage that can be reached in each row is close to It is ensured that the charging of each row is equivalent, and in the prior art, the situation in which the influence of the gate driving voltage VGH on the capacitive coupling (Coupling) when charging each pixel row is different can be improved.
  • FIG. 1 is a schematic plan view of a conventional liquid crystal display panel including a COF (chip on film) module and a GOA circuit.
  • COF chip on film
  • FIG. 2A and 2B are waveform diagrams of the clock signal transmitted by the traces relatively close to the COF module and the clock signal transmitted by the traces relatively far from the COF module in the liquid crystal display panel of FIG.
  • FIG. 3 is a circuit block diagram of a driving circuit according to an embodiment of the invention.
  • FIG. 4 is a schematic diagram of a voltage dividing circuit provided by a driving circuit according to an embodiment of the present invention to provide multiple different gate driving voltages.
  • 5A and 5B are schematic diagrams of an amplifier circuit in a driving circuit according to an embodiment of the invention.
  • FIG. 3 is a circuit block diagram of a driving circuit according to an embodiment of the present invention.
  • the driving circuit of the present invention is mainly applied to a liquid crystal display panel including a pixel array, a flip chip circuit module and a GOA circuit.
  • the pixel array includes a plurality of pixel rows and can be divided into a plurality of row partitions, and each row partition includes more than one pixel row.
  • the flip-chip thin film circuit module may be disposed on one side of the liquid crystal display panel, where the side is parallel to the row partition of the pixel array.
  • the driving circuit 1 is connected to the GOA circuit 2 and includes a power management circuit 10, a clock control circuit 11 and a level conversion circuit 12.
  • FIG. 4 is a schematic diagram of a voltage dividing circuit provided by a driving circuit according to an embodiment of the present invention to provide a plurality of different gate driving voltages.
  • the power management circuit 10 is used to provide a plurality of different gate drive voltages through a voltage divider circuit, specifically, the power management circuit 10 provides a larger drive voltage VGHF, and through a plurality of series resistors The voltage division is performed to generate a plurality of different gate driving voltages VGH_1, VGH_2, VGH_3, ..., VGH_N-1, VGH_N.
  • the power management circuit 10 specifically generates a gradually increasing or decreasing starting gate voltage according to the distribution relationship of the row partitions of the pixel array.
  • the gate drive voltage of each row partition can be reduced from the largest 35V to 0.3V in each region in sequence until the last row partition is 30.5V; the gate-off voltage of each row partition can be increased from the minimum of -10V, increasing 0.1V in each region in sequence, until the last row partition is -8.5V.
  • the clock control circuit 11 is used to output a clock control signal corresponding to each row partition based on the distribution relationship of the row partitions of the pixel array.
  • the distribution relationship of the row partitions of the pixel array refers to the distance relationship between each row partition and the flip-chip thin film circuit module, for example, when the pixel array is divided into 16 rows In partitioning, the first row partition may be the row partition farthest from the flip-chip thin film circuit module, and the 16th row partition may be the row partition closest to the flip-chip thin film circuit module.
  • the clock control circuit 11 determines the supply to all the pixels according to the distance between the row partition and the flip-chip thin film circuit module The clock control signal of the level conversion circuit 12 will be described.
  • the level conversion circuit 12 may be integrated in the flip-chip thin film circuit module.
  • the level conversion circuit 12 is used to connect the clock control circuit 11, the power management circuit 10 and the GOA circuit, and is used to select the corresponding gate driving voltage according to the clock control signal corresponding to each row partition And level shift the selected gate drive voltage and output it to the GOA circuit.
  • the clock control circuit 11 determines the clock control signal provided to the level conversion circuit 12 according to the distance between each row partition and the flip-chip thin film circuit module , Where the clock control signal corresponding to the row partition farther away from the flip chip circuit module is to control the level shift circuit 12 to select a larger gate drive voltage; corresponding to the closer to the flip chip circuit module The clock control signal of the row partition is to control the level conversion circuit 12 to select a smaller gate driving voltage.
  • the wiring connected to the row partition farther away from the flip-chip thin film circuit module will cause a larger RC product value, and the wiring connected to the row partition closer to the flip-chip thin film circuit module will cause Small RC product value, when selecting a larger gate drive voltage for the row partition farther away from the flip-chip thin film circuit module and using a smaller trace for the row partition closer to the flip-chip thin film circuit module
  • the level conversion circuit 12 will eventually output a consistent gate drive voltage to the GOA circuit to drive the scanning lines of the liquid crystal display panel line by line. In this way, it can be ensured that the charging of each row is equivalent, and in the prior art, the situation in which the influence of the gate driving voltage VGH on the capacitive coupling (Coupling) when charging each pixel row is different can also be improved.
  • the level conversion circuit 12 may include an amplifying circuit 120 for performing level conversion on the selected gate driving voltage VGH_n, and finally outputting a consistent gate driving voltage VGH.
  • the power management circuit 10 is also used to provide multiple different gate-off voltages through a voltage divider circuit.
  • the level conversion circuit 12 is controlled by the clock control signal corresponding to each row partition to select the corresponding gate turn-off voltage, and the selected gate turn-off voltage is level-converted and output to the GOA circuit.
  • the clock control circuit 11 determines the clock control signal provided to the level conversion circuit 12 according to the distance between each row partition and the flip-chip thin film circuit module, corresponding to The clock control signal of the row partition of the flip-chip thin film circuit module is to control the level conversion circuit to select a smaller gate-off voltage; the clock control signal corresponding to the row partition of the flip-chip thin film circuit module is The level conversion circuit is controlled to select a larger gate-off voltage.
  • the level conversion circuit 12 may include an amplifying circuit for performing level conversion on the selected gate-off voltage VGL_n, and finally outputting a consistent gate-off voltage VGL.
  • the wiring connected to the row partition farther away from the flip-chip thin film circuit module will cause a larger RC product value, and the wiring connected to the row partition closer to the flip-chip thin film circuit module will cause Small RC product value, when selecting a smaller gate-off voltage for the row partition farther away from the flip-chip thin-film circuit module and a larger routing for the row partition closer to the flip-chip thin-film circuit module
  • the level conversion circuit 12 will eventually output a consistent gate-off voltage to the GOA circuit to turn off the scanning lines of the liquid crystal display panel line by line. In this way, the charging rate of the liquid crystal display panel in the far area and the near area relative to the position of the flip-chip thin film circuit module can be consistent, ensuring the uniformity and consistency of the panel display.
  • the present invention also provides a liquid crystal display panel including the driving circuit as described above.
  • the present invention is mainly to change the output method of the traditional level shifter IC (Level Shifter IC) according to the relative position of each row partition of the pixel array and the COF circuit module To select the appropriate VGH and VGL voltage output to the GOA circuit to ensure that the final voltage that can be reached in each row is close to ensure that the charging of each row is equivalent, and in the prior art, the gate drive voltage VGH charges each pixel row The situation where there are different differences in the effects of capacitive coupling at the time can also be improved.
  • Level Shifter IC Level Shifter IC

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Liquid Crystal Display Device Control (AREA)
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Abstract

一种液晶显示面板及其驱动电路（1），驱动电路（1）包括电源管理电路（10）、时钟控制电路（11）及一电平转换电路（12），电源管理电路（10）通过分压电路提供多个不同的栅极驱动电压（VGH_1、VGH_2、VGH_3、...、VGH_N-1、VGH_N），时钟控制电路（11）用以基于像素阵列的多个行分区的分布关系输出对应各行分区的时钟控制信号，电平转换电路（12）连接时钟控制电路（11）、电源管理电路（10）及GOA电路，用以受控于对应各行分区的时钟控制信号选用对应的栅极驱动电压（VGH_1、VGH_2、VGH_3、...、VGH_N-1、VGH_N），并将选用的栅极驱动电压（VGH_1、VGH_2、VGH_3、...、VGH_N-1、VGH_N）进行电平转换后输出至GOA电路。

Description

液晶显示面板及其驱动电路 技术领域
本发明涉及显示领域，特别是涉及一种液晶显示面板及其驱动电路。
 背景技术
GOA（Gate Driver on Array）电路的基本概念是将TFT-LCD的栅极驱动电路集成在玻璃基板上，形成对液晶面板的扫描驱动。GOA相比传统的利用COF(Chip on Film)的驱动技术不但可以大幅节约制造成本，而且省去栅极(gate)侧COF的bonding制程，对产能提升也是极为有利的。因此，GOA是未来液晶面板发展的重点技术。
请参考图1，是现有一种包括COF(Chip on Film, 覆晶薄膜)模组90与GOA电路91的液晶显示面板9，所述GOA电路91制作于COF模组90的相邻侧边，COF模组90上包含时钟控制电路，用于输出多个时钟控制信号以传输至所述GOA电路91，使得所述GOA电路91对该液晶显示面板的扫描线逐行进行驱动。由于现在液晶显示面板的尺寸越来越大，且要求能够满足窄边框的需求，这个时候GOA电路91的走线分布造成的RC乘积值是比较大的，导致在所述GOA电路91的走线中，相对接近所述COF模组90的走线所传输的时钟信号(如图2A所示)以及相对远离所述COF模组90的走线所传输的时钟信号(如图2B所示)，其波形是不一样的，甚至其峰值电压也是不一致的，这种情况下可能会影响所述液晶显示面板在相对于所述COF模组90位置的远端区域和近端区域的充电率的一致性以及面内均匀性，甚至于GOA电路91输出的栅极驱动电压VGH对于每个像素行充电时的电容耦合(Coupling)的影响也是不一样的。
故，有必要提供一种液晶显示面板及其驱动电路，以解决现有技术所存在的问题。
 技术问题
有鉴于现有技术的缺点，本发明的主要目的在于提供一种液晶显示面板及其驱动电路，可以根据液晶显示面板的像素阵列的不同行分区选择适合的初始栅极电压(VGH和VGL)来输出到GOA电路，保证GOA电路最终用于操作每一行像素的栅极电压是相近的，以保证每一行的充电是相当的。
 技术解决方案
为达成本发明的前述目的，本发明提供一种驱动电路，其应用于一包括像素阵列、覆晶薄膜电路模组与GOA电路的液晶显示面板，其中所述驱动电路包含：一电源管理电路，用于通过分压电路提供多个不同的栅极驱动电压；一时钟控制电路，用以基于所述像素阵列的多个行分区的分布关系输出对应各行分区的时钟控制信号，其中所述像素阵列的多个行分区的分布关系是各个所述行分区与所述覆晶薄膜电路模组之间的距离关系；以及一电平转换电路，连接所述时钟控制电路、所述电源管理电路及所述GOA电路，用以受控于所述对应各行分区的时钟控制信号选用对应的栅极驱动电压，并将选用的栅极驱动电压进行电平转换后输出至所述GOA电路；其中对应至较远离所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较大的栅极驱动电压；对应较接近所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较小的栅极驱动电压；其中所述电源管理电路还用于通过分压电路提供多个不同的栅极关闭电压；所述电平转换电路受控于所述对应各行分区的时钟控制信号选用对应的栅极关闭电压，并将选用的栅极关闭电压进行电平转换后输出至所述GOA电路。
在本发明的一实施例中，所述电平转换电路包括一放大电路，用以对所述选用的栅极驱动电压和栅极关闭电压进行电平转换。
本发明还提供另一种驱动电路，其应用于一包括像素阵列、覆晶薄膜(COF)电路模组与GOA电路的液晶显示面板，所述驱动电路包含：一电源管理电路，用于通过分压电路提供多个不同的栅极驱动电压；一时钟控制电路，用以基于所述像素阵列的多个行分区的分布关系输出对应各行分区的时钟控制信号；以及一电平转换电路，连接所述时钟控制电路、所述电源管理电路及所述GOA电路，用以受控于所述对应各行分区的时钟控制信号选用对应的栅极驱动电压，并将选用的栅极驱动电压进行电平转换后输出至所述GOA电路。
在本发明的一实施例中，所述像素阵列的多个行分区的分布关系是各个所述行分区与所述覆晶薄膜电路模组之间的距离关系。
在本发明的一实施例中，对应至较远离所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较大的栅极驱动电压；对应较接近所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较小的栅极驱动电压。
在本发明的一实施例中，所述电平转换电路包括一放大电路，用以对所述选用的栅极驱动电压进行电平转换。
在本发明的一实施例中，所述电源管理电路，还用于通过分压电路提供多个不同的栅极关闭电压；所述电平转换电路受控于所述对应各行分区的时钟控制信号选用对应的栅极关闭电压，并将选用的栅极关闭电压进行电平转换后输出至所述GOA电路。
在本发明的一实施例中，对应至较远离所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较小的栅极关闭电压；对应较接近所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较大的栅极关闭电压。
在本发明的一实施例中，所述电平转换电路包括一放大电路，用以对所述选用的栅极关闭电压进行电平转换。
在本发明的一实施例中，所述电平转换电路集成于所述覆晶薄膜电路模组中。
在本发明的一实施例中，所述覆晶薄膜电路模组设置于所述液晶显示面板的一侧边，所述侧边与所述像素阵列的行分区平行。
为了解决上述问题，本发明另提供一种液晶显示面板，其包括像素阵列、覆晶薄膜电路模组、GOA电路以及驱动电路，其中所述像素阵列包括多个像素行，并分成多个行分区，每个行分区包括一个以上的像素行，其中所述驱动电路包括：一电源管理电路，用于通过分压电路提供多个不同的栅极驱动电压；一时钟控制电路，用以基于所述像素阵列的多个行分区的分布关系输出对应各行分区的时钟控制信号；以及一电平转换电路，连接所述时钟控制电路、所述电源管理电路及所述GOA电路，用以受控于所述对应各行分区的时钟控制信号选用对应的栅极驱动电压，并将选用的栅极驱动电压进行电平转换后输出至所述GOA电路。
在本发明的一实施例中，所述像素阵列的多个行分区的分布关系是各个所述行分区与所述覆晶薄膜电路模组之间的距离关系。
在本发明的一实施例中，对应至较远离所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较大的栅极驱动电压；对应较接近所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较小的栅极驱动电压。
在本发明的一实施例中，所述电平转换电路包括一放大电路，用以对所述选用的栅极驱动电压进行电平转换。
在本发明的一实施例中，所述电源管理电路，还用于通过分压电路提供多个不同的栅极关闭电压；所述电平转换电路受控于所述对应各行分区的时钟控制信号选用对应的栅极关闭电压，并将选用的栅极关闭电压进行电平转换后输出至所述GOA电路。
在本发明的一实施例中，对应至较远离所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较小的栅极关闭电压；对应较接近所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较大的栅极关闭电压。
在本发明的一实施例中，所述电平转换电路包括一放大电路，用以对所述选用的栅极关闭电压进行电平转换。
在本发明的一实施例中，所述电平转换电路集成于所述覆晶薄膜电路模组中。
在本发明的一实施例中，所述覆晶薄膜电路模组设置于所述液晶显示面板的一侧边，所述侧边与所述像素阵列的行分区平行。
本发明主要是更改传统Level Shifter IC的输出方式，根据像素阵列每一行分区与COF模组的相对位置来选择适合的VGH及VGL电压输出到GOA电路，保证在每一行能够达到的电压接近，以保证每一行的充电是相当的，同时现有技术中栅极驱动电压VGH对于每个像素行充电时的电容耦合(Coupling)的影响存在不同差异的状况也能获得改善。
 有益效果
本发明主要是更改传统Level Shifter IC的输出方式，根据像素阵列每一行分区与COF模组的相对位置来选择适合的VGH及VGL电压输出到GOA电路，保证在每一行能够达到的电压接近，以保证每一行的充电是相当的，同时现有技术中栅极驱动电压VGH对于每个像素行充电时的电容耦合(Coupling)的影响存在不同差异的状况也能获得改善。
 附图说明
图1是现有包括COF(覆晶薄膜)模组与GOA电路的液晶显示面板的平面示意图。
图2A和图2B是图1的液晶显示面板中相对接近COF模组的走线所传输的时钟信号以及相对远离COF模组的走线所传输的时钟信号的波形示意图。
图3是本发明一实施例的驱动电路的电路方块图。
图4是本发明一实施例的驱动电路提供多个不同的栅极驱动电压的分压电路示意图。
图5A和图5B是本发明一实施例的驱动电路中的放大电路示意图。
 本发明的实施方式
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明如下。再者，本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参考图3所示，图3是本发明一实施例的驱动电路的电路方块图。本发明的驱动电路主要是应用于一种包括像素阵列、覆晶薄膜电路模组与GOA电路的液晶显示面板。所述像素阵列包括多个像素行(pixel row)，并可分成多个行分区，每个行分区包括一个以上的像素行。所述覆晶薄膜电路模组可以是设置于所述液晶显示面板的一侧边，其中所述侧边与所述像素阵列的行分区平行。
如图3所示，所述驱动电路1连接所述GOA电路2，包含一电源管理电路10、一时钟控制电路11以及一电平转换电路12。
进一步参考图4，图4是本发明一实施例的驱动电路提供多个不同的栅极驱动电压的分压电路示意图。所述电源管理电路10用于通过一分压电路提供多个不同的栅极驱动电压，具体而言，所述电源管理电路10是提供一较大的驱动电压VGHF，并通过多个串接电阻进行分压，产生多个不同的栅极驱动电压VGH_1、VGH_2、VGH_3、…、VGH_N-1、VGH_N。再者，所述电源管理电路10具体是依据所述像素阵列的行分区的分布关系来产生渐增或渐减的起始栅极电压。例如，当所述像素阵列从上而下分为16个行分区时，每个行分区的栅极驱动电压可从最最大的35V，按顺序每一区降低0.3V，直到最后一个行分区为30.5V；每个行分区的栅极关闭电压可从最小的-10V，按顺序每一区增大0.1V，直到最后一个行分区为-8.5V。
所述时钟控制电路11是用以基于所述像素阵列的多个行分区的分布关系输出对应各行分区的时钟控制信号。具体而言，所述像素阵列的多个行分区的分布关系是指各个所述行分区与所述覆晶薄膜电路模组之间的距离关系，例如，当所述像素阵列分为16个行分区时，第一个行分区可以是离所述覆晶薄膜电路模组最远的行分区，第16个行分区可以是离所述覆晶薄膜电路模组最近的行分区。因此，当所述时钟控制电路11欲驱动某个行分区中的像素行时，所述时钟控制电路11是依据该行分区与所述覆晶薄膜电路模组之间的远近来确定提供给所述电平转换电路12的时钟控制信号。
在一实施例中，所述电平转换电路12可以是集成于所述覆晶薄膜电路模组中。所述电平转换电路12用以连接所述时钟控制电路11、所述电源管理电路10及所述GOA电路，用以受控于所述对应各行分区的时钟控制信号选用对应的栅极驱动电压，并将选用的栅极驱动电压进行电平转换后输出至所述GOA电路。
在本实施例中，具体而言，在所述时钟控制电路11依据各个行分区与所述覆晶薄膜电路模组之间的远近来确定提供给所述电平转换电路12的时钟控制信号中，其中对应至较远离所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路12选用较大的栅极驱动电压；对应较接近所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路12选用较小的栅极驱动电压。
由于连接到较远离所述覆晶薄膜电路模组的行分区的走线会造成较大的RC乘积值，且连接到较接近所述覆晶薄膜电路模组的行分区的走线会造成较小的RC乘积值，当为较远离所述覆晶薄膜电路模组的行分区选用较大的栅极驱动电压且为较接近所述覆晶薄膜电路模组的行分区的走线选用较小的栅极驱动电压时，所述电平转换电路12最终会输出一致的栅极驱动电压到所述GOA电路，来对液晶显示面板的扫描线逐行进行驱动。如此便能够保证每一行的充电是相当的，同时现有技术中栅极驱动电压VGH对于每个像素行充电时的电容耦合(Coupling)的影响存在不同差异的状况也能获得改善。
如图5A所示，所述电平转换电路12可包括一放大电路120，用以对所述选用的栅极驱动电压VGH_n进行电平转换，最终输出一致的栅极驱动电压VGH。
在一实施例中，所述电源管理电路10还用于通过一分压电路提供多个不同的栅极关闭电压。所述电平转换电路12受控于所述对应各行分区的时钟控制信号选用对应的栅极关闭电压，并将选用的栅极关闭电压进行电平转换后输出至所述GOA电路。
具体而言，在所述时钟控制电路11依据各个行分区与所述覆晶薄膜电路模组之间的远近来确定提供给所述电平转换电路12的时钟控制信号中，对应至较远离所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较小的栅极关闭电压；对应较接近所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较大的栅极关闭电压。
如图5B所示，所述电平转换电路12可包括一放大电路，用以对所述选用的栅极关闭电压VGL_n进行电平转换，最终输出一致的栅极关闭电压VGL。
由于连接到较远离所述覆晶薄膜电路模组的行分区的走线会造成较大的RC乘积值，且连接到较接近所述覆晶薄膜电路模组的行分区的走线会造成较小的RC乘积值，当为较远离所述覆晶薄膜电路模组的行分区选用较小的栅极关闭电压且为较接近所述覆晶薄膜电路模组的行分区的走线选用较大的栅极关闭电压时，所述电平转换电路12最终会输出一致的栅极关闭电压到所述GOA电路，来对液晶显示面板的扫描线逐行进行关闭。如此便能够让所述液晶显示面板在相对于所述覆晶薄膜电路模组位置的较远区域和较近区域的充电率达到一致，保证了面板显示的均匀及一致性。
本发明另提供一种包括如上所述的驱动电路的液晶显示面板。
综上所述，相较于现有技术，本发明主要是更改传统电平转换芯片(Level Shifter IC)的输出方式，根据像素阵列每一行分区与覆晶薄膜(COF)电路模组的相对位置来选择适合的VGH及VGL电压输出到GOA电路，保证最终在每一行能够达到的电压接近，以保证每一行的充电是相当的，同时现有技术中栅极驱动电压VGH对于每个像素行充电时的电容耦合的影响存在不同差异的状况也能获得改善。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (20)

  1. 一种驱动电路，其应用于一包括像素阵列、覆晶薄膜电路模组与GOA电路的液晶显示面板，其中所述驱动电路包含：
    一电源管理电路，用于通过分压电路提供多个不同的栅极驱动电压；
    一时钟控制电路，用以基于所述像素阵列的多个行分区的分布关系输出对应各行分区的时钟控制信号，其中所述像素阵列的多个行分区的分布关系是各个所述行分区与所述覆晶薄膜电路模组之间的距离关系；以及
    一电平转换电路，连接所述时钟控制电路、所述电源管理电路及所述GOA电路，用以受控于所述对应各行分区的时钟控制信号选用对应的栅极驱动电压，并将选用的栅极驱动电压进行电平转换后输出至所述GOA电路；其中对应至较远离所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较大的栅极驱动电压；对应较接近所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较小的栅极驱动电压；其中
    所述电源管理电路还用于通过分压电路提供多个不同的栅极关闭电压；所述电平转换电路受控于所述对应各行分区的时钟控制信号选用对应的栅极关闭电压，并将选用的栅极关闭电压进行电平转换后输出至所述GOA电路。
  2. 如权利要求1所述的驱动电路，其中，所述电平转换电路包括一放大电路，用以对所述选用的栅极驱动电压和栅极关闭电压进行电平转换。
  3. 一种驱动电路，其应用于一包括像素阵列、覆晶薄膜电路模组与GOA电路的液晶显示面板，其中所述驱动电路包含：
    一电源管理电路，用于通过分压电路提供多个不同的栅极驱动电压；
    一时钟控制电路，用以基于所述像素阵列的多个行分区的分布关系输出对应各行分区的时钟控制信号；以及
    一电平转换电路，连接所述时钟控制电路、所述电源管理电路及所述GOA电路，用以受控于所述对应各行分区的时钟控制信号选用对应的栅极驱动电压，并将选用的栅极驱动电压进行电平转换后输出至所述GOA电路。
  4. 如权利要求3所述的驱动电路，其中，所述像素阵列的多个行分区的分布关系是各个所述行分区与所述覆晶薄膜电路模组之间的距离关系。
  5. 如权利要求4所述的驱动电路，其中，对应至较远离所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较大的栅极驱动电压；对应较接近所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较小的栅极驱动电压。
  6. 如权利要求5所述的驱动电路，其中，所述电平转换电路包括一放大电路，用以对所述选用的栅极驱动电压进行电平转换。
  7. 如权利要求3所述的驱动电路，其中，所述电源管理电路，还用于通过分压电路提供多个不同的栅极关闭电压；所述电平转换电路受控于所述对应各行分区的时钟控制信号选用对应的栅极关闭电压，并将选用的栅极关闭电压进行电平转换后输出至所述GOA电路。
  8. 如权利要求7所述的驱动电路，其中，对应至较远离所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较小的栅极关闭电压；对应较接近所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较大的栅极关闭电压。
  9. 如权利要求8所述的驱动电路，其中，所述电平转换电路包括一放大电路，用以对所述选用的栅极关闭电压进行电平转换。
  10. 如权利要求3所述的驱动电路，其中，所述电平转换电路集成于所述覆晶薄膜电路模组中。
  11. 如权利要求10所述的驱动电路，其中，所述覆晶薄膜电路模组设置于所述液晶显示面板的一侧边，所述侧边与所述像素阵列的行分区平行。
  12. 一种液晶显示面板，其包括像素阵列、覆晶薄膜电路模组、GOA电路以及驱动电路，其中所述像素阵列包括多个像素行，并分成多个行分区，每个行分区包括一个以上的像素行，其中所述驱动电路包括：
    一电源管理电路，用于通过分压电路提供多个不同的栅极驱动电压；
    一时钟控制电路，用以基于所述像素阵列的多个行分区的分布关系输出对应各行分区的时钟控制信号；以及
    一电平转换电路，连接所述时钟控制电路、所述电源管理电路及所述GOA电路，用以受控于所述对应各行分区的时钟控制信号选用对应的栅极驱动电压，并将选用的栅极驱动电压进行电平转换后输出至所述GOA电路。
  13. 如权利要求12所述的液晶显示面板，其中，所述像素阵列的多个行分区的分布关系是各个所述行分区与所述覆晶薄膜电路模组之间的距离关系。
  14. 如权利要求13所述的液晶显示面板，其中，对应至较远离所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较大的栅极驱动电压；对应较接近所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较小的栅极驱动电压。
  15. 如权利要求14所述的液晶显示面板，其中，所述电平转换电路包括一放大电路，用以对所述选用的栅极驱动电压进行电平转换。
  16. 如权利要求12所述的液晶显示面板，其中，所述电源管理电路，还用于通过分压电路提供多个不同的栅极关闭电压；所述电平转换电路受控于所述对应各行分区的时钟控制信号选用对应的栅极关闭电压，并将选用的栅极关闭电压进行电平转换后输出至所述GOA电路。
  17. 如权利要求16所述的液晶显示面板，其中，对应至较远离所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较小的栅极关闭电压；对应较接近所述覆晶薄膜电路模组的行分区的时钟控制信号是控制所述电平转换电路选用较大的栅极关闭电压。
  18. 如权利要求17所述的液晶显示面板，其中，所述电平转换电路包括一放大电路，用以对所述选用的栅极关闭电压进行电平转换。
  19. 如权利要求12所述的液晶显示面板，其中，所述电平转换电路集成于所述覆晶薄膜电路模组中。
  20. 如权利要求19所述的液晶显示面板，其中，所述覆晶薄膜电路模组设置于所述液晶显示面板的一侧边，所述侧边与所述像素阵列的行分区平行。
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WO2020224318A1 (zh) * 2019-05-03 2020-11-12 神盾股份有限公司 显示面板驱动装置
CN110322855A (zh) 2019-07-11 2019-10-11 深圳市华星光电技术有限公司 Goa驱动电路及显示装置
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CN112967695A (zh) * 2021-03-19 2021-06-15 武汉京东方光电科技有限公司 液晶显示模组的驱动装置、驱动方法和液晶显示装置

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