WO2021031836A1 - 像素阵列基板 - Google Patents

像素阵列基板 Download PDF

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Publication number
WO2021031836A1
WO2021031836A1 PCT/CN2020/106658 CN2020106658W WO2021031836A1 WO 2021031836 A1 WO2021031836 A1 WO 2021031836A1 CN 2020106658 W CN2020106658 W CN 2020106658W WO 2021031836 A1 WO2021031836 A1 WO 2021031836A1
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WO
WIPO (PCT)
Prior art keywords
data line
pads
line pads
scan line
scan
Prior art date
Application number
PCT/CN2020/106658
Other languages
English (en)
French (fr)
Inventor
李仰淳
郑圣谚
钟岳宏
李珉泽
廖光祥
连翔琳
王彦凯
徐雅玲
廖烝贤
Original Assignee
友达光电股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 友达光电股份有限公司 filed Critical 友达光电股份有限公司
Priority to DE112020003937.4T priority Critical patent/DE112020003937B4/de
Priority to KR1020217005464A priority patent/KR102524241B1/ko
Publication of WO2021031836A1 publication Critical patent/WO2021031836A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure

Definitions

  • the present invention relates to a pixel array substrate, and more particularly to a pixel array substrate in which scan line pads and data line pads are arranged along an arrangement direction.
  • the display panel Since the display panel has the advantages of small size and low radiation, the display panel has been widely used in various electronic products.
  • a large area of the driving circuit area is usually reserved at the periphery of the display area to install the driving circuit, and the sub-pixels are controlled by the driving circuit.
  • the driving circuit area located outside the display area makes the display panel have a very wide frame and limits the screen-to-body ratio of the product.
  • consumers With the advancement of technology, consumers have higher and higher requirements for the appearance of display panels. In order to increase consumers' willingness to buy, how to increase the screen-to-body ratio of display panels has become one of the problems that manufacturers want to solve.
  • the invention provides a pixel array substrate, which can improve the problem of signal mutual interference between scan line pads and data line pads.
  • At least one embodiment of the present invention provides a pixel array substrate including multiple scan line pads, multiple data line pads, multiple scan lines, multiple data lines, multiple gate transmission lines, multiple pixels, data Line signal chip and scan line signal chip.
  • the scan line pads and the data line pads are located on the substrate.
  • the scan line extends along the first direction.
  • the data line and the gate transmission line extend along the second direction.
  • the data line is electrically connected to the data line pad.
  • the scan line is electrically connected to the scan line pad through the gate transmission line.
  • the pixels are located on the substrate.
  • the ratio of the number of rows of pixels arranged along the first direction to the number of rows of pixels arranged along the second direction is X:Y.
  • Each pixel includes m sub-pixels, and the sub-pixels are electrically connected to the scan line and the data line.
  • the data line signal chip is electrically connected to the data line pad, and the scan line signal chip is electrically connected to the scan line pad.
  • At least one embodiment of the present invention provides a pixel array substrate including a plurality of scan line pads, a plurality of first data line pads, a plurality of second data line pads, a plurality of third data line pads, and a plurality of Scan lines, multiple data lines, multiple gate transmission lines, multiple red sub-pixels, multiple green sub-pixels, multiple blue sub-pixels, and at least one thin-film-on-chip packaging circuit.
  • the scan line pads, the first data line pads, the second data line pads and the third data line pads are located on the substrate.
  • the scan line pads, the first data line pads, the second data line pads, and the third data line pads are arranged in the arrangement direction.
  • the scan line extends along the first direction.
  • the data line and the gate transmission line extend along the second direction.
  • the scan line is electrically connected to the scan line pad through the gate transmission line.
  • the data line is electrically connected to the first data line pad, the second data line pad and the third data line pad.
  • the red sub-pixel, the green sub-pixel, and the blue sub-pixel are electrically connected to the scan line and the data line.
  • the red sub-pixel is electrically connected to the first data line pad.
  • the green sub-pixel is electrically connected to the second data line pad.
  • the blue sub-pixel is electrically connected to the third data line pad.
  • the number of scan line pads located between the first data line pads and the second data line pads or between the third data line pads and the second data line pads in the arrangement direction is less than that of the first data line pads.
  • the chip on film package circuit includes a data line signal chip and a scan line signal chip.
  • the data line signal chip is electrically connected to the first data line pad, the second data line pad and the third data line pad.
  • the scan line signal chip is electrically connected to the scan line pad.
  • FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the invention.
  • FIG. 2A is a schematic top view of a display area of a pixel array substrate according to an embodiment of the invention.
  • 2B is a schematic top view of a sub-pixel according to an embodiment of the invention.
  • 3A is a schematic top view of a chip-on-film package circuit according to an embodiment of the invention.
  • 3B is a schematic top view of a chip-on-film package circuit according to an embodiment of the invention.
  • FIG. 4 is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic top view of a pixel array substrate according to an embodiment of the invention.
  • FIG. 6 is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to Embodiment 2 of the present invention.
  • FIG. 7 is a schematic top view of a pixel array substrate according to an embodiment of the invention.
  • FIG. 8 is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to Embodiment 3 of the present invention.
  • FIG. 9 is a schematic top view of a pixel array substrate according to an embodiment of the invention.
  • Fig. 10A is a schematic cross-sectional view taken along line aa' in Fig. 9.
  • Fig. 10B is a schematic cross-sectional view taken along line bb' of Fig. 9.
  • GI Gate insulating layer
  • PE pixel electrode
  • first and second may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, and/or parts should not Subject to these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section.
  • FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the invention.
  • 2A is a schematic top view of a display area of a pixel array substrate according to an embodiment of the invention.
  • FIG. 2B is a schematic top view of the sub-pixel in FIG. 2A.
  • 3A is a schematic top view of a chip-on-film package circuit according to an embodiment of the present invention.
  • FIG. 3A is, for example, an enlarged schematic diagram of the chip-on-film package circuit COF of FIG. 3B is a schematic top view of a chip-on-film package circuit according to an embodiment of the invention.
  • the pixel array substrate 10 includes a plurality of scan line pads G and a plurality of data line pads (such as a first data line pad D1, a second data line pad D2, and a third data line pad D3) , A plurality of scan lines 110, a plurality of data lines 210, a plurality of gate transmission lines 120, a plurality of pixels (not shown in FIG. 1), and at least one COF.
  • the pixel array substrate 10 further includes a plurality of first fan-out lines 130 and a plurality of second fan-out lines 220.
  • the substrate SB has a display area AA and a peripheral area BA located outside the display area AA.
  • the material of the substrate SB can be glass, quartz, organic polymer, or opaque/reflective material (for example, conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. If conductive material or metal is used, an insulating layer (not shown) is covered on the carrier board SB to avoid short circuit problems.
  • the scan line pad G is located on the substrate SB. In this embodiment, the scan line pad G is located on the peripheral area BA.
  • the first fan-out line 130 electrically connects the scan line pad G to the gate transmission line 120.
  • the scan line 110 and the gate transmission line 120 are located on the display area AA.
  • the scan line 110 extends along the first direction E1, and the gate transmission line 120 extends along the second direction E2.
  • the gate transmission line 120 is electrically connected to the scan line 110 through the switching structure CS, and the scan line 110 is electrically connected to the scan line pad G through the gate transmission line 120 and the first fan-out line 130.
  • each scan line pad G is electrically connected to the corresponding two scan lines 110, thereby reducing the number of scan line pads G, but the invention is not limited thereto. In other embodiments, different scan lines 110 do not share the same scan line pad G.
  • the data line pads (such as the first data line pad D1, the second data line pad D2, and the third data line pad D3) are located on the substrate SB. In this embodiment, the data line pads are located on the peripheral area BA.
  • the second fan-out line 220 is electrically connected to the data line pad to the data line 210.
  • the data line 210 extends along the second direction E2.
  • each pixel 300 includes a red sub-pixel P1, a green sub-pixel P2, and a blue sub-pixel P3, but the invention is not limited to this. In other embodiments, each pixel PX further includes sub-pixels of other colors.
  • the pixel array substrate 10 is driven in a HG2D (half-gate two-data line) manner, and each sub-pixel (red sub-pixel P1, green sub-pixel P2) And the blue sub-pixel P3) overlaps the corresponding two of the data lines 210 and the corresponding one of the scan lines 110.
  • HG2D half-gate two-data line
  • the sub-pixels are electrically connected to the scan line 110 and the data line 210.
  • the red sub-pixel P1, the green sub-pixel P2, and the blue sub-pixel P3 are electrically connected to the scan line 110 and the data line 210.
  • the red sub-pixel P1 is electrically connected to the first data line pad D1.
  • the green sub-pixel P2 is electrically connected to the second data line pad D2.
  • the blue sub-pixel P3 is electrically connected to the third data line pad D3.
  • Each sub-pixel includes a switching element T and a pixel electrode PE.
  • the switching element T includes a gate GE, a channel layer CH, a source SE, and a drain DE.
  • the gate GE is located on the substrate SB and is electrically connected to the corresponding scan line 110.
  • the channel layer CH overlaps the gate GE, and a gate insulating layer is sandwiched between the channel layer CH and the gate GE (illustration omitted in the figure).
  • the source SE and the drain DE are electrically connected to the channel layer CH.
  • the source SE is electrically connected to the data line 210.
  • the flat layer (illustration omitted in the figure) is located on the source SE and the drain DE.
  • the pixel electrode PE is located on the flat layer and is electrically connected to the drain electrode DE through the opening O penetrating the flat layer.
  • the pixel array substrate 10 further includes a common signal line CL1, a common signal line CL2, and a common signal line CL3.
  • the common signal line CL1, the common signal line CL2, and the scan line 110 all extend along the first direction E1, and the common signal line CL1, the common signal line CL2, and the scan line 110 belong to the same conductive layer (for example, the first metal layer).
  • the common signal line CL3, the data line 210, and the gate transmission line 120 all extend along the second direction E2, and the common signal line CL3, the data line 210, and the gate transmission line 120 belong to the same conductive layer (for example, a second metal layer).
  • the scan line pads G and the data line pads are arranged in the arrangement direction RD.
  • the scan line pads G and the data line pads are arranged in a first row L1 and a second row L2 in the arrangement direction RD.
  • the pads in the first row L1 are aligned with each other, and the pads in the second row L2 are aligned with each other.
  • the pads located in the first row L1 and the pads located in the second row L2 belong to different metal layers.
  • the pads located in the first row L1 belong to the first metal layer
  • the pads located in the second row L1 belong to the first metal layer
  • the pads of the two rows L2 belong to the second metal layer, and an insulating layer is provided between the first metal layer and the second metal layer, so as to avoid short circuits between adjacent pads.
  • the scan line connected between the first data line pad D1 and the second data line pad D2 or between the third data line pad D3 and the second data line pad D2 in the arrangement direction RD The number of pads G is less than the number of scan line pads G located between the first data line pad D1 and the third data line pad D3, thereby improving the gap between the scan line pads G and the data line pads. The effect of signal interference on the display screen.
  • the chip on film package circuit COF is electrically connected to the scan line pad G and the data line pad D (for example, the first data line pad D1, the second data line pad D2, and the third data line pad D3).
  • the COF includes a data line signal chip DC, a scan line signal chip GC, a first insulating layer I1, a second insulating layer I2, a third insulating layer I3, and a first wire layer CC1.
  • the second wire layer CC2 a plurality of first connection structures CH1, a plurality of second connection structures CH2, a plurality of third connection structures CH3, and a plurality of fourth connection structures CH4.
  • the first insulating layer I1, the second insulating layer I2, and the third insulating layer I3 overlap in order.
  • the data line signal chip DC and the scan line signal chip GC are located on the first insulating layer I1.
  • the first wire layer CC1 is located between the second insulating layer I2 and the first conductive layer I1.
  • the plurality of first connection structures CH1 penetrate the first insulating layer I1 and are electrically connected to the first wire layer CC1.
  • the second wire layer CC2 is located between the second insulating layer I2 and the third conductive layer I3.
  • the plurality of second connecting structures CH2 penetrate the first insulating layer I1 and the second insulating layer I2, and are electrically connected to the second conductive layer CC2.
  • the wiring space of the first wire layer CC1 and the second wire layer CC2 can be effectively increased.
  • the third connection structure CH3 penetrates the second insulating layer I2 and the third conductive layer I3, and is electrically connected to the first wire layer CC1.
  • the plurality of fourth connection structures CH4 penetrate the third insulating layer I3 and are electrically connected to the second wire layer CC2.
  • the data line signal chip DC is electrically connected to one of the first conductive layer CC1 and the second conductive layer CC2, and the scan line signal chip GC is electrically connected to the other of the first conductive layer CC1 and the second conductive layer CC2 By.
  • the data line signal chip DC is electrically connected to the first conductive layer CC1
  • the scan line signal chip GC is electrically connected to the second conductive layer CC2.
  • the data line signal chip DC is electrically connected to the data line pads (for example, the first data line pad D1, the second data line pad D2, and the third data line pad D3 of FIG. 1), and the scan line signal chip GC is electrically connected Connect to the scan line pad G.
  • the data line signal chip DC and the scan line signal chip GC are both located on the same side of the display area AA. Therefore, the frame of the display panel can be reduced, thereby increasing the screen-to-body ratio of the display device.
  • the width between the side of the display area AA where the COF is not provided and the edge of the pixel array substrate 10 is less than 2 mm.
  • a chip-on-film package circuit COF includes a data line signal chip DC and a scan line signal chip GC. Therefore, the first fan-out line 130 and the second fan-out line 220 may not overlap each other, thereby improving the first The signal interference between one fan-out line 130 and the second fan-out line 220 affects the display image.
  • the pixel array substrate 10 includes n scan line signal chips GC.
  • the pixel array substrate 10 includes two chip-on-film packages COF, and each chip-on-film package circuit COF has one scan line signal chip GC. Therefore, the pixel array substrate 10 includes two scan line signal chips.
  • GC that is, n is 2. In other embodiments, n is greater than 2.
  • each scan line 110 is electrically connected to multiple scan line signal chips GC, so that the signal on the scan line 110 can be distributed more evenly.
  • the pixel array substrate 10 includes n scan line signal chips GC, and each scan line 110 is electrically connected to the n scan line signal chips GC.
  • FIG. 4 is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to Embodiment 1 of the present invention.
  • the scan line pads G and the data line pads D are arranged into a plurality of repeating units PU in the arrangement direction RD, and each The total number of scan line pads G and data line pads D in the repeating unit PU is U.
  • the scan line pads G and the data line pads D in the repeating unit PU can be divided into a first row L1 and a second row L2 as shown in FIG. 1.
  • the first pad in the first row L1 in Figure 1 is the first pad in Figure 4
  • the first pad in the second row L2 in Figure 1 is the second pad in Figure 4.
  • the second pad in the first row L1 in FIG. 1 is the third pad in FIG. 4, and the arrangement order of the other pads is similarly deduced.
  • the ratio of the number of rows of pixels PX arranged along the first direction E1 to the number of rows of pixels PX arranged along the second direction E2 is X:Y.
  • X:Y is 16:9.
  • each pixel PX includes m sub-pixels, where m is a positive integer.
  • the scan line pad G and the data line pad D conform to the rule of Formula 1.
  • n is the number of scan line signal chips, and a, k, and h are positive integers.
  • the pixel array substrate is driven in HG2D mode, and each sub-pixel overlaps two data lines and one scan line.
  • each scan line pad G is electrically connected to two corresponding scan lines.
  • part of the scan line pads G is located in the first row L1
  • another part of the scan line pads G is located in the second row L2 (as shown in FIG. 1)
  • part of the scan line pads G belongs to the first metal layer
  • another part of the scan line pad G belongs to the second metal layer.
  • a is 1
  • k is 4
  • h is 1.
  • Each pixel PX includes 3 sub-pixels, that is, m is 3.
  • the pixel array substrate has 3 scan line signal chips, that is, n is 3.
  • Embodiment 1 in order to make the scan line pads G and the data line pads D more uniformly dispersed, the number of data line pads D between two adjacent scan line pads G in the arrangement direction RD R conforms to the rules of formula 2.
  • N is an integer between 1 and k+1.
  • R 2 ⁇ 3 ⁇ 1 to 2 ⁇ 3 ⁇ 5, which means that the number of data line pads D between two adjacent scan line pads G is between 6 and 30.
  • FIG. 5 is a schematic top view of a pixel array substrate according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 5 uses the element numbers and part of the content of the embodiment of FIG. 1, wherein the same or similar reference numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the foregoing embodiment, which is not repeated here.
  • the difference between the pixel array substrate 20 of FIG. 5 and the pixel array substrate 10 of FIG. 1 is that in the pixel array substrate 20, different scan lines 110 do not share the same scan line pad G.
  • each gate transmission line 120 is electrically connected to a corresponding scan line pad G to a corresponding scan line 110.
  • FIG. 6 is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to Embodiment 2 of the present invention.
  • the scan line pads G and the data line pads D are arranged into a plurality of repeating units PU in the arrangement direction RD, and each The total number of scan line pads G and data line pads D in the repeating unit PU is U.
  • the scan line pads G and the data line pads D in the repeating unit PU can be divided into a first row L1 and a second row L2 as shown in FIG. 5.
  • the first pad in the first row L1 in Figure 5 is the first pad in Figure 6, and the first pad in the second row L2 in Figure 5 is the second pad in Figure 6,
  • the second pad in the first row L1 in FIG. 5 is the third pad in FIG. 6, and the arrangement order of the other pads is similarly deduced.
  • each pixel PX includes m sub-pixels, where m is a positive integer.
  • the scan line pad G and the data line pad D conform to the rule of Formula 1.
  • the pixel array substrate is driven in HG2D mode, and each sub-pixel overlaps two data lines and one scan line.
  • each scan line pad G is electrically connected to a corresponding scan line, and different scan lines are not directly electrically connected through the scan line pad or the gate transmission line.
  • part of the scan line pads G is located in the first row L1
  • another part of the scan line pads G is located in the second row L2 (as shown in FIG. 5)
  • part of the scan line pads G belongs to the first metal layer
  • And another part of the scan line pad G belongs to the second metal layer.
  • a 1, k is 2, and h is 1.
  • Each pixel PX includes 3 sub-pixels, that is, m is 3.
  • the pixel array substrate has 3 scan line signal chips, that is, n is 3.
  • the number of data line pads D between two adjacent scan line pads G in the arrangement direction RD R conforms to the rules of formula 2.
  • R 2 ⁇ 3 ⁇ 1 to 2 ⁇ 3 ⁇ 3, which means that the number of data line pads D between two adjacent scan line pads G is between 6 to 18.
  • FIG. 7 is a schematic top view of a pixel array substrate according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 7 uses the element numbers and part of the content of the embodiment of FIG. 2A, wherein the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the foregoing embodiment, which is not repeated here.
  • the difference between the pixel array substrate 30 of FIG. 7 and the pixel array substrate 10 of FIG. 2A is that the pixel array substrate 30 is driven in a 1G1D (one-gate one-data line) manner, and each sub-pixel (red sub-pixel P1, green sub-pixel The sub-pixel P2 and the blue sub-pixel P3) overlap the corresponding one of the data lines 210 and the corresponding one of the scan lines 110.
  • 1G1D one-gate one-data line
  • Fig. 8 is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to Embodiment 3 of the present invention.
  • the scan line pads G and the data line pads D are arranged into a plurality of repeating units PU in the arrangement direction RD, and each The total number of scan line pads G and data line pads D in the repeating unit PU is U.
  • FIG. 8 is used to show the arrangement sequence of the scan line pads G and the data line pads D in the repeating unit PU, and the scan line pads G and the data line pads D in the repeating unit PU are not completely aligned.
  • the scan line pads G and the data line pads D in the repeating unit PU can be divided into a first row L1 and a second row L2 as shown in FIG. 5.
  • the first pad in the first row L1 in Figure 1 is the first pad in Figure 8
  • the first pad in the second row L2 in Figure 5 is the second pad in Figure 8.
  • the second pad in the first row L1 in FIG. 5 is the third pad in FIG. 8, and the arrangement order of the other pads is similarly deduced.
  • each pixel PX includes m sub-pixels, where m is a positive integer.
  • the scan line pad G and the data line pad D conform to the rule of Formula 1.
  • the pixel array substrate is driven in a 1G1D manner, and each sub-pixel overlaps a data line and a scan line.
  • each scan line pad G is electrically connected to a corresponding scan line, and different scan lines are not directly electrically connected through the scan line pad or the gate transmission line.
  • part of the scan line pads G is located in the first row L1, another part of the scan line pads G is located in the second row L2 (as shown in FIG. 5), and part of the scan line pads G belongs to the first metal layer , And another part of the scan line pad G belongs to the second metal layer.
  • a is 1
  • k is 1
  • h is 1.
  • Each pixel PX includes 3 sub-pixels, that is, m is 3.
  • the pixel array substrate has 3 scan line signal chips, that is, n is 3.
  • Embodiment 3 in order to make the scan line pads G and the data line pads D more evenly dispersed, the number of data line pads D between two adjacent scan line pads G in the arrangement direction RD R conforms to the rules of formula 2.
  • R 2 ⁇ 3 ⁇ 1 to 2 ⁇ 3 ⁇ 2, which means that the number of data line pads D between two adjacent scan line pads G is between 6 and 12.
  • FIG. 9 is a schematic top view of a pixel array substrate according to an embodiment of the invention.
  • Fig. 10A is a schematic cross-sectional view taken along line aa' in Fig. 9.
  • Fig. 10B is a schematic cross-sectional view taken along line bb' of Fig. 9.
  • the embodiment of FIG. 9 uses the element numbers and part of the content of the embodiment of FIG. 5, wherein the same or similar reference numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the foregoing embodiment, which is not repeated here.
  • the scan line pads G are all located in the same row.
  • the scan line pads G are all located in the first row L1 or the scan line pads G are all located in the second row.
  • the pads located in the first row L1 (including the scan line pads G and the data line pads D) belong to the first metal layer M1
  • the pads located in the second row L2 (including the data line pads) D) belongs to the second metal layer M2.
  • the pads in the second row L2 belong to the first metal layer M1
  • the pads in the first row L1 belong to the second metal layer M2.
  • all the scan line pads G are aligned with each other in the arrangement direction RD.
  • the scan line pads G belong to the first metal layer M1. Therefore, it is possible to reduce the number of different scan lines 110 due to the transfer structure (for example, the transfer from the first metal layer M1 to the second metal layer M2). Connection structure) and cause the signal to be offset.
  • the transfer structure for example, the transfer from the first metal layer M1 to the second metal layer M2. Connection structure
  • the first metal layer M1 is located on the substrate SB.
  • the gate insulating layer GI covers the first metal layer M1.
  • the gate insulating layer GI on the pad (such as the scan line pad G) belonging to the first metal layer M1 has a through hole TH1.
  • the flat layer PL is located on the gate insulating layer GI, and on the pads belonging to the first metal layer M1 (such as the scan line pad G) and on the pads belonging to the second metal layer M2 (such as the third data line pad D3). ) Has through holes TH2.
  • a plurality of conductive structures CP are filled in the through hole TH1 and the through hole TH2 to be electrically connected to the corresponding scan line pad G and the third data line pad D3, respectively.
  • the material of the conductive structure CP includes, for example, metal oxide.
  • the pixel array substrate is driven in HG2D, and each sub-pixel overlaps two data lines and one scan line.
  • each scan line pad G is electrically connected to two corresponding scan lines.
  • all the scan line pads G belong to the same metal layer (for example, the first metal layer or the second metal layer).
  • a is 2
  • k is 4
  • h is 1.
  • Each pixel PX includes 3 sub-pixels, that is, m is 3.
  • the pixel array substrate has 3 scan line signal chips, that is, n is 3.
  • Embodiment 4 in order to make the scan line pads G and the data line pads D more evenly dispersed, the number of data line pads D between two adjacent scan line pads G in the arrangement direction RD R conforms to the rules of Equation 3.
  • N is an integer between 1 and k+1.
  • R 2 ⁇ 3 ⁇ 1+1 to 2 ⁇ 3 ⁇ 5+1, which means that the number of data line pads D between two adjacent scan line pads G is between 7 and 31.
  • the invention provides a pixel array substrate, which can improve the problem of signal mutual interference between scan line pads and data line pads.

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Abstract

一种像素阵列基板(10,20,30)，包括多个扫描线接垫(G)、多个数据线接垫(D1, D2, D3)、多条扫描线(110)、多条数据线(210)、多条栅极传输线(120)、多个像素(PX)、数据线信号晶片(DC)以及扫描线信号晶片(GC)。扫描线(110)沿着第一方向(E1)延伸。数据线(210)以及栅极传输线(120)沿着第二方向(E2)延伸。数据线(210)电性连接至数据线接垫(D1, D2, D3)。扫描线(110)通过栅极传输线(120)电性连接至扫描线接垫(G)。沿着第一方向(E1)排列的像素(PX)的排数与沿着第二方向(E2)排列的像素(PX)的排数的比为X：Y。各像素(PX)包括m个子像素(P1,P2,P3)。

Description

像素阵列基板 技术领域
本发明是有关于一种像素阵列基板，且特别是有关于一种扫描线接垫以及数据线接垫沿着一排列方向排列的像素阵列基板。
背景技术
由于显示面板具有体积小、辐射低等优点，显示面板已经普遍地被应用在各式各样的电子产品中。在现有的显示面板中，通常会于显示区的***保留大面积的驱动电路区来设置驱动电路，并藉由驱动电路来控制子像素。然而，位于显示区外侧的驱动电路区使显示面板具有很宽的边框，并限缩了产品的屏占比。随着科技的进步，消费者对显示面板外观的要求越来越高，为了要提高消费者的购买意愿，如何增加显示面板的屏占比已经成为目前各家厂商欲解决的问题之一。
发明公开
本发明提供一种像素阵列基板，能改善扫描线接垫以及数据线接垫之间信号互相干扰的问题。
本发明的至少一实施例提供一种像素阵列基板，包括多个扫描线接垫、多个数据线接垫、多条扫描线、多条数据线、多条栅极传输线、多个像素、数据线信号晶片以及扫描线信号晶片。扫描线接垫以及数据线接垫位于基板上。扫描线沿着第一方向延伸。数据线以及栅极传输线沿着第二方向延伸。数据线电性连接至数据线接垫。扫描线通过栅极传输线电性连接至扫描线接垫。像素位于基板上。沿着第一方向排列的像素的排数与沿着第二方向排列的像素的排数的比为X：Y。各像素包括m个子像素，且子像素电性连接至扫描线以及数据线。数据线信号晶片电性连接至数据线接垫，且扫描线信号晶片电性连接至扫描线接垫。扫描线接垫以及数据线接垫在一排列方向上排列成多个重复单元，且每个重复单元中的扫描线接垫以及数据线接垫的数量总合为U个。U＝a×(k×m×X+h×n×Y)，其中n为扫描线信号晶片的数量，且a、k以及h为正整数。
本发明的至少一实施例提供一种像素阵列基板包括多个扫描线接垫、多个第一数据线接垫、多个第二数据线接垫、多个第三数据线接垫、多条扫描线、多条数据线、多条栅极传输线、多个红色子像素、多个绿色子像素、多个蓝色子像素以及至少一个薄膜覆晶封装电路。扫描线接垫、第一数据线接垫、第二数据线接垫以及第三数据线接垫位于基板上。扫描线接垫、第一数据线接垫、第二数据线接垫以及第三数据线接垫在排列方向上排列。扫描线沿着第一方向延伸。数据线以及栅极传输线沿着第二方向延伸。扫描线通过栅极传输线电性连接至扫描线接垫。数据线电性连接至第一数据线接垫、第二数据线接垫以及第三数据线接垫。红色子像素、绿色子像素以及蓝色子像素电性连接至扫描线以及数据线。红色子像素电性连接至第一数据线接垫。绿色子像素电性连接至第二数据线接垫。蓝色子像素电性连接至第三数据线接垫。在排列方向上位于第一数据线接垫与第二数据线接垫之间或第三数据线接垫与第二数据线接垫之间的扫描线接垫的数量少于位于第一数据线接垫与第三数据线接垫之间的扫描线接垫的数量。薄膜覆晶封装电路包括数据线信号晶片以及扫描线信号晶片。数据线信号晶片电性连接至第一数据线接垫、第二数据线接垫以及第三数据线接垫。扫描线信号晶片电性连接至扫描线接垫。
附图简要说明
图1是依照本发明的一实施例的一种像素阵列基板的上视示意图。
图2A是依照本发明的一实施例的一种像素阵列基板的显示区的上视示意图。
图2B是依照本发明的一实施例的一种子像素的上视示意图。
图3A是依照本发明的一实施例的一种薄膜覆晶封装电路的上视示意图。
图3B是依照本发明的一实施例的一种薄膜覆晶封装电路的上视示意图。
图4是依照本发明的实施例1的一种扫描线接垫与数据线接垫的排列顺序的示意图。
图5是依照本发明的一实施例的一种像素阵列基板的上视示意图。
图6是依照本发明的实施例2的一种扫描线接垫与数据线接垫的排列顺序的示意图。
图7是依照本发明的一实施例的一种像素阵列基板的上视示意图。
图8是依照本发明的实施例3的一种扫描线接垫与数据线接垫的排列顺序的示意图。
图9是依照本发明的一实施例的一种像素阵列基板的上视示意图。
图10A是图9线aa’的剖面示意图。
图10B是图9线bb’的剖面示意图。
其中，附图标记：
10、20、30:像素阵列基板
110:扫描线
120:栅极传输线
130:第一扇出线
210:数据线
220:第二扇出线
AA:显示区
BA:周边区
CC1:第一导线层
CC2:第二导线层
CH:通道层
CH1:第一连接结构
CH2:第二连接结构
CH3:第三连接结构
CH4:第四连接结构
CS:转接结构
COF:薄膜覆晶封装电路
D1:第一数据线接垫
D2:第二数据线接垫
D3:第三数据线接垫
DC:数据线信号晶片
DE:漏极
E1:第一方向
E2:第二方向
G:扫描线接垫
GC:扫描线信号晶片
GE:栅极
GI:栅绝缘层
I1:第一绝缘层
I2:第二绝缘层
I3:第三绝缘层
L1:第一排
L2:第二排
M1:第一金属层
M2:第二金属层
P1:红色子像素
P2:绿色子像素
P3:蓝色子像素
O:开口
PE:像素电极
PL:平坦层
PU:重复单元
PX:像素
RD:排列方向
SB:基板
SE:源极
T:开关元件
TH1、TH2：通孔
实现本发明的最佳方式
以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。
在整个说明书中，相同的附图标记表示相同或类似的元件。在附图中， 为了清楚起见，放大了层、膜、面板、区域等的厚度。应当理解，当诸如层、膜、区域或基板的元件被称为“在另一元件上”或“连接另一元件”时，其可以直接在另一元件上或与另一元件连接，或者所述元件与所述另一元件中间可以也存在其他元件。相反，当元件被称为“直接在另一元件上”或“直接连接另一元件”时，所述元件与所述另一元件中间不存在其他元件。如本文所使用的，“连接”可以指物理及/或电性连接。再者，二元件互相“电性连接”或“耦合”可为二元件间存在其它元件。
应当理解，尽管术语“第一”与“第二”等在本文中可以用于描述各种元件、部件、区域、层及/或部分，但是这些元件、部件、区域、及/或部分不应受这些术语的限制。这些术语仅用于将一个元件、部件、区域、层或部分与另一个元件、部件、区域、层或部分区分开。
图1是依照本发明的一实施例的一种像素阵列基板的上视示意图。图2A是依照本发明的一实施例的一种像素阵列基板的显示区的上视示意图。图2B是图2A的子像素的上视示意图。图3A是依照本发明的一实施例的一种薄膜覆晶封装电路的上视示意图，其中图3A例如是图1的薄膜覆晶封装电路COF的放大示意图。图3B是依照本发明的一实施例的一种薄膜覆晶封装电路的上视示意图。
请参考图1，像素阵列基板10包括多个扫描线接垫G、多个数据线接垫(例如第一数据线接垫D1、第二数据线接垫D2及第三数据线接垫D3)、多条扫描线110、多条数据线210、多条栅极传输线120、多个像素(图1未绘出)以及至少一个薄膜覆晶封装电路COF。在本实施例中，像素阵列基板10还包括多条第一扇出线130以及多条第二扇出线220。
基板SB上具有显示区AA以及位于显示区AA外侧的周边区BA。基板SB的材质可为玻璃、石英、有机聚合物、或是不透光/反射材料(例如：导电材料、金属、晶圆、陶瓷或其它可适用的材料)或是其它可适用的材料。若使用导电材料或金属时，则在载板SB上覆盖一层绝缘层(未绘示)，以避免短路问题。
扫描线接垫G位于基板SB上。在本实施例中，扫描线接垫G位于周边区BA上。第一扇出线130电性连接扫描线接垫G至栅极传输线120。扫描线110以及栅极传输线120位于显示区AA上。扫描线110沿着第一方向E1延伸， 且栅极传输线120沿着第二方向E2延伸。在本实施例中，栅极传输线120通过转接结构CS而电性连接至扫描线110，扫描线110通过栅极传输线120以及第一扇出线130而电性连接至扫描线接垫G。
在本实施例中，各扫描线接垫G电性连接至对应的两条扫描线110，藉此减少扫描线接垫G的数量，但本发明不以此为限。在其他实施例中，不同条扫描线110并未共用同一个扫描线接垫G。
数据线接垫(例如第一数据线接垫D1、第二数据线接垫D2及第三数据线接垫D3)位于基板SB上。在本实施例中，数据线接垫位于周边区BA上。第二扇出线220电性连接数据线接垫至数据线210。数据线210沿着第二方向E2延伸。
请参考图1与图2A，像素PX位于基板SB上。在本实施例中，每个像素300包括红色子像素P1、绿色子像素P2以及蓝色子像素P3，但本发明不以此为限。在其他实施例中，每个像素PX还包括其他颜色的子像素。
请参考图1、图2B与图2A，在本实施例中，像素阵列基板10是以HG2D(half-gate two-data line)的方式驱动，各子像素(红色子像素P1、绿色子像素P2以及蓝色子像素P3)重叠于数据线210中对应的两条以及扫描线110中对应的一条。
子像素电性连接至扫描线110以及数据线210。在本实施例中，红色子像素P1、绿色子像素P2以及蓝色子像素P3电性连接至扫描线110以及数据线210。红色子像素P1电性连接至第一数据线接垫D1。绿色子像素P2电性连接至第二数据线接垫D2。蓝色子像素P3电性连接至第三数据线接垫D3。
各子像素包括开关元件T以及像素电极PE。开关元件T包括栅极GE、通道层CH、源极SE以及漏极DE。
栅极GE位于基板SB上，且电性连接至对应的扫描线110。通道层CH重叠于栅极GE，且通道层CH与栅极GE之间夹有栅极绝缘层(图中省略绘示)。
源极SE以及漏极DE电性连接至通道层CH。源极SE电性连接至数据线210。平坦层(图中省略绘示)位于源极SE以及漏极DE上。像素电极PE位于平坦层上，且通过贯穿平坦层的开口O而电性连接至漏极DE。
在一些实施例中，像素阵列基板10还包括共用信号线CL1、共用信号线CL2以及共用信号线CL3。共用信号线CL1、共用信号线CL2以及扫描线110 皆沿着第一方向E1延伸，且共用信号线CL1、共用信号线CL2以及扫描线110属于相同导电层(例如第一金属层)。共用信号线CL3、数据线210以及栅极传输线120皆沿着第二方向E2延伸，且共用信号线CL3、数据线210以及栅极传输线120属于相同导电层(例如第二金属层)。
扫描线接垫G以及数据线接垫(例如第一数据线接垫D1、第二数据线接垫D2及第三数据线接垫D3)在排列方向RD上排列。在本实施例中，扫描线接垫G以及数据线接垫在排列方向RD上排成第一排L1以及第二排L2。第一排L1中的接垫彼此对齐，且第二排L2中的接垫彼此对齐。藉由将扫描线接垫G以及数据线接垫在排列方向RD上排成两排能更有效的利用布线空间。在一些实施例中，位于第一排L1的接垫与位于第二排L2的接垫分别属于不同金属层，举例来说，位于第一排L1的接垫属于第一金属层，而位于第二排L2的接垫属于第二金属层，第一金属层与第二金属层之间隔有绝缘层，藉此可以避免相邻的接垫之间短路。
在一些实施例中，在排列方向RD上位于第一数据线接垫D1与第二数据线接垫D2之间或第三数据线接垫D3与第二数据线接垫D2之间的扫描线接垫G的数量少于位于第一数据线接垫D1与第三数据线接垫D3之间的扫描线接垫G的数量，藉此能改善扫描线接垫G以及数据线接垫之间的信号干扰对显示画面所造成的影响。
薄膜覆晶封装电路COF电性连接至扫描线接垫G以及数据线接垫D(例如第一数据线接垫D1、第二数据线接垫D2及第三数据线接垫D3)。
请参考图3A与图3B，薄膜覆晶封装电路COF包括数据线信号晶片DC、扫描线信号晶片GC、第一绝缘层I1、第二绝缘层I2、第三绝缘层I3、第一导线层CC1、第二导线层CC2、多个第一连接结构CH1、多个第二连接结构CH2、多个第三连接结构CH3以及多个第四连接结构CH4。
第一绝缘层I1、第二绝缘层I2以及第三绝缘层I3依序重叠。数据线信号晶片DC以及扫描线信号晶片GC位于第一绝缘层上I1。
第一导线层CC1位于第二绝缘层I2以及第一导电层I1之间。多个第一连接结构CH1贯穿第一绝缘层I1，且电性连接至第一导线层CC1。
第二导线层CC2位于第二绝缘层I2以及第三导电层I3之间。多个第二连接结构CH2贯穿第一绝缘层I1以及第二绝缘层I2，且电性连接至第二导 线层CC2。在本实施例中，由于第一导线层CC1与第二导线层CC2分别属于不同膜层，因此，可以有效增加第一导线层CC1与第二导线层CC2的布线空间。
第三连接结构CH3贯穿第二绝缘层I2以及第三导电层I3，且电性连接至第一导线层CC1。多个第四连接结构CH4贯穿第三绝缘层I3，且电性连接至第二导线层CC2。
数据线信号晶片DC电性连接至第一导电层CC1与第二导电层CC2中的一者，且扫描线信号晶片GC电性连接至第一导电层CC1与第二导电层CC2中的另一者。在本实施例中，数据线信号晶片DC电性连接至第一导电层CC1，且扫描线信号晶片GC电性连接至第二导电层CC2。
数据线信号晶片DC电性连接至数据线接垫(例如图1的第一数据线接垫D1、第二数据线接垫D2及第三数据线接垫D3)，且扫描线信号晶片GC电性连接至扫描线接垫G。
在本实施例中，数据线信号晶片DC以及扫描线信号晶片GC皆位于显示区AA的同一侧，因此，可以缩小显示面板的边框，藉此提升显示装置的屏占比。在一些实施例中，未设置薄膜覆晶封装电路COF的显示区AA的侧边与像素阵列基板10的边缘之间的宽度小于2毫米。
在本实施例中，一个薄膜覆晶封装电路COF包含了数据线信号晶片DC以及扫描线信号晶片GC，因此，第一扇出线130与第二扇出线220可以互不重叠，藉此能改善第一扇出线130与第二扇出线220之间的信号干扰对显示画面所造成的影响。
请参考图1，在本实施例中，像素阵列基板10包括n个扫描线信号晶片GC。举例来说，像素阵列基板10包括2个薄膜覆晶封装电路COF，而每个薄膜覆晶封装电路COF具有1个扫描线信号晶片GC，因此，像素阵列基板10共包括2个扫描线信号晶片GC，即n为2。在其他实施例中，n大于2。
在本实施例中，每条扫描线110电性连接至多个扫描线信号晶片GC，使扫描线110上的信号能够分布的更均匀。举例来说，像素阵列基板10共包括n个扫描线信号晶片GC，则每条扫描线110电性连接至n个扫描线信号晶片GC。
图4是依照本发明的实施例1的一种扫描线接垫与数据线接垫的排列顺 序的示意图。
扫描线接垫G以及数据线接垫D(例如第一数据线接垫、第二数据线接垫及第三数据线接垫)在排列方向RD上排列成多个重复单元PU，且每个重复单元PU中的扫描线接垫G以及数据线接垫D的数量总合为U个。
图4用于示出重复单元PU中扫描线接垫G以及数据线接垫D的排列顺序，且重复单元PU中扫描线接垫G以及数据线接垫D并非完全对齐。举例来说，重复单元PU中扫描线接垫G以及数据线接垫D可以如图1所示分成第一排L1以及第二排L2。图1中第一排L1中的第一个接垫在图4中为第一个接垫，图1中第二排L2中的第一个接垫在图4中为第二个接垫，图1中第一排L1中的第二个接垫在图4中为第三个接垫，其他接垫的排列顺序也是以此类推。
在本实施例中，如图2A所示，沿着第一方向E1排列的像素PX的排数与沿着第二方向E2排列的像素PX的排数的比为X：Y。举例来说，在解析度为1920×1080的显示面板中，X：Y为16：9。在本实施例中，各像素PX包括m个子像素，其中m为正整数。在本实施例中，为了改善扫描线接垫G以及数据线接垫D之间的信号干扰问题，扫描线接垫G以及数据线接垫D符合式1的规则。
式1：
U＝a×(k×m×X+h×n×Y)
在式1中，n为扫描线信号晶片的数量，且a、k以及h为正整数。
实施例1
在实施例1中，像素阵列基板是以HG2D的方式驱动，各子像素重叠于两条数据线以及一条扫描线。在实施例1中，各扫描线接垫G电性连接至对应的两条扫描线。在实施例1中，部分扫描线接垫G位于第一排L1，且另一部分扫描线接垫G位于第二排L2(如图1所示)，部分扫描线接垫G属于第一金属层，且另一部分扫描线接垫G属于第二金属层。在实施例1中，a为1，k为4，且h为1。
X：Y为16：9。各像素PX包括3个子像素，即m为3。像素阵列基板具有3个扫描线信号晶片，即n为3。
在实施例1中，以式1计算每个重复单元PU中的扫描线接垫G以及数据线接垫D的数量总合U，U＝1×(4×3×16+1×3×9)＝219，意即每个重复 单元PU中的扫描线接垫G以及数据线接垫D的数量总合U为219个。
在实施例1中，为了使扫描线接垫G以及数据线接垫D能更均匀的分散，在排列方向RD上相邻的两个扫描线接垫G之间的数据线接垫D的数量R符合式2的规则。
式2：
R＝2×m×N
在式2中，N为1至k+1之间的整数。
在实施例1中，R＝2×3×1至2×3×5，意即相邻的两个扫描线接垫G之间的数据线接垫D的数量介于6至30个。
图5是依照本发明的一实施例的一种像素阵列基板的上视示意图。在此必须说明的是，图5的实施例沿用图1的实施例的元件标号与部分内容，其中采用相同或近似的标号来表示相同或近似的元件，并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例，在此不赘述。
图5的像素阵列基板20与图1的像素阵列基板10的差异在于：在像素阵列基板20中，不同条扫描线110并未共用同一个扫描线接垫G。
请参考图5，在本实施例中，每条栅极传输线120电性连接对应的一个扫描线接垫G至对应的一条扫描线110。
图6是依照本发明的实施例2的一种扫描线接垫与数据线接垫的排列顺序的示意图。
扫描线接垫G以及数据线接垫D(例如第一数据线接垫、第二数据线接垫及第三数据线接垫)在排列方向RD上排列成多个重复单元PU，且每个重复单元PU中的扫描线接垫G以及数据线接垫D的数量总合为U个。
图6用于示出重复单元PU中扫描线接垫G以及数据线接垫D的排列顺序，且重复单元PU中扫描线接垫G以及数据线接垫D并非完全对齐。举例来说，重复单元PU中扫描线接垫G以及数据线接垫D可以如图5所示分成第一排L1以及第二排L2。图5中第一排L1中的第一个接垫在图6中为第一个接垫，图5中第二排L2中的第一个接垫在图6中为第二个接垫，图5中第一排L1中的第二个接垫在图6中为第三个接垫，其他接垫的排列顺序也是以此类推。
在本实施例中，如图2A所示，沿着第一方向E1排列的像素PX的排数与沿着第二方向E2排列的像素PX的排数的比为X：Y。在本实施例中，各像素 PX包括m个子像素，其中m为正整数。在本实施例中，为了改善扫描线接垫G以及数据线接垫D之间的信号干扰问题，扫描线接垫G以及数据线接垫D符合式1的规则。
实施例2
在实施例2中，像素阵列基板是以HG2D的方式驱动，各子像素重叠于两条数据线以及一条扫描线。在实施例2中，各扫描线接垫G电性连接至对应的一条扫描线，且不同条扫描线之间不直接通过扫描线接垫或栅极传输线而电性相连。在实施例2中，部分扫描线接垫G位于第一排L1，且另一部分扫描线接垫G位于第二排L2(如图5所示)，部分扫描线接垫G属于第一金属层，且另一部分扫描线接垫G属于第二金属层。在实施例2中，a为1，且k为2，且h为1。
X：Y为16：9。各像素PX包括3个子像素，即m为3。像素阵列基板具有3个扫描线信号晶片，即n为3。
在实施例2中，以式1计算每个重复单元PU中的扫描线接垫G以及数据线接垫D的数量总合U，U＝1×(2×3×16+1×3×9)＝123，意即每个重复单元PU中的扫描线接垫G以及数据线接垫D的数量总合U为123个。
在实施例2中，为了使扫描线接垫G以及数据线接垫D能更均匀的分散，在排列方向RD上相邻的两个扫描线接垫G之间的数据线接垫D的数量R符合式2的规则。
在实施例2中，R＝2×3×1至2×3×3，意即相邻的两个扫描线接垫G之间的数据线接垫D的数量介于6至18个。
图7是依照本发明的一实施例的一种像素阵列基板的上视示意图。在此必须说明的是，图7的实施例沿用图2A的实施例的元件标号与部分内容，其中采用相同或近似的标号来表示相同或近似的元件，并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例，在此不赘述。
图7的像素阵列基板30与图2A的像素阵列基板10的差异在于：在像素阵列基板30是以1G1D(one-gate one-data line)的方式驱动，各子像素(红色子像素P1、绿色子像素P2以及蓝色子像素P3)重叠于数据线210中对应的一条以及扫描线110中对应的一条。
图8是依照本发明的实施例3的一种扫描线接垫与数据线接垫的排列顺 序的示意图。
扫描线接垫G以及数据线接垫D(例如第一数据线接垫、第二数据线接垫及第三数据线接垫)在排列方向RD上排列成多个重复单元PU，且每个重复单元PU中的扫描线接垫G以及数据线接垫D的数量总合为U个。
图8用于示出重复单元PU中扫描线接垫G以及数据线接垫D的排列顺序，且重复单元PU中扫描线接垫G以及数据线接垫D并非完全对齐。举例来说，重复单元PU中扫描线接垫G以及数据线接垫D可以如图5所示分成第一排L1以及第二排L2。图1中第一排L1中的第一个接垫在图8中为第一个接垫，图5中第二排L2中的第一个接垫在图8中为第二个接垫，图5中第一排L1中的第二个接垫在图8中为第三个接垫，其他接垫的排列顺序也是以此类推。
在本实施例中，如图7所示，沿着第一方向E1排列的像素PX的排数与沿着第二方向E2排列的像素PX的排数的比为X：Y。在本实施例中，各像素PX包括m个子像素，其中m为正整数。在本实施例中，为了改善扫描线接垫G以及数据线接垫D之间的信号干扰问题，扫描线接垫G以及数据线接垫D符合式1的规则。
实施例3
在实施例3中，像素阵列基板是以1G1D的方式驱动，各子像素重叠于一条数据线以及一条扫描线。在实施例3中，各扫描线接垫G电性连接至对应的一条扫描线，且不同条扫描线之间不直接通过扫描线接垫或栅极传输线而电性相连。在实施例3中，部分扫描线接垫G位于第一排L1，且另一部分扫描线接垫G位于第二排L2(如图5所示)，部分扫描线接垫G属于第一金属层，且另一部分扫描线接垫G属于第二金属层。在实施例3中，a为1，且k为1，且h为1。
X：Y为16：9。各像素PX包括3个子像素，即m为3。像素阵列基板具有3个扫描线信号晶片，即n为3。
在实施例3中，以式1计算每个重复单元PU中的扫描线接垫G以及数据线接垫D的数量总合U，U＝1×(1×3×16+1×3×9)＝75，意即每个重复单元PU中的扫描线接垫G以及数据线接垫D的数量总合U为75个。
在实施例3中，为了使扫描线接垫G以及数据线接垫D能更均匀的分散，在排列方向RD上相邻的两个扫描线接垫G之间的数据线接垫D的数量R符合 式2的规则。
在实施例3中，R＝2×3×1至2×3×2，意即相邻的两个扫描线接垫G之间的数据线接垫D的数量介于6至12个。
图9是依照本发明的一实施例的一种像素阵列基板的上视示意图。图10A是图9线aa’的剖面示意图。图10B是图9线bb’的剖面示意图。在此必须说明的是，图9的实施例沿用图5的实施例的元件标号与部分内容，其中采用相同或近似的标号来表示相同或近似的元件，并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例，在此不赘述。
请参考图9，在像素阵列基板30中，扫描线接垫G皆位于同一排，举例来说，扫描线接垫G皆位于第一排L1或扫描线接垫G皆位于第二排。在本实施例中，位于第一排L1的接垫(包括扫描线接垫G以及数据线接垫D)属于第一金属层M1，而位于第二排L2的接垫(包括数据线接垫D)属于第二金属层M2。在其他实施例中，位于第二排L2的接垫属于第一金属层M1，而于第一排L1的接垫属于第二金属层M2。在本实施例中，所有扫描线接垫G在排列方向RD上彼此对齐。
在本实施例中，扫描线接垫G皆属于第一金属层M1，因此，可以减少不同条扫描线110因为转接结构(例如由第一金属层M1转接至第二金属层M2的转接结构)而导致信号出现偏移的问题。
第一金属层M1位于基板SB上。栅绝缘层GI覆盖第一金属层M1。在属于第一金属层M1的接垫(例如扫描线接垫G)上的栅绝缘层GI具有通孔TH1。平坦层PL位于栅绝缘层GI上，且在属于第一金属层M1的接垫(例如扫描线接垫G)上以及在属于第二金属层M2的接垫(例如第三数据线接垫D3)上具有通孔TH2。
在一些实施例中，多个导电结构CP填入通孔TH1以及通孔TH2中，以分别电性连接至对应的扫描线接垫G以及第三数据线接垫D3。导电结构CP的材料例如包括金属氧化物。
实施例4
在实施例4中，像素阵列基板是以HG2D的方式驱动，各子像素重叠两条数据线以及一条扫描线。在实施例4中，各扫描线接垫G电性连接至对应的两条扫描线。在实施例4中，所有扫描线接垫G皆属于同一金属层(例如由 第一金属层或第二金属层)。在实施例4中，a为2，且k为4，且h为1。
X：Y为16：9。各像素PX包括3个子像素，即m为3。像素阵列基板具有3个扫描线信号晶片，即n为3。
在实施例4中，以式1计算每个重复单元PU中的扫描线接垫G以及数据线接垫D的数量总合U，U＝2×(4×3×16+1×3×9)＝438，意即每个重复单元PU中的扫描线接垫G以及数据线接垫D的数量总合U为438个。
在实施例4中，为了使扫描线接垫G以及数据线接垫D能更均匀的分散，在排列方向RD上相邻的两个扫描线接垫G之间的数据线接垫D的数量R符合式3的规则。
式3：
R＝2×m×N+1
在式3中，N为1至k+1之间的整数。
在实施例4中，R＝2×3×1+1至2×3×5+1，意即相邻的两个扫描线接垫G之间的数据线接垫D的数量介于7至31个。
工业应用性
本发明提供一种像素阵列基板，能改善扫描线接垫以及数据线接垫之间信号互相干扰的问题。

Claims (14)

  1. 一种像素阵列基板，其特征在于，包括：
    多个扫描线接垫以及多个数据线接垫，位于一基板上；
    多条扫描线，沿着一第一方向延伸；
    多条数据线以及多条栅极传输线，沿着一第二方向延伸，其中该些数据线电性连接至该些数据线接垫，且该些扫描线通过该些栅极传输线电性连接至该些扫描线接垫；
    多个像素，位于该基板上，其中沿着该第一方向排列的该些像素的排数与沿着该第二方向排列的该些像素的排数的比为X：Y，其中各该像素包括m个子像素，且该些子像素电性连接至该些扫描线以及该些数据线；
    至少一个数据线信号晶片以及至少一个扫描线信号晶片，该至少一个数据线信号晶片电性连接至该些数据线接垫，且该至少一个扫描线信号晶片电性连接至该些扫描线接垫，其中
    该些扫描线接垫以及该些数据线接垫在一排列方向上排列成多个重复单元，且各该重复单元中的该些扫描线接垫以及该些数据线接垫的数量总合为U个，其中U＝a×(k×m×X+h×n×Y)，其中n为该至少一个扫描线信号晶片的数量，且a、k以及h为正整数。
  2. 如权利要求1所述的像素阵列基板，其特征在于，各该子像素重叠于该些数据线中对应的两条以及该些扫描线中对应的一条，且各该扫描线接垫电性连接至对应的两条扫描线。
  3. 如权利要求2所述的像素阵列基板，其特征在于，部分该些扫描线接垫以及部分该些数据线接垫属于第一金属层，且另一部分该些扫描线接垫以及另一部分该些数据线接垫属于第二金属层，其中a为1、k为4且h为1。
  4. 如权利要求3所述的像素阵列基板，其特征在于，在该排列方向上相邻的两个该些扫描线接垫之间具有R个该些数据线接垫，R＝2×m×N，且N为1至k+1之间的整数。
  5. 如权利要求2所述的像素阵列基板，其特征在于，该些扫描线接垫皆属于同一层金属层，其中a为2、k为4且h为1。
  6. 如权利要求5所述的像素阵列基板，其特征在于，在该排列方向上相邻的两个该些扫描线接垫之间具有R个该些数据线接垫，R＝2×m×N+1，且N 为1至k+1之间的整数。
  7. 如权利要求5所述的像素阵列基板，其特征在于，该些扫描线接垫在该排列方向上彼此对齐。
  8. 如权利要求1所述像素阵列基板，其特征在于，各该子像素重叠于该些数据线中对应的两条以及该些扫描线中对应的一条，且不同条该些扫描线之间不直接通过该些扫描线接垫或该些栅极传输线而电性相连，其中a为1、k为2且h为1。
  9. 如权利要求8所述的像素阵列基板，其特征在于，在该排列方向上相邻的两个该些扫描线接垫之间具有R个该些数据线接垫，R＝2×m×N，且N为1至k+1之间的整数。
  10. 如权利要求1所述像素阵列基板，其特征在于，各该子像素重叠于该些数据线中对应的一条以及该些扫描线中对应的一条，其中a为1、k为1且h为1。
  11. 如权利要求10所述的像素阵列基板，其特征在于，在该排列方向上相邻的两个该些扫描线接垫之间具有R个该些数据线接垫，R＝2×m×N，且N为1至k+1之间的整数。
  12. 如权利要求1所述的像素阵列基板，其特征在于，更包括：
    多条第一扇出线，电性连接该些扫描线接垫至该些栅极传输线；以及
    多条第二扇出线，电性连接该些数据线接垫至该些数据线，其中该些第一扇出线与该些第二扇出线互不重叠。
  13. 一种像素阵列基板，其特征在于，包括：
    多个扫描线接垫、多个第一数据线接垫、多个第二数据线接垫以及多个第三数据线接垫，位于一基板上，其中该些扫描线接垫、该些第一数据线接垫、该些第二数据线接垫以及该些第三数据线接垫在一排列方向上排列；
    多条扫描线，沿着一第一方向延伸；
    多条数据线以及多条栅极传输线，沿着一第二方向延伸，其中该些扫描线通过该些栅极传输线电性连接至该些扫描线接垫，且该些数据线电性连接至该些第一数据线接垫、该些第二数据线接垫以及该些第三数据线接垫；
    多个红色子像素、多个绿色子像素以及多个蓝色子像素，电性连接至该些扫描线以及该些数据线，其中该些红色子像素电性连接至该些第一数据线 接垫，该些绿色子像素电性连接至该些第二数据线接垫，且该些蓝色子像素电性连接至该些第三数据线接垫，其中在该排列方向上位于该些第一数据线接垫与该些第二数据线接垫之间或该些第三数据线接垫与该些第二数据线接垫之间的该些扫描线接垫的数量少于位于该些第一数据线接垫与该些第三数据线接垫之间的该些扫描线接垫的数量；
    至少一个薄膜覆晶封装电路，包括至少一个数据线信号晶片以及至少一个扫描线信号晶片，该至少一个数据线信号晶片电性连接至该些第一数据线接垫、该些第二数据线接垫以及该些第三数据线接垫，且该至少一个扫描线信号晶片电性连接至该些扫描线接垫。
  14. 如权利要求13所述像素阵列基板，其特征在于，该至少一个薄膜覆晶封装电路包括：
    一第一绝缘层、一第二绝缘层以及一第三绝缘层，依序重叠，且至该至少一个数据线信号晶片以及该至少一个扫描线信号晶片位于该第一绝缘层上；
    一第一导线层，位于该第二绝缘层以及该第一导电层之间；
    一第二导线层，位于该第二绝缘层以及该第三导电层之间
    多个第一连接结构，贯穿该第一绝缘层，且电性连接至该第一导线层；
    多个第二连接结构，贯穿该第一绝缘层以及该第二绝缘层，且电性连接至该第二导线层；
    多个第三连接结构，贯穿该第二绝缘层以及该第三导电层，且电性连接至该第一导线层；以及
    多个第四连接结构，贯穿该第三绝缘层，且电性连接至该第二导线层，其中该至少一个数据线信号晶片电性连接至该第一导电层与该第二导电层中的一者，且该至少一个扫描线信号晶片电性连接至该第一导电层与该第二导电层中的另一者。
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