WO2021031358A1 - 一种阵列基板及其制作方法、显示面板 - Google Patents

一种阵列基板及其制作方法、显示面板 Download PDF

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Publication number
WO2021031358A1
WO2021031358A1 PCT/CN2019/115346 CN2019115346W WO2021031358A1 WO 2021031358 A1 WO2021031358 A1 WO 2021031358A1 CN 2019115346 W CN2019115346 W CN 2019115346W WO 2021031358 A1 WO2021031358 A1 WO 2021031358A1
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Prior art keywords
layer
inorganic film
opening
substrate
display area
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PCT/CN2019/115346
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English (en)
French (fr)
Inventor
马伟欣
陈彩琴
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武汉华星光电半导体显示技术有限公司
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Priority to US16/769,306 priority Critical patent/US11349108B2/en
Publication of WO2021031358A1 publication Critical patent/WO2021031358A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This application relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display panel.
  • AMOLED Active-matrix organic light emitting diode
  • the array substrate manufacturing process of flexible AMOLED includes 10-12 processes, which is 2 to 3 more processes than rigid AMOLED array substrate manufacturing process.
  • the extra process is mainly to etch and dig holes on the inorganic film layer with poor stress and poor flexibility in the non-display bending area, and fill it with flexible organic materials to improve The bending performance of the non-display bending area.
  • the present application provides an array substrate, a manufacturing method thereof, and a display panel, so as to reduce the manufacturing process of the array substrate and reduce the cost.
  • an embodiment of the present application provides a manufacturing method of an array substrate.
  • the manufacturing method of the array substrate includes: providing a base, the base including a display area and a non-display area at the periphery of the display area; and forming an inorganic film on the base Group layer; make an opening on the inorganic film group layer, and form a patterned source and drain layer, the opening is located in the non-display area, the source and drain layer does not cover and does not fill the opening; an organic flat layer is formed on the inorganic film group layer, The organic flat layer covers the source and drain layers, and fills and covers the opening.
  • the step of forming an opening on the inorganic film layer and forming a patterned source and drain layer specifically includes: forming a patterned source and drain layer on the inorganic film layer; An opening is made in the area covered by the layer, and the opening is located in the non-display area.
  • the opening includes a first hole and a second hole that are stacked and connected on the substrate
  • the step of making an opening on the inorganic film layer includes: making a first preset on the inorganic film layer by exposure and etching. A first hole with a depth; through the first hole, a second hole with a second preset depth is made on the inorganic film layer in a direction close to the substrate through exposure and etching.
  • the second preset depth is the same as the first preset
  • the sum of the depths is equal to the thickness of the inorganic film layer.
  • the inorganic film group layer includes a buffer layer, a first gate insulating layer, a second gate insulating layer, and an interlayer dielectric layer that are sequentially away from the substrate.
  • the step of forming an inorganic film group layer on the substrate specifically includes: depositing on the substrate A buffer layer; depositing a first gate insulating layer on the buffer layer; depositing a second gate insulating layer on the first gate insulating layer; depositing an interlayer dielectric layer on the second gate insulating layer.
  • the step of depositing the buffer layer on the substrate it further includes: forming a low-temperature polysilicon layer on the buffer layer, the low-temperature polysilicon layer is located in the display area, and the first gate insulating layer covers the low-temperature polysilicon layer; and depositing the first gate on the buffer layer
  • the insulating layer step it further includes: forming a first metal layer on the first gate insulating layer, the first metal layer is located in the display area, and the second gate insulating layer covers the first metal layer; depositing on the first gate insulating layer
  • the method further includes: forming a second metal layer on the second gate insulating layer, the second metal layer is located in the display area, and the interlayer dielectric layer covers the second metal layer.
  • an embodiment of the present application also provides an array substrate, the array substrate includes: a base, the base includes a display area and a non-display area located at the periphery of the display area; an inorganic film group layer on the base, the inorganic film group The layer is provided with openings, the openings are located in the non-display area; the patterned source and drain layers on the inorganic film layer, the source and drain layers do not cover and do not fill the opening; the organic flat layer on the inorganic film layer, organic flat The layer covers the source and drain layers, and fills and covers the opening.
  • the non-display area includes a bending area and a non-bending area located on the side of the bending area, and there are multiple openings located in the bending area.
  • a plurality of openings are distributed in an array on the bending area.
  • the opening is a groove or a through hole.
  • the inorganic film group layer includes a buffer layer, a first gate insulating layer, a second gate insulating layer, and an interlayer dielectric layer that are sequentially away from the substrate.
  • the opening includes a first hole and a second hole that are stacked and communicated on the substrate.
  • the first hole is located on the second hole, and the ratio of the depth of the first hole to the thickness of the inorganic film layer is in the range of 0.3 to 0.5.
  • the embodiments of the present application also provide a display panel, the display panel includes an array substrate, the array substrate includes: a base, the base includes a display area and a non-display area located at the periphery of the display area; an inorganic film located on the base Group layer, the inorganic film group layer is provided with openings, the openings are located in the non-display area; the patterned source/drain layer located on the inorganic film group layer, the source/drain layer does not cover and does not fill the openings; the openings are located on the inorganic film layer
  • the organic flat layer covers the source and drain layers, and fills and covers the opening.
  • the non-display area includes a bending area and a non-bending area located on the side of the bending area, and there are multiple openings located in the bending area.
  • a plurality of openings are distributed in an array on the bending area.
  • the opening is a groove or a through hole.
  • the inorganic film group layer includes a buffer layer, a first gate insulating layer, a second gate insulating layer, and an interlayer dielectric layer that are sequentially away from the substrate.
  • the opening includes a first hole and a second hole that are stacked and communicated on the substrate.
  • the first hole is located on the second hole, and the ratio of the depth of the first hole to the thickness of the inorganic film layer is in the range of 0.3 to 0.5.
  • the manufacturing method of the array substrate provided by the present application is to make openings on the inorganic film group layer located in the non-display area, and fill the openings in the subsequent flat layer manufacturing process, reducing
  • the process of filling the opening with an organic material saves the mask of the process, which is beneficial to reduce the cost.
  • FIG. 1 is a schematic flowchart of a manufacturing method of an array substrate provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of the flow of S12 in Figure 1;
  • FIG. 3 is another schematic flow chart of the manufacturing method of the array substrate provided by the embodiment of the present application.
  • FIG. 4 is a schematic top view of the structure of the array substrate provided by the embodiment of the present application.
  • Fig. 5 is a schematic cross-sectional structural diagram taken along the line O-O' in Fig. 4;
  • FIG. 6 is a schematic diagram of another structure of an array substrate provided by an embodiment of the present application.
  • FIG. 7 is another schematic top view of the structure of the array substrate provided by the embodiment of the present application.
  • FIG. 8 is a schematic diagram of the structure of the inorganic film layer in FIG. 7;
  • FIG. 9 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the manufacturing process of flexible AMOLED array substrates has the problems of many process steps and high cost.
  • the technical solution adopted in the present application is to provide a method for manufacturing an array substrate to reduce the manufacturing process of the array substrate and reduce the cost.
  • FIG. 1 is a schematic flowchart of a manufacturing method of an array substrate provided by an embodiment of the present application.
  • the specific process of the manufacturing method of the array substrate may be as follows:
  • the substrate includes a display area and a non-display area located around the display area.
  • the substrate is a flexible substrate, and its material can be one of organic polymers such as polyimide, polycarbonate, polyethylene terephthalate, and polyethersulfone substrate.
  • S12 Form an inorganic film group layer on the substrate.
  • the inorganic film group layer may include a buffer layer, a first gate insulating layer, a second gate insulating layer, and an interlayer dielectric layer that are sequentially away from the substrate.
  • S12 may include:
  • the material of the buffer layer can be SiNx, SiOx or other suitable materials.
  • S12 may specifically include: using a chemical vapor deposition process to sequentially form a silicon nitride layer and a silicon oxide layer on the substrate.
  • S122 Deposit a first gate insulating layer on the buffer layer.
  • a first gate insulating layer is formed on the buffer layer by using a chemical vapor deposition process.
  • the material of the first gate insulating layer may be SiOx.
  • S123 Deposit a second gate insulating layer on the first gate insulating layer.
  • a chemical vapor deposition process is used to form a second gate insulating layer on the first gate insulating layer.
  • the material of the second gate insulating layer may be SiNx.
  • S124 Deposit an interlayer dielectric layer on the second gate insulating layer.
  • a chemical vapor deposition process is used to form an interlayer dielectric layer on the second gate insulating layer.
  • the material of the interlayer dielectric layer can be one or two of SiNx and SiOx.
  • Step A forming a low temperature polysilicon layer on the buffer layer, the low temperature polysilicon layer is located in the display area, and the first gate insulating layer covers the low temperature polysilicon layer.
  • step A may specifically include: forming an amorphous silicon layer on the buffer layer using a chemical vapor deposition process in the display area, and then using an excimer laser annealing process to process the amorphous silicon layer to form a corresponding low-temperature polysilicon layer .
  • Step B forming a first metal layer on the first gate insulating layer, the first metal layer is located in the display area, and the second gate insulating layer covers the first metal layer.
  • the first metal layer may be a patterned gate layer, including the gate of the thin film transistor in the array substrate and the lower electrode of the storage capacitor.
  • step B may specifically include: in the display area, using a physical vapor deposition process to lay a first metal material layer on the first gate insulating layer, and then pattern the first metal material layer through exposure and etching processes to obtain Patterned gate layer.
  • the material of the first metal layer may be molybdenum.
  • Step C forming a second metal layer on the second gate insulating layer, the second metal layer is located in the display area, and the interlayer dielectric layer covers the second metal layer.
  • the second metal layer includes the upper electrode of the storage capacitor in the array substrate, and the upper electrode and the lower electrode in the first metal layer together constitute the storage capacitor in the array substrate.
  • step C may specifically include: in the display area, using a physical vapor deposition process to lay a second metal material layer on the second gate insulating layer, and then pattern the second metal material layer through an exposure and etching process to obtain The second metal layer.
  • the material of the second metal layer may be molybdenum.
  • S13 may specifically include:
  • the source-drain layer includes a plurality of wires arranged at intervals, and the wires span the display area and the non-display area, one end is connected to the pixel unit located in the display area, and the other end is connected to the driver interface located in the non-display area connection.
  • S131 may include: laying a source and drain material layer on the inorganic film layer by using a physical vapor deposition process, and then patterning the source and drain material layer through an exposure and etching process to obtain a patterned source and drain layer .
  • the material of the source and drain layer can be metal materials such as aluminum, copper, silver, etc.
  • S132 Making an opening in the area of the inorganic film group layer not covered by the source and drain layer, and the opening is located in the non-display area.
  • the non-display area may include a bending area and a non-bending area located at the side of the bending area.
  • the array substrate may be bent in the bending area, so that the drive located in the non-bending area can be bent.
  • the interface is folded to the non-light emitting surface of the array substrate, thereby achieving a narrow frame of the display panel.
  • the inorganic film group layer located on the bending area may be etched and digged.
  • S132 may specifically include: etching a predetermined position of the inorganic film layer on the bending area to form an opening, wherein the predetermined position is located in a region where the inorganic film layer is not covered by the source and drain layers.
  • the number of openings may be multiple, and the multiple openings may be evenly distributed on the bending area, or distributed in an array to ensure the flexibility of the bending area.
  • the opening may be a groove or a through hole.
  • the opening may include a first hole and a second hole that are stacked and connected on the substrate, and the first hole and the second hole are formed through two etching processes, so as to reduce the amount of time in a single etching process.
  • the thickness of the photoresist that needs to be coated, thereby reducing the energy consumption of the exposure machine in a single etching process, is beneficial to reducing equipment costs.
  • S132 may include:
  • Sub-step D through exposure and etching, a first hole with a first preset depth is made on the inorganic film layer.
  • the first predetermined depth may be 0.3 to 0.5 of the thickness of the inorganic film layer. For example, if the thickness of the inorganic film layer is 1.5 ⁇ m, the first predetermined depth may be 0.45 to 0.75 ⁇ m.
  • the sub-step D may specifically include: coating a photoresist with a first preset thickness on the inorganic film group layer; exposing, developing, and etching the inorganic film group layer coated with the photoresist, To form a first hole with a first preset depth, where the first preset depth and the first preset thickness correspond to the same value.
  • Sub-step E Making a second hole with a second preset depth in the inorganic film layer in a direction close to the substrate through the first hole through exposure and etching.
  • the second preset depth is between the second preset depth and the first preset depth. The sum is equal to the thickness of the inorganic film layer.
  • the second predetermined depth is equal to the difference between the thickness of the inorganic film layer and the first predetermined depth. For example, if the thickness of the inorganic film layer is 1.5 ⁇ m, the first preset depth is 0.45 to 0.75 ⁇ m, and the second preset depth may be 0.75 to 1.05 ⁇ m.
  • the sub-step E may specifically include: coating a photoresist with a second preset thickness on the inorganic film layer formed with the first hole; exposing the inorganic film layer coated with the photoresist, Developing and etching to form a second hole having a second preset depth, wherein the second preset depth and the second preset thickness correspond to the same value.
  • openings can also be made on the inorganic film layer, and then patterned source and drain layers are formed on the inorganic film layer. That is, S13 can specifically include: An opening is formed on the non-display area of the film group layer; a patterned source and drain layer is formed on the area of the inorganic film group layer except the opening.
  • S13 can specifically include: An opening is formed on the non-display area of the film group layer; a patterned source and drain layer is formed on the area of the inorganic film group layer except the opening.
  • a chemical vapor deposition process is used to deposit an organic flat layer on the inorganic film layer.
  • the material of the organic flat layer may be an organic insulating material such as polyimide resin, epoxy resin or acrylic resin.
  • the manufacturing method of the array substrate in this embodiment is to make openings on the inorganic film layer located in the non-display area, and fill the openings in the subsequent flat layer manufacturing process, reducing the use of organic materials to fill the openings. This process saves the mask of the process and helps reduce costs.
  • FIG. 4 is a schematic top view of the structure of the array substrate provided by an embodiment of the present application
  • FIG. 5 is a schematic cross-sectional structure view taken along the line O-O' in FIG.
  • the array substrate 40 includes a base 41, an inorganic film group layer 42, a patterned source and drain layer 43, and an organic flat layer 44 sequentially disposed on the base 41.
  • the substrate 41 includes a display area C1 and a non-display area C2 located at the periphery of the display area C1.
  • the inorganic film layer 42 is provided with an opening 421 which is located in the non-display area C2.
  • the source and drain layer 43 does not cover and does not fill the opening. 421.
  • the organic flat layer 44 covers the source and drain layer 43, and fills and covers the opening 421.
  • the base 41 is a flexible base, and its material can be one of organic polymers such as polyimide, polycarbonate, polyethylene terephthalate, and polyethersulfone substrate.
  • the material of the organic flat layer 44 may be an organic insulating material such as polyimide resin, epoxy resin, or acrylic resin.
  • the inorganic film group layer 42 may include a buffer layer 422, a first gate insulating layer 423, a second gate insulating layer 424, and an interlayer dielectric layer 425 that are sequentially away from the substrate 41.
  • the material of the buffer layer 422 may be SiNx, SiOx or other suitable materials
  • the material of the first gate insulating layer 423 may be SiOx
  • the material of the second gate insulating layer 424 may be SiNx
  • the material of the interlayer dielectric layer 424 It can be one or both of SiNx and SiOx.
  • the array substrate 40 may further include a low-temperature polysilicon layer 45, a first metal layer 46, and a second metal layer 47 that are sequentially away from the base 41.
  • the low-temperature polysilicon layer 45, the first metal layer 46 and the second metal layer 47 are all located in the display area, and the low-temperature paracrystalline silicon layer 45 is located between the buffer layer 422 and the first gate insulating layer 423, and the first metal layer 46 is located Between the first gate insulating layer 423 and the second gate insulating layer 424, the second metal layer 47 is located between the second gate insulating layer 424 and the interlayer dielectric layer 425.
  • the first metal layer 46 may be a patterned gate layer, and it includes the gate of the thin film transistor in the array substrate 40 and the lower electrode of the storage capacitor, and the second metal layer 47 may include the storage capacitor in the array substrate 40.
  • the upper electrode and the lower electrode in the above-mentioned first metal layer 46 together constitute a storage capacitor in the array substrate 40.
  • the patterned source and drain layer 43 may include a plurality of wires arranged at intervals, and the wires span the display area C1 and the non-display area C2, and one end is connected to the pixel unit (not shown in the figure) located in the display area C1. (Shown), and the other end is connected to a driver interface (not shown in the figure) located in the non-display area C2.
  • the material of the source and drain layer 43 may be metal materials such as aluminum, copper, and silver.
  • the non-display area C2 may include a bending area W1 and a non-bending area W2 located on the side of the bending area W1.
  • the array substrate 40 may be bent in the bending area W1.
  • the driver interface (not shown in the figure) located in the non-bending area W2 is folded to the non-light emitting surface of the array substrate 40, thereby achieving a narrow frame of the display panel.
  • the inorganic film layer 42 located on the bending area W1 may be etched and digging holes, so that the inorganic film layer 42 is not sourced.
  • An opening 421 is formed in the area covered by the drain layer. Specifically, the number of the openings 421 may be multiple, and the multiple openings 421 may be evenly distributed on the bending area W1, or distributed in an array to ensure the flexibility of the bending area W1.
  • the opening 421 may be a groove or a through hole.
  • the opening 421 may include a first hole 4211 and a second hole 4212 stacked on the substrate 41, and the first hole 4211 and the second hole 4212 are engraved twice.
  • the etching process is formed to reduce the thickness of the photoresist that needs to be coated in a single etching process, thereby reducing the energy consumption of the exposure machine in a single etching process, which is beneficial to reducing equipment costs.
  • the first hole 4211 is located on the second hole 4212, and the depth of the first hole 4211 may be 0.3 to 0.5 of the thickness of the inorganic film layer 42.
  • the thickness of the inorganic film layer 42 is 1.5 ⁇ m
  • the The depth of one hole 4211 may be 0.45 ⁇ 0.75 ⁇ m
  • the depth of the second hole 4212 is equal to the difference between the thickness of the inorganic film layer 42 and the depth of the first hole 4211, for example, the thickness of the inorganic film layer 42 is 1.5 ⁇ m.
  • the depth of one hole 4211 is 0.45 to 0.75 ⁇ m
  • the depth of the second hole 4212 may be 0.75 to 1.05 ⁇ m.
  • the array substrate provided in the present application forms openings on the inorganic film group layer located in the non-display area, and fills the openings in the subsequent flat layer production process, reducing the process of filling the openings with organic materials.
  • the mask of the process is saved, which is beneficial to reduce the cost.
  • FIG. 9 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel 80 includes the array substrate 81 of any of the above embodiments.
  • the array substrate 81 includes a base, and an inorganic film group layer, a patterned source and drain layer, and an organic flat layer sequentially disposed on the base.
  • the substrate includes a display area and a non-display area located at the periphery of the display area, the inorganic film group layer is provided with an opening, the opening is located in the non-display area, the source and drain layer does not cover and does not fill the opening, and the organic flat layer covers the source and drain layer , And fill and cover the opening.
  • openings are made on the inorganic film layer in the non-display area, and the openings are filled in the subsequent flat layer production process, which reduces the process of filling the openings with organic materials.
  • the mask of the process is saved, which is beneficial to reduce the cost.

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Abstract

本申请涉及一种阵列基板及其制作方法、显示面板，该阵列基板的制作方法包括：提供基底，基底包括非显示区域；在基底上形成无机膜组层；在无机膜组层上制作开口，并形成图案化的源漏极层，开口位于非显示区域，源漏极层不覆盖且不填充开口；在无机膜组层上形成有机平坦层，有机平坦层覆盖源漏极层，且填充并覆盖开口。

Description

一种阵列基板及其制作方法、显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板及其制作方法、显示面板。
 背景技术
有源矩阵有机发光二极体（Active-matrix organic light emitting diode，简称AMOLED）面板因其高对比度、广色域、低功耗、可折叠等特性，逐渐成为新一代显示技术。
目前，柔性AMOLED的阵列基板制程包括10~12道工艺，比刚性AMOLED的阵列基板制程多出2~3道工艺。其中，这多出的工艺主要是对位于非显示弯折区上的应力较差、以及柔韧性不好的无机膜层进行刻蚀挖孔，并采用柔韧性较好的有机材料填充，以提高非显示弯折区的弯曲性能。
但是，上述柔性AMOLED的阵列基板制程存在工艺步骤多、以及成本高的问题。
 技术问题
本申请提供了一种阵列基板及其制作方法、显示面板，以减少阵列基板的制程工艺，并降低成本。
 技术解决方案
为了解决上述问题，本申请实施例提供了一种阵列基板的制作方法，该阵列基板的制作方法包括：提供基底，基底包括显示区域以及位于显示区域周边的非显示区域；在基底上形成无机膜组层；在无机膜组层上制作开口，并形成图案化的源漏极层，开口位于非显示区域，源漏极层不覆盖且不填充开口；在无机膜组层上形成有机平坦层，有机平坦层覆盖源漏极层，且填充并覆盖开口。
其中，在无机膜组层上制作开口，并形成图案化的源漏极层步骤，具体包括：在无机膜组层上形成图案化的源漏极层；在无机膜组层未被源漏极层覆盖的区域上制作开口，开口位于非显示区域。
其中，开口包括在基底上层叠连通的第一孔和第二孔，在无机膜组层上制作开口的步骤，具体包括：通过曝光、刻蚀，在无机膜组层上制作具有第一预设深度的第一孔；通过曝光、刻蚀，经由第一孔，沿靠近基底的方向在无机膜组层上制作具有第二预设深度的第二孔，第二预设深度与第一预设深度之和等于无机膜组层的厚度。
其中，无机膜组层包括依次远离基底的缓冲层、第一栅绝缘层、第二栅绝缘层、以及层间介质层，在基底上形成无机膜组层的步骤，具体包括：在基底上沉积缓冲层；在缓冲层上沉积第一栅绝缘层；在第一栅绝缘层上沉积第二栅绝缘层；在第二栅绝缘层上沉积层间介质层。
其中，在基底上沉积缓冲层的步骤之后，还包括：在缓冲层上形成低温多晶硅层，低温多晶硅层位于显示区域，且第一栅绝缘层覆盖低温多晶硅层；在缓冲层上沉积第一栅绝缘层的步骤之后，还包括：在第一栅绝缘层上形成第一金属层，第一金属层位于显示区域，且第二栅绝缘层覆盖第一金属层；在第一栅绝缘层上沉积第二栅绝缘层的步骤之后，还包括：在第二栅绝缘层上形成第二金属层，第二金属层位于显示区域，且层间介质层覆盖第二金属层。
为了解决上述问题，本申请实施例还提供了一种阵列基板，该阵列基板包括：基底，基底包括显示区域以及位于显示区域周边的非显示区域；位于基底上的无机膜组层，无机膜组层上开设有开口，开口位于非显示区域；位于无机膜组层上的图案化的源漏极层，源漏极层不覆盖且不填充开口；位于无机膜层上的有机平坦层，有机平坦层覆盖源漏极层，且填充并覆盖开口。
其中，非显示区域包括弯折区以及位于弯折区侧边的非弯折区，开口位于弯折区，且为多个。
其中，多个开口在弯折区上呈阵列分布。
其中，开口为凹槽或通孔。
其中，无机膜组层包括依次远离基底的缓冲层、第一栅绝缘层、第二栅绝缘层和层间介质层。
其中，开口包括在基底上层叠连通的第一孔和第二孔。
其中，第一孔位于第二孔上，第一孔的深度与无机膜组层的厚度之比的范围为0.3~0.5。
为了解决上述问题，本申请实施例还提供了一种显示面板，该显示面板包括阵列基板，阵列基板包括：基底，基底包括显示区域以及位于显示区域周边的非显示区域；位于基底上的无机膜组层，无机膜组层上开设有开口，开口位于非显示区域；位于无机膜组层上的图案化的源漏极层，源漏极层不覆盖且不填充开口；位于无机膜层上的有机平坦层，有机平坦层覆盖源漏极层，且填充并覆盖开口。
其中，非显示区域包括弯折区以及位于弯折区侧边的非弯折区，开口位于弯折区，且为多个。
其中，多个开口在弯折区上呈阵列分布。
其中，开口为凹槽或通孔。
其中，无机膜组层包括依次远离基底的缓冲层、第一栅绝缘层、第二栅绝缘层和层间介质层。
其中，开口包括在基底上层叠连通的第一孔和第二孔。
其中，第一孔位于第二孔上，第一孔的深度与无机膜组层的厚度之比的范围为0.3~0.5。
 有益效果
本申请的有益效果是：区别于现有技术，本申请提供的阵列基板的制作方法，通过在位于非显示区域的无机膜组层上制作开口，并在后续平坦层制作工艺中填充开口，减少了采用有机材料填充开口的工艺，进而节省了该工艺的掩膜版，有利于降低成本。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的阵列基板的制作方法的流程示意图；
图2是图1中S12的流程示意图；
图3是本申请实施例提供的阵列基板的制作方法的另一流程示意图；
图4是本申请实施例提供的阵列基板的俯视结构示意图；
图5是沿图4中的线O-O’截取的横截面结构示意图；
图6是本申请实施例提供的阵列基板的另一结构示意图；
图7是本申请实施例提供的阵列基板的另一俯视结构示意图；
图8是图7中无机膜组层的结构示意图；
图9是本申请实施例提供的显示面板的结构示意图。
 本发明的实施方式
下面结合附图和实施例，对本申请作进一步的详细描述。特别指出的是，以下实施例仅用于说明本申请，但不对本申请的范围进行限定。同样的，以下实施例仅为本申请的部分实施例而非全部实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。
目前，柔性AMOLED的阵列基板制程存在工艺步骤多、以及成本高的问题。为了解决上述技术问题，本申请采用的技术方案是提供一种阵列基板的制作方法，以减少阵列基板的制程工艺，并降低成本。
请参阅图1，图1是本申请实施例提供的阵列基板的制作方法的流程示意图，该阵列基板的制作方法具体流程可以如下：
S11：提供基底，基底包括显示区域以及位于显示区域周边的非显示区域。
其中，基底为柔性基底，且其材质可以为聚酰亚胺、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚醚砜基板等有机聚合物中的一种。
S12：在基底上形成无机膜组层。
其中，无机膜组层可以包括依次远离基底的缓冲层、第一栅绝缘层、第二栅绝缘层、以及层间介质层。具体地，如图2所示，S12可以包括：
S121：在基底上沉积缓冲层。
其中，缓冲层的材质可以为SiNx、SiOx或者其他适合的材料。例如，S12可以具体包括：利用化学气相沉积工艺，在基板上依次形成氮化硅层和氧化硅层。
S122：在缓冲层上沉积第一栅绝缘层。
例如，利用化学气相沉积工艺，在缓冲层上形成第一栅绝缘层。其中，第一栅绝缘层的材质可以为SiOx。
S123：在第一栅绝缘层上沉积第二栅绝缘层。
例如，利用化学气相沉积工艺，在第一栅绝缘层上形成第二栅绝缘层。其中，第二栅绝缘层的材质可以为SiNx。
S124：在第二栅绝缘层上沉积层间介质层。
例如，利用化学气相沉积工艺，在第二栅绝缘层上形成层间介电层。其中，层间介电层的材质可以为SiNx和SiOx中的一种或两种。
在一个具体实施例中，在S121之后以及S122之前，还可以包括：
步骤A：在缓冲层上形成低温多晶硅层，低温多晶硅层位于显示区域，且第一栅绝缘层覆盖低温多晶硅层。
例如，步骤A可以具体包括：在显示区域，利用化学气相沉积工艺在缓冲层上形成非晶硅层，然后采用准分子镭射退火工艺对该非晶硅层进行处理，以形成对应的低温多晶硅层。
在S122之后以及S123之前，还可以包括：
步骤B：在第一栅绝缘层上形成第一金属层，第一金属层位于显示区域，且第二栅绝缘层覆盖第一金属层。
其中，第一金属层可以为图案化的栅极层，包括阵列基板中薄膜晶体管的栅极、以及存储电容的下电极。具体地，步骤B可以具体包括：在显示区域，利用物理气相沉积工艺在第一栅绝缘层上铺设第一金属材料层，然后通过曝光、蚀刻工艺将该第一金属材料层图形化，以得到图案化的栅极层。其中，第一金属层的材质可以为钼。
在S123之后以及S124之前，还可以包括：
步骤C：在第二栅绝缘层上形成第二金属层，第二金属层位于显示区域，且层间介质层覆盖第二金属层。
其中，第二金属层包括阵列基板中存储电容的上电极，该上电极与上述第一金属层中的下电极共同构成阵列基板中的存储电容。具体地，步骤C可以具体包括：在显示区域，利用物理气相沉积工艺在第二栅绝缘层上铺设第二金属材料层，然后通过曝光、蚀刻工艺将该第二金属材料层图形化，以得到第二金属层。其中，第二金属层的材质可以为钼。
S13：在无机膜组层上制作开口，并形成图案化的源漏极层，开口位于非显示区域，源漏极层不覆盖且不填充开口。
其中，如图3所示，S13可以具体包括：
S131：在无机膜组层上形成图案化的源漏极层。
在本实施例中，源漏极层包括多条间隔设置的导线，且该导线横跨显示区域和非显示区域，一端与位于显示区域的像素单元连接，另一端与位于非显示区域的驱动器接口连接。
具体地，S131可以包括：利用物理气相沉积工艺在无机膜组层上铺设源漏极材料层，然后通过曝光、蚀刻工艺将该源漏极材料层图形化，以得到图案化的源漏极层。其中，源漏极层的材质可以为铝、铜、银等金属材料。
S132：在无机膜组层未被源漏极层覆盖的区域上制作开口，开口位于非显示区域。
在本实施例中，非显示区域可以包括弯折区以及位于弯折区侧边的非弯折区，具体地，阵列基板可在弯折区发生弯折，以将位于非弯折区的驱动器接口折叠至阵列基板的非发光面，进而实现显示面板的窄边框化。
进一步地，为了提高弯折区的弯折性能，可以对位于弯折区上的无机膜组层进行刻蚀挖孔。例如，S132可以具体包括：对位于弯折区上的无机膜组层的预设位置进行刻蚀，以形成开口，其中，预设位置位于无机膜组层未被源漏极层覆盖的区域。
在一些实施例中，开口的数量可以为多个，且该多个开口可以在弯折区上均匀分布，或者呈阵列分布，以保证弯折区的易弯折性。
在本实施例中，开口可以为凹槽或通孔。当开口为通孔时，开口可以包括在基底上层叠连通的第一孔和第二孔，且该第一孔和第二孔经过两次刻蚀工艺形成，以减小单次刻蚀工艺中需要涂布的光刻胶的厚度，进而减小单次刻蚀工艺中曝光机的能量消耗，有利于降低设备成本。具体地，S132可以包括：
子步骤D：通过曝光、刻蚀，在无机膜组层上制作具有第一预设深度的第一孔。
其中，第一预设深度可以为无机膜组层的厚度的0.3~0.5。例如，若无机膜组层的厚度为1.5μm，则第一预设深度可以为0.45~0.75μm。
具体地，子步骤D可以具体包括：在无机膜组层上涂布具有第一预设厚度的光刻胶；对涂布有光刻胶的无机膜组层进行曝光、显影、以及刻蚀，以形成具有第一预设深度的第一孔，其中，第一预设深度与第一预设厚度对应的值相等。
子步骤E：通过曝光、刻蚀，经由第一孔，沿靠近基底的方向在无机膜组层上制作具有第二预设深度的第二孔，第二预设深度与第一预设深度之和等于无机膜组层的厚度。
其中，第二预设深度等于无机膜组层的厚度与第一预设深度之差。例如，无机膜组层的厚度为1.5μm，第一预设深度为0.45~0.75μm，则第二预设深度可以为0.75~1.05μm。
具体地，子步骤E可以具体包括：在形成有第一孔的无机膜组层上涂布具有第二预设厚度的光刻胶；对涂布有光刻胶的无机膜组层进行曝光、显影、以及刻蚀，以形成具有第二预设深度的第二孔，其中，第二预设深度与第二预设厚度对应的值相等。
值得注意的是，在一些实施例中，还可以先在无机膜组层上制作开口，然后再在无机膜组层上形成图案化的源漏极层，也即，S13可以具体包括：在无机膜组层的非显示区域上制作开口；在无机膜组层除开口以外的区域上形成图案化的源漏极层。并且，具体的实施方式可以参考上述子步骤D和子步骤E，故在此不再赘述。
S14：在无机膜组层上形成有机平坦层，有机平坦层覆盖源漏极层，且填充并覆盖开口。
例如，利用化学气相沉积工艺，在无机膜组层上沉积有机平坦层。其中，有机平坦层的材质可以为聚酰亚胺系树脂、环氧系树脂或亚克力系树脂等有机绝缘材料。
区别于现有技术，本实施例中的阵列基板的制作方法，通过在位于非显示区域的无机膜组层上制作开口，并在后续平坦层制作工艺中填充开口，减少了采用有机材料填充开口的工艺，进而节省了该工艺的掩膜版，有利于降低成本。
请参阅图4和图5，图4是本申请实施例提供的阵列基板的俯视结构示意图，图5是沿图4中的线O-O’截取的横截面结构示意图。如图4和图5所示，该阵列基板40包括基底41、以及在基底41上依次设置的无机膜组层42、图案化的源漏极层43、以及有机平坦层44。其中，基底41包括显示区域C1以及位于显示区域C1周边的非显示区域C2，无机膜组层42上开设有开口421，开口421位于非显示区域C2，源漏极层43不覆盖且不填充开口421，有机平坦层44覆盖源漏极层43，且填充并覆盖开口421。
其中，基底41为柔性基底，且其材质可以为聚酰亚胺、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚醚砜基板等有机聚合物中的一种。有机平坦层44的材质可以为聚酰亚胺系树脂、环氧系树脂或亚克力系树脂等有机绝缘材料。
具体地，如图6所示，无机膜组层42可以包括依次远离基底41的缓冲层422、第一栅绝缘层423、第二栅绝缘层424和层间介质层425。其中，缓冲层422的材质可以为SiNx、SiOx或者其他适合的材料，第一栅绝缘层423的材质可以为SiOx，第二栅绝缘层424的材质可以为SiNx，层间介电层424的材质可以为SiNx和SiOx中的一种或两种。
请继续参阅图6，阵列基板40还可以包括依次远离基底41的低温多晶硅层45、第一金属层46和第二金属层47。其中，低温多晶硅层45、第一金属层46和第二金属层47均位于显示区域，且低温对晶硅层45位于缓冲层422和第一栅绝缘层423之间，第一金属层46位于第一栅绝缘层423和第二栅绝缘层424之间，第二金属层47位于第二栅绝缘层424和层间介质层425之间。具体地，第一金属层46可以为图案化的栅极层，且其包括阵列基板40中薄膜晶体管的栅极、以及存储电容的下电极，第二金属层47可以包括阵列基板40中存储电容的上电极，且该上电极与上述第一金属层46中的下电极共同构成阵列基板40中的存储电容。
在本实施例中，图案化的源漏极层43可以包括多条间隔设置的导线，且该导线横跨显示区域C1和非显示区域C2，一端与位于显示区域C1的像素单元（图中未示出）连接，另一端与位于非显示区域C2的驱动器接口（图中未示出）连接。其中，源漏极层43的材质可以为铝、铜、银等金属材料。
具体地，如图7所示，非显示区域C2可以包括弯折区W1以及位于弯折区W1侧边的非弯折区W2，具体地，阵列基板40可在弯折区W1发生弯折，以将位于非弯折区W2的驱动器接口（图中未示出）折叠至阵列基板40的非发光面，进而实现显示面板的窄边框化。
进一步地，如图8所示，为了提高弯折区W1的弯折性能，可以对位于弯折区W1上的无机膜组层42进行刻蚀挖孔，以在无机膜组层42未被源漏极层覆盖的区域上形成开口421。具体地，开口421的数量可以为多个，且该多个开口421可以在弯折区W1上均匀分布，或者呈阵列分布，以保证弯折区W1的易弯折性。
在本实施例中，开口421可以为凹槽或通孔。请继续参阅图6，当开口421为通孔时，开口421可以包括在基底41上层叠连通的第一孔4211和第二孔4212，且该第一孔4211和第二孔4212经过两次刻蚀工艺形成，以减小单次刻蚀工艺中需要涂布的光刻胶的厚度，进而减小单次刻蚀工艺中曝光机的能量消耗，有利于降低设备成本。
具体地，第一孔4211位于第二孔4212上，第一孔4211的深度可以为无机膜组层42的厚度的0.3~0.5，例如，若无机膜组层42的厚度为1.5μm，则第一孔4211的深度可以为0.45~0.75μm，第二孔4212的深度等于无机膜组层42的厚度与第一孔4211的深度之差，例如，无机膜组层42的厚度为1.5μm，第一孔4211的深度为0.45~0.75μm，则第二孔4212的深度可以为0.75~1.05μm。
区别于现有技术，本申请提供的阵列基板，通过在位于非显示区域的无机膜组层上制作开口，并在后续平坦层制作工艺中填充开口，减少了采用有机材料填充开口的工艺，进而节省了该工艺的掩膜版，有利于降低成本。
请参阅图9，图9是本申请实施例提供的显示面板的结构示意图。如图9所示，该显示面板80包括上述任一实施例的阵列基板81。
其中，阵列基板81包括基底、以及在基底上依次设置的无机膜组层、图案化的源漏极层、以及有机平坦层。其中，基底包括显示区域以及位于显示区域周边的非显示区域，无机膜组层上开设有开口，开口位于非显示区域，源漏极层不覆盖且不填充开口，有机平坦层覆盖源漏极层，且填充并覆盖开口。
区别于现有技术，本实施例中的显示面板，通过在位于非显示区域的无机膜组层上制作开口，并在后续平坦层制作工艺中填充开口，减少了采用有机材料填充开口的工艺，进而节省了该工艺的掩膜版，有利于降低成本。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (19)

  1. 一种阵列基板的制作方法，其包括：
    提供基底，所述基底包括显示区域以及位于所述显示区域周边的非显示区域；
    在所述基底上形成无机膜组层；
    在所述无机膜组层上制作开口，并形成图案化的源漏极层，所述开口位于所述非显示区域，所述源漏极层不覆盖且不填充所述开口；
    在所述无机膜组层上形成有机平坦层，所述有机平坦层覆盖所述源漏极层，且填充并覆盖所述开口。
  2. 根据权利要求1所述的制作方法，其中，在所述无机膜组层上制作开口，并形成图案化的源漏极层步骤，具体包括：
    在所述无机膜组层上形成图案化的源漏极层；
    在所述无机膜组层未被所述源漏极层覆盖的区域上制作开口，所述开口位于所述非显示区域。
  3. 根据权利要求1所述的制作方法，其中，所述开口包括在所述基底上层叠连通的第一孔和第二孔，在所述无机膜组层上制作开口的步骤，具体包括：
    通过曝光、刻蚀，在所述无机膜组层上制作具有第一预设深度的所述第一孔；
    通过曝光、刻蚀，经由所述第一孔，沿靠近所述基底的方向在所述无机膜组层上制作具有第二预设深度的所述第二孔，所述第二预设深度与所述第一预设深度之和等于所述无机膜组层的厚度。
  4. 根据权利要求1所述的制作方法，其中，所述无机膜组层包括依次远离所述基底的缓冲层、第一栅绝缘层、第二栅绝缘层、以及层间介质层，在所述基底上形成无机膜组层的步骤，具体包括：
    在所述基底上沉积缓冲层；
    在所述缓冲层上沉积第一栅绝缘层；
    在所述第一栅绝缘层上沉积第二栅绝缘层；
    在所述第二栅绝缘层上沉积层间介质层。
  5. 根据权利要求4所述的制作方法，其中，在所述基底上沉积缓冲层的步骤之后，还包括：
    在所述缓冲层上形成低温多晶硅层，所述低温多晶硅层位于所述显示区域，且所述第一栅绝缘层覆盖所述低温多晶硅层；
    在所述缓冲层上沉积第一栅绝缘层的步骤之后，还包括：
    在所述第一栅绝缘层上形成第一金属层，所述第一金属层位于所述显示区域，且所述第二栅绝缘层覆盖所述第一金属层；
    在所述第一栅绝缘层上沉积第二栅绝缘层的步骤之后，还包括：
    在所述第二栅绝缘层上形成第二金属层，所述第二金属层位于所述显示区域，且所述层间介质层覆盖所述第二金属层。
  6. 一种阵列基板，其包括：
    基底，所述基底包括显示区域以及位于所述显示区域周边的非显示区域；
    位于所述基底上的无机膜组层，所述无机膜组层上开设有开口，所述开口位于所述非显示区域；
    位于所述无机膜组层上的图案化的源漏极层，所述源漏极层不覆盖且不填充所述开口；
    位于所述无机膜层上的有机平坦层，所述有机平坦层覆盖所述源漏极层，且填充并覆盖所述开口。
  7. 根据权利要求6所述的阵列基板，其中，所述非显示区域包括弯折区以及位于所述弯折区侧边的非弯折区，所述开口位于所述弯折区，且为多个。
  8. 根据权利要求7所述的阵列基板，其中，所述多个开口在所述弯折区上呈阵列分布。
  9. 根据权利要求6所述的阵列基板，其中，所述开口为凹槽或通孔。
  10. 根据权利要求6所述的阵列基板，其中，所述无机膜组层包括依次远离所述基底的缓冲层、第一栅绝缘层、第二栅绝缘层和层间介质层。
  11. 根据权利要求6所述的阵列基板，其中，所述开口包括在所述基底上层叠连通的第一孔和第二孔。
  12. 根据权利要求11所述的阵列基板，其中，所述第一孔位于所述第二孔上，所述第一孔的深度与所述无机膜组层的厚度之比的范围为0.3~0.5。
  13. 一种显示面板，其包括阵列基板，所述阵列基板包括：
    基底，所述基底包括显示区域以及位于所述显示区域周边的非显示区域；
    位于所述基底上的无机膜组层，所述无机膜组层上开设有开口，所述开口位于所述非显示区域；
    位于所述无机膜组层上的图案化的源漏极层，所述源漏极层不覆盖且不填充所述开口；
    位于所述无机膜层上的有机平坦层，所述有机平坦层覆盖所述源漏极层，且填充并覆盖所述开口。
  14. 根据权利要求13所述的显示面板，其中，所述非显示区域包括弯折区以及位于所述弯折区侧边的非弯折区，所述开口位于所述弯折区，且为多个。
  15. 根据权利要求14所述的显示面板，其中，所述多个开口在所述弯折区上呈阵列分布。
  16. 根据权利要求13所述的显示面板，其中，所述开口为凹槽或通孔。
  17. 根据权利要求13所述的显示面板，其中，所述无机膜组层包括依次远离所述基底的缓冲层、第一栅绝缘层、第二栅绝缘层和层间介质层。
  18. 根据权利要求13所述的显示面板，其中，所述开口包括在所述基底上层叠连通的第一孔和第二孔。
  19. 根据权利要求18所述的显示面板，其中，所述第一孔位于所述第二孔上，所述第一孔的深度与所述无机膜组层的厚度之比的范围为0.3~0.5。
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