WO2021027182A1 - 一种服务器电源前后级通讯的方法、设备及可读介质 - Google Patents
一种服务器电源前后级通讯的方法、设备及可读介质 Download PDFInfo
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- WO2021027182A1 WO2021027182A1 PCT/CN2019/121106 CN2019121106W WO2021027182A1 WO 2021027182 A1 WO2021027182 A1 WO 2021027182A1 CN 2019121106 W CN2019121106 W CN 2019121106W WO 2021027182 A1 WO2021027182 A1 WO 2021027182A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
Definitions
- the present invention relates to the field of servers, and more specifically, to a method, equipment and readable medium for front and back communication of a server power supply.
- the server power supply needs to interact with the server's BMC (Baseboard Management Controller, baseboard management controller) through the golden finger board
- the BMC needs to read the relevant information of the PSU (power supply) or configure certain parameters. This interaction It is carried out through the I2C interface and the Pmbus protocol.
- the I2C interface is installed in the latter stage of the LLC, which is the power supply.
- the BMC also needs to interact with part of the data of the previous stage. This requires the help of the LLC. Therefore, the PFC and the LLC are also Need data interaction. Therefore, a convenient, stable and reliable front and back communication method is needed.
- the purpose of the embodiments of the present invention is to propose a method and device for the communication between the front and rear of the server power supply, which mainly uses the serial port and the adjusted transmission protocol to transmit the data of the front stage to the rear stage more reliably in this way. And feedback to the BMC through the golden finger, which not only increases the data transmission rate, but also improves the reliability of the power supply.
- one aspect of the embodiments of the present invention provides a method for server power front and rear communication, which includes the following steps: regularly constructing a data update request according to a transmission protocol that deletes address bits; opening the serial port to send interrupts and judging whether there is a pending transmission Data update request; In response to a data update request to be transmitted, the data update request is sent to the previous stage through the serial port sending interrupt and the serial port sending interrupt is closed; the data returned by the previous stage is received through the serial port receiving interrupt.
- the method further includes: setting the time interval between opening the serial port to send interrupts twice adjacently to be smaller than the time interval between constructing data update requests twice adjacently.
- constructing the data update request regularly according to the transmission protocol for deleting address bits includes: setting a sending buffer, and writing the data update request to be sent into the sending buffer.
- receiving the data returned by the previous stage through the serial port interruption includes: determining whether the data length is equal to a predetermined value; and in response to the data length being equal to the predetermined value, setting the receiving flag of the serial port receiving interruption to one.
- it further includes: when it is detected that the receiving flag bit of the serial port receiving interrupt is one, analyzing the received data.
- a computer device including: at least one processor; and a memory.
- the memory stores computer instructions that can run on the processor, and the instructions are executed by the processor to implement the following steps: According to the transmission protocol that deletes the address bit, the data update request is constructed regularly; the serial port is opened to send an interrupt, and it is judged whether there is a data update request to be transmitted; in response to the data update request to be transmitted, the data update request is sent to the previous through the serial port sending interrupt Level and close the serial port to send interrupt; receive the data returned by the previous stage through the serial port receive interrupt.
- the step further includes: setting the time interval between opening the serial port and sending interrupts twice adjacently to be less than the time interval between constructing the data update request twice.
- constructing the data update request regularly according to the transmission protocol for deleting address bits includes: setting a sending buffer, and writing the data update request to be sent into the sending buffer.
- receiving the data returned by the previous stage through the serial port interruption includes: determining whether the data length is equal to a predetermined value; and in response to the data length being equal to the predetermined value, setting the receiving flag of the serial port receiving interruption to one.
- a computer-readable storage medium stores a computer program that executes the above method when executed by a processor.
- the present invention has the following beneficial technical effects: using the serial port and the adjusted transmission protocol, the data of the previous stage can be transmitted to the subsequent stage more reliably in this way and fed back to the BMC through the golden finger, which not only improves the data transmission rate, but also Improve the reliability of the power supply.
- FIG. 1 is a schematic diagram of an embodiment of a method for back-and-forth communication of a server power supply provided by the present invention
- FIG. 2 is a flowchart of an embodiment of a method for back-and-forth communication of a server power supply provided by the present invention.
- Figure 1 shows a schematic diagram of an embodiment of a method for front and back communication of a server power supply provided by the present invention.
- the embodiment of the present invention includes the following steps:
- the data update request is constructed regularly according to the transmission protocol of the deleted address bit
- the Modbus protocol is suitable for data transmission in small systems. Therefore, in this embodiment, the transmission protocol may be the modbus protocol, but this is not a limitation on the transmission protocol. In other embodiments, other transmission protocols may be used.
- the embodiment of the present invention uses a communication isolation chip to use a serial port on the hardware to connect the front and back stages of the server power supply. According to the Modbus protocol, the latter stage is set to Master (master device), and the previous stage is set to Slave (slave device).
- the data update request is constructed according to the transmission protocol of the deleted address bit.
- the master main program builds a data update request according to the transmission protocol.
- a server power supply has only one front-end part, and there is no need to distinguish the address. Therefore, the transmission protocol is simplified, the slave address in the protocol is removed, and the length of the protocol is shortened. Greatly speed up the data transmission rate, thereby speeding up the data update rate.
- the data update request also includes the data request of the input voltage of the PFC front stage and the bus voltage.
- the Master can be set to poll the required data regularly, and the data update request can also be set at the same time.
- the serial port transmission interrupt can be set to be opened every predetermined time.
- the method further includes: setting the time interval between two consecutive opening of the serial port to send interrupts to be smaller than the time interval between two consecutive construction of data update requests.
- regularly constructing a data update request according to a transmission protocol that deletes address bits includes: setting a sending buffer, and writing the data update request to be sent into the sending buffer.
- an unsigned char sending buffer with a length of 128 can be defined, and the data update request can be written into the sending buffer.
- receiving the data returned by the previous stage through the serial port receiving interrupt includes: determining whether the data length is equal to a predetermined value; and in response to the data length being equal to the predetermined value, setting the receiving flag of the serial port receiving interrupt to one.
- the serial port receiving interrupt is always in the open mode. When receiving the data returned by the Slave, it enters the serial port receiving interrupt to store the data in the receiving buffer. You can define an unsigned char receiving buffer with a length of 128. When the received data length is equal to a predetermined value, for example, the predetermined value in this embodiment is 7 (the length of the returned data is fixed to 7 bytes according to the transmission protocol), Set the received data flag to 1, which means that the data has been received.
- the method further includes: when it is detected that the receiving flag bit of the serial port receiving interrupt is one, analyzing the received data. After the LLC main program detects that the serial port receive interrupt receive data flag bit is 1, the received data is processed, and finally the data to be updated is obtained.
- Slave's serial port receive interrupt is always on. You can define an unsigned char type receive buffer with a length of 32. After receiving the data, put the data into the receive buffer, and receive the serial port when one frame of data is received. The interrupted data receiving flag bit is 1; the main program detects that the data receiving flag bit in the serial port receiving interrupt is 1 and processes the data in the receiving buffer according to the protocol; fills the processed content with the corresponding data in the return frame Or assign a value to the corresponding variable; fill the return frame data into the send buffer of the Slave, you can define an unsigned char type send buffer with a length of 32, fill the return frame data into it, and set the send flag position to 1. Open the serial port to send interrupt and start data transmission. In this way, the interaction of the front and back level data is realized.
- FIG. 2 shows a flowchart of an embodiment of a method for front and back communication of a server power supply provided by the present invention.
- FIG. 2 shows a flowchart of an embodiment of a method for front and back communication of a server power supply provided by the present invention.
- box 101 starting from box 101, then proceeding to box 102, constructing a data update request according to the transmission protocol that deletes the address bit; then proceeding to box 103, opening the serial port to send interrupt; then proceeding to box 104 to determine whether there is a waiting
- the transmitted data update request then proceed to block 105, send the data update request to the previous stage through the serial port sending interrupt; then proceed to block 106, receive the data returned by the previous stage through the serial port receiving interrupt, and then proceed to the end of block 107.
- the second aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory, the memory stores computer instructions that can run on the processor, and the instructions are executed by the processor to The following steps are implemented: S1, the data update request is constructed regularly according to the transmission protocol of the deleted address bit; S2, the serial port is opened to send an interrupt and judge whether there is a data update request to be transmitted; S3, in response to the data update request to be transmitted, through the serial port The sending interrupt sends the data update request to the previous stage and closes the serial port sending interrupt; and S4, receiving the data returned by the previous stage through the serial port receiving interrupt.
- the method further includes: setting the time interval between opening the serial port to send interrupts twice adjacently to be smaller than the time interval between constructing data update requests twice adjacently.
- constructing the data update request regularly according to the transmission protocol for deleting address bits includes: setting a sending buffer, and writing the data update request to be sent into the sending buffer.
- receiving the data returned by the previous stage through the serial port interruption includes: determining whether the data length is equal to a predetermined value; and in response to the data length being equal to the predetermined value, setting the receiving flag of the serial port receiving interruption to one.
- it further includes: when it is detected that the receiving flag bit of the serial port receiving interrupt is one, analyzing the received data.
- the present invention also provides a computer-readable storage medium, and the computer-readable storage medium stores a computer program that executes the above method when executed by a processor.
- the program for the method of server power front and back communication can be stored in a computer.
- the readable storage medium when the program is executed, it may include the procedures of the above-mentioned method embodiments.
- the storage medium of the program can be a magnetic disk, an optical disc, a read-only memory (ROM) or a random access memory (RAM), etc.
- the foregoing computer program embodiment can achieve the same or similar effects as any of the foregoing corresponding method embodiments.
- the method disclosed according to the embodiment of the present invention may also be implemented as a computer program executed by a processor, and the computer program may be stored in a computer-readable storage medium.
- the computer program executes the above-mentioned functions defined in the method disclosed in the embodiment of the present invention.
- the above method steps and system units can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to implement the above steps or unit functions.
- non-volatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory Memory.
- Volatile memory can include random access memory (RAM), which can act as external cache memory.
- RAM can be obtained in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM).
- DRAM synchronous RAM
- DRAM dynamic RAM
- SDRAM synchronous DRAM
- DDR SDRAM double data rate SDRAM
- ESDRAM enhanced SDRAM
- SLDRAM Synchronous link DRAM
- DRRAM direct Rambus RAM
- the storage devices of the disclosed aspects are intended to include, but are not limited to, these and other suitable types of memory.
- DSP digital signal processors
- ASIC application-specific integrated circuits
- FPGA Field Programmable Gate Array
- a general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
- the processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP, and/or any other such configuration.
- the steps of the method or algorithm described in combination with the disclosure herein may be directly included in hardware, a software module executed by a processor, or a combination of the two.
- the software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
- An exemplary storage medium is coupled to the processor such that the processor can read information from or write information to the storage medium.
- the storage medium may be integrated with the processor.
- the processor and the storage medium may reside in the ASIC.
- the ASIC can reside in the user terminal.
- the processor and the storage medium may reside as discrete components in the user terminal.
- functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored as one or more instructions or codes on a computer-readable medium or transmitted through the computer-readable medium.
- Computer-readable media include computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another.
- a storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer.
- the computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or may be used for carrying or storing instructions in the form of Or any other medium that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium.
- coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave to send software from a website, server, or other remote source
- coaxial cable Cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio, and microwave are all included in the definition of media.
- magnetic disks and optical disks include compact disks (CDs), laser disks, optical disks, digital versatile disks (DVD), floppy disks, and Blu-ray disks. Disks generally reproduce data magnetically, while optical disks use lasers to optically reproduce data .
- the combination of the above content should also be included in the scope of computer-readable media.
- the program can be stored in a computer-readable storage medium.
- the storage medium can be a read-only memory, a magnetic disk or an optical disk, etc.
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Claims (10)
- 一种服务器电源前后级通讯的方法,其特征在于,包括:根据删除地址位的传输协议定时构建数据更新请求;打开串口发送中断并判断是否存在待传输的数据更新请求;响应于存在待传输的数据更新请求,通过所述串口发送中断将所述数据更新请求发送到前级并关闭所述串口发送中断;通过串口接收中断接收所述前级返回的数据。
- 根据权利要求1所述的方法,其特征在于,还包括:设定相邻两次打开串口发送中断的时间间隔小于相邻两次构建数据更新请求的时间间隔。
- 根据权利要求1所述的方法,其特征在于,所述根据删除地址位的传输协议定时构建数据更新请求包括:设定发送缓冲区,将待发送的数据更新请求写入所述发送缓冲区。
- 根据权利要求1所述的方法,其特征在于,所述通过串口接收中断接收所述前级返回的数据包括:判断数据长度是否等于预定数值;以及响应于数据长度等于预定数值,将串口接收中断的接收标志位置一。
- 根据权利要求4所述的方法,其特征在于,还包括:检测到所述串口接收中断的接收标志位为一时,对接收到的数据进行解析。
- 一种计算机设备,其特征在于,包括:至少一个处理器;以及存储器,所述存储器存储有可在所述处理器上运行的计算机指令,所述指令由所述处理器执行时实现如下步骤:根据删除地址位的传输协议定时构建数据更新请求;打开串口发送中断并判断是否存在待传输的数据更新请求;响应于存在待传输的数据更新请求,通过所述串口发送中断将所述数据更新请求发送到前级并关闭所述串口发送中断;通过串口接收中断接收所述前级返回的数据。
- 根据权利要求6所述的计算机设备,其特征在于,步骤还包括:设定相邻两次打开串口发送中断的时间间隔小于相邻两次构建数据更新请求的时间间隔。
- 根据权利要求6所述的计算机设备,其特征在于,所述根据删除地址位的传输协议定时构建数据更新请求包括:设定发送缓冲区,将待发送的数据更新请求写入所述发送缓冲区。
- 根据权利要求6所述的计算机设备,其特征在于,所述通过串口接收中断接收所述前级返回的数据包括:判断数据长度是否等于预定数值;以及响应于数据长度等于预定数值,将串口接收中断的接收标志位置一。
- 一种计算机可读存储介质,所述计算机可读存储介质存储有计算机程序,其特征在于,所述计算机程序被处理器执行时执行权利要求1-5任意一项所述的方法。
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