WO2021169474A1 - 一种Avalon总线转Axi4总线的方法 - Google Patents

一种Avalon总线转Axi4总线的方法 Download PDF

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WO2021169474A1
WO2021169474A1 PCT/CN2020/134718 CN2020134718W WO2021169474A1 WO 2021169474 A1 WO2021169474 A1 WO 2021169474A1 CN 2020134718 W CN2020134718 W CN 2020134718W WO 2021169474 A1 WO2021169474 A1 WO 2021169474A1
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bus
avalon
axi4
data
converting
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PCT/CN2020/134718
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English (en)
French (fr)
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郭雷
张静东
王江为
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苏州浪潮智能科技有限公司
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Priority to EP20922306.4A priority Critical patent/EP4050491A4/en
Priority to US17/780,190 priority patent/US11657011B2/en
Publication of WO2021169474A1 publication Critical patent/WO2021169474A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4013—Coupling between buses with data restructuring with data re-ordering, e.g. Endian conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol

Definitions

  • This application relates to the technical field of data conversion, in particular to a method for converting Avalon bus to Axi4 bus; and also relates to a device, device and computer-readable storage medium for converting Avalon bus to Axi4 bus.
  • the Avalon bus is an internal interconnection bus technology developed by Altera, which can be automatically generated by the QSYS tool without user intervention. It is often used as an ideal inline bus between the system processor and peripherals. At the same time, the Avalon bus has independent address, data, and control lines, supports data widths within 128 bits, supports synchronous operation, and does not require complex handshake/response mechanisms. Therefore, the Avalon bus is widely used flexibly.
  • the Axi4 bus is a high-performance, high-bandwidth, and low-latency on-chip bus proposed by AMBA. Its main feature is that the address/control and data are independent, and it supports unaligned data transmission. At the same time, it will read and write data channels. Separate, support significant transmission access and out-of-order access.
  • the interconnection bus is usually unified into a bus protocol, and the mainstream is the Avalon bus or the Axi4 bus.
  • the interconnection bus will be different. If you consider multi-platform universal design, the code module needs to consider two bus interfaces, and the development of an interface that supports the two buses will seriously affect the development efficiency and speed, and increase the product development cycle. Or, when calling existing function modules across platforms, the code needs to be modified to match the bus interface.
  • amm_axi_bridge which realizes the conversion of avalon_mm bus (memory mapping mode of Avalon bus) to Axi4 bus.
  • this IP can only be used on the Xilinx platform, has a large delay, and does not support cross-clock domain conversion, and its use is limited.
  • the purpose of this application is to provide a method for converting Avalon bus to Axi4 bus, which can realize the conversion of Avalon bus to Axi4 bus without delay and across clock domains, and realize rapid design and matching interface work in cross-platform universal design or code migration schemes .
  • Another object of the present application is to provide an Avalon bus to Axi4 bus conversion device, equipment, and computer-readable storage medium, all of which have the above technical effects.
  • this application provides a method for converting Avalon bus to Axi4 bus, including:
  • Avalon bus When the Avalon bus is an Avalon_st bus, receive Avalon_st bus data, and perform logical processing on the received Avalon_st bus data before outputting corresponding Axi4_st bus data;
  • the Avalon bus When the Avalon bus is the Avalon_mm bus, receive the signal transmitted by each channel of the Avalon_mm bus and store the signal in the asynchronous FIFO after framing, and when the device corresponding to the Axi4 bus is ready, read from the asynchronous FIFO The signal is output to the corresponding channel of the Axi4 bus according to the timing relationship of the Axi4 bus.
  • the logically processing the received Avalon_st bus data and then outputting corresponding Axi4_st bus data includes:
  • the data in the Avalon_st bus data is assigned to the corresponding interface of the Axi4_st bus after performing high and low logic inversions in bytes as a unit;
  • a valid byte position is obtained based on the invalid byte position in the Avalon_st bus data, and the value of the valid byte position is assigned to the corresponding interface of the Axi4_st bus.
  • the signals transmitted by each channel of the Avalon_mm bus include read instructions, read addresses and burst lengths or write instructions, write addresses and burst lengths or write instructions, write data and burst lengths.
  • it also includes:
  • the waitrequest signal is output to the Avalon_mm bus.
  • it also includes:
  • this application also provides a device for converting Avalon bus to Axi4 bus, including:
  • Avalon_st bus to Axi4_st bus module used to receive Avalon_st bus data when the Avalon bus is an Avalon_st bus, and logically process the received Avalon_st bus data to output corresponding Axi4_st bus data;
  • Avalon_mm bus to Axi4 bus module used when the Avalon bus is the Avalon_mm bus, receive the signals transmitted by each channel of the Avalon_mm bus and store the signals in the asynchronous FIFO after framing, and when the device corresponding to the Axi4 bus is ready , Reading the signal from the asynchronous FIFO, and outputting the signal to the corresponding channel of the Axi4 bus according to the timing relationship of the Axi4 bus.
  • it also includes:
  • the feedback module is used to output a waitrequest signal to the Avalon_mm bus according to the depth parameter of the asynchronous FIFO and the stored data.
  • it also includes:
  • the modification module is used to modify the depth parameter of the asynchronous FIFO.
  • this application also provides a device for converting Avalon bus to Axi4 bus, including:
  • Memory used to store computer programs
  • the processor is used to implement the steps of the method for converting the Avalon bus to the Axi4 bus as described above when the computer program is executed.
  • this application also provides a computer-readable storage medium with a computer program stored on the computer-readable storage medium, and when the computer program is executed by a processor, the Avalon bus is converted to Axi4 The steps of the bus method.
  • the method for converting the Avalon bus to the Axi4 bus includes: when the Avalon bus is the Avalon_st bus, receiving Avalon_st bus data, and logically processing the received Avalon_st bus data to output corresponding Axi4_st bus data; when When the Avalon bus is the Avalon_mm bus, the signal transmitted by each channel of the Avalon_mm bus is received and the signal is framed and stored in the asynchronous FIFO, and when the device corresponding to the Axi4 bus is ready, read all the signals from the asynchronous FIFO. And output the signal to the corresponding channel of the Axi4 bus according to the timing relationship of the Axi4 bus.
  • the method of converting Avalon bus to Axi4 bus provided by this application, when the Avalon bus is the Avalon_st bus, after receiving the Avalon_st bus data, directly logically process the received Avalon_st bus data and output the corresponding Axi4_st bus data, thereby achieving Avalon_st bus is converted to Axi4_st bus without delay.
  • the Avalon bus is the Avalon_mm bus
  • the signals received by each channel of the Avalon_mm bus are stored in the asynchronous FIFO, and when the device corresponding to the Axi4 bus is ready, the signal is read from the asynchronous FIFO and output, so as to achieve the crossover.
  • the clock domain completes the conversion from Avalon_mm bus to Axi4 bus.
  • Avalon_mm bus In the same time, in cross-platform design, only the Avalon bus can be planned.
  • the method provided in this application can be used to realize the conversion from the Avalon bus to the Axi4 bus.
  • using the method provided in this application to implement the conversion from Avalon bus to Axi4 bus can effectively reduce interface debugging, improve development efficiency, and more efficiently verify the performance of function codes on multiple platforms.
  • the Avalon bus to Axi4 bus conversion device, equipment, and computer-readable storage medium provided in this application all have the above technical effects.
  • FIG. 1 is a schematic flowchart of a method for converting an Avalon bus to an Axi4 bus according to an embodiment of the application;
  • FIG. 2 is a schematic diagram of bus conversion under a read operation provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of bus conversion under a write operation provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of a device for converting Avalon bus to Axi4 bus provided by an embodiment of the application.
  • the core of this application is to provide a method for converting Avalon bus to Axi4 bus, which can realize Avalon bus to Axi4 bus without delay and across clock domains, and realize rapid design and matching interface work in cross-platform universal design or code migration schemes .
  • Another core of the application is to provide an Avalon bus to Axi4 bus device, equipment, and computer-readable storage medium, all of which have the above technical effects.
  • FIG. 1 is a schematic flowchart of a method for converting an Avalon bus to an Axi4 bus according to an embodiment of the application.
  • the method includes:
  • this step aims to realize the conversion from the Avalon_st bus to the Axi4_st bus.
  • the so-called Avalon_st bus refers to the flow mode of the Avalon bus
  • the so-called Axi4_st bus refers to the flow mode of the Axi4 bus.
  • the above-mentioned logical processing of the received Avalon_st bus data and output of the corresponding Axi4_st bus data include: assigning the values of the data packet end identifier, data valid identifier and device ready status identifier in the Avalon_st bus data to the corresponding values of the Axi4_st bus Interface; the data in the Avalon_st bus data is assigned to the corresponding interface of the Axi4_st bus by inverting the high and low logic in the byte unit; based on the invalid byte position in the Avalon_st bus data, the valid byte position is obtained, and the valid byte The value of the position is assigned to the corresponding interface of the Axi4_st bus.
  • the Avalon_st bus interface includes the start of the packet (start of packet), the data channel (date), the end of the packet (end of packet), the position of the invalid byte in the data (empty), and the data valid identifier (valid). ), whether the target device is in the ready state (ready).
  • the Axi4_st bus interface includes a data channel (date), data valid identification (valid), data valid location (keep), data packet end identification (last), and whether the target device is in a ready state identification (ready).
  • the Avalon_st bus interface includes the data packet start identifier, and the Axi4_st bus interface does not have the data packet start identifier, so the data packet start identifier in the Avalon_st bus interface can not be processed.
  • the data packet end flag in the Avalon_st bus interface has the same function as the data packet end flag in the Axi4_st bus interface. Therefore, the value of the data packet end flag in the Avalon_st bus interface is assigned to the data packet end flag in the Axi4_st bus interface.
  • the Avalon_st bus interface and the Axi4_st bus interface have data channel input high and low logic opposite, so the Avalon_st bus data is inverted by the high and low logic in bytes, and the inverted data is assigned to the data channel of the Axi4_st bus. That is, the value of the highest byte of Avalon_st bus data is assigned to the lowest byte of Axi4_st bus data, and the value of the next highest byte of Avalon_st bus data is assigned to the next lowest byte of Axi4_st bus data, and so on to complete the conversion.
  • the Avalon_st bus interface contains the invalid byte position in the data, while the Axi4_st bus interface contains the valid byte position in the data. Therefore, the valid byte position is first obtained based on the invalid byte position in the Avalon_st bus data, and then the valid byte position is The value is assigned to the invalid byte position in the data in the Axi4_st bus interface. For example, the empty of the 64bit data is 3'd0, which means that the invalid data is 0, and the converted keep is 8'hff, which also means that the invalid data is 0. The empty of the 64bit data is 3'd1, and the converted keep is 8. 'h7f.
  • the data valid identifier in the Avalon_st bus interface has the same function as the data valid identifier in the Axi4_st bus interface. Therefore, the value of the data valid identifier in the Avalon_st bus interface is assigned to the data valid identifier in the Axi4_st bus interface.
  • the identification of whether the target device in the Avalon_st bus interface is in the ready state has the same function as the identification of whether the target device in the Axi4_st bus interface is in the ready state. Therefore, the value of the identification whether the target device in the Avalon_st bus interface is in the ready state is assigned to the Axi4_st bus interface Whether the target device in is in the ready state.
  • this step aims to realize the conversion from the Avalon_mm bus to the Axi4 bus.
  • the so-called Avalon_mm bus is the memory mapping mode of the Avalon bus.
  • the read and write instructions in the Avalon_mm bus are separated from the channels for reading and writing data, and the read and write operation address bus is shared.
  • the Axi4 bus contains 5 channels, which are read address channel, read data channel, write address channel, write data channel, and write response channel.
  • the controller After the controller receives the signal transmitted by each channel of the Avalon_mm bus, it first frames the received signal and stores it in the asynchronous FIFO (First Input First Output), and then when the device corresponding to the Axi4 bus is ready, Read the signal in the asynchronous FIFO, disassemble and reassemble the signal, and output the signal to the corresponding channel of the Axi4 bus according to the timing relationship of the Axi4 bus.
  • asynchronous FIFO First Input First Output
  • the signals transmitted by each channel of the Avalon_mm bus include read instructions, read addresses, and burst lengths, or write instructions, write addresses, and burst lengths, or receive write instructions, write data, and burst lengths.
  • the controller receives the read command (Avalon_mm_read), read address (Avalon_mm_address) and burst length (Avalon_mm_burstcount) of the Avalon_mm bus, and reads the command, read address, and burst count.
  • the length information is grouped and stored in the asynchronous FIFO.
  • the ready status of the device receiving the Axi4 data that is, the ready status
  • the entire frame of data is taken out at the other end of the asynchronous FIFO, and the information is disassembled and reorganized according to the timing relationship of the Axi4 bus protocol, and then output Read command, read address and burst length information of Axi4 bus.
  • the meaning of the burst length of the Avalon_mm bus is different from the burst length of the Axi4 bus.
  • the value of the burst length of the Avalon_mm bus is added by one to obtain the value of the burst length of the Axi4 bus.
  • the controller receives the read command and other signals of the Avalon_mm bus, packs the read command and other frames into the asynchronous FIFO, according to the ready status of the device receiving the Axi4 data, that is, the ready status At the other end of the asynchronous FIFO, the entire frame of data is taken out, and the information is disassembled and reorganized according to the timing relationship of the Axi4 bus protocol, and then the relevant instructions corresponding to the Axi4 bus are output. Furthermore, the device corresponding to the Axi4 bus receives the information such as the read address and burst length and feeds the corresponding data back to the controller.
  • the controller further stores the data and command framing in the asynchronous FIFO according to the signal relationship of axi4_rdata, axi4_rdatavalid and axi4_rlast, and further reads the data from the asynchronous FIFO according to the timing relationship of the Avalon_mm bus and feeds it back to the readdata and readdatavalid channels of the Avalon_mm bus.
  • the controller also receives the write response information of the corresponding peripheral and the completion signal of the write signal.
  • the controller also has a fault-tolerant mechanism to process partial errors or inaccurate timing of the bus data, so that valid data can proceed normally. For example, when the avalon_ready signal is pulled low, the avolin_valid signal needs to remain in the original state and cannot be jumped. However, in fact, no matter whether the avolin_valid signal has a jump or not, it will not affect the normal transmission and reception of data. Therefore, when ready is low, even if the avolin_valid signal jumps, the controller can accept it, and the data can continue to be sent and received normally. Receive and realize bus conversion.
  • it may also include:
  • the waitrequest signal is output to the Avalon_mm bus.
  • the controller after the controller receives the address, data, and burst length of the Avalon_mm bus, and stores the address, data, and burst length in the asynchronous FIFO, the controller further according to the depth parameters of the asynchronous FIFO and When the data has been stored, that is, whether the asynchronous FIFO is full, the waitrequest signal is output to the Avalon_mm bus to inform the corresponding device to wait or continue to transmit data.
  • it may also include: modifying the depth parameter of the asynchronous FIFO.
  • the depth application of the asynchronous FIFO is different under different working conditions.
  • the depth parameters of the asynchronous FIFO can also be modified to avoid affecting the speed and efficiency of the conversion after the asynchronous FIFO is full.
  • the depth parameter of the asynchronous FIFO can be modified to a relatively small value at this time.
  • the Avalon bus to Axi4 bus method provided by this application, when the Avalon bus is the Avalon_st bus, after receiving the Avalon_st bus data, directly logically process the received Avalon_st bus data and output the corresponding Axi4_st bus data , So as to realize the conversion from Avalon_st bus to Axi4_st bus without delay.
  • the Avalon bus is the Avalon_mm bus
  • the signals received by each channel of the Avalon_mm bus are stored in the asynchronous FIFO, and when the device corresponding to the Axi4 bus is ready, the signal is read from the asynchronous FIFO and output, so as to achieve the crossover.
  • the clock domain completes the conversion from Avalon_mm bus to Axi4 bus.
  • Avalon_mm bus In the same time, in cross-platform design, only the Avalon bus can be planned.
  • the method provided in this application can be used to realize the conversion from the Avalon bus to the Axi4 bus.
  • using the method provided in this application to implement the conversion from Avalon bus to Axi4 bus can effectively reduce interface debugging, improve development efficiency, and more efficiently verify the performance of function codes on multiple platforms.
  • the present application also provides a device for converting Avalon bus to Axi4 bus, and the device described below may correspond to the method described above with reference to each other.
  • the device includes:
  • the Avalon_st bus to Axi4_st bus module 10 is used for receiving Avalon_st bus data when the Avalon bus is an Avalon_st bus, and logically processing the received Avalon_st bus data to output corresponding Axi4_st bus data;
  • the Avalon_mm bus to Axi4 bus module 20 is used to receive the signals transmitted by each channel of the Avalon_mm bus when the Avalon bus is the Avalon_mm bus and store the signals in the asynchronous FIFO after framing, and when the device corresponding to the Axi4 bus is ready At this time, the signal is read from the asynchronous FIFO, and the signal is output to the corresponding channel of the Axi4 bus according to the timing relationship of the Axi4 bus.
  • the Avalon_st bus to Axi4_st bus module 10 is specifically configured to assign the values of the data packet end identifier, data valid identifier, and device ready status identifier in the Avalon_st bus data to the Axi4_st bus Corresponding interface; the data in the Avalon_st bus data is assigned to the corresponding interface of the Axi4_st bus by inverting the high and low logic in byte units; valid bytes are obtained based on the invalid byte position in the Avalon_st bus data And assign the value of the effective byte position to the corresponding interface of the Axi4_st bus.
  • the feedback module is used to output a waitrequest signal to the Avalon_mm bus according to the depth parameter of the asynchronous FIFO and the stored data.
  • the modification module is used to modify the depth parameter of the asynchronous FIFO.
  • This application also provides a device for converting Avalon bus to Axi4 bus, and the device includes a memory and a processor.
  • the memory is used to store the computer program; the processor is used to execute the computer program to implement the following steps:
  • the Avalon bus When the Avalon bus is the Avalon_st bus, receive the Avalon_st bus data, perform logical processing on the received Avalon_st bus data, and output the corresponding Axi4_st bus data; when the Avalon bus is the Avalon_mm bus, receive the channel transmission of the Avalon_mm bus And store the signal in the asynchronous FIFO after framing, and when the device corresponding to the Axi4 bus is ready, read the signal from the asynchronous FIFO, and convert the signal according to the timing relationship of the Axi4 bus The signal is output to the corresponding channel of the Axi4 bus.
  • the present application also provides a computer-readable storage medium with a computer program stored on the computer-readable storage medium, and when the computer program is executed by a processor, the following steps can be implemented:
  • the Avalon bus When the Avalon bus is the Avalon_st bus, receive the Avalon_st bus data, perform logical processing on the received Avalon_st bus data, and output the corresponding Axi4_st bus data; when the Avalon bus is the Avalon_mm bus, receive the channel transmission of the Avalon_mm bus And store the signal in the asynchronous FIFO after framing, and when the device corresponding to the Axi4 bus is ready, read the signal from the asynchronous FIFO, and convert the signal according to the timing relationship of the Axi4 bus The signal is output to the corresponding channel of the Axi4 bus.
  • the computer-readable storage medium may include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk, etc., which can store program codes Medium.
  • the steps of the method or algorithm described in the embodiments disclosed in this document can be directly implemented by hardware, a software module executed by a processor, or a combination of the two.
  • the software module can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or all areas in the technical field. Any other known storage media.

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Abstract

一种Avalon总线转Axi4总线的方法，包括：当Avalon总线为Avalon_st总线时，接收Avalon_st总线数据，并对接收到的Avalon_st总线数据进行逻辑处理后输出相应的Axi4_st总线数据；当Avalon总线为Avalon_mm总线时，接收Avalon_mm总线各通道传输的信号并将信号组帧后存入异步FIFO，且当Axi4总线对应的设备准备就绪时，从异步FIFO中读取信号，并依据Axi4总线的时序关系将信号输出至Axi4总线的相应通道。该方法能够无延时、跨时钟域的实现Avalon总线转Axi4总线，在跨平台通用设计或代码移植方案中实现快速设计和匹配接口的工作。

Description

一种Avalon总线转Axi4总线的方法
本申请要求于2020年02月29日提交至中国专利局、申请号为202010132403.7、发明名称为“一种Avalon总线转Axi4总线的方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及数据转换技术领域，特别涉及一种Avalon总线转Axi4总线的方法；还涉及一种Avalon总线转Axi4总线的装置、设备以及计算机可读存储介质。
背景技术
Avalon总线是由Altera开发的一种内部互联的总线技术，可由QSYS工具自动生成无需用户干预，其经常被作为***处理器与外设之间理想的内联总线。同时，Avalon总线具有独立地址、数据以及控制线，支持128位以内的数据宽度，支持同步操作，且不需要复杂的握手/应答机制等优势，因此Avalon总线被灵活广泛应用。Axi4总线是AMBA公司提出的一种面向高性能、高宽带、低延时的片内总线，其主要特点是地址/控制以及数据均独立，支持不对齐的数据传输，同时其将读写数据通道分离开，支持显著的传输访问和乱序访问。
目前，在大多数的FPGA工程设计中，互联总线通常会统一为一种总线协议，主流的即为Avalon总线或Axi4总线。使用不同的厂家芯片、开发工具，互联总线会不同。若考虑多平台通用设计，代码模块需要考虑两种总线接口，而开发支持两种总线的接口会严重影响开发效率和速度，增加产品的研发周期。或者，跨平台调用已有功能模块时，还需修改代码以匹配总线接口。
针对上述问题，Xilinx芯片厂家提供了一种名为amm_axi_bridge的IP，由此实现avalon_mm总线(Avalon总线的内存映射模式)到Axi4总线的转换。然而，该IP仅支持在Xilinx的平台上使用，有较大延时，且不支持跨时钟域的转换，使用局限性较大。
有鉴于此，如何解决上述技术问题已成为本领域技术人员亟待解决的 技术问题。
发明内容
本申请的目的是提供一种Avalon总线转Axi4总线的方法，能够无延时、跨时钟域的实现Avalon总线转Axi4总线，在跨平台通用设计或代码移植方案中实现快速设计和匹配接口的工作。本申请的另一目的是提供一种Avalon总线转Axi4总线的装置、设备以及计算机可读存储介质，均具有上述技术效果。
为解决上述技术问题，本申请提供了一种Avalon总线转Axi4总线的方法，包括：
当Avalon总线为Avalon_st总线时，接收Avalon_st总线数据，并对接收到的所述Avalon_st总线数据进行逻辑处理后输出相应的Axi4_st总线数据；
当所述Avalon总线为Avalon_mm总线时，接收Avalon_mm总线各通道传输的信号并将所述信号组帧后存入异步FIFO，且当Axi4总线对应的设备准备就绪时，从所述异步FIFO中读取所述信号，并依据所述Axi4总线的时序关系将所述信号输出至所述Axi4总线的相应通道。
可选的，所述对接收到的所述Avalon_st总线数据进行逻辑处理后输出相应的Axi4_st总线数据，包括：
将所述Avalon_st总线数据中的数据包结束标识、数据有效标识以及设备就绪状态标识的值赋值给Axi4_st总线的相应接口；
将所述Avalon_st总线数据中的数据以字节为单位进行高低位逻辑取反后赋值给所述Axi4_st总线的相应接口；
基于所述Avalon_st总线数据中的无效字节位置得到有效字节位置，并将所述有效字节位置的值赋值给所述Axi4_st总线的相应接口。
可选的，所述Avalon_mm总线各通道传输的信号包括读指令、读地址以及猝发长度或写指令、写地址以及猝发长度或写指令、写数据以及猝发长度。
可选的，还包括：
根据所述异步FIFO的深度参数以及已存储数据情况，输出waitrequest信号至所述Avalon_mm总线。
可选的，还包括：
修改所述异步FIFO的所述深度参数。
为解决上述技术问题，本申请还提供了一种Avalon总线转Axi4总线的装置，包括：
Avalon_st总线转Axi4_st总线模块，用于当Avalon总线为Avalon_st总线时，接收Avalon_st总线数据，并对接收到的所述Avalon_st总线数据进行逻辑处理后输出相应的Axi4_st总线数据；
Avalon_mm总线转Axi4总线模块，用于当所述Avalon总线为Avalon_mm总线时，接收Avalon_mm总线各通道传输的信号并将所述信号组帧后存入异步FIFO，且当Axi4总线对应的设备准备就绪时，从所述异步FIFO中读取所述信号，依据所述Axi4总线的时序关系将所述信号输出至所述Axi4总线的相应通道。
可选的，还包括：
反馈模块，用于根据所述异步FIFO的深度参数以及已存储数据情况，输出waitrequest信号至所述Avalon_mm总线。
可选的，还包括：
修改模块，用于修改所述异步FIFO的所述深度参数。
为解决上述技术问题，本申请还提供了一种Avalon总线转Axi4总线的设备，包括：
存储器，用于存储计算机程序；
处理器，用于执行所述计算机程序时实现如上所述的Avalon总线转Axi4总线的方法的步骤。
为解决上述技术问题，本申请还提供了一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如上所述的Avalon总线转Axi4总线的方法的步骤。
本申请所提供的Avalon总线转Axi4总线的方法，包括：当Avalon总线为Avalon_st总线时，接收Avalon_st总线数据，并对接收到的所述Avalon_st总线数据进行逻辑处理后输出相应的Axi4_st总线数据；当所述Avalon总线为Avalon_mm总线时，接收Avalon_mm总线各通道传输的信号并将所述信号组帧后存入异步FIFO，且当Axi4总线对应的设备准备就绪时，从所述异 步FIFO中读取所述信号，并依据所述Axi4总线的时序关系将所述信号输出至所述Axi4总线的相应通道。
可见，本申请所提供的Avalon总线转Axi4总线的方法，在Avalon总线为Avalon_st总线情况下，接收Avalon_st总线数据后直接对接收到的Avalon_st总线数据进行逻辑处理并输出相应的Axi4_st总线数据，从而实现Avalon_st总线向Axi4_st总线无延时的转换。另外，在Avalon总线为Avalon_mm总线情况下，将接收到Avalon_mm总线各通道传输的信号存入异步FIFO，并当Axi4总线对应的设备准备就绪时，从异步FIFO中读取信号并输出，从而达到跨时钟域的完成Avalon_mm总线向Axi4总线的转换。同时，跨平台设计时，可只规划Avalon总线，当需要Axi4总线时，采用本申请所提供的方法即可实现Avalon总线向Axi4总线的转换。并且，跨平台调用已有功能代码时，采用本申请所提供的方法实现Avalon总线向Axi4总线的转换，可以有效减少接口调试工作，提高开发效率，更高效的验证功能代码在多平台的性能。
本申请所提供的Avalon总线转Axi4总线的装置、设备以及计算机可读存储介质均具有上述技术效果。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对现有技术和实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例所提供的一种Avalon总线转Axi4总线的方法的流程示意图；
图2为本申请实施例所提供的一种读操作下的总线转换示意图；
图3为本申请实施例所提供的一种写操作下的总线转换示意图；
图4为本申请实施例所提供的一种Avalon总线转Axi4总线的装置的示意图。
具体实施方式
本申请的核心是提供一种Avalon总线转Axi4总线的方法，能够无延时、 跨时钟域的实现Avalon总线转Axi4总线，在跨平台通用设计或代码移植方案中实现快速设计和匹配接口的工作。本申请的另一核心是提供一种Avalon总线转Axi4总线的装置、设备以及计算机可读存储介质，均具有上述技术效果。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参考图1，图1为本申请实施例所提供的一种Avalon总线转Axi4总线的方法的流程示意图。参考图1所示，该方法包括：
S101：当Avalon总线为Avalon_st总线时，接收Avalon_st总线数据，并对接收到的Avalon_st总线数据进行逻辑处理后输出相应的Axi4_st总线数据；
具体的，本步骤旨在实现Avalon_st总线向Axi4_st总线的转换。所谓Avalon_st总线，即Avalon总线的流模式，所谓Axi4_st总线，即Axi4总线的流模式。控制器接收到Avalon_st总线协议格式的数据即Avalon_st总线数据后，直接对接收到的Avalon_st总线数据进行逻辑处理，并输出Axi4_st总线协议格式的数据即Axi4_st总线数据，达到无延时的将Avalon_st总线转换为Axi4_st总线的目的。
其中，上述对接收到的Avalon_st总线数据进行逻辑处理后输出相应的Axi4_st总线数据，包括：将Avalon_st总线数据中的数据包结束标识、数据有效标识以及设备就绪状态标识的值赋值给Axi4_st总线的相应接口；将Avalon_st总线数据中的数据以字节为单位进行高低位逻辑取反后赋值给Axi4_st总线的相应接口；基于Avalon_st总线数据中的无效字节位置得到有效字节位置，并将有效字节位置的值赋值给Axi4_st总线的相应接口。
具体而言，Avalon_st总线接口包括数据包起始标识(start of packet)、数据通道(date)、数据包结束标识(end of packet)、数据中无效字节位置(empty)、数据有效标识(valid)、目标设备是否处于就绪状态标识 (ready)。Axi4_st总线接口包括数据通道(date)、数据有效标识(valid)、数据有效位置(keep)、数据包结束标识(last)、目标设备是否处于就绪状态标识(ready)。
对比Avalon_st总线接口与Axi4_st总线接口可知，Avalon_st总线接口包括数据包起始标识，而Axi4_st总线接口没有数据包起始标识，故可对Avalon_st总线接口中的数据包起始标识不做处理。Avalon_st总线接口中的数据包结束标识与Axi4_st总线接口中的数据包结束标识功能相同，因此，将Avalon_st总线接口中的数据包结束标识的值赋值给Axi4_st总线接口中的数据包结束标识。Avalon_st总线接口与Axi4_st总线接口的数据通道输入高低位逻辑相反，故将Avalon_st总线数据以字节为单位进行高低位逻辑取反，并将取反后的数据赋予Axi4_st总线的数据通道。即将Avalon_st总线数据的最高字节的值赋予Axi4_st总线数据的最低字节，将Avalon_st总线数据的次高字节的值赋予Axi4_st总线数据的次低字节，依此类推，完成转换。
Avalon_st总线接口中包含数据中无效字节位置，而Axi4_st总线接口则包含数据中有效字节位置，故首先基于Avalon_st总线数据中的无效字节位置得到有效字节位置，进而将有效字节位置的值赋值给Axi4_st总线接口中的数据中无效字节位置。例如，64bit数据的empty为3’d0，代表无效数据为0，则转换后的keep为8’hff，同样代表无效数据为0。64bit数据的empty为3’d1，则转换后的keep为8’h7f。
Avalon_st总线接口中的数据有效标识与Axi4_st总线接口中的数据有效标识功能相同，因此，将Avalon_st总线接口中的数据有效标识的值赋值给Axi4_st总线接口中的数据有效标识。Avalon_st总线接口中的目标设备是否处于就绪状态标识与Axi4_st总线接口中的目标设备是否处于就绪状态标识功能相同，因此，将Avalon_st总线接口中的目标设备是否处于就绪状态标识的值赋值给Axi4_st总线接口中的目标设备是否处于就绪状态标识。
S102：当Avalon总线为Avalon_mm总线时，接收Avalon_mm总线各通道传输的信号并将信号组帧后存入异步FIFO，且当Axi4总线对应的设 备准备就绪时，从异步FIFO中读取信号，依据Axi4总线的时序关系将信号输出至Axi4总线的相应通道。
具体的，本步骤旨在实现Avalon_mm总线向Axi4总线的转换。所谓Avalon_mm总线即Avalon总线的内存映射模式。Avalon_mm总线中的读写指令和读写数据的通道分离，读写操作地址总线共享。Axi4总线包含5个通道，分别为读地址通道、读数据通道、写地址通道、写数据通道以及写响应通道。控制器在接收到Avalon_mm总线各通道传输的信号后，首先将所接收的信号组帧后存入异步FIFO(First Input First Output，先入先出)，进而当Axi4总线对应的设备准备就绪时，从异步FIFO中读取信号，拆解重组信号并依据Axi4总线的时序关系将信号输出至Axi4总线的相应通道。
其中，Avalon_mm总线各通道传输的信号包括读指令、读地址以及猝发长度或或写指令、写地址以及猝发长度或接收写指令、写数据以及猝发长度。
具体而言，对于读地址操作下的总线转换：参考图2，控制器接收Avalon_mm总线的读指令(Avalon_mm_read)、读地址(Avalon_mm_address)以及猝发长度(Avalon_mm_burstcount)，并将读指令、读地址以及猝发长度信息组帧打包存入异步FIFO，根据接收Axi4数据的设备的就绪情况即arready情况，在异步FIFO的另一端将整帧数据取出，并依据Axi4总线协议的时序关系拆解重组信息，进而输出Axi4总线的读指令、读地址以及猝发长度信息。其中，Avalon_mm总线的猝发长度与Axi4总线的猝发长度的含义不同，将Avalon_mm总线的猝发长度的值加一后得到Axi4总线的猝发长度的值。
对于读数据操作下的总线转换，参考图2所示，控制器接收Avalon_mm总线的读指令等信号，将读指令等组帧打包存入异步FIFO，根据接收Axi4数据的设备的就绪情况即arready情况，在异步FIFO的另一端将整帧数据取出，并依据Axi4总线协议的时序关系拆解重组信息，进而输出Axi4总线对应的相关指令。进而，Axi4总线对应的设备接收到读地址以及猝发长度等信息后将相应的数据反馈给控制器。控制器进一步依据axi4_rdata、axi4_rdatavalid以及axi4_rlast的信号关系，将数据和指令组帧存入异步FIFO，并进一步依据Avalon_mm总线的时序关系，从异步FIFO读取数据并 反馈给Avalon_mm总线的readdata与readdatavalid通道。
对于写地址操作下的总线转换，参考图3所示，接收Avalon_mm总线的写指令(Avalon_mm_write)、写地址(Avalon_mm_address)以及猝发长度信息(Avalon_mm_burstcount)，并将写指令、写地址以及猝发长度信息组帧打包存入异步FIFO，根据接收Axi4总线数据的设备的就绪情况，在异步FIFO的另一端将整帧数据取出，并依据Axi4总线协议的时序关系拆解重组信息，进而输出Axi4总线的写指令(Axi4_awvalid)、写地址(Axi4_awaddr)以及猝发长度信息(Axi4_awlenth)。
对于写数据操作下的总线转换，参考图3所示，接收Avalon_mm总线的写指令、写数据(Avalon_mm_writedata)以及猝发长度信息，并将写指令、写数据以及猝发长度信息组帧打包存入异步FIFO，根据接收Axi4总线数据的设备的就绪情况以及接收的awready情况，在异步FIFO的另一端将整帧数据取出，并依据Axi4总线协议的时序关系拆解重组信息，进而输出Axi4总线的写指令、写数据以及猝发长度信息。
其中，对于Axi4总线的其他接口的配置，本申请在此不作赘述以及限定，根据实际需要进行相应的配置即可。另外，控制器还接收对应外设的写响应信息，接收写信号的完成信号。此外，控制器还具有容错机制，以处理部分出错或时序不严整的总线数据，使有效数据可以正常进行。例如，avalon_ready信号拉低时，avolin_valid信号需保持原有状态，不能做跳变。然而实际上此时无论avolin_valid信号有没有跳变都不会影响数据的正常发送和接收，因此，当ready为低时，即使avolin_valid信号发生跳变，控制器也可以接受，数据可继续正常发送和接收，实现总线转换。
进一步，在上述实施例的基础上，还可以包括：
根据异步FIFO的深度参数以及已存储数据的情况，输出waitrequest信号至Avalon_mm总线。
具体的，本实施例中，控制器在接收Avalon_mm总线的地址、数据以及猝发长度并将地址、数据以及猝发长度组帧存入异步FIFO的基础上，控制器还进一步根据异步FIFO的深度参数以及已经存储数据的情况即异步FIFO是否存满，输出waitrequest信号至Avalon_mm总线，以告知对应的设备等待或继续传输数据。
进一步，在上述实施例的基础上，还可以包括：修改异步FIFO的深度参数。
具体的，不同工况下异步FIFO的深度应用不同，为更好的满足不同工况的需求，还可以对异步FIFO的深度参数进行修改，以免造成存满异步FIFO后影响转换的速度和效率。例如，对于快入慢出的工况，此时可将异步FIFO的深度参数修改为一个相对小的值。
综上所述，本申请所提供的Avalon总线转Axi4总线的方法，在Avalon总线为Avalon_st总线情况下，接收Avalon_st总线数据后直接对接收到的Avalon_st总线数据进行逻辑处理并输出相应的Axi4_st总线数据，从而实现Avalon_st总线向Axi4_st总线无延时的转换。另外，在Avalon总线为Avalon_mm总线情况下，将接收到Avalon_mm总线各通道传输的信号存入异步FIFO，并当Axi4总线对应的设备准备就绪时，从异步FIFO中读取信号并输出，从而达到跨时钟域的完成Avalon_mm总线向Axi4总线的转换。同时，跨平台设计时，可只规划Avalon总线，当需要Axi4总线时，采用本申请所提供的方法即可实现Avalon总线向Axi4总线的转换。并且，跨平台调用已有功能代码时，采用本申请所提供的方法实现Avalon总线向Axi4总线的转换，可以有效减少接口调试工作，提高开发效率，更高效的验证功能代码在多平台的性能。
本申请还提供了一种Avalon总线转Axi4总线的装置，下文描述的该装置可以与上文描述的方法相互对应参照。请参考图4所示，该装置包括：
Avalon_st总线转Axi4_st总线模块10，用于当Avalon总线为Avalon_st总线时，接收Avalon_st总线数据，并对接收到的所述Avalon_st总线数据进行逻辑处理后输出相应的Axi4_st总线数据；
Avalon_mm总线转Axi4总线模块20，用于当所述Avalon总线为Avalon_mm总线时，接收Avalon_mm总线各通道传输的信号并将所述信号组帧后存入异步FIFO，且当Axi4总线对应的设备准备就绪时，从所述异步FIFO中读取所述信号，并依据所述Axi4总线的时序关系将所述信号输出至所述Axi4总线的相应通道。
在上述实施例的基础上，可选的，Avalon_st总线转Axi4_st总线模块10具体用于将所述Avalon_st总线数据中的数据包结束标识、数据有效标识以及设备就绪状态标识的值赋值给Axi4_st总线的相应接口；将所述Avalon_st总线数据中的数据以字节为单位进行高低位逻辑取反后赋值给所述Axi4_st总线的相应接口；基于所述Avalon_st总线数据中的无效字节位置得到有效字节位置，并将所述有效字节位置的值赋值给所述Axi4_st总线的相应接口。
在上述实施例的基础上，可选的，还包括：
反馈模块，用于根据所述异步FIFO的深度参数以及已存储数据情况，输出waitrequest信号至所述Avalon_mm总线。
在上述实施例的基础上，可选的，还包括：
修改模块，用于修改所述异步FIFO的所述深度参数。
本申请还提供了一种Avalon总线转Axi4总线的设备，该设备包括存储器和处理器。其中存储器，用于存储计算机程序；处理器，用于执行计算机程序实现如下步骤：
当Avalon总线为Avalon_st总线时，接收Avalon_st总线数据，并对接收到的所述Avalon_st总线数据进行逻辑处理后输出相应的Axi4_st总线数据；当所述Avalon总线为Avalon_mm总线时，接收Avalon_mm总线各通道传输的信号并将所述信号组帧后存入异步FIFO，且当Axi4总线对应的设备准备就绪时，从所述异步FIFO中读取所述信号，并依据所述Axi4总线的时序关系将所述信号输出至所述Axi4总线的相应通道。
对于本申请所提供的设备的介绍请参照上述方法实施例，本申请在此不做赘述。
本申请还提供了一种计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，计算机程序被处理器执行时可实现如下步骤：
当Avalon总线为Avalon_st总线时，接收Avalon_st总线数据，并对接收到的所述Avalon_st总线数据进行逻辑处理后输出相应的Axi4_st总线数据；当所述Avalon总线为Avalon_mm总线时，接收Avalon_mm总线各通道传输 的信号并将所述信号组帧后存入异步FIFO，且当Axi4总线对应的设备准备就绪时，从所述异步FIFO中读取所述信号，并依据所述Axi4总线的时序关系将所述信号输出至所述Axi4总线的相应通道。
该计算机可读存储介质可以包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
对于本申请所提供的计算机可读存储介质的介绍请参照上述方法实施例，本申请在此不做赘述。
说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的装置、设备以及计算机可读存储介质而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
专业人员还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
结合本文中所公开的实施例描述的方法或算法的步骤可以直接用硬件、处理器执行的软件模块，或者二者的结合来实施。软件模块可以置于随机存储器(RAM)、内存、只读存储器(ROM)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、或技术领域内所公知的任意其它形式的存储介质中。
以上对本申请所提供的技术方案进行了详细介绍。本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想。应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以对本申请进行若干 改进和修饰，这些改进和修饰也落入本申请权利要求的保护范围。

Claims (10)

  1. 一种Avalon总线转Axi4总线的方法，其特征在于，包括：
    当Avalon总线为Avalon_st总线时，接收Avalon_st总线数据，并对接收到的所述Avalon_st总线数据进行逻辑处理后输出相应的Axi4_st总线数据；
    当所述Avalon总线为Avalon_mm总线时，接收Avalon_mm总线各通道传输的信号并将所述信号组帧后存入异步FIFO，且当Axi4总线对应的设备准备就绪时，从所述异步FIFO中读取所述信号，并依据所述Axi4总线的时序关系将所述信号输出至所述Axi4总线的相应通道。
  2. 根据权利要求1所述的Avalon总线转Axi4总线的方法，其特征在于，所述对接收到的所述Avalon_st总线数据进行逻辑处理后输出相应的Axi4_st总线数据，包括：
    将所述Avalon_st总线数据中的数据包结束标识、数据有效标识以及设备就绪状态标识的值赋值给Axi4_st总线的相应接口；
    将所述Avalon_st总线数据中的数据以字节为单位进行高低位逻辑取反后赋值给所述Axi4_st总线的相应接口；
    基于所述Avalon_st总线数据中的无效字节位置得到有效字节位置，并将所述有效字节位置的值赋值给所述Axi4_st总线的相应接口。
  3. 根据权利要求2所述的Avalon总线转Axi4总线的方法，其特征在于，所述Avalon_mm总线各通道传输的信号包括读指令、读地址以及猝发长度或写指令、写地址以及猝发长度或写指令、写数据以及猝发长度。
  4. 根据权利要求2所述的Avalon总线转Axi4总线的方法，其特征在于，还包括：
    根据所述异步FIFO的深度参数以及已存储数据情况，输出waitrequest信号至所述Avalon_mm总线。
  5. 根据权利要求4所述的Avalon总线转Axi4总线的方法，其特征在于，还包括：
    修改所述异步FIFO的所述深度参数。
  6. 一种Avalon总线转Axi4总线的装置，其特征在于，包括：
    Avalon_st总线转Axi4_st总线模块，用于当Avalon总线为Avalon_st总线时，接收Avalon_st总线数据，并对接收到的所述Avalon_st总线数据进行逻辑处理后输出相应的Axi4_st总线数据；
    Avalon_mm总线转Axi4总线模块，用于当所述Avalon总线为Avalon_mm总线时，接收Avalon_mm总线各通道传输的信号并将所述信号组帧后存入异步FIFO，且当Axi4总线对应的设备准备就绪时，从所述异步FIFO中读取所述信号，并依据所述Axi4总线的时序关系将所述信号输出至所述Axi4总线的相应通道。
  7. 根据权利要求6所述的Avalon总线转Axi4总线的装置，其特征在于，还包括：
    反馈模块，用于根据所述异步FIFO的深度参数以及已存储数据情况，输出waitrequest信号至所述Avalon_mm总线。
  8. 根据权利要求6所述的Avalon总线转Axi4总线的装置，其特征在于，还包括：
    修改模块，用于修改所述异步FIFO的所述深度参数。
  9. 一种Avalon总线转Axi4总线的设备，其特征在于，包括：
    存储器，用于存储计算机程序；
    处理器，用于执行所述计算机程序时实现如权利要求1至5任一项所述的Avalon总线转Axi4总线的方法的步骤。
  10. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至5任一项所述的Avalon总线转Axi4总线的方法的步骤。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111414325B (zh) * 2020-02-29 2021-09-17 苏州浪潮智能科技有限公司 一种Avalon总线转Axi4总线的方法
CN112162941B (zh) * 2020-09-29 2022-09-27 超越科技股份有限公司 一种NVMe固态存储***的实现方法及架构
CN112597086B (zh) * 2020-12-22 2023-12-19 北京时代民芯科技有限公司 一种基于AXI总线的RapidIO接口转换方法
CN115599717B (zh) * 2022-11-15 2023-03-10 浪潮电子信息产业股份有限公司 一种数据搬移方法、装置、设备及介质
CN117234977B (zh) * 2023-11-10 2024-02-27 浪潮电子信息产业股份有限公司 数据处理方法、***、设备及计算机可读存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103001827A (zh) * 2012-11-30 2013-03-27 无锡众志和达存储技术股份有限公司 基于万兆网卡的以太网包检验和fpga硬件校验方法
CN105183680A (zh) * 2015-09-18 2015-12-23 烽火通信科技股份有限公司 实现PCIe接口转CF卡接口的FPGA芯片及方法
US20190303317A1 (en) * 2013-06-07 2019-10-03 Altera Corporation Integrated circuit device with embedded programmable logic
CN111414325A (zh) * 2020-02-29 2020-07-14 苏州浪潮智能科技有限公司 一种Avalon总线转Axi4总线的方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102880427A (zh) * 2012-08-20 2013-01-16 北京奇作电子有限公司 一种基于fpga的sata主控制器
CN103744817B (zh) * 2013-10-08 2016-09-07 苏州智汇谱电子科技有限公司 用于Avalon总线向Crossbar总线的通讯转换桥设备及其通讯转换方法
CN104750644B (zh) * 2015-04-20 2017-11-03 哈尔滨工业大学 Dsp的emif读写时序与fpga的avalon读写时序的转换方法
WO2016191304A1 (en) * 2015-05-22 2016-12-01 Gray Research LLC Directional two-dimensional router and interconnection network for field programmable gate arrays, and other circuits, and applications of the router and network
US10019546B1 (en) * 2015-10-30 2018-07-10 Amazon Technologies, Inc. Modular system on chip configuration system
CN105279127B (zh) * 2015-11-25 2017-12-08 哈尔滨工业大学 一种基于PCI或PCIe总线的FPGA程序下载***及方法
US11301415B2 (en) * 2018-01-04 2022-04-12 Intel Corporation Interface discovery between partitions of a programmable logic device
CN110196824B (zh) * 2018-05-31 2022-12-09 腾讯科技（深圳）有限公司 实现数据传输的方法及装置、电子设备
US11580054B2 (en) * 2018-08-24 2023-02-14 Intel Corporation Scalable network-on-chip for high-bandwidth memory
CN208820795U (zh) * 2018-11-27 2019-05-03 威海威高生物科技有限公司 基于自反馈的eth-can通讯前端检测装置
US10833679B2 (en) * 2018-12-28 2020-11-10 Intel Corporation Multi-purpose interface for configuration data and user fabric data
US11036660B2 (en) * 2019-03-28 2021-06-15 Intel Corporation Network-on-chip for inter-die and intra-die communication in modularized integrated circuit devices
CN110399317B (zh) * 2019-07-15 2020-12-25 西安微电子技术研究所 一种嵌入式***的软件自适应的多功能控制器
CN110545158B (zh) * 2019-07-23 2022-05-10 国网福建省电力有限公司 一种光数字测试仪多种接口的虚拟化与自适应通信***及其通信方法
CN110545319A (zh) * 2019-08-23 2019-12-06 武汉久同智能科技有限公司 一种SoC核***的设计和核间任务通信的实现方法
CN110704351A (zh) * 2019-09-24 2020-01-17 山东华芯半导体有限公司 基于axi总线的主机设备数据传输扩展方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103001827A (zh) * 2012-11-30 2013-03-27 无锡众志和达存储技术股份有限公司 基于万兆网卡的以太网包检验和fpga硬件校验方法
US20190303317A1 (en) * 2013-06-07 2019-10-03 Altera Corporation Integrated circuit device with embedded programmable logic
CN105183680A (zh) * 2015-09-18 2015-12-23 烽火通信科技股份有限公司 实现PCIe接口转CF卡接口的FPGA芯片及方法
CN111414325A (zh) * 2020-02-29 2020-07-14 苏州浪潮智能科技有限公司 一种Avalon总线转Axi4总线的方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4050491A4

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