WO2020224137A1

WO2020224137A1 - Drive circuit

Info

Publication number: WO2020224137A1
Application number: PCT/CN2019/104321
Authority: WO
Inventors: 宋乔乔
Original assignee: 深圳市华星光电半导体显示技术有限公司
Priority date: 2019-05-07
Filing date: 2019-09-04
Publication date: 2020-11-12
Also published as: CN110010055A

Abstract

A drive circuit. A pull-up control module (10) is configured to pull a predetermined node (Q(N)) up to a high potential; a pull-up module (20) is configured to output an Nth-level gate drive signal; a pull-down module (60) is configured to reset the predetermined node (Q(N)) and the Nth-level gate drive signal output end (G(N)) to a low potential; a pull-down holding module is configured to hold the waveform stability of signals in the predetermined node (Q(N)) and the Nth-level gate drive signal output end (G(N)), so that the stability of transistors in the drive circuit can be improved.

Description

驱动电路Drive circuit

技术领域Technical field

本发明涉及显示面板的驱动技术领域，特别涉及一种驱动电路。The present invention relates to the technical field of driving display panels, and in particular to a driving circuit.

背景技术Background technique

传统的驱动电路一般包括多个级联的子电路，每一子电路与显示面板的一扫描线电性连接，该子电路用于产生栅极驱动信号，并通过该扫描线向显示面板的一像素行发送该栅极驱动信号。A conventional driving circuit generally includes a plurality of cascaded sub-circuits, and each sub-circuit is electrically connected to a scan line of the display panel. The sub-circuit is used to generate a gate driving signal and send it to a scan line of the display panel. The pixel row sends the gate drive signal.

在实践中，发明人发现现有技术至少存在以下问题：In practice, the inventor found that the prior art has at least the following problems:

子电路中的部分晶体管会出现栅极和源极之间的电压差过大或漏极和源极之间的电压差过大的问题，而栅极和源极之间的电压差过大或漏极和源极之间的电压差过大会导致晶体管的内部电压压力过高，影响了晶体管的稳定性。Some transistors in the sub-circuit will have too much voltage difference between the gate and source or the voltage difference between the drain and source is too large, and the voltage difference between the gate and the source is too large or The excessive voltage difference between the drain and the source causes the internal voltage pressure of the transistor to be too high, which affects the stability of the transistor.

故，有必要提出一种新的技术方案，以解决上述技术问题。Therefore, it is necessary to propose a new technical solution to solve the above technical problems.

技术问题technical problem

本发明的目的在于提供一种驱动电路，其能提高驱动电路内的晶体管的稳定性。The object of the present invention is to provide a driving circuit which can improve the stability of the transistors in the driving circuit.

技术解决方案Technical solutions

为解决上述问题，本发明的技术方案如下：To solve the above problems, the technical solution of the present invention is as follows:

一种驱动电路，所述驱动电路包括至少两栅极驱动单元电路，至少两所述栅极驱动单元电路以级联的方式电性连接；至少两所述栅极驱动单元电路中的第N级栅极驱动单元电路包括上拉控制模块、上拉模块、下拉模块、下拉维持模块，所述上拉控制模块、所述上拉模块、所述下拉模块、所述下拉维持模块中的任意两者电性连接，其中，N为大于0的整数；所述上拉控制模块用于将所述第N级栅极驱动单元电路中的预定节点拉升至高电位；所述上拉模块用于通过所述第N级栅极驱动单元电路的第N级栅极驱动信号输出端输出第N级栅极驱动信号；所述下拉模块用于将所述第N级栅极驱动单元电路的所述预定节点和第N级栅极驱动信号输出端重新设定至低电位；所述下拉维持模块用于维持所述预定节点和第N级栅极驱动信号输出端中的信号的波形稳定性；所述上拉控制模块包括第一晶体管，所述第一晶体管的第一极与第N-2级栅极驱动信号输出端电性连接，所述第一晶体管的第二极与第N-2级起始信号输出端电性连接，所述第一晶体管的第三极与预定节点电性连接；其中，所述预定节点位于所述第一晶体管的第三极与上拉模块的第二晶体管的第一极之间；所述第N级栅极驱动单元电路还包括重置模块，所述重置模块与所述上拉控制模块、所述上拉模块、所述下拉模块、所述下拉维持模块均电性连接，所述重置模块用于重置所述第N级栅极驱动单元电路。A driving circuit, the driving circuit includes at least two gate driving unit circuits, at least two of the gate driving unit circuits are electrically connected in a cascade connection; at least two of the gate driving unit circuits are in the Nth stage The gate drive unit circuit includes a pull-up control module, a pull-up module, a pull-down module, a pull-down maintenance module, and any two of the pull-up control module, the pull-up module, the pull-down module, and the pull-down maintenance module Are electrically connected, wherein N is an integer greater than 0; the pull-up control module is used to pull a predetermined node in the N-th stage gate drive unit circuit to a high potential; the pull-up module is used to pass all The Nth stage gate drive signal output terminal of the Nth stage gate drive unit circuit outputs the Nth stage gate drive signal; the pull-down module is used to connect the predetermined node of the Nth stage gate drive unit circuit And the Nth gate drive signal output terminal is reset to a low level; the pull-down maintenance module is used to maintain the predetermined node and the signal waveform stability of the Nth gate drive signal output terminal; the upper The pull control module includes a first transistor, the first pole of the first transistor is electrically connected to the N-2th stage gate drive signal output terminal, and the second pole of the first transistor is connected to the N-2th stage start The signal output terminal is electrically connected, and the third electrode of the first transistor is electrically connected to a predetermined node; wherein, the predetermined node is located between the third electrode of the first transistor and the first transistor of the second transistor of the pull-up module. Between the poles; the Nth stage gate drive unit circuit also includes a reset module, the reset module and the pull-up control module, the pull-up module, the pull-down module, the pull-down maintenance module are all Electrically connected, the reset module is used to reset the Nth stage gate driving unit circuit.

在上述驱动电路中，所述第N级栅极驱动单元电路还包括交流信号输入端和时钟信号输入端；所述上拉模块包括第二晶体管、第三晶体管和电容，所述第二晶体管的第一极与所述预定节点、所述第三晶体管的第一极以及所述电容的第一极板电性连接，所述第二晶体管的第二极与所述交流信号输入端电性连接，所述第二晶体管的第三极与第N级起始信号输出端电性连接，所述第三晶体管的第二极与所述时钟信号输入端电性连接，所述第三晶体管的第三极与所述下拉模块的第十八晶体管的第二极电性连接，所述电容的第二极与第N级栅极驱动信号输出端电性连接。In the above-mentioned driving circuit, the N-th stage gate driving unit circuit further includes an AC signal input terminal and a clock signal input terminal; the pull-up module includes a second transistor, a third transistor, and a capacitor. The first electrode is electrically connected to the predetermined node, the first electrode of the third transistor, and the first plate of the capacitor, and the second electrode of the second transistor is electrically connected to the AC signal input terminal , The third electrode of the second transistor is electrically connected to the N-th stage start signal output terminal, the second electrode of the third transistor is electrically connected to the clock signal input terminal, and the third electrode of the third transistor is electrically connected to the clock signal input terminal. The three poles are electrically connected to the second pole of the eighteenth transistor of the pull-down module, and the second pole of the capacitor is electrically connected to the N-th stage gate drive signal output terminal.

在上述驱动电路中，所述交流信号输入端所传输的交流信号的低电位电压等于所述时钟信号输入端所传输的时钟信号的低电位电压；所述交流信号输入端所传输的交流信号的高电位电压低于所述时钟信号输入端所传输的时钟信号的高电位电压；所述交流信号输入端所传输的交流信号的频率和周期分别与所述时钟信号输入端所传输的时钟信号的频率和周期相同。In the above driving circuit, the low potential voltage of the AC signal transmitted by the AC signal input terminal is equal to the low potential voltage of the clock signal transmitted by the clock signal input terminal; The high potential voltage is lower than the high potential voltage of the clock signal transmitted by the clock signal input terminal; the frequency and period of the AC signal transmitted by the AC signal input terminal are respectively the same as those of the clock signal transmitted by the clock signal input terminal. The frequency and period are the same.

在上述驱动电路中，所述交流信号的高电位电压为15V，所述时钟信号的高电位电压为28V。In the above driving circuit, the high potential voltage of the AC signal is 15V, and the high potential voltage of the clock signal is 28V.

在上述驱动电路中，所述第N级栅极驱动单元电路还包括直流低电位信号输入端；所述下拉模块包括第十七晶体管和第十八晶体管，所述第十七晶体管的第一极、所述第十八晶体管的第一极均与第N+2级栅极驱动信号输出端电性连接，所述第十七晶体管的第二极与所述预定节点电性连接，所述第十七晶体管的第二极、第十八晶体管的第三极均与所述直流低电位信号输入端电性连接。In the above driving circuit, the Nth stage gate driving unit circuit further includes a DC low-potential signal input terminal; the pull-down module includes a seventeenth transistor and an eighteenth transistor, and the first pole of the seventeenth transistor , The first pole of the eighteenth transistor is electrically connected to the N+2 stage gate drive signal output terminal, the second pole of the seventeenth transistor is electrically connected to the predetermined node, and the The second pole of the seventeenth transistor and the third pole of the eighteenth transistor are electrically connected to the DC low-potential signal input terminal.

一种驱动电路，所述驱动电路包括至少两栅极驱动单元电路，至少两所述栅极驱动单元电路以级联的方式电性连接；至少两所述栅极驱动单元电路中的第N级栅极驱动单元电路包括上拉控制模块、上拉模块、下拉模块、下拉维持模块，所述上拉控制模块、所述上拉模块、所述下拉模块、所述下拉维持模块中的任意两者电性连接，其中，N为大于0的整数；所述上拉控制模块用于将所述第N级栅极驱动单元电路中的预定节点拉升至高电位；所述上拉模块用于通过所述第N级栅极驱动单元电路的第N级栅极驱动信号输出端输出第N级栅极驱动信号；所述下拉模块用于将所述第N级栅极驱动单元电路的所述预定节点和第N级栅极驱动信号输出端重新设定至低电位；所述下拉维持模块用于维持所述预定节点和第N级栅极驱动信号输出端中的信号的波形稳定性。A driving circuit, the driving circuit includes at least two gate driving unit circuits, at least two of the gate driving unit circuits are electrically connected in a cascade connection; at least two of the gate driving unit circuits are in the Nth stage The gate drive unit circuit includes a pull-up control module, a pull-up module, a pull-down module, a pull-down maintenance module, and any two of the pull-up control module, the pull-up module, the pull-down module, and the pull-down maintenance module Are electrically connected, wherein N is an integer greater than 0; the pull-up control module is used to pull a predetermined node in the N-th stage gate drive unit circuit to a high potential; the pull-up module is used to pass all The Nth stage gate drive signal output terminal of the Nth stage gate drive unit circuit outputs the Nth stage gate drive signal; the pull-down module is used to connect the predetermined node of the Nth stage gate drive unit circuit And the Nth stage gate drive signal output terminal is reset to a low level; the pull-down maintenance module is used to maintain the predetermined node and the signal waveform stability of the N stage gate drive signal output terminal.

在上述驱动电路中，所述上拉控制模块包括第一晶体管，所述第一晶体管的第一极与第N-2级栅极驱动信号输出端电性连接，所述第一晶体管的第二极与第N-2级起始信号输出端电性连接，所述第一晶体管的第三极与预定节点电性连接；其中，所述预定节点位于所述第一晶体管的第三极与上拉模块的第二晶体管的第一极之间。In the above driving circuit, the pull-up control module includes a first transistor, a first pole of the first transistor is electrically connected to the N-2th stage gate drive signal output terminal, and a second transistor of the first transistor The electrode is electrically connected to the N-2th stage start signal output terminal, and the third electrode of the first transistor is electrically connected to a predetermined node; wherein, the predetermined node is located on the third electrode of the first transistor and Pull the module between the first pole of the second transistor.

在上述驱动电路中，所述交流信号输入端所传输的交流信号的低电位电压等于所述时钟信号输入端所传输的时钟信号的低电位电压；In the above driving circuit, the low-potential voltage of the AC signal transmitted by the AC signal input terminal is equal to the low-potential voltage of the clock signal transmitted by the clock signal input terminal;

所述交流信号输入端所传输的交流信号的高电位电压低于所述时钟信号输入端所传输的时钟信号的高电位电压；所述交流信号输入端所传输的交流信号的频率和周期分别与所述时钟信号输入端所传输的时钟信号的频率和周期相同。The high potential voltage of the AC signal transmitted by the AC signal input terminal is lower than the high potential voltage of the clock signal transmitted by the clock signal input terminal; the frequency and period of the AC signal transmitted by the AC signal input terminal are respectively equal to The frequency and period of the clock signal transmitted by the clock signal input terminal are the same.

在上述驱动电路中，所述下拉维持模块包括第一下拉维持子模块和第二下拉维持子模块，所述第一下拉维持子模块和所述第二下拉维持子模块电性连接，并且，所述第一下拉维持子模块和所述第二下拉维持子模块与所述上拉控制模块、所述上拉模块、所述下拉模块中的任意两者电性连接；所述第一下拉维持子模块用于在第一时间段维持所述预定节点和第N级栅极驱动信号输出端中的信号的波形稳定性；所述第二下拉维持子模块用于在与所述第一时间段不同的第二时间段维持所述预定节点和第N级栅极驱动信号输出端中的信号的波形稳定性。In the above driving circuit, the pull-down maintenance module includes a first pull-down maintenance sub-module and a second pull-down maintenance sub-module, the first pull-down maintenance sub-module and the second pull-down maintenance sub-module are electrically connected, and , The first pull-down maintaining sub-module and the second pull-down maintaining sub-module are electrically connected to any two of the pull-up control module, the pull-up module, and the pull-down module; the first The pull-down maintenance sub-module is used to maintain the predetermined node and the waveform stability of the signal in the N-th stage gate drive signal output terminal during the first time period; the second pull-down maintenance sub-module is used to A second time period with a different time period maintains the waveform stability of the signal at the predetermined node and the Nth stage gate drive signal output terminal.

在上述驱动电路中，所述第N级栅极驱动单元电路还包括第一控制信号输入端和第二控制信号输入端，所述第一控制信号输入端与所述第一下拉维持子模块电性连接，所述第二控制信号输入端与所述第二下拉维持子模块电性连接；所述第一控制信号和所述第二控制信号相位相差1/2周期，所述第一控制信号和所述第二控制信号用于交替地驱动所述第一下拉维持子模块和所述第二下拉维持子模块。In the above driving circuit, the N-th stage gate driving unit circuit further includes a first control signal input terminal and a second control signal input terminal, the first control signal input terminal and the first pull-down sustaining sub-module Electrically connected, the second control signal input terminal is electrically connected to the second pull-down maintenance sub-module; the first control signal and the second control signal have a phase difference of 1/2 period, the first control signal The signal and the second control signal are used to alternately drive the first pull-down maintenance sub-module and the second pull-down maintenance sub-module.

在上述驱动电路中，所述第一控制信号输入端所提供的第一控制信号和所述第二控制信号输入端所提供的第二控制信号均是周期为200倍帧周期，占空比为1/2的信号。In the above-mentioned driving circuit, the first control signal provided by the first control signal input terminal and the second control signal provided by the second control signal input terminal have a period of 200 times the frame period, and the duty cycle is 1/2 signal.

在上述驱动电路中，所述第一下拉维持子模块包括第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管和第十晶体管，所述第五晶体管的第一极和第二极均与第一控制信号输入端和所述第六晶体管的第二极电性连接，所述第五晶体管的第三极与所述第六晶体管的第一极、所述第七晶体管的第二极电性连接，所述第六晶体管的第三极与所述第八晶体管的第二极、所述第九晶体管的第一极和所述第十晶体管的第一极电性连接，所述第七晶体管的第一极与第一晶体管的第三极、所述第八晶体管的第一极电性连接，所述第七晶体管的第三极、所述第八晶体管的第三极、所述第九晶体管的第三极和所述第十晶体管的第三极均与直流低电位信号输入端电性连接，所述第九晶体管的第二极与第N级栅极驱动信号输出端电性连接，所述第十晶体管的第二极与所述预定节点电性连接。In the above driving circuit, the first pull-down sustaining sub-module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor. The first electrode of the fifth transistor is The second pole is electrically connected to the first control signal input terminal and the second pole of the sixth transistor, and the third pole of the fifth transistor is connected to the first pole of the sixth transistor and the seventh transistor. The second electrode of the sixth transistor is electrically connected, and the third electrode of the sixth transistor is electrically connected to the second electrode of the eighth transistor, the first electrode of the ninth transistor, and the first electrode of the tenth transistor. , The first pole of the seventh transistor is electrically connected to the third pole of the first transistor and the first pole of the eighth transistor. The third pole of the seventh transistor and the third pole of the eighth transistor are electrically connected. The third electrode of the ninth transistor and the third electrode of the tenth transistor are all electrically connected to the DC low-potential signal input terminal, and the second electrode of the ninth transistor is connected to the Nth gate drive signal The output terminal is electrically connected, and the second electrode of the tenth transistor is electrically connected to the predetermined node.

在上述驱动电路中，所述第二下拉维持子模块包括第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第十六晶体管，所述第十一晶体管的第二极与第二控制信号输入端电性连接，所述第十二晶体管的第一极、第二极均与第二控制信号输入端电性连接，所述第十二晶体管的第三极与所述第十一晶体管的第一极、所述第十六晶体管的第二极电性连接，所述第十一晶体管的第三极与所述第十三晶体管的第一极、所述第十四晶体管的第一极以及第十五晶体管的第二极电性连接，所述第十三晶体管的第二极与所述预定节点电性连接，所述第十三晶体管的第三极、所述第十四晶体管的第三极、所述第十五晶体管的第三极以及所述第十六晶体管的第三极均与直流低电位信号输入端电性连接，所述第十四晶体管的第二极与第N级栅极驱动信号输出端电性连接，所述第十五晶体管的第一极与所述第十六晶体管的第一极、第一晶体管的第三极电性连接。In the above driving circuit, the second pull-down sustaining sub-module includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor. The second electrode of the transistor is electrically connected to the second control signal input terminal, the first electrode and the second electrode of the twelfth transistor are electrically connected to the second control signal input terminal, and the second electrode of the twelfth transistor is electrically connected to the second control signal input terminal. The three poles are electrically connected to the first pole of the eleventh transistor and the second pole of the sixteenth transistor. The third pole of the eleventh transistor is electrically connected to the first pole of the thirteenth transistor. The first electrode of the fourteenth transistor and the second electrode of the fifteenth transistor are electrically connected, the second electrode of the thirteenth transistor is electrically connected to the predetermined node, and the first electrode of the thirteenth transistor is electrically connected. The three poles, the third pole of the fourteenth transistor, the third pole of the fifteenth transistor, and the third pole of the sixteenth transistor are all electrically connected to the DC low-potential signal input terminal. The second electrode of the fourteenth transistor is electrically connected to the N-th stage gate drive signal output terminal, and the first electrode of the fifteenth transistor is connected to the first electrode of the sixteenth transistor and the third electrode of the first transistor. Electrical connection.

在上述驱动电路中，第N级栅极驱动单元电路还包括重置模块，所述重置模块与所述上拉控制模块、所述上拉模块、所述下拉模块、所述下拉维持模块均电性连接，所述重置模块用于重置所述第N级栅极驱动单元电路。In the above-mentioned driving circuit, the Nth stage gate driving unit circuit further includes a reset module, and the reset module and the pull-up control module, the pull-up module, the pull-down module, and the pull-down maintenance module are all Electrically connected, the reset module is used to reset the Nth stage gate driving unit circuit.

在上述驱动电路中，所述第N级栅极驱动单元电路还包括重置信号输入端；所述重置模块包括第四晶体管，所述第四晶体管的第一极与所述重置信号输入端电性连接，所述第四晶体管的第二极与所述预定节点电性连接，所述第四晶体管的第三极与直流低电位信号输入端、所述下拉维持模块中的第一下拉维持子模块的第七晶体管的第三极电性连接。In the above driving circuit, the Nth stage gate driving unit circuit further includes a reset signal input terminal; the reset module includes a fourth transistor, and the first electrode of the fourth transistor is connected to the reset signal input terminal. The second electrode of the fourth transistor is electrically connected to the predetermined node, the third electrode of the fourth transistor is electrically connected to the DC low-potential signal input terminal, and the first lower electrode of the pull-down maintaining module is electrically connected. Pull to maintain the electrical connection of the third electrode of the seventh transistor of the sub-module.

在上述驱动电路中，所述第四晶体管用于在所述重置信号输入端所提供的重置信号为高电平时开启，以使所述预定节点的电位通过直流低电位信号输入端所提供的信号恢复至低电位。In the above driving circuit, the fourth transistor is used to turn on when the reset signal provided by the reset signal input terminal is at a high level, so that the potential of the predetermined node is provided by the DC low potential signal input terminal The signal returns to a low level.

在上述驱动电路中，所述驱动电路还包括时钟信号生成电路和交流信号生成电路；所述时钟信号生成电路用于生成M个不同的时钟信号，M个不同的时钟信号分别通过M个不同的时钟信号输入端与M个不同的栅极驱动单元电路电性连接；所述交流信号生成电路用于生成M个不同的交流信号，M个不同的交流信号分别通过M个不同的交流信号输入端与M个不同的栅极驱动单元电路电性连接；其中，M为正整数。In the above driving circuit, the driving circuit further includes a clock signal generating circuit and an AC signal generating circuit; the clock signal generating circuit is used to generate M different clock signals, and the M different clock signals pass through M different clock signals. The clock signal input terminal is electrically connected to M different gate drive unit circuits; the AC signal generating circuit is used to generate M different AC signals, and the M different AC signals pass through M different AC signal input terminals respectively It is electrically connected to M different gate driving unit circuits; where M is a positive integer.

有益效果Beneficial effect

在本发明中，由于所述第二晶体管的第二极与交流信号输入端电性连接，在所述第二晶体管开启时，所述交流信号输入端所提供的交流信号通过所述第二晶体管从第N-2级起始信号输出端输出，第N-2级起始信号输出端所输出的起始信号输入至第N级栅极驱动单元电路中，所述交流信号的高电位电压低于时钟信号的高电位电压，因此，当所述第三晶体管开启时，所述第三晶体管的栅极和源极之间的电压差Vgs=48V，与传统技术相比，降低了约12伏；在所述第十七晶体管开启时，所述第十七晶体管的漏极和源极之间的电压差Vds=37V，与传统技术相比，降低了约11伏。因此，本发明的技术方案降低了驱动电路内的部分晶体管（例如所述第三晶体管和所述第十七晶体管）的电压压力，避免这些晶体管出现阈值电压偏移的情况，提升了这些晶体管的稳定性，延长了驱动电路及与驱动电路搭配使用的显示面板的使用寿命。In the present invention, since the second electrode of the second transistor is electrically connected to the AC signal input terminal, when the second transistor is turned on, the AC signal provided by the AC signal input terminal passes through the second transistor It is output from the N-2th stage start signal output terminal, and the start signal output from the N-2th stage start signal output terminal is input to the Nth stage gate drive unit circuit. The high potential voltage of the AC signal is low Because of the high potential voltage of the clock signal, when the third transistor is turned on, the voltage difference between the gate and source of the third transistor Vgs=48V, which is about 12 volts lower than the conventional technology When the seventeenth transistor is turned on, the voltage difference between the drain and the source of the seventeenth transistor Vds=37V, which is about 11 volts lower than the conventional technology. Therefore, the technical solution of the present invention reduces the voltage pressure of some transistors in the driving circuit (such as the third transistor and the seventeenth transistor), avoids the threshold voltage shift of these transistors, and improves the performance of these transistors. The stability extends the service life of the driving circuit and the display panel used with the driving circuit.

附图说明Description of the drawings

图1为本发明的驱动电路中的第N级栅极驱动单元电路的示意图；FIG. 1 is a schematic diagram of the Nth stage gate driving unit circuit in the driving circuit of the present invention;

图2为本发明的驱动电路中第N级栅极驱动单元电路的时钟信号、交流信号、第N级栅极驱动信号输出端中的信号、控制信号输入端的控制信号的波形图；2 is a waveform diagram of a clock signal, an AC signal, a signal at the output terminal of the N-th gate drive signal, and a control signal at the control signal input terminal of the N-th gate drive unit circuit in the drive circuit of the present invention;

图3为本发明的驱动电路中的第N级栅极驱动单元电路的时钟信号、第N级栅极驱动信号输出端中的信号、以及预定节点中的信号的波形图。3 is a waveform diagram of the clock signal of the gate drive unit circuit of the Nth stage, the signal in the output terminal of the gate drive signal of the Nth stage, and the signal in the predetermined node in the driving circuit of the present invention.

本发明的实施方式Embodiments of the invention

本说明书所使用的词语“实施例”意指实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为“一个或多个”，除非另外指定或从上下文可以清楚确定单数形式。The word "embodiment" used in this specification means an example, example, or illustration. In addition, the article "a" used in this specification and appended claims can generally be construed as "one or more" unless otherwise specified or the singular form can be clearly determined from the context.

本发明的驱动电路用于向显示面板的像素单元提供栅极驱动信号。所述显示面板可以是TFT-LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示面板）、OLED（Organic Light Emitting Diode，有机发光二极管显示面板）等。The driving circuit of the present invention is used to provide gate driving signals to the pixel units of the display panel. The display panel may be TFT-LCD (Thin Film Transistor Liquid Crystal Display), OLED (Organic Light Crystal Display) Emitting Diode, organic light emitting diode display panel) etc.

所述驱动电路包括至少两栅极驱动单元电路，至少两所述栅极驱动单元电路以级联的方式电性连接。每一所述栅极驱动单元电路与所述显示面板中的一扫描线电性连接，以通过所述扫描线向所述显示面板中的一行像素单元提供所述栅极驱动信号。The driving circuit includes at least two gate driving unit circuits, and at least two of the gate driving unit circuits are electrically connected in a cascade connection. Each of the gate driving unit circuits is electrically connected to a scan line in the display panel to provide the gate driving signal to a row of pixel units in the display panel through the scan line.

至少两所述栅极驱动单元电路中的第N级栅极驱动单元电路包括上拉控制模块10、上拉模块20、下拉模块60、下拉维持模块，所述上拉控制模块10、所述上拉模块20、所述下拉模块60、所述下拉维持模块中的任意两者电性连接，如图1所示，其中，N为大于0的整数。At least two of the gate drive unit circuits of the Nth stage include a pull-up control module 10, a pull-up module 20, a pull-down module 60, a pull-down maintenance module, the pull-up control module 10, the pull-up module Any two of the pull module 20, the pull module 60, and the pull maintenance module are electrically connected, as shown in FIG. 1, where N is an integer greater than zero.

所述上拉控制模块10用于将所述第N级栅极驱动单元电路中的预定节点Q(N)拉升至高电位。The pull-up control module 10 is used to pull the predetermined node Q(N) in the N-th gate driving unit circuit to a high potential.

所述上拉模块20用于通过所述第N级栅极驱动单元电路的第N级栅极驱动信号输出端G(N)输出第N级栅极驱动信号。The pull-up module 20 is used to output the Nth stage gate drive signal through the Nth stage gate drive signal output terminal G(N) of the Nth stage gate drive unit circuit.

所述下拉模块60用于将所述第N级栅极驱动单元电路的所述预定节点Q(N)和第N级栅极驱动信号输出端G(N)重新设定至低电位。The pull-down module 60 is used to reset the predetermined node Q(N) of the Nth stage gate drive unit circuit and the Nth stage gate drive signal output terminal G(N) to a low level.

所述下拉维持模块用于维持所述预定节点Q(N)和第N级栅极驱动信号输出端G(N)中的信号的波形稳定性。The pull-down maintaining module is used to maintain the waveform stability of the signal in the predetermined node Q(N) and the Nth gate drive signal output terminal G(N).

所述上拉控制模块10包括第一晶体管101，所述第一晶体管101的第一极与第N-2级栅极驱动信号输出端G(N-2)电性连接，所述第一晶体管101的第二极与第N-2级起始信号输出端ST(N-2)电性连接，所述第一晶体管101的第三极与预定节点Q(N)、所述重置模块30的第四晶体管301的第二极电性连接。The pull-up control module 10 includes a first transistor 101, a first pole of the first transistor 101 is electrically connected to the N-2th stage gate drive signal output terminal G(N-2), and the first transistor The second pole of 101 is electrically connected to the N-2th stage start signal output terminal ST(N-2), the third pole of the first transistor 101 is connected to the predetermined node Q(N), and the reset module 30 The second electrode of the fourth transistor 301 is electrically connected.

其中，所述预定节点Q(N)位于所述第一晶体管101的第三极与上拉模块20的第二晶体管201的第一极之间。The predetermined node Q(N) is located between the third pole of the first transistor 101 and the first pole of the second transistor 201 of the pull-up module 20.

所述驱动电路还包括时钟信号生成电路和交流信号生成电路，所述时钟信号生成电路用于生成M个不同的时钟信号，M个不同的时钟信号分别通过M个不同的时钟信号输入端与M个不同的栅极驱动单元电路电性连接。同样，所述交流信号生成电路用于生成M个不同的交流信号，M个不同的交流信号分别通过M个不同的交流信号输入端与M个不同的栅极驱动单元电路电性连接。The driving circuit also includes a clock signal generating circuit and an AC signal generating circuit. The clock signal generating circuit is used to generate M different clock signals, and the M different clock signals pass through M different clock signal input terminals and M Different gate drive unit circuits are electrically connected. Similarly, the AC signal generating circuit is used to generate M different AC signals, and the M different AC signals are electrically connected to M different gate drive unit circuits through M different AC signal input terminals, respectively.

所述上拉模块20包括第二晶体管201、第三晶体管202和电容203，所述第二晶体管201的第一极与所述预定节点Q(N)、所述第三晶体管203的第一极以及所述电容203的第一极板电性连接，所述第二晶体管201的第二极与交流信号输入端STX(M)电性连接，所述第二晶体管201的第三极与第N级起始信号输出端ST(N)电性连接，所述第三晶体管202的第二极与时钟信号输入端CK(M)电性连接，所述第三晶体管202的第三极与所述下拉模块60的第十八晶体管602的第二极电性连接，所述电容的第二极与第N级栅极驱动信号输出端G(N)电性连接。其中，所述第N级栅极驱动信号输出端G(N)与所述显示面板的扫描线电性连接。第N级起始信号输出端ST(N)所提供的第N级起始信号是用于开启所述第N级栅极驱动单元电路的起始信号。其中，M为正整数；且1≤M≤4，或者，1≤M≤6，或者，1≤M≤8。The pull-up module 20 includes a second transistor 201, a third transistor 202, and a capacitor 203. The first electrode of the second transistor 201 is connected to the predetermined node Q(N) and the first electrode of the third transistor 203. And the first electrode of the capacitor 203 is electrically connected, the second electrode of the second transistor 201 is electrically connected to the AC signal input terminal STX(M), and the third electrode of the second transistor 201 is electrically connected to the Nth electrode. The stage start signal output terminal ST(N) is electrically connected, the second electrode of the third transistor 202 is electrically connected to the clock signal input terminal CK(M), and the third electrode of the third transistor 202 is electrically connected to the The second electrode of the eighteenth transistor 602 of the pull-down module 60 is electrically connected, and the second electrode of the capacitor is electrically connected to the N-th stage gate drive signal output terminal G(N). Wherein, the gate drive signal output terminal G(N) of the Nth stage is electrically connected to the scan line of the display panel. The Nth stage start signal provided by the Nth stage start signal output terminal ST(N) is a start signal for turning on the Nth stage gate drive unit circuit. Wherein, M is a positive integer; and 1≤M≤4, or, 1≤M≤6, or, 1≤M≤8.

如图2所示，在M=4的情况下，M个不同的时钟信号依次相差四分之一个时钟信号周期。同样，在M=4的情况下，M个不同的交流信号依次相差四分之一个交流信号周期。相邻四个栅极驱动单元电路所输出的栅极驱动信号依次相差四分之一个栅极驱动信号周期。As shown in Fig. 2, in the case of M=4, the M different clock signals differ in sequence by a quarter of the clock signal period. Similarly, in the case of M=4, M different AC signals differ in sequence by a quarter of the AC signal cycle. The gate drive signals output by the four adjacent gate drive unit circuits are sequentially different by a quarter of the gate drive signal period.

交流信号输入端STX(M)所传输的交流信号的低电位电压等于时钟信号输入端CK(M)所传输的时钟信号的低电位电压。此处所述的“等于”是指所述交流信号的低电位电压与所述时钟信号的低电位电压在数值上相等或者两者的差值的绝对值与所述时钟信号的低电位电压的数值的比例小于或等于5%。The low potential voltage of the AC signal transmitted by the AC signal input terminal STX(M) is equal to the low potential voltage of the clock signal transmitted by the clock signal input terminal CK(M). The "equal to" mentioned here means that the low-potential voltage of the AC signal and the low-potential voltage of the clock signal are equal in value or the absolute value of the difference between the two and the low-potential voltage of the clock signal The ratio of the value is less than or equal to 5%.

交流信号输入端STX(M)所传输的交流信号的高电位电压低于时钟信号输入端CK(M)所传输的时钟信号的高电位电压。所述交流信号的高电位电压可例如为15V。所述时钟信号的高电位电压可例如为28V。The high potential voltage of the AC signal transmitted by the AC signal input terminal STX (M) is lower than the high potential voltage of the clock signal transmitted by the clock signal input terminal CK (M). The high potential voltage of the AC signal may be 15V, for example. The high potential voltage of the clock signal may be 28V, for example.

所述交流信号是一组时序信号，所述交流信号的频率和周期分别与时钟信号输入端CK(M)所传输的时钟信号的频率和周期相同。即，所述交流信号与所述时钟信号的波形相似，只是所述交流信号的高电位电压比所述时钟信号的高电位电压更低。The AC signal is a set of timing signals, and the frequency and period of the AC signal are respectively the same as the frequency and period of the clock signal transmitted by the clock signal input terminal CK(M). That is, the waveforms of the AC signal and the clock signal are similar, except that the high potential voltage of the AC signal is lower than the high potential voltage of the clock signal.

所述下拉模块60包括第十七晶体管601和第十八晶体管602，所述第十七晶体管601的第一极、所述第十八晶体管602的第一极均与第N+2级栅极驱动信号输出端G(N+2)电性连接，所述第十七晶体管601的第二极与所述预定节点Q(N)电性连接，所述第十七晶体管601的第二极、第十八晶体管602的第三极均与直流低电位信号输入端VSS电性连接。所述直流低电位信号输入端VSS所提供的信号是直流低电位信号。The pull-down module 60 includes a seventeenth transistor 601 and an eighteenth transistor 602. The first pole of the seventeenth transistor 601 and the first pole of the eighteenth transistor 602 are both connected to the gate of the N+2 stage. The driving signal output terminal G(N+2) is electrically connected, the second electrode of the seventeenth transistor 601 is electrically connected to the predetermined node Q(N), and the second electrode of the seventeenth transistor 601 is electrically connected to The third pole of the eighteenth transistor 602 is electrically connected to the DC low-potential signal input terminal VSS. The signal provided by the DC low potential signal input terminal VSS is a DC low potential signal.

第N-2级栅极驱动信号输出端G(N-2)所提供的第N-2级栅极驱动信号（高电位）开启所述第一晶体管101后，第N-2级起始信号输出端ST(N-2)所提供的第N-2级起始信号对所述预定节点Q(N)进行预充电，在第一阶段（所述预定节点Q(N)被预充电的阶段）P1，所述预定节点Q(N)被所述第N-2级起始信号充到约14V，如图3所示。在第二阶段（所述预定节点Q(N)的电位被抬升的阶段）P2，所述预定节点Q(N)通过时钟信号输入端CK(M)所提供的第N级时钟信号被抬高至约42V，所述第三晶体管202开启，第三晶体管202的栅极（第一极）电压Vgate=42V，漏极（第二极）Vd=28V，源极（第三极）Vs= -6V。因此，所述第三晶体管202工作时，所述第三晶体管202的栅极（第一极）和源极（第二极）之间的电压差Vgs=48V，与传统技术相比，降低了约12伏。在第三阶段（所述预定节点Q(N)的电位被下拉的阶段）P3，第N+2级栅极驱动信号输出端G(N+2)所提供的第N+2级栅极驱动信号开启所述第十七晶体管601，所述第十七晶体管601的栅极电压Vgate=28V，漏极（第二极）电压Vd=31V，源极（第三极）电压Vs= -6V。因此，所述第十七晶体管601工作时，所述第十七晶体管601的漏极和源极之间的电压差Vds=37V，与传统技术相比，降低了约11伏。因此，降低了所述第三晶体管202和所述第十七晶体管601的电压压力，避免所述第三晶体管202和所述第十七晶体管601出现阈值电压偏移（Vth Shift）的情况，提升了所述第三晶体管202和所述第十七晶体管601的稳定性，延长了驱动电路及与驱动电路搭配使用的显示面板的使用寿命。The N-2th stage gate drive signal (high potential) provided by the N-2th stage gate drive signal output terminal G(N-2) turns on the first transistor 101, the N-2th stage start signal The N-2th stage start signal provided by the output terminal ST(N-2) precharges the predetermined node Q(N). In the first stage (the stage when the predetermined node Q(N) is precharged) ) P1, the predetermined node Q(N) is charged to about 14V by the N-2th level start signal, as shown in FIG. 3. In the second stage (the stage where the potential of the predetermined node Q(N) is raised) P2, the predetermined node Q(N) is raised by the Nth stage clock signal provided by the clock signal input terminal CK(M) To about 42V, the third transistor 202 is turned on, the gate (first pole) voltage of the third transistor 202 is Vgate=42V, the drain (second pole) Vd=28V, and the source (third pole) Vs=- 6V. Therefore, when the third transistor 202 is working, the voltage difference between the gate (first electrode) and the source (second electrode) of the third transistor 202 is Vgs=48V, which is reduced compared with the conventional technology. About 12 volts. In the third stage (the stage where the potential of the predetermined node Q(N) is pulled down) P3, the N+2 stage gate drive provided by the N+2 stage gate drive signal output terminal G(N+2) The signal turns on the seventeenth transistor 601, the gate voltage of the seventeenth transistor 601 is Vgate=28V, the drain (second pole) voltage Vd=31V, and the source (third pole) voltage Vs=-6V. Therefore, when the seventeenth transistor 601 works, the voltage difference between the drain and the source of the seventeenth transistor 601 is Vds=37V, which is about 11 volts lower than the conventional technology. Therefore, the voltage pressure of the third transistor 202 and the seventeenth transistor 601 is reduced, and the threshold voltage shift (Vth Shift) of the third transistor 202 and the seventeenth transistor 601 is avoided, and the The stability of the third transistor 202 and the seventeenth transistor 601 is improved, and the service life of the driving circuit and the display panel used with the driving circuit is prolonged.

所述下拉维持模块包括第一下拉维持子模块40和第二下拉维持子模块50，所述第一下拉维持子模块40和所述第二下拉维持子模块50电性连接，并且，所述第一下拉维持子模块40和所述第二下拉维持子模块50与所述上拉控制模块10、所述上拉模块20、所述下拉模块60中的任意两者电性连接。The pull-down maintenance module includes a first pull-down maintenance sub-module 40 and a second pull-down maintenance sub-module 50. The first pull-down maintenance sub-module 40 and the second pull-down maintenance sub-module 50 are electrically connected, and The first pull-down maintaining sub-module 40 and the second pull-down maintaining sub-module 50 are electrically connected to any two of the pull-up control module 10, the pull-up module 20, and the pull-down module 60.

所述第一下拉维持子模块40用于在第一时间段维持所述预定节点Q(N)和第N级栅极驱动信号输出端G(N) 中的信号的波形稳定性。The first pull-down maintenance sub-module 40 is used to maintain the waveform stability of the signal in the predetermined node Q(N) and the Nth gate drive signal output terminal G(N) in the first time period.

所述第二下拉维持子模块50用于在与所述第一时间段不同的第二时间段维持所述预定节点Q(N)和第N级栅极驱动信号输出端G(N) 中的信号的波形稳定性。The second pull-down maintaining sub-module 50 is used to maintain the predetermined node Q(N) and the Nth gate drive signal output terminal G(N) in a second time period different from the first time period. The waveform stability of the signal.

即，所述第一下拉维持子模块40和所述第二下拉维持子模块50用于交替地维持所述预定节点Q(N)和第N级栅极驱动信号输出端G(N)中的信号的波形稳定性。That is, the first pull-down sustaining sub-module 40 and the second pull-down sustaining sub-module 50 are used to alternately maintain the predetermined node Q(N) and the Nth stage gate drive signal output terminal G(N). The waveform stability of the signal.

所述第一下拉维持子模块40包括第五晶体管401、第六晶体管402、第七晶体管403、第八晶体管404、第九晶体管405和第十晶体管406，所述第五晶体管401的第一极和第二极均与第一控制信号输入端LC1和所述第六晶体管402的第二极电性连接，所述第五晶体管401的第三极与所述第六晶体管402的第一极、所述第七晶体管403的第二极电性连接，所述第六晶体管402的第三极与所述第八晶体管404的第二极、所述第九晶体管405的第一极和所述第十晶体管406的第一极电性连接，所述第七晶体管403的第一极与所述第一晶体管101的第三极、所述第八晶体管404的第一极电性连接，所述第七晶体管403的第三极、所述第八晶体管404的第三极、所述第九晶体管405的第三极和所述第十晶体管406的第三极均与直流低电位信号输入端VSS电性连接，所述第九晶体管405的第二极与第N级栅极驱动信号输出端G(N)电性连接，所述第十晶体管406的第二极与所述预定节点Q(N)电性连接。The first pull-down sustain sub-module 40 includes a fifth transistor 401, a sixth transistor 402, a seventh transistor 403, an eighth transistor 404, a ninth transistor 405, and a tenth transistor 406. The first transistor of the fifth transistor 401 Both the first electrode and the second electrode are electrically connected to the first control signal input terminal LC1 and the second electrode of the sixth transistor 402. The third electrode of the fifth transistor 401 is connected to the first electrode of the sixth transistor 402. The second electrode of the seventh transistor 403 is electrically connected, the third electrode of the sixth transistor 402 and the second electrode of the eighth transistor 404, the first electrode of the ninth transistor 405 and the The first electrode of the tenth transistor 406 is electrically connected, and the first electrode of the seventh transistor 403 is electrically connected to the third electrode of the first transistor 101 and the first electrode of the eighth transistor 404. The third pole of the seventh transistor 403, the third pole of the eighth transistor 404, the third pole of the ninth transistor 405, and the third pole of the tenth transistor 406 are all connected to the DC low potential signal input terminal VSS. The second electrode of the ninth transistor 405 is electrically connected to the Nth gate drive signal output terminal G(N), and the second electrode of the tenth transistor 406 is electrically connected to the predetermined node Q(N). ) Electrical connection.

所述第二下拉维持子模块50包括第十一晶体管501、第十二晶体管502、第十三晶体管503、第十四晶体管504、第十五晶体管505和第十六晶体管506，所述第十一晶体管501的第二极与第二控制信号输入端LC2电性连接，所述第十二晶体管502的第一极、第二极均与第二控制信号输入端LC2电性连接，所述第十二晶体管502的第三极与所述第十一晶体管501的第一极、所述第十六晶体管506的第二极电性连接，所述第十一晶体管501的第三极与所述第十三晶体管503的第一极、所述第十四晶体管504的第一极以及第十五晶体管505的第二极电性连接，所述第十三晶体管503的第二极与所述预定节点Q(N)电性连接，所述第十三晶体管503的第三极、所述第十四晶体管504的第三极、所述第十五晶体管505的第三极以及所述第十六晶体管506的第三极均与直流低电位信号输入端VSS电性连接，所述第十四晶体管504的第二极与第N级栅极驱动信号输出端G(N)电性连接，所述第十五晶体管505的第一极与所述第十六晶体管506的第一极、所述第一晶体管101的第三极电性连接。The second pull-down sustain sub-module 50 includes an eleventh transistor 501, a twelfth transistor 502, a thirteenth transistor 503, a fourteenth transistor 504, a fifteenth transistor 505, and a sixteenth transistor 506. The second electrode of a transistor 501 is electrically connected to the second control signal input terminal LC2, and the first electrode and the second electrode of the twelfth transistor 502 are electrically connected to the second control signal input terminal LC2. The third electrode of the twelve transistor 502 is electrically connected to the first electrode of the eleventh transistor 501 and the second electrode of the sixteenth transistor 506, and the third electrode of the eleventh transistor 501 is electrically connected to the The first electrode of the thirteenth transistor 503, the first electrode of the fourteenth transistor 504, and the second electrode of the fifteenth transistor 505 are electrically connected, and the second electrode of the thirteenth transistor 503 is connected to the predetermined The node Q(N) is electrically connected, the third pole of the thirteenth transistor 503, the third pole of the fourteenth transistor 504, the third pole of the fifteenth transistor 505, and the sixteenth pole The third pole of the transistor 506 is electrically connected to the DC low-potential signal input terminal VSS, and the second pole of the fourteenth transistor 504 is electrically connected to the N-th stage gate drive signal output terminal G(N). The first electrode of the fifteenth transistor 505 is electrically connected to the first electrode of the sixteenth transistor 506 and the third electrode of the first transistor 101.

第一控制信号输入端LC1所提供的第一控制信号和第二控制信号输入端LC2所提供的第二控制信号均是低频方波信号，所述第一控制信号和所述第二控制信号用于对下拉模块60进行控制。具体地，如图2所示，其中第一控制信号和第二控制信号的周期T均是200倍帧周期，占空比为1/2的低频信号，第一控制信号和第二控制信号相位相差1/2周期，第一控制信号和第二控制信号用于交替地驱动所述第一下拉维持子模块40和所述第二下拉维持子模块50工作。The first control signal provided by the first control signal input terminal LC1 and the second control signal provided by the second control signal input terminal LC2 are both low-frequency square wave signals, and the first control signal and the second control signal are used To control the pull-down module 60. Specifically, as shown in FIG. 2, the period T of the first control signal and the second control signal are both 200 times the frame period, a low-frequency signal with a duty cycle of 1/2, and the phases of the first control signal and the second control signal With a difference of 1/2 period, the first control signal and the second control signal are used to alternately drive the first pull-down maintenance sub-module 40 and the second pull-down maintenance sub-module 50 to work.

第N级栅极驱动单元电路还包括重置模块30，所述重置模块30与所述上拉控制模块10、所述上拉模块20、所述下拉模块60、所述下拉维持模块均电性连接，所述重置模块30用于重置所述第N级栅极驱动单元电路。The N-th stage gate drive unit circuit further includes a reset module 30, and the reset module 30 is electrically connected to the pull-up control module 10, the pull-up module 20, the pull-down module 60, and the pull-down maintenance module. The reset module 30 is used to reset the Nth stage gate driving unit circuit.

所述重置模块30包括第四晶体管301，所述第四晶体管的第一极与重置信号输入端RST电性连接，所述第四晶体管的第二极与所述预定节点Q(N)电性连接，所述第四晶体管301的第三极与直流低电位信号输入端VSS、所述下拉维持模块中的第一下拉维持子模块40的第七晶体管403的第三极电性连接。The reset module 30 includes a fourth transistor 301, the first electrode of the fourth transistor is electrically connected to the reset signal input terminal RST, and the second electrode of the fourth transistor is connected to the predetermined node Q(N). Electrically connected, the third electrode of the fourth transistor 301 is electrically connected to the DC low-potential signal input terminal VSS, and the third electrode of the seventh transistor 403 of the first pull-down maintenance submodule 40 in the pull-down maintenance module .

具体地，当重置信号输入端RST所提供的重置信号为高电平时，所述第四晶体管301开启，所述预定节点的电位将通过直流低电位信号输入端VSS所提供的信号恢复至低电位。Specifically, when the reset signal provided by the reset signal input terminal RST is at a high level, the fourth transistor 301 is turned on, and the potential of the predetermined node will be restored to the signal provided by the DC low potential signal input terminal VSS. Low potential.

上述晶体管（包括第一晶体管101、第二晶体管201、第三晶体管202、第四晶体管301、第五晶体管401、第六晶体管402、第七晶体管403、第八晶体管404、第九晶体管405、第十晶体管406、第十一晶体管501、第十二晶体管502、第十三晶体管503、第十四晶体管504、第十五晶体管505、第十六晶体管506、第十七晶体管601和第十八晶体管602）的第一极可例如为栅极，所述晶体管的第二极可例如为源极或漏极，所述晶体管的第三极可例如为漏极或源极。The above transistors (including the first transistor 101, the second transistor 201, the third transistor 202, the fourth transistor 301, the fifth transistor 401, the sixth transistor 402, the seventh transistor 403, the eighth transistor 404, the ninth transistor 405, the Ten transistor 406, eleventh transistor 501, twelfth transistor 502, thirteenth transistor 503, fourteenth transistor 504, fifteenth transistor 505, sixteenth transistor 506, seventeenth transistor 601, and eighteenth transistor The first electrode of 602) can be, for example, a gate, the second electrode of the transistor can be, for example, a source or a drain, and the third electrode of the transistor can be, for example, a drain or a source.

通过上述技术方案，由于所述第二晶体管的第二极与交流信号输入端电性连接，在所述第二晶体管开启时，所述交流信号输入端所提供的交流信号通过所述第二晶体管从第N-2级起始信号输出端输出，第N-2级起始信号输出端所输出的起始信号输入至第N级栅极驱动单元电路中，所述交流信号的高电位电压低于时钟信号的高电位电压，因此，当所述第三晶体管开启时，所述第三晶体管的栅极和源极之间的电压差Vgs=48V，与传统技术相比，降低了约12伏；在所述第十七晶体管开启时，所述第十七晶体管的漏极和源极之间的电压差Vds=37V，与传统技术相比，降低了约11伏。因此，本发明的技术方案降低了驱动电路内的部分晶体管（例如所述第三晶体管和所述第十七晶体管）的电压压力，避免这些晶体管出现阈值电压偏移的情况，提升了这些晶体管的稳定性，延长了驱动电路及与驱动电路搭配使用的显示面板的使用寿命。With the above technical solution, since the second electrode of the second transistor is electrically connected to the AC signal input terminal, when the second transistor is turned on, the AC signal provided by the AC signal input terminal passes through the second transistor It is output from the N-2th stage start signal output terminal, and the start signal output from the N-2th stage start signal output terminal is input to the Nth stage gate drive unit circuit. The high potential voltage of the AC signal is low Because of the high potential voltage of the clock signal, when the third transistor is turned on, the voltage difference between the gate and source of the third transistor Vgs=48V, which is about 12 volts lower than the conventional technology When the seventeenth transistor is turned on, the voltage difference between the drain and the source of the seventeenth transistor Vds=37V, which is about 11 volts lower than the conventional technology. Therefore, the technical solution of the present invention reduces the voltage pressure of some transistors in the driving circuit (such as the third transistor and the seventeenth transistor), avoids the threshold voltage shift of these transistors, and improves the performance of these transistors. The stability extends the service life of the driving circuit and the display panel used with the driving circuit.

综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。In summary, although the present invention has been disclosed as above in preferred embodiments, the above-mentioned preferred embodiments are not intended to limit the present invention. Those of ordinary skill in the art can make various modifications without departing from the spirit and scope of the present invention. Such changes and modifications, therefore, the protection scope of the present invention is subject to the scope defined by the claims.

Claims

一种驱动电路，其中，所述驱动电路包括至少两栅极驱动单元电路，至少两所述栅极驱动单元电路以级联的方式电性连接；A driving circuit, wherein the driving circuit includes at least two gate driving unit circuits, and at least two of the gate driving unit circuits are electrically connected in a cascade manner;

至少两所述栅极驱动单元电路中的第N级栅极驱动单元电路包括上拉控制模块、上拉模块、下拉模块、下拉维持模块，所述上拉控制模块、所述上拉模块、所述下拉模块、所述下拉维持模块中的任意两者电性连接，其中，N为大于0的整数；At least two of the gate drive unit circuits of the Nth stage include a pull-up control module, a pull-up module, a pull-down module, and a pull-down maintenance module. The pull-up control module, the pull-up module, and the Any two of the pull-down module and the pull-down maintenance module are electrically connected, wherein N is an integer greater than 0;

所述上拉控制模块用于将所述第N级栅极驱动单元电路中的预定节点拉升至高电位；The pull-up control module is used to pull a predetermined node in the N-th gate drive unit circuit to a high potential;

所述上拉模块用于通过所述第N级栅极驱动单元电路的第N级栅极驱动信号输出端输出第N级栅极驱动信号；The pull-up module is configured to output the Nth stage gate drive signal through the Nth stage gate drive signal output terminal of the Nth stage gate drive unit circuit;

所述下拉模块用于将所述第N级栅极驱动单元电路的所述预定节点和第N级栅极驱动信号输出端重新设定至低电位；The pull-down module is used to reset the predetermined node of the Nth stage gate drive unit circuit and the Nth stage gate drive signal output terminal to a low potential;

所述下拉维持模块用于维持所述预定节点和第N级栅极驱动信号输出端中的信号的波形稳定性；The pull-down maintenance module is used to maintain the waveform stability of the signal at the predetermined node and the Nth gate drive signal output terminal;

所述上拉控制模块包括第一晶体管，所述第一晶体管的第一极与第N-2级栅极驱动信号输出端电性连接，所述第一晶体管的第二极与第N-2级起始信号输出端电性连接，所述第一晶体管的第三极与预定节点电性连接；The pull-up control module includes a first transistor, a first electrode of the first transistor is electrically connected to the N-2th stage gate drive signal output terminal, and a second electrode of the first transistor is electrically connected to the N-2th stage gate drive signal output terminal. The stage start signal output terminal is electrically connected, and the third electrode of the first transistor is electrically connected to a predetermined node;

其中，所述预定节点位于所述第一晶体管的第三极与上拉模块的第二晶体管的第一极之间；Wherein, the predetermined node is located between the third pole of the first transistor and the first pole of the second transistor of the pull-up module;

所述第N级栅极驱动单元电路还包括重置模块，所述重置模块与所述上拉控制模块、所述上拉模块、所述下拉模块、所述下拉维持模块均电性连接，所述重置模块用于重置所述第N级栅极驱动单元电路。The Nth stage gate driving unit circuit further includes a reset module, and the reset module is electrically connected to the pull-up control module, the pull-up module, the pull-down module, and the pull-down maintenance module. The reset module is used to reset the Nth stage gate driving unit circuit.
根据权利要求1所述的驱动电路，其中，所述第N级栅极驱动单元电路还包括交流信号输入端和时钟信号输入端；The driving circuit according to claim 1, wherein the Nth stage gate driving unit circuit further comprises an AC signal input terminal and a clock signal input terminal;

所述上拉模块包括第二晶体管、第三晶体管和电容，所述第二晶体管的第一极与所述预定节点、所述第三晶体管的第一极以及所述电容的第一极板电性连接，所述第二晶体管的第二极与所述交流信号输入端电性连接，所述第二晶体管的第三极与第N级起始信号输出端电性连接，所述第三晶体管的第二极与所述时钟信号输入端电性连接，所述第三晶体管的第三极与所述下拉模块的第十八晶体管的第二极电性连接，所述电容的第二极与第N级栅极驱动信号输出端电性连接。The pull-up module includes a second transistor, a third transistor, and a capacitor. The first electrode of the second transistor is connected to the predetermined node, the first electrode of the third transistor, and the first plate of the capacitor. The second electrode of the second transistor is electrically connected to the AC signal input terminal, the third electrode of the second transistor is electrically connected to the N-th stage start signal output terminal, and the third transistor The second electrode of the capacitor is electrically connected to the clock signal input terminal, the third electrode of the third transistor is electrically connected to the second electrode of the eighteenth transistor of the pull-down module, and the second electrode of the capacitor is electrically connected to The gate drive signal output terminal of the Nth stage is electrically connected.
根据权利要求2所述的驱动电路，其中，所述交流信号输入端所传输的交流信号的低电位电压等于所述时钟信号输入端所传输的时钟信号的低电位电压；3. The driving circuit of claim 2, wherein the low potential voltage of the AC signal transmitted by the AC signal input terminal is equal to the low potential voltage of the clock signal transmitted by the clock signal input terminal;

所述交流信号输入端所传输的交流信号的高电位电压低于所述时钟信号输入端所传输的时钟信号的高电位电压；The high potential voltage of the AC signal transmitted by the AC signal input terminal is lower than the high potential voltage of the clock signal transmitted by the clock signal input terminal;

所述交流信号输入端所传输的交流信号的频率和周期分别与所述时钟信号输入端所传输的时钟信号的频率和周期相同。The frequency and period of the AC signal transmitted by the AC signal input terminal are respectively the same as the frequency and period of the clock signal transmitted by the clock signal input terminal.
根据权利要求3所述的驱动电路，其中，所述交流信号的高电位电压为15V，所述时钟信号的高电位电压为28V。3. The driving circuit of claim 3, wherein the high potential voltage of the AC signal is 15V, and the high potential voltage of the clock signal is 28V.
根据权利要求1所述的驱动电路，其中，所述第N级栅极驱动单元电路还包括直流低电位信号输入端；The driving circuit according to claim 1, wherein the Nth stage gate driving unit circuit further comprises a DC low-potential signal input terminal;

所述下拉模块包括第十七晶体管和第十八晶体管，所述第十七晶体管的第一极、所述第十八晶体管的第一极均与第N+2级栅极驱动信号输出端电性连接，所述第十七晶体管的第二极与所述预定节点电性连接，所述第十七晶体管的第二极、第十八晶体管的第三极均与所述直流低电位信号输入端电性连接。The pull-down module includes a seventeenth transistor and an eighteenth transistor. The first pole of the seventeenth transistor and the first pole of the eighteenth transistor are both electrically connected to the N+2 stage gate drive signal output terminal. The second pole of the seventeenth transistor is electrically connected to the predetermined node, and the second pole of the seventeenth transistor and the third pole of the eighteenth transistor are both connected to the DC low-potential signal input The terminals are electrically connected.
一种驱动电路，其中，所述驱动电路包括至少两栅极驱动单元电路，至少两所述栅极驱动单元电路以级联的方式电性连接；A driving circuit, wherein the driving circuit includes at least two gate driving unit circuits, and at least two of the gate driving unit circuits are electrically connected in a cascade manner;

至少两所述栅极驱动单元电路中的第N级栅极驱动单元电路包括上拉控制模块、上拉模块、下拉模块、下拉维持模块，所述上拉控制模块、所述上拉模块、所述下拉模块、所述下拉维持模块中的任意两者电性连接，其中，N为大于0的整数；At least two of the gate drive unit circuits of the Nth stage include a pull-up control module, a pull-up module, a pull-down module, and a pull-down maintenance module. The pull-up control module, the pull-up module, and the Any two of the pull-down module and the pull-down maintenance module are electrically connected, wherein N is an integer greater than 0;

所述上拉控制模块用于将所述第N级栅极驱动单元电路中的预定节点拉升至高电位；The pull-up control module is used to pull a predetermined node in the N-th gate drive unit circuit to a high potential;

所述上拉模块用于通过所述第N级栅极驱动单元电路的第N级栅极驱动信号输出端输出第N级栅极驱动信号；The pull-up module is configured to output the Nth stage gate drive signal through the Nth stage gate drive signal output terminal of the Nth stage gate drive unit circuit;

所述下拉模块用于将所述第N级栅极驱动单元电路的所述预定节点和第N级栅极驱动信号输出端重新设定至低电位；The pull-down module is used to reset the predetermined node of the Nth stage gate drive unit circuit and the Nth stage gate drive signal output terminal to a low potential;

所述下拉维持模块用于维持所述预定节点和第N级栅极驱动信号输出端中的信号的波形稳定性。The pull-down maintenance module is used to maintain the waveform stability of the signal at the predetermined node and the Nth gate drive signal output terminal.
根据权利要求6所述的驱动电路，其中，所述上拉控制模块包括第一晶体管，所述第一晶体管的第一极与第N-2级栅极驱动信号输出端电性连接，所述第一晶体管的第二极与第N-2级起始信号输出端电性连接，所述第一晶体管的第三极与预定节点电性连接；7. The driving circuit of claim 6, wherein the pull-up control module comprises a first transistor, the first electrode of the first transistor is electrically connected to the N-2th stage gate drive signal output terminal, and the The second electrode of the first transistor is electrically connected to the N-2th stage start signal output terminal, and the third electrode of the first transistor is electrically connected to a predetermined node;

其中，所述预定节点位于所述第一晶体管的第三极与上拉模块的第二晶体管的第一极之间。Wherein, the predetermined node is located between the third pole of the first transistor and the first pole of the second transistor of the pull-up module.
根据权利要求6所述的驱动电路，其中，所述第N级栅极驱动单元电路还包括交流信号输入端和时钟信号输入端；7. The driving circuit of claim 6, wherein the Nth stage gate driving unit circuit further comprises an AC signal input terminal and a clock signal input terminal;

所述上拉模块包括第二晶体管、第三晶体管和电容，所述第二晶体管的第一极与所述预定节点、所述第三晶体管的第一极以及所述电容的第一极板电性连接，所述第二晶体管的第二极与所述交流信号输入端电性连接，所述第二晶体管的第三极与第N级起始信号输出端电性连接，所述第三晶体管的第二极与所述时钟信号输入端电性连接，所述第三晶体管的第三极与所述下拉模块的第十八晶体管的第二极电性连接，所述电容的第二极与第N级栅极驱动信号输出端电性连接。The pull-up module includes a second transistor, a third transistor, and a capacitor. The first electrode of the second transistor is connected to the predetermined node, the first electrode of the third transistor, and the first plate of the capacitor. The second electrode of the second transistor is electrically connected to the AC signal input terminal, the third electrode of the second transistor is electrically connected to the N-th stage start signal output terminal, and the third transistor The second electrode of the capacitor is electrically connected to the clock signal input terminal, the third electrode of the third transistor is electrically connected to the second electrode of the eighteenth transistor of the pull-down module, and the second electrode of the capacitor is electrically connected to The gate drive signal output terminal of the Nth stage is electrically connected.
根据权利要求8所述的驱动电路，其中，所述交流信号输入端所传输的交流信号的低电位电压等于所述时钟信号输入端所传输的时钟信号的低电位电压；8. The driving circuit according to claim 8, wherein the low potential voltage of the AC signal transmitted by the AC signal input terminal is equal to the low potential voltage of the clock signal transmitted by the clock signal input terminal;

所述交流信号输入端所传输的交流信号的高电位电压低于所述时钟信号输入端所传输的时钟信号的高电位电压；The high potential voltage of the AC signal transmitted by the AC signal input terminal is lower than the high potential voltage of the clock signal transmitted by the clock signal input terminal;

所述交流信号输入端所传输的交流信号的频率和周期分别与所述时钟信号输入端所传输的时钟信号的频率和周期相同。The frequency and period of the AC signal transmitted by the AC signal input terminal are respectively the same as the frequency and period of the clock signal transmitted by the clock signal input terminal.
根据权利要求9所述的驱动电路，其中，所述交流信号的高电位电压为15V，所述时钟信号的高电位电压为28V。9. The driving circuit according to claim 9, wherein the high potential voltage of the AC signal is 15V, and the high potential voltage of the clock signal is 28V.
根据权利要求6所述的驱动电路，其中，所述第N级栅极驱动单元电路还包括直流低电位信号输入端；7. The driving circuit according to claim 6, wherein the Nth stage gate driving unit circuit further comprises a DC low-potential signal input terminal;

所述下拉模块包括第十七晶体管和第十八晶体管，所述第十七晶体管的第一极、所述第十八晶体管的第一极均与第N+2级栅极驱动信号输出端电性连接，所述第十七晶体管的第二极与所述预定节点电性连接，所述第十七晶体管的第二极、第十八晶体管的第三极均与所述直流低电位信号输入端电性连接。The pull-down module includes a seventeenth transistor and an eighteenth transistor. The first pole of the seventeenth transistor and the first pole of the eighteenth transistor are both electrically connected to the N+2 stage gate drive signal output terminal. The second pole of the seventeenth transistor is electrically connected to the predetermined node, and the second pole of the seventeenth transistor and the third pole of the eighteenth transistor are both connected to the DC low-potential signal input The terminals are electrically connected.
根据权利要求6所述的驱动电路，其中，所述下拉维持模块包括第一下拉维持子模块和第二下拉维持子模块，所述第一下拉维持子模块和所述第二下拉维持子模块电性连接，并且，所述第一下拉维持子模块和所述第二下拉维持子模块与所述上拉控制模块、所述上拉模块、所述下拉模块中的任意两者电性连接；The driving circuit according to claim 6, wherein the pull-down maintaining module includes a first pull-down maintaining sub-module and a second pull-down maintaining sub-module, the first pull-down maintaining sub-module and the second pull-down maintaining sub-module The modules are electrically connected, and the first pull-down maintenance sub-module and the second pull-down maintenance sub-module are electrically connected to any two of the pull-up control module, the pull-up module, and the pull-down module connection;

所述第一下拉维持子模块用于在第一时间段维持所述预定节点和第N级栅极驱动信号输出端中的信号的波形稳定性；The first pull-down maintenance sub-module is used to maintain the waveform stability of the signal in the predetermined node and the Nth gate drive signal output terminal in the first time period;

所述第二下拉维持子模块用于在与所述第一时间段不同的第二时间段维持所述预定节点和第N级栅极驱动信号输出端中的信号的波形稳定性。The second pull-down maintenance sub-module is configured to maintain the waveform stability of the signal in the predetermined node and the N-th stage gate drive signal output terminal in a second time period different from the first time period.
根据权利要求12所述的驱动电路，其中，所述第N级栅极驱动单元电路还包括第一控制信号输入端和第二控制信号输入端，所述第一控制信号输入端与所述第一下拉维持子模块电性连接，所述第二控制信号输入端与所述第二下拉维持子模块电性连接；The driving circuit according to claim 12, wherein the Nth stage gate driving unit circuit further comprises a first control signal input terminal and a second control signal input terminal, the first control signal input terminal and the first control signal input terminal A pull-down maintenance sub-module is electrically connected, and the second control signal input terminal is electrically connected with the second pull-down maintenance sub-module;

所述第一控制信号和所述第二控制信号相位相差1/2周期，所述第一控制信号和所述第二控制信号用于交替地驱动所述第一下拉维持子模块和所述第二下拉维持子模块。The first control signal and the second control signal have a phase difference of 1/2 period. The first control signal and the second control signal are used to alternately drive the first pull-down sustaining sub-module and the The second pull-down maintains the sub-module.
根据权利要求13所述的驱动电路，其中，所述第一控制信号输入端所提供的第一控制信号和所述第二控制信号输入端所提供的第二控制信号均是周期为200倍帧周期，占空比为1/2的信号。The driving circuit according to claim 13, wherein the first control signal provided by the first control signal input terminal and the second control signal provided by the second control signal input terminal both have a period of 200 times the frame Period, a signal with a duty cycle of 1/2.
根据权利要求12所述的驱动电路，其中，所述第一下拉维持子模块包括第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管和第十晶体管，所述第五晶体管的第一极和第二极均与第一控制信号输入端和所述第六晶体管的第二极电性连接，所述第五晶体管的第三极与所述第六晶体管的第一极、所述第七晶体管的第二极电性连接，所述第六晶体管的第三极与所述第八晶体管的第二极、所述第九晶体管的第一极和所述第十晶体管的第一极电性连接，所述第七晶体管的第一极与第一晶体管的第三极、所述第八晶体管的第一极电性连接，所述第七晶体管的第三极、所述第八晶体管的第三极、所述第九晶体管的第三极和所述第十晶体管的第三极均与直流低电位信号输入端电性连接，所述第九晶体管的第二极与第N级栅极驱动信号输出端电性连接，所述第十晶体管的第二极与所述预定节点电性连接。The driving circuit according to claim 12, wherein the first pull-down sustaining sub-module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor, and the fifth The first electrode and the second electrode of the transistor are electrically connected to the first control signal input terminal and the second electrode of the sixth transistor, and the third electrode of the fifth transistor is connected to the first electrode of the sixth transistor. , The second pole of the seventh transistor is electrically connected, the third pole of the sixth transistor is connected to the second pole of the eighth transistor, the first pole of the ninth transistor and the tenth transistor The first electrode of the seventh transistor is electrically connected to the third electrode of the first transistor and the first electrode of the eighth transistor. The third electrode of the seventh transistor is electrically connected to the The third electrode of the eighth transistor, the third electrode of the ninth transistor, and the third electrode of the tenth transistor are all electrically connected to the DC low-potential signal input terminal, and the second electrode of the ninth transistor is electrically connected to the The N-level gate drive signal output terminal is electrically connected, and the second electrode of the tenth transistor is electrically connected to the predetermined node.
根据权利要求12所述的驱动电路，其中，所述第二下拉维持子模块包括第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第十六晶体管，所述第十一晶体管的第二极与第二控制信号输入端电性连接，所述第十二晶体管的第一极、第二极均与第二控制信号输入端电性连接，所述第十二晶体管的第三极与所述第十一晶体管的第一极、所述第十六晶体管的第二极电性连接，所述第十一晶体管的第三极与所述第十三晶体管的第一极、所述第十四晶体管的第一极以及第十五晶体管的第二极电性连接，所述第十三晶体管的第二极与所述预定节点电性连接，所述第十三晶体管的第三极、所述第十四晶体管的第三极、所述第十五晶体管的第三极以及所述第十六晶体管的第三极均与直流低电位信号输入端电性连接，所述第十四晶体管的第二极与第N级栅极驱动信号输出端电性连接，所述第十五晶体管的第一极与所述第十六晶体管的第一极、第一晶体管的第三极电性连接。The driving circuit according to claim 12, wherein the second pull-down sustain sub-module includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor , The second electrode of the eleventh transistor is electrically connected to the second control signal input terminal, the first electrode and the second electrode of the twelfth transistor are electrically connected to the second control signal input terminal, the The third pole of the twelfth transistor is electrically connected to the first pole of the eleventh transistor and the second pole of the sixteenth transistor, and the third pole of the eleventh transistor is electrically connected to the thirteenth pole. The first electrode of the transistor, the first electrode of the fourteenth transistor, and the second electrode of the fifteenth transistor are electrically connected, the second electrode of the thirteenth transistor is electrically connected to the predetermined node, and the The third pole of the thirteenth transistor, the third pole of the fourteenth transistor, the third pole of the fifteenth transistor, and the third pole of the sixteenth transistor are all connected to the DC low-potential signal input terminal. The second pole of the fourteenth transistor is electrically connected to the N-th stage gate drive signal output terminal, and the first pole of the fifteenth transistor is electrically connected to the first pole and the first pole of the sixteenth transistor. The third pole of a transistor is electrically connected.
根据权利要求6所述的驱动电路，其中，第N级栅极驱动单元电路还包括重置模块，所述重置模块与所述上拉控制模块、所述上拉模块、所述下拉模块、所述下拉维持模块均电性连接，所述重置模块用于重置所述第N级栅极驱动单元电路。The driving circuit according to claim 6, wherein the Nth stage gate driving unit circuit further comprises a reset module, the reset module and the pull-up control module, the pull-up module, the pull-down module, The pull-down maintaining modules are all electrically connected, and the reset module is used to reset the Nth stage gate driving unit circuit.
根据权利要求17所述的驱动电路，其中，所述第N级栅极驱动单元电路还包括重置信号输入端；17. The driving circuit according to claim 17, wherein the Nth stage gate driving unit circuit further comprises a reset signal input terminal;

所述重置模块包括第四晶体管，所述第四晶体管的第一极与所述重置信号输入端电性连接，所述第四晶体管的第二极与所述预定节点电性连接，所述第四晶体管的第三极与直流低电位信号输入端、所述下拉维持模块中的第一下拉维持子模块的第七晶体管的第三极电性连接。The reset module includes a fourth transistor, a first pole of the fourth transistor is electrically connected to the reset signal input terminal, a second pole of the fourth transistor is electrically connected to the predetermined node, so The third electrode of the fourth transistor is electrically connected to the DC low-potential signal input terminal and the third electrode of the seventh transistor of the first pull-down maintenance sub-module in the pull-down maintenance module.
根据权利要求18所述的驱动电路，其中，所述第四晶体管用于在所述重置信号输入端所提供的重置信号为高电平时开启，以使所述预定节点的电位通过直流低电位信号输入端所提供的信号恢复至低电位。The driving circuit according to claim 18, wherein the fourth transistor is used to turn on when the reset signal provided by the reset signal input terminal is at a high level, so that the potential of the predetermined node passes through a DC low The signal provided by the potential signal input terminal is restored to a low potential.
根据权利要求6所述的驱动电路，其中，所述驱动电路还包括时钟信号生成电路和交流信号生成电路；The driving circuit according to claim 6, wherein the driving circuit further comprises a clock signal generating circuit and an AC signal generating circuit;

所述时钟信号生成电路用于生成M个不同的时钟信号，M个不同的时钟信号分别通过M个不同的时钟信号输入端与M个不同的栅极驱动单元电路电性连接；The clock signal generating circuit is used to generate M different clock signals, and the M different clock signals are electrically connected to M different gate driving unit circuits through M different clock signal input terminals;

所述交流信号生成电路用于生成M个不同的交流信号，M个不同的交流信号分别通过M个不同的交流信号输入端与M个不同的栅极驱动单元电路电性连接；The AC signal generating circuit is used to generate M different AC signals, and the M different AC signals are electrically connected to M different gate drive unit circuits through M different AC signal input terminals, respectively;

其中，M为正整数。Among them, M is a positive integer.