WO2020224095A1 - 阵列基板及制备方法、显示装置 - Google Patents

阵列基板及制备方法、显示装置 Download PDF

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WO2020224095A1
WO2020224095A1 PCT/CN2019/102163 CN2019102163W WO2020224095A1 WO 2020224095 A1 WO2020224095 A1 WO 2020224095A1 CN 2019102163 W CN2019102163 W CN 2019102163W WO 2020224095 A1 WO2020224095 A1 WO 2020224095A1
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Prior art keywords
layer
thin film
film transistor
array substrate
low
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PCT/CN2019/102163
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English (en)
French (fr)
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方俊雄
吴元均
吕伯彦
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/616,980 priority Critical patent/US11355519B2/en
Publication of WO2020224095A1 publication Critical patent/WO2020224095A1/zh

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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
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    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
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    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • This application relates to the field of display technology, in particular to an array substrate, a manufacturing method, and a display device.
  • Low-temperature polysilicon thin-film transistors and metal oxide semiconductor thin-film transistors are two different types of thin-film transistors, each with its own advantages.
  • low-temperature polysilicon thin-film transistors have high carrier mobility, high stability, and are suitable for display drive circuits.
  • Metal oxide semiconductor thin film transistors have good electrical uniformity and extremely low off-state leakage current, and are suitable for pixel circuits of displays.
  • the two thin film transistors have different requirements on the working environment, such as whether hydrogen ions are required, they cannot work in the same environment for a long time, for example, they cannot work stably for a long time in the same display panel.
  • the prior art has a technical problem that different types of thin film transistors cannot work stably for a long time in the same display panel, which needs to be improved.
  • the present application provides an array substrate, a manufacturing method, and a display device to alleviate the technical problem that different types of thin film transistors cannot work stably for a long time in the same display panel in the prior art.
  • An embodiment of the present application provides an array substrate, which includes:
  • the hydrogen ion thin film is formed between the active layer and the source and drain layers of the low-temperature polysilicon thin film transistor, and an opening is formed in the setting area of the metal oxide semiconductor thin film transistor.
  • the array substrate includes a first insulating layer located between the active layer and the gate of the low-temperature polysilicon thin film transistor, and the first insulating layer includes a first silicon oxide layer And a first silicon nitride layer, the first silicon nitride layer being patterned to form a first hydrogen ion film in the hydrogen ion film.
  • the array substrate includes a second insulating layer located between the gate and source and drain layers of the low-temperature polysilicon thin film transistor, and the second insulating layer includes a second silicon dioxide layer. Layer and a second silicon nitride layer, the second silicon nitride layer is patterned to form a second hydrogen ion film in the hydrogen ion film.
  • the second silicon dioxide layer is disposed between the gate and the active layer of the metal oxide semiconductor thin film transistor.
  • the array substrate includes a buffer layer formed on the substrate, and a third insulating layer located between the gate of the low-temperature polysilicon thin film transistor and the second insulating layer.
  • An insulating layer, the first silicon oxide layer and the third insulating laminated layer are disposed between the buffer layer and the gate of the metal oxide semiconductor thin film transistor.
  • the active layer of the low-temperature polysilicon thin film transistor is disposed on the buffer layer.
  • the material of the buffer layer is silicon oxide.
  • the array substrate further includes a storage capacitor
  • the first electrode plate of the storage capacitor is arranged in the same layer as the gate electrode of the low-temperature polysilicon thin film transistor, and the second electrode plate of the storage capacitor is arranged in the same layer as the gate electrode of the metal oxide semiconductor thin film transistor.
  • the array substrate further includes a protective layer; the first silicon oxide layer and the first silicon nitride layer are disposed on the buffer layer and the first layer of the storage capacitor. Between the electrode plates, the third insulating layer is provided between the first electrode plate and the second electrode plate of the storage capacitor, and the second silicon dioxide layer and the second silicon nitride layer are provided on the Between the second electrode plate of the storage capacitor and the protective layer.
  • the embodiment of the present application also provides a method for preparing an array substrate, which includes:
  • a thin film transistor and a hydrogen ion thin film are prepared; wherein the thin film transistor includes a low temperature polysilicon thin film transistor and a metal oxide semiconductor thin film transistor formed above the substrate, and the hydrogen ion thin film is formed on the low temperature polysilicon thin film transistor.
  • An opening is formed between the source layer and the source drain layer and in the setting area of the metal oxide semiconductor thin film transistor.
  • An embodiment of the present application also provides a display device, which includes a display panel, and an array substrate of the display panel includes:
  • the hydrogen ion thin film is formed between the active layer and the source and drain layers of the low-temperature polysilicon thin film transistor, and an opening is formed in the setting area of the metal oxide semiconductor thin film transistor.
  • the array substrate includes a first insulating layer between the active layer and the gate of the low-temperature polysilicon thin film transistor, and the first insulating layer includes a first silicon oxide layer And a first silicon nitride layer, the first silicon nitride layer being patterned to form a first hydrogen ion film in the hydrogen ion film.
  • the array substrate includes a second insulating layer located between the gate and source and drain layers of the low-temperature polysilicon thin film transistor, and the second insulating layer includes a second silicon dioxide layer. Layer and a second silicon nitride layer, the second silicon nitride layer is patterned to form a second hydrogen ion film in the hydrogen ion film.
  • the second silicon dioxide layer is disposed between the gate and the active layer of the metal oxide semiconductor thin film transistor.
  • the array substrate includes a buffer layer formed on the substrate, and a third insulating layer located between the gate of the low-temperature polysilicon thin film transistor and the second insulating layer. Insulating layer; the first silicon oxide layer and the third insulating stack layer are disposed between the buffer layer and the gate of the metal oxide semiconductor thin film transistor.
  • the active layer of the low-temperature polysilicon thin film transistor is disposed on the buffer layer.
  • the material of the buffer layer is silicon oxide.
  • the array substrate further includes a storage capacitor
  • the first electrode plate of the storage capacitor is arranged in the same layer as the gate electrode of the low-temperature polysilicon thin film transistor, and the second electrode plate of the storage capacitor is arranged in the same layer as the gate electrode of the metal oxide semiconductor thin film transistor.
  • the array substrate further includes a protective layer; the first silicon oxide layer and the first silicon nitride layer are disposed on the buffer layer and the first layer of the storage capacitor. Between the electrode plates, the third insulating layer is provided between the first electrode plate and the second electrode plate of the storage capacitor, and the second silicon dioxide layer and the second silicon nitride layer are provided on the Between the second electrode plate of the storage capacitor and the protective layer.
  • the display panel is a liquid crystal display panel or an OLED display panel.
  • the application provides an array substrate, a preparation method, and a display device.
  • the array substrate includes a low-temperature polysilicon thin film transistor and a metal oxide semiconductor thin film transistor formed above the substrate, and a hydrogen ion thin film formed on the Between the active layer and the source and drain layers of the low-temperature polysilicon thin film transistor, and an opening is formed in the setting area of the metal oxide semiconductor thin film transistor; based on the hydrogen element generated by the hydrogen ion thin film, it bonds with silicon atoms , And then repair the defects in the aforementioned silicon thin film, improve the electrical characteristics and stability of low-temperature polysilicon thin film transistors, and at the same time, the hydrogen element cannot diffuse into the setting area of the metal oxide semiconductor thin film transistor, and thus will not interact with the metal of the metal oxide semiconductor thin film transistor.
  • Oxide generates oxygen holes to prevent the electrical characteristics and stability of the metal oxide semiconductor thin film transistor from being affected by hydrogen, and alleviate the technical problem that different types of thin film transistors cannot work stably for a long
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the application.
  • 2 to 10 are schematic diagrams of preparing the array substrate provided by the embodiments of the application.
  • the array substrate 10 provided by the embodiment of the present application includes:
  • the hydrogen ion thin film 400 is formed between the active layer 201 and the source and drain layers 203 of the low-temperature polysilicon thin film transistor 200, and an opening is formed in the setting area of the metal oxide semiconductor thin film transistor 300.
  • amorphous silicon is not perfectly crystallized. There are many Si vacancy and grain boundaries inside the silicon thin film. Defects such as boundary boundary) and dislocation (dislocation), these defects will seriously affect the electrical characteristics and stability of the thin film transistor.
  • the embodiment of the present application deposits a large amount of hydrogen element [H] above and below the polysilicon film Hydrogen ion film, such as silicon nitride (SiNx-H) film, in the subsequent high temperature process, hydrogen will diffuse into the polysilicon film and bond with silicon atoms to repair the defects in the aforementioned silicon film and improve the low temperature polysilicon film Electrical characteristics and stability of transistors.
  • Hydrogen ion film such as silicon nitride (SiNx-H) film
  • the hydrogen ion thin film in the embodiment of the present application forms openings in the area where the metal oxide semiconductor thin film transistor is installed. There is no hydrogen ion film such as silicon nitride around, which can ensure that the metal oxide active layer (that is, the active layer) will not be affected by hydrogen atoms to change the electrical characteristics of the metal oxide semiconductor thin film transistor.
  • the array substrate includes a low temperature polysilicon thin film transistor and a metal oxide semiconductor thin film transistor formed above the substrate, and a hydrogen ion thin film formed on the low temperature polysilicon thin film transistor Between the active layer and the source and drain layers of the metal oxide semiconductor thin film transistor, an opening is formed in the setting area of the metal oxide semiconductor thin film transistor; based on the hydrogen element generated by the hydrogen ion thin film, it is bonded with silicon atoms to repair the aforementioned The defects in the silicon film improve the electrical characteristics and stability of low-temperature polysilicon thin film transistors. At the same time, the hydrogen element cannot diffuse into the setting area of the metal oxide semiconductor thin film transistor, and will not generate oxygen with the metal oxide of the metal oxide semiconductor thin film transistor. Holes prevent the electrical characteristics and stability of the metal oxide semiconductor thin film transistor from being affected by hydrogen, and alleviate the technical problem that different types of thin film transistors cannot work stably for a long time in the same display panel in the prior art.
  • the array substrate 10 includes a substrate located between the active layer 201 and the gate 202 of the low-temperature polysilicon thin film transistor 200
  • a first insulating layer 500, the first insulating layer 500 includes a first silicon oxide layer M103 and a first silicon nitride layer M104 that are stacked, and the first silicon nitride layer M104 is patterned to form the hydrogen ion thin film 400 In the first hydrogen ion film.
  • the array substrate 10 includes a gate electrode 202 and a source drain layer 203 of the low temperature polysilicon thin film transistor 200.
  • the second insulating layer 600 includes a second silicon dioxide layer M108 and a second silicon nitride layer M109.
  • the second silicon nitride layer M109 is patterned to form the hydrogen ion thin film 400 The second hydrogen ion film.
  • the second silicon dioxide layer M108 is disposed on the gate 301 and the active electrode of the metal oxide semiconductor thin film transistor 300. Between layer 302.
  • the array substrate 10 includes a buffer layer M101 formed on the substrate, and a low-temperature polysilicon thin film transistor
  • the third insulating layer M106 between the gate 202 of the 200 and the second insulating layer 600, the first silicon oxide layer M103 and the third insulating layer M106 are stacked on the buffer layer M101 and the Between the gate 301 of the metal oxide semiconductor thin film transistor 300.
  • the material of the third insulating layer M106 is silicon oxide to reduce material complexity.
  • the active layer 201 of the low-temperature polysilicon thin film transistor 200 is disposed on the buffer layer M101.
  • the material of the buffer layer M101 is silicon oxide, so as to reduce the material complexity.
  • the array substrate 10 further includes a storage capacitor 700;
  • the first electrode plate 701 of the storage capacitor 700 and the gate 202 of the low-temperature polysilicon thin film transistor 200 are arranged in the same layer, and the second electrode plate 702 of the storage capacitor 700 is connected to the gate of the metal oxide semiconductor thin film transistor 300.
  • Pole 301 is set on the same floor.
  • the array substrate 10 further includes a protective layer M112; the first silicon oxide layer M103 and the first nitride
  • the silicon layer M104 is disposed between the buffer layer M101 and the first electrode plate 701 of the storage capacitor 700, and the third insulating layer M106 is disposed on the first electrode plate 701 and the second electrode plate of the storage capacitor 700
  • the second silicon dioxide layer M108 and the second silicon nitride layer M109 are disposed between the second electrode plate 702 of the storage capacitor 700 and the protection layer M112.
  • the material of the protective layer M112 is silicon oxide to reduce the material complexity.
  • the polysilicon layer M102 is patterned to form the active layer 201 of the low temperature polysilicon thin film transistor 200.
  • the first metal layer M105 is patterned to form the gate 202 of the low-temperature polysilicon thin film transistor 200 and the first electrode plate 701 of the storage capacitor 700.
  • the second metal layer M107 is patterned to form the second electrode plate 702 of the storage capacitor 700 and the gate 301 of the metal oxide semiconductor thin film transistor 300.
  • the material of the first metal layer M105 and the second metal layer M107 is copper, or a titanium aluminum titanium alloy or the like.
  • the metal oxide layer M110 is patterned to form the active layer 302 of the metal oxide semiconductor thin film transistor 300.
  • the source and drain layers M111 are patterned to form the source and drain 203 of the low-temperature polysilicon thin film transistor 200 and the source and drain 303 of the metal oxide semiconductor thin film transistor 300.
  • the present application also provides a display device, the display device includes a display panel, and the array substrate of the display panel includes:
  • the hydrogen ion thin film is formed between the active layer and the source and drain layers of the low-temperature polysilicon thin film transistor, and an opening is formed in the setting area of the metal oxide semiconductor thin film transistor.
  • the array substrate includes a first insulating layer located between the active layer and the gate of the low-temperature polysilicon thin film transistor, and the first insulating layer
  • the layer includes a first silicon oxide layer and a first silicon nitride layer, and the first silicon nitride layer is patterned to form a first hydrogen ion thin film in the hydrogen ion thin film.
  • the array substrate includes a second insulating layer located between the gate and the source and drain layers of the low-temperature polysilicon thin film transistor, and the second insulating layer
  • the insulating layer includes a second silicon dioxide layer and a second silicon nitride layer, and the second silicon nitride layer is patterned to form a second hydrogen ion thin film in the hydrogen ion thin film.
  • the second silicon dioxide layer is disposed between the gate and the active layer of the metal oxide semiconductor thin film transistor.
  • the array substrate includes a buffer layer formed on the substrate, and a gate located on the low-temperature polysilicon thin film transistor and the second A third insulating layer between insulating layers, and the first silicon oxide layer and the third insulating laminated layer are disposed between the buffer layer and the gate of the metal oxide semiconductor thin film transistor.
  • the active layer of the low-temperature polysilicon thin film transistor is disposed on the buffer layer.
  • the material of the buffer layer is silicon oxide.
  • the array substrate further includes a storage capacitor
  • the first electrode plate of the storage capacitor is arranged in the same layer as the gate electrode of the low-temperature polysilicon thin film transistor, and the second electrode plate of the storage capacitor is arranged in the same layer as the gate electrode of the metal oxide semiconductor thin film transistor.
  • the array substrate further includes a protective layer; the first silicon oxide layer and the first silicon nitride layer are disposed on the buffer layer and Between the first electrode plate of the storage capacitor, the third insulating layer is arranged between the first electrode plate and the second electrode plate of the storage capacitor, the second silicon dioxide layer and the second nitrogen The silicon dioxide layer is arranged between the second electrode plate of the storage capacitor and the protective layer.
  • the display panel is a liquid crystal display panel or an OLED display panel.
  • an embodiment of the present application also provides a method for preparing an array substrate, which includes the following steps:
  • Step 1 Provide substrates, such as glass plates, transparent flexible substrates, etc.;
  • Step two preparing a thin film transistor and a hydrogen ion thin film; wherein the thin film transistor includes a low temperature polysilicon thin film transistor and a metal oxide semiconductor thin film transistor formed above the substrate, and the hydrogen ion thin film is formed on the low temperature polysilicon thin film An opening is formed between the active layer and the source and drain layers of the transistor and in the setting area of the metal oxide semiconductor thin film transistor.
  • This embodiment provides a method for preparing an array substrate.
  • the obtained array substrate includes a low-temperature polysilicon thin film transistor and a metal oxide semiconductor thin film transistor formed above the substrate, and a hydrogen ion thin film.
  • the hydrogen ion thin film is formed on the Between the active layer and the source and drain layers of the low-temperature polysilicon thin film transistor, and an opening is formed in the setting area of the metal oxide semiconductor thin film transistor; based on the hydrogen element generated by the hydrogen ion thin film, it bonds with silicon atoms , And then repair the defects in the aforementioned silicon thin film, improve the electrical characteristics and stability of low-temperature polysilicon thin film transistors, and at the same time, the hydrogen element cannot diffuse into the setting area of the metal oxide semiconductor thin film transistor, and thus will not interact with the metal of the metal oxide semiconductor thin film transistor.
  • Oxide generates oxygen holes to prevent the electrical characteristics and stability of the metal oxide semiconductor thin film transistor from being affected by hydrogen, and alleviate the technical problem that different types of thin film transistors cannot work
  • the method for manufacturing an array substrate provided in the embodiment of the present application includes the following steps:
  • Step A Deposit a silicon oxide film on the substrate M100 as the buffer layer M101, and deposit an amorphous silicon film on the buffer layer M101, use high temperature to remove the hydrogen atoms in the amorphous silicon film, and clean the surface of the amorphous silicon film through a cleaning process , Use a laser to crystallize the amorphous silicon film into a polysilicon layer M102. Use yellow light and etching process to make polysilicon island 201. After removing the photoresist, use ion implantation and other processes to adjust the threshold voltage of the thin film transistor; again use yellow light process to define the channel region, source region and drain region, and use ion Processes such as implantation make heavily doped source and drain regions, and remove photoresist.
  • Step B Deposit a gate insulating layer (that is, the first insulating layer 500 above) on the polysilicon island 201.
  • the gate insulating layer sequentially includes the first silicon oxide layer M103 and the first silicon nitride layer from bottom to top M104 two-layer film.
  • Step C Deposit a first metal layer M105 on the gate insulating layer, and use a yellow light/etching process to define the required first metal layer pattern, including the gate 202 and the first electrode plate 701. While the first metal layer is being etched, the process parameters of the dry etching are adjusted to etch and remove the first silicon nitride layer M104 except under the first metal layer pattern to remove the photoresist.
  • Step D Depositing a silicon oxide layer on the fabricated first metal layer pattern as a dielectric interlayer between the two electrode plates of the storage capacitor 700 (ie, the third insulating layer M106 above).
  • Step E deposit a second metal layer M107 on the dielectric interlayer, and use a yellow light/etching process to define the second metal layer pattern, including the second electrode plate 702 and the gate 301, and remove the photoresist.
  • step F two dielectric layers (ie, the second insulating layer 600 above) are sequentially deposited on the second metal layer pattern, the second silicon dioxide layer M108 and the second silicon nitride layer M109.
  • the dielectric layer is located on the gate. Between the electrode 202 and the source and drain metal layer M111.
  • Step G Use a grayscale mask to make the photoresist pattern of FIG. 8.
  • the first part is a via hole connecting the polysilicon, and this part exposes/develops all the photoresist through the via hole.
  • the second part is the photoresist above the gate 301, this part is the area of the gray-scale photomask, and only part of the thickness of the photoresist is removed.
  • Step H dry etching the array substrate with the photoresist in FIG. 8 to etch the via holes of the active layer 201 and at the same time also etch away the second silicon nitride layer M109 above the metal oxide semiconductor thin film transistor. Remove the photoresist.
  • Step I Deposit a metal oxide thin film (IGZO) layer M110 on the structure of FIG. 9, and use a yellow light/etching process to define the pattern of the oxide metal active layer. After removing the photoresist, deposit a source and drain metal layer M111 on top , And use the yellow light/etching process to define the source and drain patterns (including the source and drain 203 and the source and drain 303), and after removing the photoresist, deposit a silicon oxide layer as the protective layer M112 on the source and drain patterns.
  • IGZO metal oxide thin film
  • the embodiments of the present application provide an array substrate and a preparation method thereof, and a display device.
  • the array substrate includes a low-temperature polysilicon thin film transistor and a metal oxide semiconductor thin film transistor formed above the substrate, and a hydrogen ion thin film.
  • An opening is formed between the active layer and the source and drain layers of the low-temperature polysilicon thin film transistor, and an opening is formed in the setting area of the metal oxide semiconductor thin film transistor; based on the hydrogen elements generated by the hydrogen ion thin film, and silicon atoms Bonding, and then repairing the defects in the aforementioned silicon film, improving the electrical characteristics and stability of low-temperature polysilicon thin film transistors, and at the same time, the hydrogen element cannot diffuse into the setting area of the metal oxide semiconductor thin film transistor, and thus will not interact with the metal oxide semiconductor thin film transistor.
  • the metal oxide produces oxygen holes to prevent the electrical characteristics and stability of the metal oxide semiconductor thin film transistor from being affected by hydrogen, and alleviate the existing technology that different types of thin film transistors cannot work stably for a long time in the same display panel problem.

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Abstract

本申请提供一种阵列基板及制备方法、显示装置，该阵列基板包括氢离子薄膜，形成于低温多晶硅薄膜晶体管的有源层和源漏极层之间，且在金属氧化物半导体薄膜晶体管的设置区域内形成开孔；基于该氢离子薄膜，改善了低温多晶硅薄膜晶体管的电器特性与稳定性，同时氢元素不能扩散到金属氧化物半导体薄膜晶体管的设置区域。

Description

阵列基板及制备方法、显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及制备方法、显示装置。
 背景技术
低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管是两种不同类型的薄膜晶体管，各有各的优点，例如低温多晶硅薄膜晶体管具有高载子迁移率, 高稳定性, 适合用于显示器的驱动电路，而金属氧化物半导体薄膜晶体管则具有较好的电性均匀性以及极低的关态漏电流, 适合用于显示器的像素电路。
但是由于这两种薄膜晶体管对工作环境的要求不同，例如是否需要氢离子的不同等，不能长时间的工作于同一环境下，例如不能在同一显示面板中长时间稳定工作。
所以，现有技术存在不同类型薄膜晶体管不能在同一显示面板中长时间稳定工作的技术问题，需要改进。
 技术问题
本申请提供一种阵列基板及制备方法、显示装置，以缓解现有技术存在的不同类型薄膜晶体管不能在同一显示面板中长时间稳定工作的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种阵列基板，其包括：
衬底；
形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管；以及
氢离子薄膜，形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间，且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔。
在本申请实施例提供的阵列基板中，所述阵列基板包括位于所述低温多晶硅薄膜晶体管的有源层和栅极之间的第一绝缘层，所述第一绝缘层包括第一氧化硅层和第一氮化硅层，所述第一氮化硅层图案化形成所述氢离子薄膜中的第一氢离子薄膜。
在本申请实施例提供的阵列基板中，所述阵列基板包括位于所述低温多晶硅薄膜晶体管的栅极和源漏极层之间的第二绝缘层，所述第二绝缘层包括第二氧化硅层和第二氮化硅层，所述第二氮化硅层图案化形成所述氢离子薄膜中的第二氢离子薄膜。
在本申请实施例提供的阵列基板中，所述第二氧化硅层设置于所述金属氧化物半导体薄膜晶体管的栅极和有源层之间。
在本申请实施例提供的阵列基板中，所述阵列基板包括形成于所述衬底上的缓冲层、以及位于所述低温多晶硅薄膜晶体管的栅极和所述第二绝缘层之间的第三绝缘层，所述第一氧化硅层和所述第三绝缘层叠层设置于所述缓冲层和所述金属氧化物半导体薄膜晶体管的栅极之间。
在本申请实施例提供的阵列基板中，所述低温多晶硅薄膜晶体管的有源层设置在所述缓冲层上。
在本申请实施例提供的阵列基板中，所述缓冲层的材料为氧化硅。
在本申请实施例提供的阵列基板中，所述阵列基板还包括存储电容；
所述存储电容的第一电极板与所述低温多晶硅薄膜晶体管的栅极同层设置，所述存储电容的第二电极板与所述金属氧化物半导体薄膜晶体管的栅极同层设置。
在本申请实施例提供的阵列基板中，所述阵列基板还包括保护层；所述第一氧化硅层和所述第一氮化硅层设置于所述缓冲层和所述存储电容的第一电极板之间，所述第三绝缘层设置于所述存储电容的第一电极板和第二电极板之间，所述第二氧化硅层和所述第二氮化硅层设置于所述存储电容的第二电极板和所述保护层之间。
本申请实施例还提供一种阵列基板制备方法，其包括；
提供衬底；
制备薄膜晶体管和氢离子薄膜；其中，所述薄膜晶体管包括形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管，所述氢离子薄膜形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间、且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔。
本申请实施例还提供一种显示装置，其包括显示面板，所述显示面板的阵列基板包括：
衬底；
形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管；以及
氢离子薄膜，形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间，且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔。
在本申请实施例提供的显示装置中，所述阵列基板包括位于所述低温多晶硅薄膜晶体管的有源层和栅极之间的第一绝缘层，所述第一绝缘层包括第一氧化硅层和第一氮化硅层，所述第一氮化硅层图案化形成所述氢离子薄膜中的第一氢离子薄膜。
在本申请实施例提供的显示装置中，所述阵列基板包括位于所述低温多晶硅薄膜晶体管的栅极和源漏极层之间的第二绝缘层，所述第二绝缘层包括第二氧化硅层和第二氮化硅层，所述第二氮化硅层图案化形成所述氢离子薄膜中的第二氢离子薄膜。
在本申请实施例提供的显示装置中，所述第二氧化硅层设置于所述金属氧化物半导体薄膜晶体管的栅极和有源层之间。
在本申请实施例提供的显示装置中，所述阵列基板包括形成于所述衬底上的缓冲层、以及位于所述低温多晶硅薄膜晶体管的栅极和所述第二绝缘层之间的第三绝缘层；所述第一氧化硅层和所述第三绝缘层叠层设置于所述缓冲层和所述金属氧化物半导体薄膜晶体管的栅极之间。
在本申请实施例提供的显示装置中，所述低温多晶硅薄膜晶体管的有源层设置在所述缓冲层上。
在本申请实施例提供的显示装置中，所述缓冲层的材料为氧化硅。
在本申请实施例提供的显示装置中，所述阵列基板还包括存储电容；
所述存储电容的第一电极板与所述低温多晶硅薄膜晶体管的栅极同层设置，所述存储电容的第二电极板与所述金属氧化物半导体薄膜晶体管的栅极同层设置。
在本申请实施例提供的显示装置中，所述阵列基板还包括保护层；所述第一氧化硅层和所述第一氮化硅层设置于所述缓冲层和所述存储电容的第一电极板之间，所述第三绝缘层设置于所述存储电容的第一电极板和第二电极板之间，所述第二氧化硅层和所述第二氮化硅层设置于所述存储电容的第二电极板和所述保护层之间。
在本申请实施例提供的显示装置中，所述显示面板为液晶显示面板或者OLED显示面板。
 有益效果
本申请提供一种阵列基板及制备方法、显示装置，该阵列基板包括形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管，以及氢离子薄膜，氢离子薄膜形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间，且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔；基于该氢离子薄膜所产生的氢元素，与硅原子键结,进而修补前述硅薄膜内的缺陷,改善低温多晶硅薄膜晶体管的电器特性与稳定性，同时氢元素不能扩散到金属氧化物半导体薄膜晶体管的设置区域，进而不会与金属氧化物半导体薄膜晶体管的金属氧化物产生氧空穴，避免金属氧化物半导体薄膜晶体管的电器特性与稳定性受到氢元素影响，缓解了现有技术存在的不同类型薄膜晶体管不能在同一显示面板中长时间稳定工作的技术问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的阵列基板的结构示意图。
图2至图10为本申请实施例提供的阵列基板的制备示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
在附图中，为了清楚表示器件，夸大了层和区域的厚度。相同的标号在整个说明书和附图中表示相同的元器件。
针对现有技术存在的不同类型薄膜晶体管不能在同一显示面板中长时间稳定工作的技术问题，本申请实施例可以缓解。
在一种实施例中，如图1所示，本申请实施例提供的阵列基板10包括：
衬底M100；
形成于所述衬底M100上方的低温多晶硅薄膜晶体管200和金属氧化物半导体薄膜晶体管300；以及
氢离子薄膜400，形成于所述低温多晶硅薄膜晶体管200的有源层201和源漏极层203之间，且在所述金属氧化物半导体薄膜晶体管300的设置区域内形成开孔。
在低温多晶硅薄膜晶体管的制备工艺中, 非晶硅并非完美的结晶, 硅薄膜内部有许多硅空隙（Si vacancy）、晶界(grain boundary boundary)、缺排(dislocation)等缺陷, 这些缺陷将严重影响薄膜晶体管的电气特性和稳定性，针对该缺陷，本申请实施例在多晶硅薄膜的上下方沉积含有大量的氢元素【H】的氢离子薄膜，如氮化硅（SiNx-H）薄膜, 在后续的高温工艺中,氢元素将会扩散到多晶硅薄膜内与硅原子键结,进而修补前述硅薄膜内的缺陷,改善低温多晶硅薄膜晶体管的电器特性与稳定性。
但是对于金属氧化物半导体薄膜晶体管而言,氢原子同样会扩散到金属氧化物薄膜内(例如铟镓锌氧化物等)，还原金属氧化物产生氧空穴,而氧空穴会影响金属氧化物半导体薄膜晶体管的导电性,导致金属氧化物电气特性偏移,针对此问题，本申请实施例中的氢离子薄膜在金属氧化物半导体薄膜晶体管的设置区域内形成开孔，金属氧化物半导体薄膜晶体管周围并无氮化硅等氢离子薄膜, 可以确保金属氧化物主动层（即有源层）不会受到氢原子影响而改变金属氧化物半导体薄膜晶体管电气特性。
本实施例提供了一种阵列基板，该阵列基板包括形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管，以及氢离子薄膜，氢离子薄膜形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间，且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔；基于该氢离子薄膜所产生的氢元素，与硅原子键结,进而修补前述硅薄膜内的缺陷,改善低温多晶硅薄膜晶体管的电器特性与稳定性，同时氢元素不能扩散到金属氧化物半导体薄膜晶体管的设置区域，进而不会与金属氧化物半导体薄膜晶体管的金属氧化物产生氧空穴，避免金属氧化物半导体薄膜晶体管的电器特性与稳定性受到氢元素影响，缓解了现有技术存在的不同类型薄膜晶体管不能在同一显示面板中长时间稳定工作的技术问题。
在一种实施例中，如图1所示，在本申请实施例提供的阵列基板中，所述阵列基板10包括位于所述低温多晶硅薄膜晶体管200的有源层201和栅极202之间的第一绝缘层500，所述第一绝缘层500包括层叠设置的第一氧化硅层M103和第一氮化硅层M104，所述第一氮化硅层M104图案化形成所述氢离子薄膜400中的第一氢离子薄膜。
在一种实施例中，如图1所示，在本申请实施例提供的阵列基板中，所述阵列基板10包括位于所述低温多晶硅薄膜晶体管200的栅极202和源漏极层203之间的第二绝缘层600，所述第二绝缘层600包括第二氧化硅层M108和第二氮化硅层M109，所述第二氮化硅层M109图案化形成所述氢离子薄膜400中的第二氢离子薄膜。
在一种实施例中，如图1所示，在本申请实施例提供的阵列基板中，所述第二氧化硅层M108设置于所述金属氧化物半导体薄膜晶体管300的栅极301和有源层302之间。
在一种实施例中，如图1所示，在本申请实施例提供的阵列基板中，所述阵列基板10包括形成于所述衬底上的缓冲层M101、以及位于所述低温多晶硅薄膜晶体管200的栅极202和所述第二绝缘层600之间的第三绝缘层M106，所述第一氧化硅层M103和所述第三绝缘层M106叠层设置于所述缓冲层M101和所述金属氧化物半导体薄膜晶体管300的栅极301之间。
在一种实施例中，所述第三绝缘层M106的材料为氧化硅，以降低材料复杂度。
在一种实施例中，如图1所示，在本申请实施例提供的阵列基板中，所述低温多晶硅薄膜晶体管200的有源层201设置在所述缓冲层上M101。
在一种实施例中，在本申请实施例提供的阵列基板中，所述缓冲层M101的材料为氧化硅，以降低材料复杂度。
在一种实施例中，如图1所示，在本申请实施例提供的阵列基板中，所述阵列基板10还包括存储电容700；
所述存储电容700的第一电极板701与所述低温多晶硅薄膜晶体管200的栅极202同层设置，所述存储电容700的第二电极板702与所述金属氧化物半导体薄膜晶体管300的栅极301同层设置。
在一种实施例中，如图1所示，在本申请实施例提供的阵列基板中，所述阵列基板10还包括保护层M112；所述第一氧化硅层M103和所述第一氮化硅层M104设置于所述缓冲层M101和所述存储电容700的第一电极板701之间，所述第三绝缘层M106设置于所述存储电容700的第一电极板701和第二电极板702之间，所述第二氧化硅层M108和所述第二氮化硅层M109设置于所述存储电容700的第二电极板702和所述保护层M112之间。
在一种实施例中，在本申请实施例提供的阵列基板中，所述保护层M112的材料为氧化硅，以降低材料复杂度。
在一种实施例中，多晶硅层M102图案化形成低温多晶硅薄膜晶体管200的有源层201。
在一种实施例中，第一金属层M105图案化形成低温多晶硅薄膜晶体管200的栅极202、以及存储电容700的第一电极板701。
在一种实施例中，第二金属层M107图案化形成存储电容700的第二电极板702、以及金属氧化物半导体薄膜晶体管300的栅极301。
在一种实施例中，第一金属层M105和第二金属层M107的材料为铜、或者钛铝钛合金等。
在一种实施例中，金属氧化物层M110图案化形成金属氧化物半导体薄膜晶体管300的有源层302。
在一种实施例中，源漏极层M111图案化形成低温多晶硅薄膜晶体管200的源漏极203、以及金属氧化物半导体薄膜晶体管300的源漏极303。
在一种实施例中，本申请还提供了一种显示装置，该显示装置包括显示面板，该显示面板的阵列基板包括：
衬底；
形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管；以及
氢离子薄膜，形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间，且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔。
在一种实施例中，在本申请实施例提供的显示装置中，所述阵列基板包括位于所述低温多晶硅薄膜晶体管的有源层和栅极之间的第一绝缘层，所述第一绝缘层包括第一氧化硅层和第一氮化硅层，所述第一氮化硅层图案化形成所述氢离子薄膜中的第一氢离子薄膜。
在一种实施例中，在本申请实施例提供的显示装置中，所述阵列基板包括位于所述低温多晶硅薄膜晶体管的栅极和源漏极层之间的第二绝缘层，所述第二绝缘层包括第二氧化硅层和第二氮化硅层，所述第二氮化硅层图案化形成所述氢离子薄膜中的第二氢离子薄膜。
在一种实施例中，在本申请实施例提供的显示装置中，所述第二氧化硅层设置于所述金属氧化物半导体薄膜晶体管的栅极和有源层之间。
在一种实施例中，在本申请实施例提供的显示装置中，所述阵列基板包括形成于所述衬底上的缓冲层、以及位于所述低温多晶硅薄膜晶体管的栅极和所述第二绝缘层之间的第三绝缘层，所述第一氧化硅层和所述第三绝缘层叠层设置于所述缓冲层和所述金属氧化物半导体薄膜晶体管的栅极之间。
在一种实施例中，在本申请实施例提供的显示装置中，所述低温多晶硅薄膜晶体管的有源层设置在所述缓冲层上。
在一种实施例中，在本申请实施例提供的显示装置中，所述缓冲层的材料为氧化硅。
在一种实施例中，在本申请实施例提供的显示装置中，所述阵列基板还包括存储电容；
所述存储电容的第一电极板与所述低温多晶硅薄膜晶体管的栅极同层设置，所述存储电容的第二电极板与所述金属氧化物半导体薄膜晶体管的栅极同层设置。
在一种实施例中，在本申请实施例提供的显示装置中，所述阵列基板还包括保护层；所述第一氧化硅层和所述第一氮化硅层设置于所述缓冲层和所述存储电容的第一电极板之间，所述第三绝缘层设置于所述存储电容的第一电极板和第二电极板之间，所述第二氧化硅层和所述第二氮化硅层设置于所述存储电容的第二电极板和所述保护层之间。
在一种实施例中，在本申请实施例提供的显示装置中，所述显示面板为液晶显示面板或者OLED显示面板。
为了制备得到上述实施例中的阵列基板，本申请实施例还提供了一种阵列基板制备方法，该阵列基板制备方法包括以下步骤：
步骤一、提供衬底，如玻璃板、透明柔性基材等；
步骤二、制备薄膜晶体管和氢离子薄膜；其中，所述薄膜晶体管包括形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管，所述氢离子薄膜形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间、且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔。
本实施例提供了一种阵列基板制备方法，其得到的阵列基板包括形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管，以及氢离子薄膜，氢离子薄膜形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间，且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔；基于该氢离子薄膜所产生的氢元素，与硅原子键结,进而修补前述硅薄膜内的缺陷,改善低温多晶硅薄膜晶体管的电器特性与稳定性，同时氢元素不能扩散到金属氧化物半导体薄膜晶体管的设置区域，进而不会与金属氧化物半导体薄膜晶体管的金属氧化物产生氧空穴，避免金属氧化物半导体薄膜晶体管的电器特性与稳定性受到氢元素影响，缓解了现有技术存在的不同类型薄膜晶体管不能在同一显示面板中长时间稳定工作的技术问题。
在一种实施例中，本申请实施例提供的阵列基板制备方法包括以下步骤：
步骤A、在衬底M100上沉积氧化硅薄膜作为缓冲层M101，并在缓冲层M101上方沉积非晶硅薄膜，使用高温去除非晶硅薄膜内的氢原子，经过清洗制程清洁非晶硅薄膜表面, 使用激光将非晶硅薄膜结晶为多晶硅层M102。采用黄光、蚀刻制程制作多晶硅硅岛201，去除光阻后, 使用离子注入等制程调节薄膜晶体管的阈值电压；再次使用黄光制程定义出沟道区域与源极区域和漏极区域，利用离子注入等制程制作重掺杂的源极区域和漏极区域，去除光阻。
执行本步骤A之后，得到如图2所示的结构。
步骤B、在多晶硅硅岛201上方沉积栅极绝缘层（即上文中的第一绝缘层500），栅极绝缘层由下往上依序包含第一氧化硅层M103以及第一氮化硅层M104两层薄膜。
执行本步骤B之后，得到如图3所示的结构。
步骤C、在栅极绝缘层上方沉积第一金属层M105，并使用黄光/蚀刻制程定义出所需要的第一金属层图案，包括栅极202和第一电极板701。在蚀刻第一金属层同时, 调节干式蚀刻的工艺参数，将第一金属层图案底下以外的第一氮化硅层M104蚀刻去除，去除光阻。
执行本步骤C之后，得到如图4所示的结构。
步骤D、在制作好的第一金属层图案上方沉积氧化硅层作为储存电容700两个电极板中间的介电夹层（即上文中的第三绝缘层M106）。
执行本步骤D之后，得到如图5所示的结构。
步骤E、在介电夹层上方沉积第二金属层M107，并使用黄光/蚀刻工艺定义出第二金属层图案，包括第二电极板702和栅极301，去除光阻。
执行本步骤E之后，得到如图6所示的结构。
步骤F、在第二金属层图案上方依序沉积第二氧化硅层M108以及第二氮化硅层M109两层介电层（即上文中的第二绝缘层600），此介电层位于栅极202与源漏极金属层M111之间。
执行本步骤F之后，得到如图7所示的结构。
步骤G、使用灰阶光罩制作出图8的光阻图案，第一部分为连结多晶硅的过孔，此部份将过孔的光阻全部曝光/显影去除。第二部分为栅极301上方的光阻, 此部份是灰阶光罩的区域, 只将部分厚度的光阻去除。
执行本步骤G之后，得到如图8所示的结构。
步骤H、将图8制作好光阻的阵列基板进行干式蚀刻，将有源层201的过孔蚀刻开，同时也将金属氧化物半导体薄膜晶体管上方的第二氮化硅层M109蚀刻去除，去除光阻。
执行本步骤H之后，得到如图9所示的结构。
步骤I、在图9的结构上沉积金属氧化物薄膜(IGZO)层M110，并使用黄光/蚀刻制程定义出氧化物金属主动层的图案, 去除光阻后在上方沉积源漏极金属层M111, 并使用黄光/蚀刻制程定义出源漏极图案（包括源漏极203和源漏极303），去除光阻后在源漏极图案上方沉积氧化硅层作为保护层M112。
执行本步骤I之后，得到如图10所示的结构。
如此薄膜晶体管器件结构已经完成，后续上方可以依据OLED或是LCD显示器的需求制作不同的结构在此不赘述。
根据上述实施例可知：
本申请实施例提供一种阵列基板及制备方法、显示装置，该阵列基板包括形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管，以及氢离子薄膜，氢离子薄膜形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间，且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔；基于该氢离子薄膜所产生的氢元素，与硅原子键结,进而修补前述硅薄膜内的缺陷,改善低温多晶硅薄膜晶体管的电器特性与稳定性，同时氢元素不能扩散到金属氧化物半导体薄膜晶体管的设置区域，进而不会与金属氧化物半导体薄膜晶体管的金属氧化物产生氧空穴，避免金属氧化物半导体薄膜晶体管的电器特性与稳定性受到氢元素影响，缓解了现有技术存在的不同类型薄膜晶体管不能在同一显示面板中长时间稳定工作的技术问题。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，其包括：
    衬底；
    形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管；以及
    氢离子薄膜，形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间，且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔。
  2. 如权利要求1所述的阵列基板，其中，所述阵列基板包括位于所述低温多晶硅薄膜晶体管的有源层和栅极之间的第一绝缘层，所述第一绝缘层包括第一氧化硅层和第一氮化硅层，所述第一氮化硅层图案化形成所述氢离子薄膜中的第一氢离子薄膜。
  3. 如权利要求2所述的阵列基板，其中，所述阵列基板包括位于所述低温多晶硅薄膜晶体管的栅极和源漏极层之间的第二绝缘层，所述第二绝缘层包括第二氧化硅层和第二氮化硅层，所述第二氮化硅层图案化形成所述氢离子薄膜中的第二氢离子薄膜。
  4. 如权利要求3所述的阵列基板，其中，所述第二氧化硅层设置于所述金属氧化物半导体薄膜晶体管的栅极和有源层之间。
  5. 如权利要求3所述的阵列基板，其中，所述阵列基板包括形成于所述衬底上的缓冲层、以及位于所述低温多晶硅薄膜晶体管的栅极和所述第二绝缘层之间的第三绝缘层；所述第一氧化硅层和所述第三绝缘层叠层设置于所述缓冲层和所述金属氧化物半导体薄膜晶体管的栅极之间。
  6. 如权利要求5所述的阵列基板，其中，所述低温多晶硅薄膜晶体管的有源层设置在所述缓冲层上。
  7. 如权利要求5所述的阵列基板，其中，所述缓冲层的材料为氧化硅。
  8. 如权利要求5所述的阵列基板，其中，所述阵列基板还包括存储电容；
    所述存储电容的第一电极板与所述低温多晶硅薄膜晶体管的栅极同层设置，所述存储电容的第二电极板与所述金属氧化物半导体薄膜晶体管的栅极同层设置。
  9. 如权利要求8所述的阵列基板，其中，所述阵列基板还包括保护层；所述第一氧化硅层和所述第一氮化硅层设置于所述缓冲层和所述存储电容的第一电极板之间，所述第三绝缘层设置于所述存储电容的第一电极板和第二电极板之间，所述第二氧化硅层和所述第二氮化硅层设置于所述存储电容的第二电极板和所述保护层之间。
  10. 一种阵列基板制备方法，其包括；
    提供衬底；
    制备薄膜晶体管和氢离子薄膜；其中，所述薄膜晶体管包括形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管，所述氢离子薄膜形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间、且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔。
  11. 一种显示装置，其包括显示面板，所述显示面板的阵列基板包括：
    衬底；
    形成于所述衬底上方的低温多晶硅薄膜晶体管和金属氧化物半导体薄膜晶体管；以及
    氢离子薄膜，形成于所述低温多晶硅薄膜晶体管的有源层和源漏极层之间，且在所述金属氧化物半导体薄膜晶体管的设置区域内形成开孔。
  12. 如权利要求11所述的显示装置，其中，所述阵列基板包括位于所述低温多晶硅薄膜晶体管的有源层和栅极之间的第一绝缘层，所述第一绝缘层包括第一氧化硅层和第一氮化硅层，所述第一氮化硅层图案化形成所述氢离子薄膜中的第一氢离子薄膜。
  13. 如权利要求12所述的显示装置，其中，所述阵列基板包括位于所述低温多晶硅薄膜晶体管的栅极和源漏极层之间的第二绝缘层，所述第二绝缘层包括第二氧化硅层和第二氮化硅层，所述第二氮化硅层图案化形成所述氢离子薄膜中的第二氢离子薄膜。
  14. 如权利要求13所述的显示装置，其中，所述第二氧化硅层设置于所述金属氧化物半导体薄膜晶体管的栅极和有源层之间。
  15. 如权利要求13所述的显示装置，其中，所述阵列基板包括形成于所述衬底上的缓冲层、以及位于所述低温多晶硅薄膜晶体管的栅极和所述第二绝缘层之间的第三绝缘层；所述第一氧化硅层和所述第三绝缘层叠层设置于所述缓冲层和所述金属氧化物半导体薄膜晶体管的栅极之间。
  16. 如权利要求15所述的显示装置，其中，所述低温多晶硅薄膜晶体管的有源层设置在所述缓冲层上。
  17. 如权利要求15所述的显示装置，其中，所述缓冲层的材料为氧化硅。
  18. 如权利要求15所述的显示装置，其中，所述阵列基板还包括存储电容；
    所述存储电容的第一电极板与所述低温多晶硅薄膜晶体管的栅极同层设置，所述存储电容的第二电极板与所述金属氧化物半导体薄膜晶体管的栅极同层设置。
  19. 如权利要求18所述的显示装置，其中，所述阵列基板还包括保护层；所述第一氧化硅层和所述第一氮化硅层设置于所述缓冲层和所述存储电容的第一电极板之间，所述第三绝缘层设置于所述存储电容的第一电极板和第二电极板之间，所述第二氧化硅层和所述第二氮化硅层设置于所述存储电容的第二电极板和所述保护层之间。
  20. 如权利要求11所述的显示装置，其中，所述显示面板为液晶显示面板或者OLED显示面板。
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