WO2020215404A1 - 阵列基板及其制造方法、显示面板 - Google Patents

阵列基板及其制造方法、显示面板 Download PDF

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Publication number
WO2020215404A1
WO2020215404A1 PCT/CN2019/087140 CN2019087140W WO2020215404A1 WO 2020215404 A1 WO2020215404 A1 WO 2020215404A1 CN 2019087140 W CN2019087140 W CN 2019087140W WO 2020215404 A1 WO2020215404 A1 WO 2020215404A1
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Prior art keywords
light
shielding conductive
layer
substrate
array substrate
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PCT/CN2019/087140
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English (en)
French (fr)
Inventor
聂晓辉
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武汉华星光电技术有限公司
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Priority to US16/608,129 priority Critical patent/US11335711B2/en
Publication of WO2020215404A1 publication Critical patent/WO2020215404A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14616—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor characterised by the channel of the transistor, e.g. channel having a doping gradient
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate, a manufacturing method thereof, and a display panel.
  • LTPS-TFT Low Temperature Poly Silicon Thin Film Transistor
  • LTPS-TFT Low Temperature Poly Silicon Thin Film Transistor
  • the gate scanning line voltage of progressive scanning is lower than the threshold voltage of the TFT, the conductive channel of the TFT is in a cut-off state, and the pixel circuit is in the off state; when the progressive scanning gate
  • the scan line voltage is higher than the TFT threshold voltage, the TFT conduction channel is in the on state, and the information voltage connected from the source is loaded on the pixel (drain) circuit and the storage capacitor, and the pixel circuit is in the on state; scanning is complete After the pixel row TFTs are all closed, the information voltage that has been written remains unchanged, and the information is rewritten until the next frame is scanned.
  • the metal impedance of the gate scan line determines the power consumption of the driving circuit and the pixel charge and discharge response speed.
  • the aperture ratio of the Crystal Display (LCD) and the metal line width of the gate scan line are generally designed to be small, which leads to a large metal impedance and a significant increase in LCD driving power consumption.
  • the purpose of the present application is to provide an array substrate, a manufacturing method thereof, and a display panel.
  • the gate scanning lines of the array substrate are electrically connected to the light-shielding conductive layer, so that the array substrate has a high aperture ratio, and the display panel has a driving function during operation. Consumption is reduced.
  • a plurality of gate scan lines formed on the first insulating layer and directly above the light-shielding conductive layer;
  • the gate scan line is electrically connected to the light-shielding conductive layer.
  • the light-shielding conductive layer includes a plurality of light-shielding conductive lines, and each of the light-shielding conductive lines and each of the gate scanning lines pass through the buffer layer and the first insulating line one to one. At least two vias of the layer are electrically connected.
  • the orthographic projection of each of the gate scanning lines on the substrate and corresponding to each of the light-shielding conductive lines electrically connected to the gate scanning lines on the substrate coincide.
  • the size of the via hole along the first direction is larger than the width of the gate scan line, and the first direction is a direction perpendicular to the gate scan line.
  • the channel layer includes a plurality of interdigitated semiconductor members arranged in an array, and at least one via hole is respectively provided on two opposite sides of each of the interdigitated semiconductor members.
  • each of the via holes includes a first connection hole penetrating the buffer layer and the second connection hole penetrating the first insulating layer, and the first connection hole and the second connection hole The connecting hole is connected.
  • the orthographic projection of the second connecting hole on the substrate is located within the orthographic projection of the first connecting hole on the substrate.
  • the preparation material of the light-shielding conductive layer is the same as the preparation material of the gate scan line.
  • a manufacturing method of an array substrate includes the following steps:
  • the gate scan line is electrically connected to the light-shielding conductive layer.
  • the light-shielding conductive layer includes a plurality of light-shielding conductive lines, and each of the light-shielding conductive lines and each of the gate scanning lines pass through the buffer layer and the At least two vias of the first insulating layer are electrically connected.
  • the orthographic projection of each of the gate scan lines on the substrate and each of the light-shielding conductive lines electrically connected to the gate scan lines on the substrate coincide.
  • the size of the via hole along the first direction is greater than the width of the gate scan line, and the first direction is a direction perpendicular to the gate scan line.
  • the channel layer includes a plurality of interdigitated semiconductor members arranged in an array, and at least one of the via holes is respectively provided on opposite sides of each of the interdigitated semiconductor members.
  • each of the via holes includes a first connection hole penetrating the buffer layer and the second connection hole penetrating the first insulating layer, and the first connection hole is connected to the The second connecting hole communicates.
  • the orthographic projection of the second connecting hole on the substrate is located within the orthographic projection of the first connecting hole on the substrate.
  • a display panel the display panel includes an array substrate, and the array substrate includes:
  • a plurality of gate scan lines formed on the first insulating layer and directly above the light-shielding conductive layer;
  • the gate scan line is electrically connected to the light-shielding conductive layer.
  • the light-shielding conductive layer includes a plurality of light-shielding conductive lines, and each of the light-shielding conductive lines and each of the gate scanning lines pass through the buffer layer and the first insulating line one-to-one. At least two vias of the layer are electrically connected.
  • the orthographic projection of each of the gate scan lines on the substrate and the corresponding to each of the light-shielding conductive lines electrically connected to the gate scan lines on the substrate coincide.
  • the size of the via hole along the first direction is greater than the width of the gate scan line, and the first direction is a direction perpendicular to the gate scan line.
  • the channel layer includes a plurality of interdigitated semiconductor members arranged in an array, and at least one of the via holes is respectively provided on two opposite sides of each of the interdigitated semiconductor members.
  • the present application provides an array substrate, a manufacturing method thereof, and a display panel.
  • the gate scanning line is electrically connected to the light-shielding conductive layer, so that the width of the gate scanning line is basically unchanged compared with the conventional technology to ensure the opening of the display panel.
  • the impedance of the wire used to transmit the scanning electrical signal is reduced, so that the driving power consumption of the display panel is reduced, and the corresponding speed of pixel charging and discharging is improved.
  • FIG. 1 is a schematic plan view of an array substrate according to the first embodiment of the application.
  • FIG. 2 is a schematic cross-sectional view taken along the A-A tangent line of the array substrate shown in FIG. 1;
  • FIG. 3 is a schematic plan view of an array substrate according to a second embodiment of the application.
  • FIG. 4 is a schematic cross-sectional view taken along the line A-A of the array substrate shown in FIG. 3;
  • FIG. 5 is a flowchart of the manufacturing method of the array substrate according to the first embodiment of the application.
  • FIG. 1 is a schematic plan view of the array substrate according to the first embodiment of the application
  • FIG. 2 is a schematic cross-sectional view taken along the A-A line of the array substrate shown in FIG.
  • the array substrate 100 is a thin film transistor array substrate, that is, a plurality of thin film transistors (not shown) are arranged in a distributed array on the substrate 10.
  • the array substrate 100 includes a substrate 10, a light-shielding conductive layer 11, a buffer layer 12, a channel layer 13, a first insulating layer 14, a gate scan line 15 and a via hole 16.
  • the substrate 10 may be a glass substrate or a flexible substrate.
  • the light-shielding conductive layer 11 is used to prevent the backlight from irradiating the channel 1311 of the channel layer 13, thereby avoiding the problem of photo-generated leakage current in the channel 1311.
  • the light-shielding conductive layer 11 is formed on the substrate 10, and the light-shielding conductive layer 11 includes a plurality of light-shielding conductive wires 111, and the multiple light-shielding conductive wires 111 are arranged in parallel.
  • the width D1 of each light-shielding conductive line 111 is greater than the width d of the channel 1311 of each interdigitated semiconductor member 131 in the channel layer 13 to prevent the backlight from irradiating the channel 1311.
  • each light-shielding conductive line 111 is electrically connected to each gate scan line 15 through at least two vias 16 penetrating the buffer layer 12 and the first insulating layer 14 one-to-one.
  • the material for preparing the light-shielding conductive layer 11 is at least one of molybdenum, aluminum, titanium, and copper.
  • the preparation material 11 of the light-shielding conductive layer 11 is the same as the preparation material of the gate scan line 15.
  • the buffer layer 12 is used to prevent metal ions (aluminum, barium, sodium, etc.) in the substrate 10 from diffusing into the channel 1311 in the channel layer 13 during the thermal process, thereby affecting the electrical performance of the thin film transistor.
  • the buffer layer 12 covers the substrate 10 and the light-shielding conductive layer 11.
  • the buffer layer 12 is a silicon oxide layer and a silicon nitride layer covering the light-shielding conductive layer 11 and the substrate 10, and the silicon nitride layer is located on the side close to the substrate 10.
  • the thickness of the buffer layer 12 is 3000-4000 angstroms.
  • the buffer layer 12 is prepared by chemical vapor deposition.
  • the channel layer 13 is formed on the buffer layer 12.
  • the channel layer 13 includes a plurality of interdigitated semiconductor members 131 arranged in an array.
  • the plurality of interdigitated semiconductor members 131 are located above the plurality of light-shielding conductive wires 111.
  • the plurality of interdigital semiconductor members 131 are arranged in multiple rows, each interdigital semiconductor member 131 is of an interdigital type, and each interdigital semiconductor member 131 has two channels 1311 in the same line, so as to reduce the time when the thin film transistor is in the off state. Leakage current.
  • Each interdigital semiconductor member 131 has a source contact area and a drain contact area for electrical contact with a source electrode (not shown) and a drain electrode (not shown), respectively.
  • the channel layer 13 is made of polysilicon.
  • the preparation material of the channel layer 13 may also be one of metal oxide semiconductor or single crystal silicon.
  • the channel layer 13 is formed by chemical vapor deposition to form an entire surface of amorphous silicon, and then through an excimer laser annealing process to convert the amorphous silicon into polysilicon, and then go through a yellow light process to pattern the polysilicon to form multiple arrays. Interdigital semiconductor components.
  • the first insulating layer 14 is a gate insulating layer.
  • the first insulating layer 14 covers the buffer layer 12 and the channel layer 13.
  • the first insulating layer 14 is a silicon nitride layer. It can be understood that the first insulating layer 14 may also be a silicon oxide layer or a stack of a silicon oxide layer and a silicon nitride layer.
  • the thickness of the first insulating layer 14 is 1000-1500 angstroms.
  • the first insulating layer 14 is prepared by chemical vapor deposition.
  • the gate scanning line 15 is used to transmit scanning electrical signals to control the working state of the thin film transistor.
  • the gate scan line 15 is formed on the first insulating layer 14 and directly above the light-shielding conductive layer 11.
  • the gate scan line 15 is also formed in the via hole 16 to electrically connect the gate scan line 15 on the first insulating layer 14 and the light-shielding conductive layer 11.
  • the gate scan line 15 includes a plurality of parallel metal lines.
  • the width of each gate scan line 15 is equal to the width d of the channel 1311, that is, the width d of each gate scan line 15 is smaller than the width D1 of each conductive shading line 111. Specifically, the width of each gate scan line 15 is 3 ⁇ 0.1 microns.
  • the gate scan line 15 is electrically connected to the light-shielding conductive layer 11, so that when the width of the gate scan line 15 is basically unchanged compared to the conventional technology, the wires used to transmit the scanning electric signal (including the gate scan line 15 and the conductive light-shielding layer)
  • the effective area of the layer 11) is increased, which significantly reduces the resistance of the wires used to transmit the scanning electrical signal, reduces the power consumption of the scanning driving circuit, and improves the speed of the charge and discharge response of the pixel (not shown).
  • the via hole 16 is used to electrically connect the gate scan line 15 and the light-shielding conductive layer 11.
  • the via hole 16 penetrates the buffer layer 12 and the first insulating layer 14.
  • At least one via 16 is provided on opposite sides of each interdigital semiconductor member 131 to improve the yield of the electrical connection between each light-shielding conductive line 111 and the corresponding gate scan line 15, and a plurality of vias 16
  • the overall resistance of the wire (the gate scan line located in the via hole 16) connecting the gate scan line 15 and the light-shielding conductive layer 11 can be reduced.
  • each interdigitated semiconductor member 131 is provided with a via hole 16 on opposite sides respectively.
  • a via hole 16 is provided between two adjacent interdigitated semiconductor members 131.
  • the vias 16 are distributed periodically.
  • a full-surface photoresist is formed on the first insulating layer 14, and then a part of the photoresist is exposed by the photomask to etch the first insulating layer 14 that is not covered by the photoresist and the buffer Layer 12 to form via 16.
  • the dimension D2 of the via hole 16 along the first direction is greater than the width D1 of the gate scan line.
  • the first direction is a direction perpendicular to the gate scan line 15 (gate scan line extension direction).
  • the first direction is arranged with the substrate 10
  • the planes of the gate scan lines are parallel, so that the gate scan line 15 in each via 16 is in full contact with the light-shielding conductive layer 11, thereby reducing the impedance of the gate scan line 15 formed in the via 16.
  • the via hole 16 may be circular, and the radius of the via hole 16 is larger than the width of the gate scan line 15.
  • the via hole 16 may also be a square, and the side length of the via hole 16 is larger than the width of the gate scan line 15.
  • FIG. 3 is a schematic plan view of the array substrate according to the second embodiment of the application
  • FIG. 4 is a schematic cross-sectional view taken along the line A-A of the array substrate shown in FIG.
  • the array substrate 100 shown in FIG. 3 is basically similar to the array substrate 100 shown in FIG. 1, except that the orthographic projection of each gate scan line 15 on the substrate 10 corresponds to the one electrically connected to the gate scan line 10.
  • each gate scanning line 15 is the same as each light-shielding conductive line 111 electrically connected to the gate scanning line 15 (including the gate scanning line 15
  • the width d and the width D1 of the light-shielding conductive line 111 are the same) to ensure that the light-shielding conductive line 111 plays a light-shielding function and further improves the aperture ratio of the display panel made of the array substrate.
  • each via hole 16 includes a first connection hole 121 penetrating the buffer layer 12 and a second connection hole 141 penetrating the first insulating layer 14.
  • the first connection hole 121 communicates with the second connection hole 141, and the second connection hole 141
  • the orthographic projection on the substrate 10 is located within the orthographic projection of the first connecting hole 121 on the substrate 10, that is, the size of the first connecting hole 121 is larger than the size of the second connecting hole 141 to ensure that the second connecting hole 141 can be formed. It communicates with the first connection hole 121.
  • the first connecting hole 121 is formed after the buffer layer 12 is formed, and then the buffer layer 12 is processed by a yellow light process.
  • the second connection hole 141 is formed after the first insulating layer 14 is formed, and then the first insulating layer 14 is processed by a yellow light process.
  • the size of the second connection hole 141 along the first direction is greater than the width of each gate scan line 15, and the first direction is a direction perpendicular to the gate scan line 15.
  • the array substrate of the present application electrically connects the gate scanning line and the light-shielding conductive layer, so that the width of the gate scanning line is basically unchanged compared with the conventional technology to ensure the aperture ratio of the display panel, and is used for transmitting scanning electrical signals.
  • the impedance of the wires is reduced, so that the driving power consumption of the display panel is reduced, and the corresponding speed of pixel charging and discharging is improved.
  • FIG. 5 is a flowchart of the manufacturing method of the array substrate according to the first embodiment of the application.
  • the manufacturing method of the array substrate includes the following steps:
  • S15 forming a plurality of gate scan lines on the first insulating layer, the plurality of gate scan lines are located directly above the light-shielding conductive layer, and the gate scan lines and the light-shielding conductive layer are electrically connected.
  • the manufacturing method of the array substrate of the present application electrically connects the gate scan line and the light-shielding conductive layer, so that the width of the gate scan line is basically unchanged compared with the conventional technology to ensure the aperture ratio of the display panel, and is used for transmission scan
  • the wire impedance of the electrical signal is reduced, so that the driving power consumption of the display panel is reduced, and the corresponding speed of pixel charging and discharging is improved.
  • the light-shielding conductive layer includes a plurality of light-shielding conductive lines, and each light-shielding conductive line is electrically connected to each gate scanning line one-to-one through at least two vias penetrating the buffer layer and the first insulating layer. .
  • the orthographic projection of each gate scanning line on the substrate coincides with the orthographic projection of each light-shielding conductive line electrically connected to the gate scanning line on the substrate to ensure that the light-shielding conductive line rises. While shielding the light, the aperture ratio of the display panel made of the array substrate is further improved.
  • the size of the via hole along the first direction is larger than the width of the gate scan line, and the first direction is a direction perpendicular to the gate scan line, so that the gate scan line in each via hole is conductive to light.
  • the layers are in full contact, thereby reducing the resistance of the gate scan line formed in the via hole.
  • This application also provides a display panel, which is a liquid crystal display panel or an organic light emitting diode display panel.
  • the display panel includes the above-mentioned array substrate.
  • the display panel of the present application electrically connects the gate scan line of the array substrate and the light-shielding conductive layer, so that the width of the gate scan line is basically unchanged compared with the conventional technology to ensure the aperture ratio of the display panel, and is used for transmission scan
  • the impedance of the electrical signal wires is reduced, so that the driving power consumption of the display panel is reduced, and the corresponding speed of pixel charging and discharging is improved.

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Abstract

本申请提供一种阵列基板及其制造方法、显示面板，通过使栅极扫描线和遮光导电层电性连接，以使栅极扫描线的宽度相对于传统技术基本不变以保证显示面板的开口率的同时，用于传输扫描电信号的导线的阻抗减小，从而使得显示面板的驱动功耗减小，提高像素充放电的相应速度。

Description

阵列基板及其制造方法、显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制造方法、显示面板。
 背景技术
低温多晶硅薄膜晶体管（Low Temperature Poly Silicon Thin Film Transistor，LTPS-TFT）具有制备温度低、载流子迁移率高以及器件尺寸小等突出优点，是发展低功耗以及高集成度显示面板的关键技术。基于矩阵显示逐行扫描的原理，当逐行扫描的栅极扫描线电压低于TFT的阈值电压时，TFT的导电沟道处于截断状态，此时像素电路处于关态；当逐行扫描的栅极扫描线电压高于TFT阈值电压时，TFT导电沟道处于导通状态，由源极接入的信息电压将加载到像素（漏极）电路和存储电容上，像素电路处于开态；扫描完成后像素行TFT全部关闭，已经写入的信息电压保持不变，直到下一帧扫描到时再重新写入信息。栅极扫描线金属阻抗决定了驱动电路的功耗大小和像素充放电响应速度。在实际生产过程中，为保证液晶显示面板(Liquid Crystal Display，LCD)的开口率，栅极扫描线金属线宽一般设计较小，导致金属阻抗较大，LCD驱动功耗的显著增加。
因此，有必要提出一种技术方案以解决扫描金属线的阻抗较大导致LCD的驱动功耗增加的问题。
 技术问题
本申请的目的在于提供一种阵列基板及其制造方法、显示面板，该阵列基板的栅极扫描线和遮光导电层电性连接，使得阵列基板具有高开口率的同时，显示面板工作时驱动功耗减小。
 技术解决方案
一种阵列基板，所述阵列基板包括：
一衬底；
形成于所述衬底上的遮光导电层；
覆盖所述衬底和所述遮光导电层的缓冲层；
形成于所述缓冲层上的沟道层；
覆盖所述缓冲层和所述沟道层的第一绝缘层；
形成于所述第一绝缘层上且位于所述遮光导电层正上方的多条栅极扫描线；
其中，所述栅极扫描线和所述遮光导电层电性连接。
在上述阵列基板中，所述遮光导电层包括多条遮光导电线，每条所述遮光导电线与每条所述栅极扫描线一对一地通过贯穿所述缓冲层和所述第一绝缘层的至少两个过孔电性连接。
在上述阵列基板中，每条所述栅极扫描线在所述衬底上的正投影和对应与所述栅极扫描线电性连接的每条所述遮光导电线在所述衬底上的正投影重合。
在上述阵列基板中，所述过孔沿第一方向的尺寸大于所述栅极扫描线的宽度，所述第一方向为垂直于所述栅极扫描线的方向。
在上述阵列基板中，所述沟道层包括多个阵列排布的叉指半导体构件，每个所述叉指半导体构件相对的两侧均分别设置有至少一所述过孔。
在上述阵列基板中，每个所述过孔包括贯穿所述缓冲层的第一连接孔和贯穿所述第一绝缘层的所述第二连接孔，所述第一连接孔与所述第二连接孔连通。
在上述阵列基板中，所述第二连接孔在所述衬底上的正投影位于所述第一连接孔在所述衬底的正投影内。
在上述阵列基板中，所述遮光导电层的制备材料和所述栅极扫描线的制备材料相同。
一种阵列基板的制造方法，所述制造方法包括如下步骤：
提供一衬底；
于所述衬底上形成遮光导电层；
形成覆盖所述衬底和所述遮光导电层的缓冲层；
于所述缓冲层上形成沟道层；
形成覆盖所述缓冲层和所述沟道层的第一绝缘层；
于所述第一绝缘层上形成多个栅极扫描线，多条所述栅极扫描线位于所述遮光导电层的正上方；
其中，所述栅极扫描线和所述遮光导电层电性连接。
在上述阵列基板的制造方法中，所述遮光导电层包括多条遮光导电线，每条所述遮光导电线与每条所述栅极扫描线一对一地通过贯穿所述缓冲层和所述第一绝缘层的至少两个过孔电性连接。
在上述阵列基板的制造方法中，每条所述栅极扫描线在所述衬底上的正投影和对应与所述栅极扫描线电性连接的每条所述遮光导电线在所述衬底上的正投影重合。
在上述阵列基板的制造方法中，所述过孔沿第一方向的尺寸大于所述栅极扫描线的宽度，所述第一方向为垂直于所述栅极扫描线的方向。
在上述阵列基板的制造方法中，所述沟道层包括多个阵列排布的叉指半导体构件，每个所述叉指半导体构件相对的两侧均分别设置有至少一所述过孔。
在上述阵列基板的制造方法中，每个所述过孔包括贯穿所述缓冲层的第一连接孔和贯穿所述第一绝缘层的所述第二连接孔，所述第一连接孔与所述第二连接孔连通。
在上述阵列基板的制造方法中，所述第二连接孔在所述衬底上的正投影位于所述第一连接孔在所述衬底的正投影内。
一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括：
一衬底；
形成于所述衬底上的遮光导电层；
覆盖所述衬底和所述遮光导电层的缓冲层；
形成于所述缓冲层上的沟道层；
覆盖所述缓冲层和所述沟道层的第一绝缘层；
形成于所述第一绝缘层上且位于所述遮光导电层正上方的多条栅极扫描线；
其中，所述栅极扫描线和所述遮光导电层电性连接。
在上述显示面板中，所述遮光导电层包括多条遮光导电线，每条所述遮光导电线与每条所述栅极扫描线一对一地通过贯穿所述缓冲层和所述第一绝缘层的至少两个过孔电性连接。
在上述显示面板中，每条所述栅极扫描线在所述衬底上的正投影和对应与所述栅极扫描线电性连接的每条所述遮光导电线在所述衬底上的正投影重合。
在上述显示面板中，所述过孔沿第一方向的尺寸大于所述栅极扫描线的宽度，所述第一方向为垂直于所述栅极扫描线的方向。
在上述显示面板中，所述沟道层包括多个阵列排布的叉指半导体构件，每个所述叉指半导体构件相对的两侧均分别设置有至少一所述过孔。
 有益效果
本申请提供一种阵列基板及其制造方法、显示面板，通过使栅极扫描线和遮光导电层电性连接，以使栅极扫描线的宽度相对于传统技术基本不变以保证显示面板的开口率的同时，用于传输扫描电信号的导线阻抗减小，从而使得显示面板驱动功耗减小，提高像素充放电的相应速度。
 附图说明
图1为本申请第一实施例阵列基板的平面示意图；
图2为沿图1所示阵列基板A-A切线的截面示意图；
图3为本申请第二实施例阵列基板的平面示意图；
图4为沿图3所示阵列基板A-A切线的截面示意图；
图5为本申请第一实施例阵列基板的制造方法的流程图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1和图2，图1为本申请第一实施例阵列基板的平面示意图，图2为沿图1所示阵列基板A-A切线的截面示意图。阵列基板100为薄膜晶体管阵列基板，即多个薄膜晶体管(未示出)阵列分布地设置于衬底10上。阵列基板100包括衬底10、遮光导电层11、缓冲层12、沟道层13、第一绝缘层14、栅极扫描线15以及过孔16。
衬底10可以玻璃基板，也可以为柔性基板。
遮光导电层11一方面用于避免背光照射至沟道层13的沟道1311上，从而避免沟道1311出现光生漏电流的问题。遮光导电层11形成于衬底10上，遮光导电层11包括多条遮光导电线111，多条遮光导电线111平行排列。每条遮光导电线111的宽度D1比沟道层13中每个叉指半导体构件131的沟道1311的宽度d大以避免背光照射到沟道1311上。栅极扫描线15和遮光导电层11电性连接，以使遮光导电层11还用于传导扫描电信号。具体，每条遮光导电线111与每条栅极扫描线15一对一地通过贯穿缓冲层12和第一绝缘层14的至少两个过孔16电性连接。遮光导电层11的制备材料为钼、铝、钛以及铜中的至少一种。遮光导电层11的制备材料11和栅极扫描线15的制备材料相同。
缓冲层12用于防止衬底10中的金属离子（铝、钡以及钠等）在热工艺中扩散到沟道层13中的沟道1311中而影响薄膜晶体管的电性能。缓冲层12覆盖衬底10和遮光导电层11。缓冲层12为覆盖遮光导电层11和衬底10的氧化硅层和氮化硅层，氮化硅层位于靠近衬底10的一侧。缓冲层12的厚度为3000埃-4000埃。缓冲层12是通过化学气相沉积制备得到。
沟道层13形成于缓冲层12上。沟道层13包括多个阵列排布的叉指半导体构件131。多个叉指半导体构件131位于多条遮光导电线111的上方。多个叉指半导体构件131分为多行排列，每个叉指半导体构件131为叉指型，每个叉指半导体构件131具有同行的两个沟道1311，以降低薄膜晶体管处于关态时的漏电流。每个叉指半导体构件131具有一个源极接触区和一个漏极接触区，以分别用于与源电极（未示出）和漏电极（未示出）电性接触。沟道层13的制备材料为多晶硅。沟道层13的制备材料也可以为金属氧化物半导体或单晶硅中的一种。沟道层13是利用化学气相沉积形成整面的非晶硅，再通过准分子激光退火工艺使非晶硅转化为多晶硅，再经过黄光制程以使得多晶硅图案化以形成多个阵列排布的叉指半导体构件。
第一绝缘层14为栅极绝缘层。第一绝缘层14覆盖缓冲层12和沟道层13。第一绝缘层14为氮化硅层。可以理解的是，第一绝缘层14也可以为氧化硅层或氧化硅层和氮化硅层的叠层。第一绝缘层14的厚度为1000埃-1500埃。第一绝缘层14是通过化学气相沉积制备得到。
栅极扫描线15用于传输扫描电信号以控制薄膜晶体管的工作状态。栅极扫描线15形成于第一绝缘层14上且位于遮光导电层11正上方。栅极扫描线15也形成于过孔16中以使第一绝缘层14上的栅极扫描线15和遮光导电层11电性连接。栅极扫描线15包括多条平行的金属线。每条栅极扫描线15的宽度等于沟道1311的宽度d，即每条栅极扫描线15的宽度d小于每个导电遮光线111的宽度D1。具体地，每条栅极扫描线15的宽度为3±0.1微米。栅极扫描线15与遮光导电层11电性连接，使得相对于传统技术中栅极扫描线15的宽度基本不变时，用于传输扫描电信号的导线（包括栅极扫描线15和导电遮光层11）的有效面积增大，显著地降低用于传输扫描电信号的导线的电阻，降低扫描驱动电路的功耗，提高像素（未示出）充放电响应的速度。
过孔16用于使栅极扫描线15和遮光导电层11电性连接。过孔16贯穿缓冲层12和第一绝缘层14。每个叉指半导体构件131相对的两侧均分别设置有至少一过孔16，以提高每条遮光导电线111和对应栅极扫描线15的电性连接的良率，而且多个过孔16能减小连接栅极扫描线15和遮光导电层11之间的导线（位于过孔16中的栅极扫描线）的整体阻值。具体地，每个叉指半导体构件131相对的两侧均分别设置有一个过孔16，同一行叉指半导体构件131中，相邻两个叉指半导体构件131之间设置有一个过孔16，使得过孔16周期性地分布。过孔16通过形成第一绝缘层14后，通过于第一绝缘层14上形成整面光阻，再利用光罩曝光部分光阻，刻蚀未被光阻覆盖的第一绝缘层14以及缓冲层12以形成过孔16。过孔16沿第一方向的尺寸D2大于栅极扫描线的宽度D1，第一方向为垂直于栅极扫描线15（栅极扫描线延伸方向）的方向，第一方向与衬底10设置有栅极扫描线的平面平行，以使每个过孔16中的栅极扫描线15与遮光导电层11充分接触，从而降低形成于过孔16中的栅极扫描线15的阻抗。过孔16可以为圆形，过孔16的半径大于栅极扫描线15的宽度。过孔16也可以为正方形，过孔16的边长大于栅极扫描线15的宽度。
请参阅图3和图4，图3为本申请第二实施例阵列基板的平面示意图，图4为沿图3所示阵列基板A-A切线的截面示意图。图3所示阵列基板100与图1所示阵列基板100基本相似，不同之处在于，每条栅极扫描线15在衬底10上的正投影和对应与栅极扫描线10电性连接的每条遮光导电线111在衬底10上的正投影重合，即每条栅极扫描线15和与栅极扫描线15电性连接的每条遮光导电线111相同(包括栅极扫描线15的宽度d以及遮光导电线111的宽度D1相同)，以保证遮光导电线111起到遮光作用的同时，进一步地提高阵列基板制成的显示面板的开口率。另外，每个过孔16包括贯穿缓冲层12的第一连接孔121和贯穿第一绝缘层14的第二连接孔141，第一连接孔121与第二连接孔141连通，第二连接孔141在衬底10上的正投影位于第一连接孔121在衬底10的正投影内，即第一连接孔121的尺寸大于第二连接孔141的尺寸，以保证形成的第二连接孔141能与第一连接孔121连通。第一连接孔121是形成缓冲层12后，采用黄光制程处理缓冲层12形成。第二连接孔141是形成第一绝缘层14后，采用黄光制程处理第一绝缘层14形成。第二连接孔141沿第一方向的尺寸大于每条栅极扫描线15的宽度，第一方向为垂直于栅极扫描线15的方向。
本申请阵列基板通过使栅极扫描线和遮光导电层电性连接，以使栅极扫描线的宽度相对于传统技术基本不变以保证显示面板的开口率的同时，用于传输扫描电信号的导线的阻抗减小，从而使得显示面板驱动功耗减小，提高像素充放电的相应速度。
请参阅图5，其为本申请第一实施例阵列基板的制造方法的流程图。阵列基板的制造方法包括如下步骤：
S10:提供一衬底；
S11:于衬底上形成遮光导电层；
S12:形成覆盖衬底和遮光导电层的缓冲层；
S13:于缓冲层上形成沟道层；
S14:形成覆盖缓冲层和沟道层的第一绝缘层；
S15:于第一绝缘层上形成多个栅极扫描线，多条栅极扫描线位于遮光导电层的正上方，栅极扫描线和遮光导电层电性连接。
本申请阵列基板的制造方法通过使栅极扫描线和遮光导电层电性连接，以使栅极扫描线的宽度相对于传统技术基本不变以保证显示面板的开口率的同时，用于传输扫描电信号的导线阻抗减小，从而使得显示面板驱动功耗减小，提高像素充放电的相应速度。
在本实施例中，遮光导电层包括多条遮光导电线，每条遮光导电线与每条栅极扫描线一对一地通过贯穿缓冲层和第一绝缘层的至少两个过孔电性连接。
在本实施例中，每条栅极扫描线在衬底上的正投影和对应与栅极扫描线电性连接的每条遮光导电线在衬底上的正投影重合，以保证遮光导电线起到遮光作用的同时，进一步地提高阵列基板制成的显示面板的开口率。
在本实施例中，过孔沿第一方向的尺寸大于栅极扫描线的宽度，第一方向为垂直于栅极扫描线的方向，以使每个过孔中的栅极扫描线与遮光导电层充分接触，从而降低形成于过孔中的栅极扫描线的阻抗。
本申请还提供一种显示面板，该显示面板为液晶显示面板或有机发光二极管显示面板。显示面板包括上述阵列基板。
本申请显示面板通过使阵列基板的栅极扫描线和遮光导电层电性连接，以使栅极扫描线的宽度相对于传统技术基本不变以保证显示面板的开口率的同时，用于传输扫描电信号的导线的阻抗减小，从而使得显示面板驱动功耗减小，提高像素充放电的相应速度。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板包括：
    一衬底；
    形成于所述衬底上的遮光导电层；`
    覆盖所述衬底和所述遮光导电层的缓冲层；
    形成于所述缓冲层上的沟道层；
    覆盖所述缓冲层和所述沟道层的第一绝缘层；
    形成于所述第一绝缘层上且位于所述遮光导电层正上方的多条栅极扫描线；
    其中，所述栅极扫描线和所述遮光导电层电性连接。
  2. 根据权利要求1所述阵列基板，其中，所述遮光导电层包括多条遮光导电线，每条所述遮光导电线与每条所述栅极扫描线一对一地通过贯穿所述缓冲层和所述第一绝缘层的至少两个过孔电性连接。
  3. 根据权利要求2所述的阵列基板，其中，每条所述栅极扫描线在所述衬底上的正投影和对应与所述栅极扫描线电性连接的每条所述遮光导电线在所述衬底上的正投影重合。
  4. 根据权利要求2所述的阵列基板，其中，所述过孔沿第一方向的尺寸大于所述栅极扫描线的宽度，所述第一方向为垂直于所述栅极扫描线的方向。
  5. 根据权利要求2所述的阵列基板，其中，所述沟道层包括多个阵列排布的叉指半导体构件，每个所述叉指半导体构件相对的两侧均分别设置有至少一所述过孔。
  6. 根据权利要求5所述的阵列基板，其中，每个所述过孔包括贯穿所述缓冲层的第一连接孔和贯穿所述第一绝缘层的所述第二连接孔，所述第一连接孔与所述第二连接孔连通。
  7. 根据权利要求6所述的阵列基板，其中，所述第二连接孔在所述衬底上的正投影位于所述第一连接孔在所述衬底的正投影内。
  8. 根据权利要求1所述的阵列基板，其中，所述遮光导电层的制备材料和所述栅极扫描线的制备材料相同。
  9. 一种阵列基板的制造方法，其中，所述制造方法包括如下步骤：
    提供一衬底；
    于所述衬底上形成遮光导电层；
    形成覆盖所述衬底和所述遮光导电层的缓冲层；
    于所述缓冲层上形成沟道层；
    形成覆盖所述缓冲层和所述沟道层的第一绝缘层；
    于所述第一绝缘层上形成多个栅极扫描线，多条所述栅极扫描线位于所述遮光导电层的正上方；
    其中，所述栅极扫描线和所述遮光导电层电性连接。
  10. 根据权利要求9所述的阵列基板的制造方法，其中，所述遮光导电层包括多条遮光导电线，每条所述遮光导电线与每条所述栅极扫描线一对一地通过贯穿所述缓冲层和所述第一绝缘层的至少两个过孔电性连接。
  11. 根据权利要求10所述的阵列基板的制造方法，其中，每条所述栅极扫描线在所述衬底上的正投影和对应与所述栅极扫描线电性连接的每条所述遮光导电线在所述衬底上的正投影重合。
  12. 根据权利要求10所述的阵列基板的制造方法，其中，所述过孔沿第一方向的尺寸大于所述栅极扫描线的宽度，所述第一方向为垂直于所述栅极扫描线的方向。
  13. 根据权利要求10所述的阵列基板的制造方法，其中，所述沟道层包括多个阵列排布的叉指半导体构件，每个所述叉指半导体构件相对的两侧均分别设置有至少一所述过孔。
  14. 根据权利要求13所述的阵列基板的制造方法，其中，每个所述过孔包括贯穿所述缓冲层的第一连接孔和贯穿所述第一绝缘层的所述第二连接孔，所述第一连接孔与所述第二连接孔连通。
  15. 根据权利要求14所述的阵列基板的制造方法，其中，所述第二连接孔在所述衬底上的正投影位于所述第一连接孔在所述衬底的正投影内。
  16. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板包括：
    一衬底；
    形成于所述衬底上的遮光导电层；
    覆盖所述衬底和所述遮光导电层的缓冲层；
    形成于所述缓冲层上的沟道层；
    覆盖所述缓冲层和所述沟道层的第一绝缘层；
    形成于所述第一绝缘层上且位于所述遮光导电层正上方的多条栅极扫描线；
    其中，所述栅极扫描线和所述遮光导电层电性连接。
  17. 根据权利要求16所述的显示面板，其中，所述遮光导电层包括多条遮光导电线，每条所述遮光导电线与每条所述栅极扫描线一对一地通过贯穿所述缓冲层和所述第一绝缘层的至少两个过孔电性连接。
  18. 根据权利要求17所述的显示面板，其中，每条所述栅极扫描线在所述衬底上的正投影和对应与所述栅极扫描线电性连接的每条所述遮光导电线在所述衬底上的正投影重合。
  19. 根据权利要求17所述的显示面板，其中，所述过孔沿第一方向的尺寸大于所述栅极扫描线的宽度，所述第一方向为垂直于所述栅极扫描线的方向。
  20. 根据权利要求17所述的显示面板，其中，所述沟道层包括多个阵列排布的叉指半导体构件，每个所述叉指半导体构件相对的两侧均分别设置有至少一所述过孔。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100033645A1 (en) * 2008-08-05 2010-02-11 Seiko Epson Corporation Electro-optical device and electronic apparatus
CN106019738A (zh) * 2015-03-31 2016-10-12 精工爱普生株式会社 电光学装置以及电子设备
CN109300917A (zh) * 2018-09-30 2019-02-01 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI396025B (zh) * 2009-06-30 2013-05-11 Au Optronics Corp 主動元件陣列基板
EP2960943B1 (en) * 2014-06-27 2019-08-07 LG Display Co., Ltd. Thin film transistor of display apparatus
CN104465675B (zh) * 2014-12-31 2017-08-25 深圳市华星光电技术有限公司 薄膜晶体管阵列基板、液晶面板以及液晶显示器
CN106992214B (zh) * 2017-04-25 2019-12-31 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板、显示装置
CN109346482B (zh) * 2018-09-30 2024-01-05 武汉华星光电技术有限公司 薄膜晶体管阵列基板及其制造方法、显示面板

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100033645A1 (en) * 2008-08-05 2010-02-11 Seiko Epson Corporation Electro-optical device and electronic apparatus
CN106019738A (zh) * 2015-03-31 2016-10-12 精工爱普生株式会社 电光学装置以及电子设备
CN109300917A (zh) * 2018-09-30 2019-02-01 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板

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