WO2024027397A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2024027397A1
WO2024027397A1 PCT/CN2023/103682 CN2023103682W WO2024027397A1 WO 2024027397 A1 WO2024027397 A1 WO 2024027397A1 CN 2023103682 W CN2023103682 W CN 2023103682W WO 2024027397 A1 WO2024027397 A1 WO 2024027397A1
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WO
WIPO (PCT)
Prior art keywords
metal layer
layer
substrate
electrically connected
light
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PCT/CN2023/103682
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English (en)
French (fr)
Inventor
阳志林
戴超
张淑媛
Original Assignee
武汉华星光电半导体显示技术有限公司
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Publication of WO2024027397A1 publication Critical patent/WO2024027397A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present application relates to the field of display technology, and specifically to an array substrate and a display panel.
  • LCD Liquid Crystal Display, liquid crystal display
  • AMOLED Active-Matrix Organic Light-Emitting Diode, active matrix organic light-emitting diode
  • LCD Liquid Crystal Display, liquid crystal display
  • AMOLED Active-Matrix Organic Light-Emitting Diode, active matrix organic light-emitting diode
  • AMOLED's array substrate pixel circuit and array are highly complex, and mobile terminal displays using AMOLED need to continuously optimize power consumption reduction solutions.
  • AMOLED displays are gradually used in high-resolution tablets and notebooks, it is of great significance to further reduce the load on the array substrate.
  • This application provides an array substrate and a display panel to reduce the load of the array substrate.
  • This application provides an array substrate, which includes:
  • An active layer is provided on the substrate;
  • a first metal layer disposed on a side of the active layer away from the substrate, where the first metal layer includes scanning lines;
  • a second metal layer is provided on the side of the first metal layer away from the substrate.
  • the second metal layer includes a source electrode, a drain electrode and an auxiliary scan line.
  • the source electrode and the drain electrode are respectively connected to the
  • the active layer is electrically connected
  • the auxiliary scanning line is electrically connected to the scanning line.
  • the resistivity of the auxiliary scan line is smaller than the resistivity of the scan line, and the width of the auxiliary scan line is greater than the width of the scan line.
  • the array substrate further includes a third metal layer, the third metal layer is disposed on a side of the active layer close to the substrate, and the third metal layer It includes a light-shielding member, the orthographic projection of the light-shielding member on the substrate at least covers the orthographic projection of the active layer on the substrate, the light-shielding member is electrically connected to the scan line, and is connected to the same electrical signal. .
  • the third metal layer includes a plurality of the light-shielding parts, each of the light-shielding parts includes a first light-shielding part and a second light-shielding part, and the first light-shielding part
  • the orthographic projection on the substrate at least covers the orthographic projection of the active layer on the substrate, the second light shielding part is electrically connected to the scan line; two adjacent first light shielding parts It is electrically connected through the second light shielding part.
  • the line width of the first light shielding part is greater than the line width of the active layer, and the line width of the second light shielding part is greater than or equal to the line width of the auxiliary scanning line. Width.
  • the array substrate further includes a third metal layer, the third metal layer is disposed on a side of the active layer close to the substrate, and the third metal layer It includes a light-shielding component, the light-shielding component includes a first light-shielding part and a second light-shielding part, and the orthographic projection of the first light-shielding part on the substrate at least covers the orthographic projection of the active layer on the substrate, so The second light shielding part is spaced apart from and insulated from the first light shielding part, and the second light shielding part is electrically connected to the scan line.
  • the first metal layer further includes a plurality of gates spaced apart and insulated, and the second metal layer further includes a plurality of gate scan lines;
  • each gate electrode is electrically connected to the corresponding gate scan line, and two adjacent gate electrodes are electrically connected through the corresponding gate scan line, and the gate scan line is electrically connected to the corresponding gate scan line.
  • the auxiliary scan lines are electrically connected.
  • the material of the first metal layer is molybdenum or molybdenum-titanium alloy
  • the material of the second metal layer is copper, copper/copper, molybdenum/copper or molybdenum-titanium alloy/ copper.
  • the array substrate further includes a fourth metal layer, the fourth metal layer is disposed on a side of the second metal layer away from the substrate, and the fourth metal layer A layer includes data lines electrically connected to the source.
  • the array substrate further includes a first insulating layer, a second insulating layer, a fifth metal layer and an interlayer insulating layer;
  • the first insulating layer is disposed on a side of the first metal layer close to the active layer, and the second insulating layer is disposed on a side of the first metal layer close to the second metal layer.
  • the fifth metal layer is disposed on the side of the second insulating layer close to the second metal layer, and the interlayer insulating layer is disposed on the side of the fifth metal layer close to the second metal layer.
  • the first metal layer also includes a first electrode plate
  • the fifth metal layer includes a second electrode plate
  • the second metal layer also includes a third electrode plate; the first electrode plate and the second The electrode plate forms a first capacitor, and the second electrode plate and the third electrode plate form a second capacitor.
  • the array substrate further includes a passivation layer, a first planar layer and a second planar layer, and the passivation layer is disposed on the second metal layer close to the fourth
  • the first flat layer is disposed on a side of the passivation layer close to the fourth metal layer
  • the second flat layer is disposed on a side of the fourth metal layer away from the substrate. side;
  • the passivation layer has a first via hole, the first via hole penetrates the passivation layer, and the first flat layer fills the first via hole.
  • the interlayer insulating layer has a second via hole, and the second via hole penetrates the interlayer insulating layer and extends to the first insulating layer.
  • the first insulating layer has a third via hole, and the third via hole at least penetrates the first insulating layer;
  • the first via hole, the second via hole and the third via hole are all connected, and the aperture of the second via hole is larger than the aperture of the third via hole.
  • this application also provides a display panel, which includes the array substrate described in any one of the above.
  • the array substrate includes:
  • An active layer is provided on the substrate;
  • a first metal layer is provided on a side of the active layer away from the substrate, the first metal layer includes scanning lines;
  • a second metal layer is provided on the side of the first metal layer away from the substrate.
  • the second metal layer includes a source electrode, a drain electrode and an auxiliary scan line.
  • the source electrode and the drain electrode are respectively connected to the
  • the active layer is electrically connected
  • the auxiliary scanning line is electrically connected to the scanning line.
  • the resistivity of the auxiliary scan line is smaller than the resistivity of the scan line, and the width of the auxiliary scan line is greater than the width of the scan line.
  • the array substrate further includes a third metal layer, the third metal layer is disposed on a side of the active layer close to the substrate, and the third metal layer It includes a light-shielding member, the orthographic projection of the light-shielding member on the substrate at least covers the orthographic projection of the active layer on the substrate, the light-shielding member is electrically connected to the scan line, and is connected to the same electrical signal. .
  • the third metal layer includes a plurality of the light-shielding parts, each of the light-shielding parts includes a first light-shielding part and a second light-shielding part, and the first light-shielding part
  • the orthographic projection on the substrate at least covers the orthographic projection of the active layer on the substrate, the second light shielding part is electrically connected to the scan line; two adjacent first light shielding parts It is electrically connected through the second light shielding part.
  • the line width of the first light shielding part is greater than the line width of the active layer, and the line width of the second light shielding part is greater than or equal to the line width of the auxiliary scanning line. Width.
  • the array substrate further includes a third metal layer, the third metal layer is disposed on a side of the active layer close to the substrate, and the third metal layer It includes a light-shielding component, the light-shielding component includes a first light-shielding part and a second light-shielding part, and the orthographic projection of the first light-shielding part on the substrate at least covers the orthographic projection of the active layer on the substrate, so The second light shielding part is spaced apart from and insulated from the first light shielding part, and the second light shielding part is electrically connected to the scan line.
  • the first metal layer further includes a plurality of gates spaced apart and insulated, and the second metal layer further includes a plurality of gate scan lines;
  • each gate electrode is electrically connected to the corresponding gate scan line, and two adjacent gate electrodes are electrically connected through the corresponding gate scan line, and the gate scan line is electrically connected to the corresponding gate scan line.
  • the auxiliary scan lines are electrically connected.
  • the material of the first metal layer is molybdenum or molybdenum-titanium alloy
  • the material of the second metal layer is copper, copper/copper, molybdenum/copper or molybdenum-titanium alloy/ copper.
  • the array substrate includes a substrate, an active layer, a first metal layer and a second metal layer.
  • the active layer is provided on the substrate;
  • the first metal layer is provided on a side of the active layer away from the substrate, and the first metal layer includes a gate electrode and a scan line;
  • the second metal layer is disposed on the side of the first metal layer away from the substrate.
  • the second metal layer includes a source electrode, a drain electrode and an auxiliary scan line. The source electrode and the drain electrode are respectively connected with the The active layer is electrically connected, and the auxiliary scan line is electrically connected to the scan line.
  • This application can reduce the impedance of the scan line by setting the auxiliary scan line to be electrically connected to the scan line, thereby reducing the load on the array substrate.
  • the auxiliary scan line, source electrode and drain electrode are patterned and formed from the same layer of metal, the manufacturing process can be simplified.
  • Figure 1 is a first structural schematic diagram of the array substrate provided by this application.
  • Figure 2 is a second structural schematic diagram of the array substrate provided by this application.
  • Figure 3 is a first top schematic view of the array substrate provided by the present application.
  • Figure 4 is a third structural schematic diagram of the array substrate provided by this application.
  • Figure 5 is a second top schematic view of the array substrate provided by the present application.
  • Figures 6A-6K are schematic structural diagrams of each step obtained in a manufacturing method of an array substrate provided by this application;
  • Figure 7 is a schematic structural diagram of a display panel provided by this application.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as “first”, “second”, etc. may explicitly or implicitly include one or more of the described features, and therefore cannot be construed as a limitation of the present application.
  • the terms “connected” and “connected” should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection; it can be a direct connection or a connection through The intermediate medium is indirectly connected, which can be the internal connection between two components.
  • the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.
  • This application provides an array substrate and a display panel, which are described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments of the present application.
  • the array substrate 100 includes a substrate 10, an active layer 16, a first metal layer 18 and a second metal layer 21.
  • the active layer 16 is provided on the substrate 10 .
  • the first metal layer 18 is disposed on a side of the active layer 16 away from the substrate 10 .
  • the first metal layer 18 includes scan lines 182 .
  • the second metal layer 21 is disposed on the side of the first metal layer 18 away from the substrate 10 .
  • the second metal layer 21 includes a source electrode 211, a drain electrode 212 and an auxiliary scanning line 213.
  • the source electrode 211 and the drain electrode 212 are electrically connected to the active layer 16 respectively.
  • the auxiliary scan line 213 is electrically connected to the scan line 182.
  • the auxiliary scan line 213 is provided in the array substrate 100 and the auxiliary scan line 213 is electrically connected to the scan line 182, which is equivalent to connecting the auxiliary scan line 213 and the scan line 213 in parallel, so the impedance of the scan line 182 can be reduced. , thereby reducing the load on the array substrate 100 and obtaining a high-quality display product.
  • the auxiliary scanning line 213, the source electrode 211 and the drain electrode 212 are patterned and formed from the same layer of metal, the manufacturing process can be simplified.
  • the first metal layer 18 also includes a gate electrode 181 .
  • the gate electrode 181 is electrically connected to the scan line 182 .
  • the resistivity of the auxiliary scanning line 213 is smaller than the resistivity of the scanning line 182 , and the width of the auxiliary scanning line 213 is larger than the width of the scanning line 182 .
  • the material of the first metal layer 18 is molybdenum, molybdenum-titanium alloy and other metals with small line width deviation. Therefore, dry etching can be used to obtain the gate electrode 181 and the scan line 182 with a smaller line width, thereby achieving higher PPI (Pixels Per Inch, pixel density unit) performance. At the same time, the line width of the gate 181 can be uniform, and stable electrical characteristics of the transistor can be achieved.
  • the resistivity of the second metal layer 21 is smaller than the resistivity of the first metal layer 18 .
  • the second metal layer 21 may be a single layer of metal copper, a double layer of metal, a bottom layer of molybdenum and a layer of copper, a bottom layer of molybdenum and titanium alloy and a layer of copper, etc. Since the resistivity of the second metal layer 21 is smaller than the resistivity of the first metal layer 18 , the impedance of the scan line 182 can be further reduced and the load of the array substrate 100 can be reduced.
  • the material of the active layer 16 may be a metal oxide semiconductor or low-temperature polysilicon.
  • LTPO Low Temperature Polycrystalline-Si Oxide, low temperature polycrystalline oxide
  • the substrate 10 may include, but is not limited to, a substrate 11 , a double-layer PI (Polyimide, polyimide) layer 12 and a barrier layer 13 that are stacked sequentially from bottom to top.
  • the substrate 11 may be a glass substrate.
  • the material of the barrier layer 13 may be silicon oxide, silicon nitride, etc.
  • the barrier layer 13 can function as a water barrier and oxygen barrier.
  • the second metal layer 21 may also include gate scanning lines 214 .
  • the gate scanning line 214 is electrically connected to the gate electrode 181 . Since the resistivity of the second metal layer 21 is small, the resistance of the gate electrode 181 can be reduced.
  • the array substrate 100 may further include a first insulating layer 17 and an interlayer insulating layer 20 .
  • the first insulating layer 17 is disposed on the side of the first metal layer 18 close to the active layer 16 .
  • the first insulating layer 17 includes a gate insulating layer 171 .
  • the gate insulating layer 171 is provided between the gate electrode 181 and the active layer 16 .
  • the interlayer insulating layer 20 is provided on the side of the first metal layer 18 close to the second metal layer 21 .
  • the interlayer insulating layer 20 has a first contact hole 20a, a second contact hole 20b and a third contact hole 20c.
  • the first contact hole 20 a and the second contact hole 20 b both penetrate the interlayer insulating layer 20 and extend to the active layer 16 . Both the first contact hole 20 a and the second contact hole 20 b expose a side surface of the active layer 16 away from the substrate 10 .
  • the source electrode 211 is electrically connected to the active layer 16 through the first contact hole 20a.
  • the drain electrode 212 is electrically connected to the active layer 16 through the second contact hole 20b.
  • the third contact hole 20 c penetrates the interlayer insulating layer 20 and extends to the scan line 182 .
  • the third contact hole 20 c exposes a side surface of the scan line 182 away from the substrate 10 .
  • the auxiliary scan line 213 is electrically connected to the scan line 182 through the third contact hole 20c.
  • the interlayer insulating layer 20 also has a fourth contact hole 20d.
  • the fourth contact hole 20d penetrates the interlayer insulating layer 20 and extends to the gate electrode 181.
  • the fourth contact hole 20d exposes a side surface of the gate 181 away from the substrate 10 .
  • the gate scanning line 214 is electrically connected to the gate electrode 181 through the fourth contact hole 20d.
  • the first metal layer 18 also includes a first electrode plate 183 .
  • the second metal layer 21 also includes a third electrode plate 215 . In a direction perpendicular to the substrate 100, the first electrode plate 183 and the third electrode plate 215 are at least partially overlapped.
  • the first electrode plate 183 and the third electrode plate 215 may constitute a storage capacitor.
  • the source electrode 211 and the drain electrode 212 may also be electrically connected to the active layer 16 respectively, and in this case, the interlayer insulating layer 20 may not be provided.
  • the array substrate 100 may also include a second insulation layer 19 and a fifth metal layer 30 .
  • the second insulating layer 19 is disposed on the side of the first metal layer 18 close to the second metal layer 21 .
  • the fifth metal layer 30 is provided on the side of the second insulating layer 19 close to the second metal layer 21 .
  • the interlayer insulating layer 20 is provided on the side of the fifth metal layer 30 close to the second metal layer 21 .
  • the fifth metal layer 30 includes the second electrode plate 31 .
  • the first electrode plate 183 and the second electrode plate 31 form a first capacitor.
  • the second electrode plate 31 and the third electrode plate 215 form a second capacitor.
  • the array substrate 100 may further include a fourth metal layer 24 .
  • the fourth metal layer 24 is disposed on the side of the second metal layer 21 away from the substrate 10 .
  • the fourth metal layer 24 includes data lines (not shown in the figure).
  • auxiliary scan line 213 and the data line are arranged crosswise in the plane. Since the auxiliary scan line 213, the source electrode 211 and the drain electrode 212 are arranged in the same layer, the data line is arranged in the fourth metal layer 24, so that the data The lines and the auxiliary scanning lines 213 are arranged in different layers to avoid cross-short circuits between the data lines and the auxiliary scanning lines 213 .
  • the fourth metal layer 24 also includes a first electrode 241 and a second electrode 242.
  • the data line is electrically connected to the source electrode 211 through the first electrode 241.
  • the second electrode 242 is electrically connected to the drain electrode 212 .
  • the first electrode 241 can also be considered as a data line.
  • the fourth metal layer 24 may be a single layer of metal copper, a double layer of metal, a bottom layer of molybdenum and a layer of copper, a bottom layer of molybdenum and titanium alloy and a layer of copper, etc.
  • the material of the fourth metal layer 24 may be the same as the material of the second metal layer 21 , or may be different.
  • the first electrode 241 is electrically connected to the source electrode 211
  • the second electrode 242 is electrically connected to the drain electrode 212, which can further reduce the impedance of the source electrode 211 and the drain electrode 212 and reduce the load of the array substrate 100.
  • the line width of the second metal layer 21 and the fourth metal layer 24 can be About 20% thinner, further achieving higher PPI performance.
  • the array substrate 100 may further include a passivation layer 22 , a first planarization layer 23 and a second planarization layer 25 .
  • the passivation layer 22 is provided on the side of the second metal layer 21 close to the fourth metal layer 24 .
  • the first flat layer 23 is disposed on the side of the passivation layer 22 close to the fourth metal layer 24 and the second flat layer 25 is disposed on the side of the fourth metal layer 24 away from the substrate 10 .
  • the first flat layer 23 has a first electrical connection hole 23a and a second electrical connection hole 23b.
  • the first electrical connection hole 23 a penetrates the first planar layer 23 and extends to the source electrode 211 .
  • the first electrical connection hole 23 a exposes a side surface of the source electrode 211 away from the substrate 10 .
  • the first electrode 241 is electrically connected to the source electrode 211 through the first electrical connection hole 23a.
  • the second electrical connection hole 23b penetrates the first planar layer 23 and extends to the drain electrode 212 .
  • the second electrical connection hole 23 b exposes a side surface of the drain electrode 212 away from the substrate 10 .
  • the second electrode 242 is electrically connected to the drain electrode 212 through the second electrical connection hole 23b.
  • the passivation layer 22 has a first via hole 22a.
  • the first via hole 22 a penetrates the passivation layer 22 .
  • the first flat layer 23 fills the first via hole 22a.
  • the first flat layer 23 and the second flat layer 25 are made of organic materials to improve the flexibility of the array substrate 100 .
  • the organic material can be a positive organic photoresist (the main component is PI).
  • the material of the first flat layer 23 is an organic material, providing the first via hole 22 a in the passivation layer 22 and filling the first flat layer 23 can further improve the bending resistance of the array substrate 100 .
  • the interlayer insulating layer 20 has a second via hole 20e.
  • the second via hole 20 e penetrates the interlayer insulating layer 20 and extends to the first insulating layer 17 .
  • the first insulating layer 17 has a third via hole 17a.
  • the third via hole 17 a at least penetrates the first insulating layer 17 .
  • the first via hole 22a, the second via hole 20e and the third via hole 17a are all connected.
  • the diameter of the second via hole 20e is larger than the diameter of the third via hole 17a.
  • the third via hole 17 a may penetrate the first insulating layer 17 and extend to the side of the double-layer PI layer 12 away from the substrate 11 .
  • the first flat layer 23 is filled in the first via hole 22a, the second via hole 20e and the third via hole 17a, which can further improve the bending resistance of the array substrate 100.
  • the fourth metal layer 24 also includes at least one signal trace 243 .
  • the signal trace 243 is provided corresponding to the first via hole 22a.
  • the signal wiring 243 is a bridge connecting the signal lines at the Fan-out (fan-shaped wiring area) on the periphery of the display area in the array substrate 100 .
  • the array substrate 100 may further include a third metal layer 14 .
  • the third metal layer 14 is disposed on the side of the active layer 16 close to the substrate 10 .
  • the third metal layer 14 includes a light shielding member 141 .
  • the orthographic projection of the light shielding member 141 on the substrate 10 at least covers the orthographic projection of the active layer 16 on the substrate 10 .
  • the material of the third metal layer 14 is a metal with excellent conductivity and good light-shielding properties, generally molybdenum, copper, aluminum, titanium or composite metal, which is not limited in this application.
  • the array substrate 100 further includes a buffer layer 15 .
  • the buffer layer 15 is disposed between the third metal layer 14 and the active layer 16 to play the role of insulation protection.
  • the light-shielding member 141 can block the light incident from the substrate 10 in a direction away from the light-shielding member 141 , thereby reducing the interference of external light on the active layer 16 , thereby improving the working performance of the array substrate 100 .
  • the array substrate 100 may further include a sixth metal layer 26, a pixel definition layer 27 and a spacer 28.
  • the sixth metal layer 26 includes an anode 261 .
  • Anode 261 and drain 212 are electrically connected.
  • the pixel definition layer 27 has openings 27a.
  • the opening 27 a exposes the side surface of the anode 261 away from the substrate 10 .
  • Functional film layers such as a light-emitting layer may be provided in the opening 27a, which will not be described again here.
  • Figure 2 is a second structural schematic diagram of the array substrate provided by the present application. The difference from the array substrate 100 shown in FIG. 1 is that in the embodiment of the present application, the light shielding member 141 is electrically connected to the scanning line 182 .
  • the first insulation layer 17 has a fourth via hole 17b.
  • the light shielding member 141 is electrically connected to the scanning line 182 through the fourth via hole 17b.
  • the light shielding member 141 , the scanning line 182 and the auxiliary scanning line 213 are all electrically connected together, further reducing the resistivity of the scanning line 182 and reducing the load on the array substrate 100 .
  • the transistors in the array substrate 100 have a top-bottom dual-gate structure.
  • the transistor includes an active layer 16, a gate electrode 181, a source electrode 211, a drain electrode 212, and a light shielding member 141 (as a bottom gate).
  • the light shielding member 141 and the gate 181 receive the same electrical signal through the scanning line 182 and the auxiliary scanning line 213 .
  • FIG. 3 is a first schematic top view of the array substrate provided by this application.
  • the third metal layer 14 includes a plurality of light shielding members 141 .
  • Each light shielding member 141 includes a first light shielding portion 1411 and a second light shielding portion 1412 .
  • the orthographic projection of the first light shielding portion 1411 on the substrate 10 at least covers the orthographic projection of the active layer 16 on the substrate 10 .
  • the second light shielding part 1412 and the scanning line 182 are electrically connected together. Two adjacent first light shielding parts 1411 are electrically connected through the second light shielding part 1412. That is, in the display area of the array substrate 100, the plurality of light shielding members 141 have a continuous structure.
  • the second metal layer 21 includes a plurality of gate scanning lines 214 arranged at intervals.
  • the first metal layer 18 includes a plurality of gate electrodes 181 that are spaced apart and insulated. One end of each gate is electrically connected to a corresponding gate scan line 214 . The other end of each gate is also electrically connected to a corresponding gate scan line 214 .
  • a gate 181 (top gate) and a light shield 141 (bottom gate) are respectively provided on the upper and lower sides of the active layer 16, and the active layer 16 is driven by dual gates, making it easier to control the threshold voltage; at the same time, , and can also significantly increase carrier mobility.
  • the line width of the first light shielding portion 1411 is greater than the line width of the active layer 16
  • the line width of the second light shielding portion 1412 is greater than or equal to the line width of the auxiliary scanning line 213 .
  • the line width of the first light shielding portion 1411 By setting the line width of the first light shielding portion 1411 to be larger than the line width of the active layer 16 , interference caused by external light to the active layer 16 can be reduced.
  • the line width of the second light shielding portion 1412 By setting the line width of the second light shielding portion 1412 to be greater than or equal to the line width of the auxiliary scanning line 213, the coupling capacitance of the same layer of the auxiliary scanning line 213 can be reduced. At the same time, the parasitic capacitance generated by the overlap between the auxiliary scan line 213 and other layers of metal can also be reduced.
  • auxiliary scanning line 213 and the gate scanning line 214 belong to the second metal layer 21 , and the auxiliary scanning line 213 and the gate scanning line 214 may be the same.
  • the transistors in the array substrate 100 have a top-gate structure.
  • FIG. 4 is a third structural schematic diagram of the array substrate provided by the present application
  • FIG. 5 is a second schematic top view of the array substrate provided by the present application.
  • the light shielding member 141 includes a first light shielding part 1411 and a second light shielding part 1412.
  • the orthographic projection of the first light shielding portion 1411 on the substrate 10 at least covers the orthographic projection of the active layer 16 on the substrate 10 .
  • the second light shielding part 1412 is spaced apart from the first light shielding part 1411 and is insulated.
  • the second light shielding part 1412 is electrically connected to the scanning line 182 .
  • the second metal layer 21 further includes a plurality of gate scan lines 214 arranged at intervals.
  • the first metal layer 18 includes a plurality of gate electrodes 181 that are spaced apart and insulated. Each gate electrode 181 is electrically connected to the corresponding gate scanning line 214 through the fourth contact hole 20d, and two adjacent gate electrodes 181 are electrically connected through the corresponding gate scanning line 214.
  • FIGS. 6A to 6K are schematic structural diagrams of each step obtained in a manufacturing method of an array substrate provided by the present application.
  • This application takes the array substrate 100 shown in FIG. 2 as an example for description, but this application should not be understood as limiting the application.
  • the manufacturing method of the array substrate 100 provided by the embodiment of the present application specifically includes the following steps:
  • the substrate 10 may include, but is not limited to, a substrate 11 , a double-layer PI (Polyimide, polyimide) layer 12 and a barrier layer 13 that are stacked sequentially from bottom to top.
  • the substrate 11 may be a glass substrate.
  • the third metal layer 14 includes a light shielding member 141.
  • the first insulating layer 17 is formed on the side of the active layer 16 away from the substrate 10 , and the first photoresist 41 is coated on the side of the first insulating layer 17 away from the substrate 10 , as shown in FIG. 6A .
  • the first metal layer 18 is patterned to form a gate electrode 181, a scan line 182 and a first electrode plate 183, as shown in FIG. 6D.
  • the fifth metal layer 30 is patterned to form a second electrode plate 31 .
  • An interlayer insulating layer 20 is formed on the fifth metal layer 30, as shown in FIG. 6E.
  • first contact holes 20a, second contact holes 20b, third contact holes 20c, and fourth contact holes 20d are formed in the interlayer insulating layer 20.
  • the first contact hole 20 a and the second contact hole 20 b both penetrate the interlayer insulating layer 20 and extend to the active layer 16 .
  • Both the first contact hole 20 a and the second contact hole 20 b expose a side surface of the active layer 16 away from the substrate 10 .
  • the third contact hole 20 c exposes a side surface of the scan line 182 away from the substrate 10 .
  • the fourth contact hole 20d exposes a side surface of the gate 181 away from the substrate 10 . As shown in Figure 6G.
  • a second metal layer 21 having low resistivity is formed, as shown in FIG. 6H.
  • the fourth photoresist 44 is coated on the second metal layer 21, as shown in FIG. 6I. Patterning is completed after exposure and etching, and the source electrode 211, the drain electrode 212, the auxiliary scanning line 213, the gate scanning line 214 and the third electrode plate 215 are formed.
  • the source electrode 211 is electrically connected to the active layer 16 through the first contact hole 20a.
  • the drain electrode 212 is electrically connected to the active layer 16 through the second contact hole 20b.
  • the auxiliary scan line 213 is electrically connected to the scan line 182 through the third contact hole 20c.
  • the gate electrode 181 is electrically connected to the gate scanning line 214 through the fourth contact hole 20d.
  • the first electrode plate 183 and the second electrode plate 31 form a first capacitor.
  • the second electrode plate 31 and the third electrode plate 215 form a second capacitor. As shown in Figure 6J.
  • the fourth metal layer 24 is patterned to form a first electrode 241, a second electrode 242 and at least one signal trace 243.
  • the first electrode 241 is electrically connected to the source electrode 211 .
  • the second electrode 242 is electrically connected to the drain electrode 212 .
  • the formation of the second flat layer 25 and the formation of the sixth metal layer 26 are completed.
  • the sixth metal layer 26 is patterned to form an anode 261 .
  • the pixel definition layer 27 and the spacers 28 are patterned to complete the entire array substrate 100 process.
  • Deep holes are formed through three etchings.
  • the passivation layer 22 has a first via hole 22a.
  • the first via hole 22 a penetrates the passivation layer 22 .
  • the interlayer insulating layer 20 has a second via hole 20e.
  • the second via hole 20 e penetrates the interlayer insulating layer 20 and extends to the first insulating layer 17 .
  • the first insulating layer 17 has a third via hole 17a.
  • the third via hole 17 a at least penetrates the first insulating layer 17 .
  • the first via hole 22a, the second via hole 20e and the third via hole 17a are all connected to form a deep hole.
  • the diameter of the second via hole 20e is larger than the diameter of the third via hole 17a.
  • the three etchings of the first via hole 22a, the second via hole 20e, and the third via hole 17a can be combined with the etching step of each hole in the above steps, thereby simplifying the manufacturing process.
  • the first flat layer 23 is filled in the first via hole 22a, the second via hole 20e and the third via hole 17a, which can further improve the bending resistance of the array substrate 100.
  • each film layer in the array substrate 100 can be referred to the above embodiments, and will not be described again in the manufacturing method of the array substrate 100 .
  • this application also provides a display panel, which includes the array substrate 100 described in any of the above embodiments.
  • the display panel provided by this application can be an organic light-emitting diode display panel, an active matrix organic light-emitting diode display panel, a passive matrix organic light-emitting diode display panel, a quantum dot organic light-emitting diode display panel or a micro-light emitting diode display panel. No specific limitation is made.
  • FIG. 7 is a schematic structural diagram of a display panel provided by the present application.
  • the display panel 1000 provided by the embodiment of the present application also includes a GOA circuit 300 and other functional components.
  • the GOA circuit 300 and other functional components in the embodiment of the present application are related technologies well known to those skilled in the art, and will not be described again here.
  • the display panel 1000 provided by this application includes an array substrate 100.
  • the array substrate includes a substrate, an active layer, a first metal layer, and a second metal layer.
  • the active layer is disposed on the substrate;
  • the first metal layer is disposed on a side of the active layer away from the substrate, and the first metal layer includes gate electrodes and scan lines;
  • the second metal layer is disposed on a side away from the first metal layer.
  • the second metal layer includes a source electrode, a drain electrode and an auxiliary scan line; the source electrode and the drain electrode are electrically connected to the active layer respectively, and the auxiliary scan line is electrically connected to the scan line.
  • Embodiments of the present application can reduce the impedance of the scan lines by setting auxiliary scan lines to be electrically connected to the scan lines, thereby reducing the load on the array substrate and improving the quality of the display panel 1000 .
  • the auxiliary scan line, source electrode and drain electrode are patterned and formed from the same layer of metal, the manufacturing process can be simplified.

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Abstract

本申请公开一种阵列基板及显示面板。阵列基板包括基板、有源层、第一金属层以及第二金属层。有源层设置在基板上；第一金属层包括扫描线；第二金属层设置在第一金属层远离基板的一侧，第二金属层包括源极、漏极以及辅助扫描线，源极和漏极分别与有源层电连接，所述辅助扫描线与所述扫描线电连接。

Description

阵列基板及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板及显示面板。
 背景技术
随着显示技术的快速发展和革新，显示面板主流主要分为LCD（Liquid Crystal Display，液晶显示）和AMOLED（Active-Matrix Organic Light-Emitting Diode，有源矩阵有机发光二极管）。其中AMOLED因具有高对比度、高亮度、轻薄、可弯折等优势，越来越受到显示终端市场以及面板行业的青睐。
但是，AMOLED的阵列基板像素电路及阵列复杂程度较高，采用AMOLED的移动终端显示器需要不断优化降功耗的方案。随着AMOLED显示屏逐渐应用于高分辨率的平板电脑和笔记本等领域，进一步降低阵列基板发的负载技术意义重大。
 发明概述
本申请提供一种阵列基板及显示面板，以降低阵列基板的负载。
本申请提供一种阵列基板，其包括：
基板；
有源层，设置在所述基板上；
第一金属层，设置在所述有源层远离所述基板的一侧，所述第一金属层包括扫描线；
第二金属层，设置在所述第一金属层远离所述基板的一侧，所述第二金属层包括源极、漏极以及辅助扫描线，所述源极和所述漏极分别与所述有源层电连接，所述辅助扫描线与所述扫描线电连接。
可选的，在本申请一些实施例中，所述辅助扫描线的电阻率小于所述扫描线的电阻率，所述辅助扫描线的宽度大于所述扫描线的宽度。
可选的，在本申请一些实施例中，所述阵列基板还包括第三金属层，所述第三金属层设置在所述有源层靠近所述基板的一侧，所述第三金属层包括遮光件，所述遮光件在所述基板上的正投影至少覆盖所述有源层在所述基板上的正投影，所述遮光件与所述扫描线电连接，并接入同一电信号。
可选的，在本申请一些实施例中，所述第三金属层包括多个所述遮光件，每一所述遮光件均包括第一遮光部和第二遮光部，所述第一遮光部在所述基板上的正投影至少覆盖所述有源层在所述基板上的正投影，所述第二遮光部与所述扫描线电连接在一起；相邻两个所述第一遮光部通过所述第二遮光部电连接。
可选的，在本申请一些实施例中，所述第一遮光部的线宽大于所述有源层的线宽，所述第二遮光部的线宽大于或等于所述辅助扫描线的线宽。
可选的，在本申请一些实施例中，所述阵列基板还包括第三金属层，所述第三金属层设置在所述有源层靠近所述基板的一侧，所述第三金属层包括遮光件，所述遮光件包括第一遮光部和第二遮光部，所述第一遮光部在所述基板上的正投影至少覆盖所述有源层在所述基板上的正投影，所述第二遮光部与所述第一遮光部间隔且绝缘设置，所述第二遮光部与所述扫描线电连接。
可选的，在本申请一些实施例中，所述第一金属层还包括多个间隔且绝缘设置的栅极，所述第二金属层还包括多个栅极扫描线；
其中，每一所述栅极与相应的所述栅极扫描线电连接，且相邻两个所述栅极之间通过相应的所述栅极扫描线电连接，所述栅极扫描线与所述辅助扫描线电连接。
可选的，在本申请一些实施例中，所述第一金属层的材料为钼或钼钛合金，所述第二金属层的材料为铜、铜/铜、钼/铜或钼钛合金/铜。
可选的，在本申请一些实施例中，所述阵列基板还包括第四金属层，所述第四金属层设置在所述第二金属层远离所述基板的一侧，所述第四金属层包括数据线，所述数据线与所述源极电连接。
可选的，在本申请一些实施例中，所述阵列基板还包括第一绝缘层、第二绝缘层、第五金属层以及层间绝缘层；
其中，所述第一绝缘层设置在所述第一金属层靠近所述有源层的一侧，所述第二绝缘层设置在所述第一金属层靠近所述第二金属层的一侧，所述第五金属层设置在所述第二绝缘层靠近所述第二金属层的一侧，所述层间绝缘层设置在所述第五金属层靠近所述第二金属层的一侧；所述第一金属层还包括第一电极板，所述第五金属层包括第二电极板，所述第二金属层还包括第三电极板；所述第一电极板和所述第二电极板构成第一电容，所述第二电极板和所述第三电极板构成第二电容。
可选的，在本申请一些实施例中，所述阵列基板还包括钝化层、第一平坦层以及第二平坦层，所述钝化层设置在所述第二金属层靠近所述第四金属层的一侧，所述第一平坦层设置在所述钝化层靠近所述第四金属层的一侧，所述第二平坦层设置在所述第四金属层远离所述基板的一侧；
其中，所述钝化层具有第一过孔，所述第一过孔贯穿所述钝化层，所述第一平坦层填充所述第一过孔。
可选的，在本申请一些实施例中，所述层间绝缘层具有第二过孔，所述第二过孔贯穿所述层间绝缘层，并延伸至所述第一绝缘层，所述第一绝缘层具有第三过孔，所述第三过孔至少贯穿所述第一绝缘层；
其中，所述第一过孔、所述第二过孔以及所述第三过孔均连通，且所述第二过孔的孔径大于所述第三过孔的孔径。
相应的，本申请还提供一种显示面板，其包括上述任一项所述的阵列基板。所述阵列基板，包括：
基板；
有源层，设置在所述基板上；
第一金属层，设置在所述有源层远离所述基板的一侧，所述第一金属层包括扫描线；以及
第二金属层，设置在所述第一金属层远离所述基板的一侧，所述第二金属层包括源极、漏极以及辅助扫描线，所述源极和所述漏极分别与所述有源层电连接，所述辅助扫描线与所述扫描线电连接。
可选的，在本申请一些实施例中，所述辅助扫描线的电阻率小于所述扫描线的电阻率，所述辅助扫描线的宽度大于所述扫描线的宽度。
可选的，在本申请一些实施例中，所述阵列基板还包括第三金属层，所述第三金属层设置在所述有源层靠近所述基板的一侧，所述第三金属层包括遮光件，所述遮光件在所述基板上的正投影至少覆盖所述有源层在所述基板上的正投影，所述遮光件与所述扫描线电连接，并接入同一电信号。
可选的，在本申请一些实施例中，所述第三金属层包括多个所述遮光件，每一所述遮光件均包括第一遮光部和第二遮光部，所述第一遮光部在所述基板上的正投影至少覆盖所述有源层在所述基板上的正投影，所述第二遮光部与所述扫描线电连接在一起；相邻两个所述第一遮光部通过所述第二遮光部电连接。
可选的，在本申请一些实施例中，所述第一遮光部的线宽大于所述有源层的线宽，所述第二遮光部的线宽大于或等于所述辅助扫描线的线宽。
可选的，在本申请一些实施例中，所述阵列基板还包括第三金属层，所述第三金属层设置在所述有源层靠近所述基板的一侧，所述第三金属层包括遮光件，所述遮光件包括第一遮光部和第二遮光部，所述第一遮光部在所述基板上的正投影至少覆盖所述有源层在所述基板上的正投影，所述第二遮光部与所述第一遮光部间隔且绝缘设置，所述第二遮光部与所述扫描线电连接。
可选的，在本申请一些实施例中，所述第一金属层还包括多个间隔且绝缘设置的栅极，所述第二金属层还包括多个栅极扫描线；
其中，每一所述栅极与相应的所述栅极扫描线电连接，且相邻两个所述栅极之间通过相应的所述栅极扫描线电连接，所述栅极扫描线与所述辅助扫描线电连接。
可选的，在本申请一些实施例中，所述第一金属层的材料为钼或钼钛合金，所述第二金属层的材料为铜、铜/铜、钼/铜或钼钛合金/铜。
有益效果
本申请提供一种阵列基板及显示面板。所述阵列基板包括基板、有源层、第一金属层以及第二金属层。其中，所述有源层设置在所述基板上；所述第一金属层设置在所述有源层远离所述基板的一侧，所述第一金属层包括栅极和扫描线；所述第二金属层设置在所述第一金属层远离所述基板的一侧，所述第二金属层包括源极、漏极以及辅助扫描线，所述源极以及所述漏极分别与所述有源层电连接，所述辅助扫描线与所述扫描线电连接。本申请通过设置辅助扫描线与扫描线电连接，可以降低扫描线的阻抗，从而降低阵列基板的负载。此外，由于辅助扫描线、源极以及漏极由同一层金属图案化形成，可以简化制程工艺。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获取其他的附图。
图1是本申请提供的阵列基板的第一结构示意图；
图2是本申请提供的阵列基板的第二结构示意图；
图3是本申请提供的阵列基板的第一俯视示意图；
图4是本申请提供的阵列基板的第三结构示意图；
图5是本申请提供的阵列基板的第二俯视示意图；
图6A-6K是在本申请提供的阵列基板的一种制作方法中各步骤获得的结构示意图；
图7是本申请提供的显示面板的一种结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获取的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”和“第二”等的特征可以明示或者隐含地包括一个或者更多个所述特征，因此不能理解为对本申请的限制。此外，需要说明的是，除非另有明确的规定和限定，术语“相连”、“连接”应做广义理解，例如，可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
本申请提供一种阵列基板及显示面板，以下进行详细说明。需要说明的是，以下实施例的描述顺序不作为对本申请实施例优选顺序的限定。
请参阅图1，图1是本申请提供的阵列基板的第一结构示意图。在本申请实施例中，阵列基板100包括基板10、有源层16、第一金属层18以及第二金属层21。
其中，有源层16设置在基板10上。第一金属层18设置在有源层16远离基板10的一侧。第一金属层18包括扫描线182。第二金属层21设置在第一金属层18远离基板10的一侧。第二金属层21包括源极211、漏极212以及辅助扫描线213。源极211和漏极212分别与有源层16电连接。辅助扫描线213与扫描线182电连接。
本申请实施例通过在阵列基板100中设置辅助扫描线213，并将辅助扫描线213与扫描线182电连接，相当于将辅助扫描线213与扫描线213并联，因此可以降低扫描线182的阻抗，从而降低阵列基板100的负载，获得高品质显示产品。此外，由于辅助扫描线213、源极211以及漏极212由同一层金属图案化形成，可以简化制程工艺。
在本申请实施例中，第一金属层18还包括栅极181。栅极181与扫描线182电连接。
在本申请实施例中，辅助扫描线213的电阻率小于扫描线182的电阻率，辅助扫描线213的宽度大于扫描线182的宽度。
其中，第一金属层18的材料为钼、钼钛合金等具有线宽偏差小的金属。从而能够采用干法蚀刻得到具有较小线宽的栅极181和扫描线182，进而实现较高的PPI（Pixels Per Inch，像素的密度单位）性能。同时可实现栅极181的线宽均一性，实现稳定的晶体管电学特性。
其中，第二金属层21的电阻率小于第一金属层18的电阻率。比如，第二金属层21可以是单层金属铜、双层金属、底层钼上层铜、底层钼钛合金上层铜等结构。由于第二金属层21的电阻率小于第一金属层18的电阻率，可以进一步降低扫描线182的阻抗，降低阵列基板100的负载。
在本申请实施例中，有源层16的材料可以是金属氧化物半导体，也可以是低温多晶硅。当然，在本申请一些实施例中，也可以采用LTPO (Low Temperature Polycrystalline-Si Oxide，低温多晶氧化物)技术，本申请对此不作具体限定。
在本申请实施例中，基板10可以包括但不限于从下至上依次叠层设置的衬底11、双层PI（Polyimide，聚酰亚胺）层12以及阻隔层13。其中，衬底11可以是玻璃基板。阻隔层13的材料可以是氧化硅、氮化硅等。阻隔层13可以起到阻水隔氧的作用。
在本申请实施例中，第二金属层21还可以包括栅极扫描线214。栅极扫描线214与栅极181电连接。由于第二金属层21的电阻率较小，可以减小栅极181的阻抗。
在本申请实施例中，阵列基板100还可以包括第一绝缘层17和层间绝缘层20。第一绝缘层17设置在第一金属层18靠近有源层16的一侧。第一绝缘层17包括栅绝缘层171。栅绝缘层171设置在栅极181和有源层16之间。层间绝缘层20设置在第一金属层18靠近第二金属层21的一侧。
其中，层间绝缘层20具有第一接触孔20a、第二接触孔20b以及第三接触孔20c。第一接触孔20a和第二接触孔20b均贯穿层间绝缘层20，并延伸至有源层16。第一接触孔20a和第二接触孔20b均暴露出有源层16远离基板10的一侧表面。源极211通过第一接触孔20a与有源层16电连接。漏极212通过第二接触孔20b与有源层16电连接。第三接触孔20c贯穿层间绝缘层20，并延伸至扫描线182。第三接触孔20c暴露出扫描线182远离基板10的一侧表面。辅助扫描线213通过第三接触孔20c与扫描线182电连接。
其中，层间绝缘层20还具有第四接触孔20d。第四接触孔20d贯穿层间绝缘层20，并延伸至栅极181。第四接触孔20d暴露出栅极181远离基板10的一侧表面。栅极扫描线214通过第四接触孔20d与栅极181电连接。
其中，第一金属层18还包括第一电极板183。第二金属层21还包括第三电极板215。在垂直于基板100的方向上，第一电极板183和第三电极板215至少部分重叠设置。第一电极板183和第三电极板215可以构成存储电容。
当然，在本申请一些实施例中，源极211以及漏极212也可以分别与有源层16接触电连接，此时可以不设置层间绝缘层20。
进一步的，在本申请一些实施例中，阵列基板100还可以包括第二绝缘层19和第五金属层30。
其中，第二绝缘层19设置在第一金属层18靠近第二金属层21的一侧。第五金属层30设置在第二绝缘层19靠近第二金属层21的一侧。层间绝缘层20设置在第五金属层30靠近第二金属层21的一侧。第五金属层30包括第二电极板31。第一电极板183和第二电极板31板构成第一电容。第二电极板31和第三电极板215构成第二电容。由此，简化阵列基板100内的电容结构。
在本申请实施例中，阵列基板100还可以包括第四金属层24。第四金属层24设置在第二金属层21远离基板10的一侧。第四金属层24包括数据线（图中未示出）。
可以理解的是，辅助扫描线213与数据线在面内交叉排布，由于辅助扫描线213、源极211以及漏极212同层设置，将数据线设置在第四金属层24中，使得数据线与辅助扫描线213异层设置，可以避免数据线与辅助扫描线213交叉短接。
其中，第四金属层24还包括第一电极241和第二电极242。数据线通过第一电极241与源极211电连接。第二电极242与漏极212电连接。当然，在一些实施例中，也可以认为第一电极241为数据线。
其中，第四金属层24可以是单层金属铜、双层金属、底层钼上层铜、底层钼钛合金上层铜等结构。第四金属层24的材料可以与第二金属层21的材料相同，也可以不相同。
本申请实施例设置第一电极241与源极211电连接，以及第二电极242与漏极212电连接，可以进一步降低源极211和漏极212的阻抗，降低阵列基板100的负载。
此外，由于第二金属层21和第四金属层24的线阻抗低，在垂直于基板10的方向上，基于同样的厚度，可以将第二金属层21和第四金属层24的线宽做细约20%，进一步实现较高的PPI性能。
在本申请实施例中，阵列基板100还可以包括钝化层22、第一平坦层23以及第二平坦层25。钝化层22设置在第二金属层21靠近第四金属层24的一侧。第一平坦层23设置在钝化层22靠近第四金属层24的一侧第二平坦层25设置在第四金属层24远离基板10的一侧。
其中，第一平坦层23具有第一电连接孔23a和第二电连接孔23b。第一电连接孔23a贯穿第一平坦层23，并延伸至源极211。第一电连接孔23a暴露出源极211远离基板10的一侧表面。第一电极241通过第一电连接孔23a与源极211电连接。第二电连接孔23b贯穿第一平坦层23，并延伸至漏极212。第二电连接孔23b暴露出漏极212远离基板10的一侧表面。第二电极242通过第二电连接孔23b与漏极212电连接。
在本申请一些实施例中，钝化层22具有第一过孔22a。第一过孔22a贯穿钝化层22。第一平坦层23填充第一过孔22a。
其中，第一平坦层23和第二平坦层25的材料为有机材料，以提高阵列基板100的柔韧性。比如，有机材料可以是正型的有机光阻（主体是PI的成分）。
由于第一平坦层23的材料为有机材料，在钝化层22中设置第一过孔22a，并填充第一平坦层23，可以进一步提高阵列基板100的抗弯折性。
进一步的，在本申请一些实施例中，层间绝缘层20具有第二过孔20e。第二过孔20e贯穿层间绝缘层20，并延伸至第一绝缘层17。第一绝缘层17具有第三过孔17a。第三过孔17a至少贯穿第一绝缘层17。其中，第一过孔22a、第二过孔20e以及第三过孔17a均连通。且第二过孔20e的孔径大于第三过孔17a的孔径。
其中，第三过孔17a可以贯穿第一绝缘层17，并延伸至双层PI层12远离衬底11的一侧。第一平坦层23填充在第一过孔22a、第二过孔20e以及第三过孔17a中，可以进一步提高阵列基板100的抗弯折性。
进一步的，第四金属层24还包括至少一信号走线243。信号走线243对应第一过孔22a设置。信号走线243是阵列基板100中实现显示区域***Fan-out（扇形走线区）处的信号线的桥接。
在本申请实施例中，阵列基板100还可以包括第三金属层14。第三金属层14设置在有源层16靠近基板10的一侧。第三金属层14包括遮光件141。遮光件141在基板10上的正投影至少覆盖有源层16在基板10上的正投影。
其中，第三金属层14的材料为导电性优、遮光性好的金属，一般为钼、铜、铝、钛或复合金属，本申请对此不作限定。此外，阵列基板100还包括缓冲层15。缓冲层15设置在第三金属层14和有源层16之间，起到绝缘保护的作用。
可以理解的是，有源层16在受到来自基板10一侧的光照射后会使得光生载流子增加，造成薄膜晶体管产生阈值电压漂移、漏电流增加等不良现象。遮光件141可以遮挡从基板10远离遮光件141的方向射入的光线，进而减弱外部光线对有源层16产生的干扰，从而提高阵列基板100的工作性能。
在本申请实施例中，阵列基板100还可以包括第六金属层26、像素定义层27以及间隔物28。第六金属层26包括阳极261。阳极261与漏极212电连接。像素定义层27具有开口27a。开口27a暴露出阳极261远离基板10的一侧表面。开口27a内可以设置发光层等功能膜层，在此不再赘述。
请参阅图2，图2是本申请提供的阵列基板的第二结构示意图。与图1所示的阵列基板100的不同之处在于，在本申请实施例中，遮光件141与扫描线182电连接。
具体的，第一绝缘层17具有第四过孔17b。遮光件141通过第四过孔17b与扫描线182电连接。由此，遮光件141、扫描线182以及辅助扫描线213均电连接在一起，进一步降低了扫描线182的电阻率，降低了阵列基板100的负载。
在本申请一些实施例中，阵列基板100中的晶体管为顶底双栅结构。其中，晶体管包括有源层16、栅极181、源极211、漏极212以及遮光件141（作为底栅）。遮光件141与栅极181通过扫描线182和辅助扫描线213接入同一电信号。
具体的，请参阅图2和图3。图3是本申请提供的阵列基板的第一俯视示意图。第三金属层14包括多个遮光件141。每一遮光件141均包括第一遮光部1411和第二遮光部1412。第一遮光部1411在基板10上的正投影至少覆盖有源层16在基板10上的正投影。第二遮光部1412与扫描线182电连接在一起。相邻两个第一遮光部1411通过第二遮光部1412电连接。也即，在阵列基板100的显示区域中，多个遮光件141是连续的结构。
其中，第二金属层21包括多个间隔设置的栅极扫描线214。第一金属层18包括多个间隔且绝缘设置的栅极181。每一栅极一端与相应的一条栅极扫描线214电连接。每一栅极另一端也与相应的一条栅极扫描线214电连接。
本申请实施例在有源层16的上下两侧分别设置栅极181（顶栅极）和遮光件141（底栅极），通过双栅极驱动有源层16，更容易控制阈值电压；同时，还可以大幅提升载流子迁移率。
在本申请一些实施例中，第一遮光部1411的线宽大于有源层16的线宽，第二遮光部1412的线宽大于或等于辅助扫描线213的线宽。
通过设置第一遮光部1411的线宽大于有源层16的线宽，可以减弱外部光线对有源层16产生的干扰。通过设置第二遮光部1412的线宽大于或等于辅助扫描线213的线宽，这样可以实现减少辅助扫描线213同层的耦合电容。同时也可以减少辅助扫描线213与其它层金属之间交叠产生的寄生电容。
需要说明的是，辅助扫描线213与栅极扫描线214属于第二金属层21，辅助扫描线213与栅极扫描线214可以相同。
在本申请一些实施例中，阵列基板100中的晶体管为顶栅结构。
具体的，请参阅图4和图5，图4是本申请提供的阵列基板的第三结构示意图；图5是本申请提供的阵列基板的第二俯视示意图。与图2所示的阵列基板100的不同之处在于，在本申请实施例中，遮光件141包括第一遮光部1411和第二遮光部1412。第一遮光部1411在基板10上的正投影至少覆盖有源层16在基板10上的正投影。第二遮光部1412与第一遮光部1411间隔且绝缘设置。第二遮光部1412与扫描线182电连接。
其中，第二金属层21还包括多个间隔设置的栅极扫描线214。第一金属层18包括多个间隔且绝缘设置的栅极181。每一栅极181通过第四接触孔20d与相应的栅极扫描线214电连接，且相邻两个栅极181之间通过相应的栅极扫描线214电连接。
请同时参阅图2、图6A-图6K，图6A-6K是在本申请提供的阵列基板的一种制作方法中各步骤获得的结构示意图。本申请以图2所示的阵列基板100为例进行说明，但不能理解为对本申请的限定。本申请实施例提供的阵列基板100的制作方法具体包括以下步骤：
101、提供基板10。
其中，基板10可以包括但不限于从下至上依次叠层设置的衬底11、双层PI（Polyimide，聚酰亚胺）层12以及阻隔层13。其中，衬底11可以是玻璃基板。
102、在完成基板10上的第三金属层14、有源层16的图案化后，第三金属层14包括遮光件141。然后，在有源层16远离基板10的一侧形成第一绝缘层17，并在第一绝缘层17远离基板10的一侧涂布第一光刻胶41，如图6A所示。
103、依次对第一绝缘层17进行成膜、曝光以及干法蚀刻，在第一绝缘层17中形成第四过孔17b。如图6B所示。
104、完成第一金属层18成膜、在第一金属层18上涂布第二光刻胶42，如图6C所示。
然后，对第一金属层18进行图形化处理，形成栅极181、扫描线182以及第一电极板183，如图6D所示。
随后，完成第二绝缘层19成膜以及第五金属层30成膜。对第五金属层30图形化处理，形成包括第二电极板31。在第五金属层30上形成层间绝缘层20，如图6E所示。
105、在层间绝缘层20成膜后，在层间绝缘层20涂布第三光刻胶43，如图6F所示。
然后进行曝光以及干法蚀刻，在层间绝缘层20中形成第一接触孔20a、第二接触孔20b、第三接触孔20c以及第四接触孔20d。第一接触孔20a和第二接触孔20b均贯穿层间绝缘层20，并延伸至有源层16。第一接触孔20a和第二接触孔20b均暴露出有源层16远离基板10的一侧表面。第三接触孔20c暴露出扫描线182远离基板10的一侧表面。第四接触孔20d暴露出栅极181远离基板10的一侧表面。如图6G所示。
随后，形成具有低电阻率的第二金属层21，如图6H所示。第二金属层21上涂布第四光刻胶44，如图6I所示。经过曝光和蚀刻完成图形化，形成源极211、漏极212以及辅助扫描线213、栅极扫描线214以及第三电极板215。源极211通过第一接触孔20a与有源层16电连接。漏极212通过第二接触孔20b与有源层16电连接。辅助扫描线213通过第三接触孔20c与扫描线182电连接。栅极181通过第四接触孔20d与栅极扫描线214电连接。第一电极板183和第二电极板31板构成第一电容。第二电极板31和第三电极板215构成第二电容。如图6J所示。
106、依次在完成钝化层22成膜、第一平坦层23成膜以及第四金属层24成膜。对第四金属层24进行图形化处理，形成第一电极241、第二电极242以及至少一信号走线243。第一电极241与源极211电连接。第二电极242与漏极212电连接。
然后完成第二平坦层25成膜和第六金属层26成膜。对第六金属层26进行图形化处理，形成阳极261。最后再进行像素定义层27和间隔物28的图形化处理，完成整个阵列基板100的工艺。
需要说明的是，图6A-6J中未示出深孔的具体形成过程。在本申请一实施例中。深孔通过三次刻蚀形成。具体的，如图6K钝化层22具有第一过孔22a。第一过孔22a贯穿钝化层22。层间绝缘层20具有第二过孔20e。第二过孔20e贯穿层间绝缘层20，并延伸至第一绝缘层17。第一绝缘层17具有第三过孔17a。第三过孔17a至少贯穿第一绝缘层17。其中，第一过孔22a、第二过孔20e以及第三过孔17a均连通，形成深孔。且第二过孔20e的孔径大于第三过孔17a的孔径。其中，第一过孔22a、第二过孔20e以及第三过孔17a经过的三次刻蚀可以与上述步骤中各孔的刻蚀步骤一起，从而简化制成工艺。
其中，第一平坦层23填充在第一过孔22a、第二过孔20e以及第三过孔17a中，可以进一步提高阵列基板100的抗弯折性。
此外，阵列基板100中各膜层的材料以及功能可参阅上述实施例，在阵列基板100的制作方法中不再赘述。
相应的，本申请还提供一种显示面板，其包括上述任一实施例所述的阵列基板100。具体可参阅以上内容，在此不再赘述。此外，本申请提供的显示面板可以是有机发光二极管显示面板、主动矩阵有机发光二极管显示面板、被动矩阵有机发光二极管显示面板、量子点有机发光二极管显示面板或者微发光二极管显示面板，本申请对此不作具体限定。
在本申请一实施例中，请参阅图7，图7是本申请提供的显示面板的一种结构示意图。本申请实施例提供的显示面板1000还包括GOA电路300和其他功能部件。此外，本申请实施例中的GOA电路300和其他功能部件是本领域技术人员所熟知的相关技术，在此不再赘述。
本申请提供的显示面板1000包括阵列基板100，阵列基板包括基板、有源层、第一金属层以及第二金属层。其中，有源层设置在基板上；第一金属层设置在有源层远离所述基板的一侧，第一金属层包括栅极和扫描线；第二金属层设置在第一金属层远离所述基板的一侧；第二金属层包括源极、漏极以及辅助扫描线；源极以及漏极分别与有源层电连接，辅助扫描线与扫描线电连接。本申请实施例通过设置辅助扫描线与扫描线电连接，可以降低扫描线的阻抗，从而降低阵列基板的负载，提高显示面板1000的品质。此外，由于辅助扫描线、源极以及漏极由同一层金属图案化形成，可以简化制程工艺。
以上对本申请实施例提供的阵列基板及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板，包括：
    基板；
    有源层，设置在所述基板上；
    第一金属层，设置在所述有源层远离所述基板的一侧，所述第一金属层包括扫描线；以及
    第二金属层，设置在所述第一金属层远离所述基板的一侧，所述第二金属层包括源极、漏极以及辅助扫描线，所述源极和所述漏极分别与所述有源层电连接，所述辅助扫描线与所述扫描线电连接。
  2. 根据权利要求1所述的阵列基板，其中，所述辅助扫描线的电阻率小于所述扫描线的电阻率，所述辅助扫描线的宽度大于所述扫描线的宽度。
  3. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括第三金属层，所述第三金属层设置在所述有源层靠近所述基板的一侧，所述第三金属层包括遮光件，所述遮光件在所述基板上的正投影至少覆盖所述有源层在所述基板上的正投影，所述遮光件与所述扫描线电连接，并接入同一电信号。
  4. 根据权利要求3所述的阵列基板，其中，所述第三金属层包括多个所述遮光件，每一所述遮光件均包括第一遮光部和第二遮光部，所述第一遮光部在所述基板上的正投影至少覆盖所述有源层在所述基板上的正投影，所述第二遮光部与所述扫描线电连接在一起；相邻两个所述第一遮光部通过所述第二遮光部电连接。
  5. 根据权利要求4所述的阵列基板，其中，所述第一遮光部的线宽大于所述有源层的线宽，所述第二遮光部的线宽大于或等于所述辅助扫描线的线宽。
  6. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括第三金属层，所述第三金属层设置在所述有源层靠近所述基板的一侧，所述第三金属层包括遮光件，所述遮光件包括第一遮光部和第二遮光部，所述第一遮光部在所述基板上的正投影至少覆盖所述有源层在所述基板上的正投影，所述第二遮光部与所述第一遮光部间隔且绝缘设置，所述第二遮光部与所述扫描线电连接。
  7. 根据权利要求3所述的阵列基板，其中，所述第一金属层还包括多个间隔且绝缘设置的栅极，所述第二金属层还包括多个栅极扫描线；
    其中，每一所述栅极与相应的所述栅极扫描线电连接，且相邻两个所述栅极之间通过相应的所述栅极扫描线电连接，所述栅极扫描线与所述辅助扫描线电连接。
  8. 根据权利要求1所述的阵列基板，其中，所述第一金属层的材料为钼或钼钛合金，所述第二金属层的材料为铜、铜/铜、钼/铜或钼钛合金/铜。
  9. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括第四金属层，所述第四金属层设置在所述第二金属层远离所述基板的一侧，所述第四金属层包括数据线，所述数据线与所述源极电连接。
  10. 根据权利要求9所述的阵列基板，其中，所述阵列基板还包括第一绝缘层、第二绝缘层、第五金属层以及层间绝缘层；
    其中，所述第一绝缘层设置在所述第一金属层靠近所述有源层的一侧，所述第二绝缘层设置在所述第一金属层靠近所述第二金属层的一侧，所述第五金属层设置在所述第二绝缘层靠近所述第二金属层的一侧，所述层间绝缘层设置在所述第五金属层靠近所述第二金属层的一侧；所述第一金属层还包括第一电极板，所述第五金属层包括第二电极板，所述第二金属层还包括第三电极板；所述第一电极板和所述第二电极板构成第一电容，所述第二电极板和所述第三电极板构成第二电容。
  11. 根据权利要求10所述的阵列基板，其中，所述阵列基板还包括钝化层、第一平坦层以及第二平坦层，所述钝化层设置在所述第二金属层靠近所述第四金属层的一侧，所述第一平坦层设置在所述钝化层靠近所述第四金属层的一侧，所述第二平坦层设置在所述第四金属层远离所述基板的一侧；
    其中，所述钝化层具有第一过孔，所述第一过孔贯穿所述钝化层，所述第一平坦层填充所述第一过孔。
  12. 根据权利要求11所述的阵列基板，其中，所述层间绝缘层具有第二过孔，所述第二过孔贯穿所述层间绝缘层，并延伸至所述第一绝缘层，所述第一绝缘层具有第三过孔，所述第三过孔至少贯穿所述第一绝缘层；
    其中，所述第一过孔、所述第二过孔以及所述第三过孔均连通，且所述第二过孔的孔径大于所述第三过孔的孔径。
  13. 一种显示面板，包括阵列基板，所述阵列基板，包括：
    基板；
    有源层，设置在所述基板上；
    第一金属层，设置在所述有源层远离所述基板的一侧，所述第一金属层包括扫描线；以及
    第二金属层，设置在所述第一金属层远离所述基板的一侧，所述第二金属层包括源极、漏极以及辅助扫描线，所述源极和所述漏极分别与所述有源层电连接，所述辅助扫描线与所述扫描线电连接。
  14. 根据权利要求13所述的显示面板，其中，所述辅助扫描线的电阻率小于所述扫描线的电阻率，所述辅助扫描线的宽度大于所述扫描线的宽度。
  15. 根据权利要求13所述的显示面板，其中，所述阵列基板还包括第三金属层，所述第三金属层设置在所述有源层靠近所述基板的一侧，所述第三金属层包括遮光件，所述遮光件在所述基板上的正投影至少覆盖所述有源层在所述基板上的正投影，所述遮光件与所述扫描线电连接，并接入同一电信号。
  16. 根据权利要求15所述的显示面板，其中，所述第三金属层包括多个所述遮光件，每一所述遮光件均包括第一遮光部和第二遮光部，所述第一遮光部在所述基板上的正投影至少覆盖所述有源层在所述基板上的正投影，所述第二遮光部与所述扫描线电连接在一起；相邻两个所述第一遮光部通过所述第二遮光部电连接。
  17. 根据权利要求16所述的显示面板，其中，所述第一遮光部的线宽大于所述有源层的线宽，所述第二遮光部的线宽大于或等于所述辅助扫描线的线宽。
  18. 根据权利要求13所述的显示面板，其中，所述阵列基板还包括第三金属层，所述第三金属层设置在所述有源层靠近所述基板的一侧，所述第三金属层包括遮光件，所述遮光件包括第一遮光部和第二遮光部，所述第一遮光部在所述基板上的正投影至少覆盖所述有源层在所述基板上的正投影，所述第二遮光部与所述第一遮光部间隔且绝缘设置，所述第二遮光部与所述扫描线电连接。
  19. 根据权利要求15所述的显示面板，其中，所述第一金属层还包括多个间隔且绝缘设置的栅极，所述第二金属层还包括多个栅极扫描线；
    其中，每一所述栅极与相应的所述栅极扫描线电连接，且相邻两个所述栅极之间通过相应的所述栅极扫描线电连接，所述栅极扫描线与所述辅助扫描线电连接。
  20. 根据权利要求13所述的显示面板，其中，所述第一金属层的材料为钼或钼钛合金，所述第二金属层的材料为铜、铜/铜、钼/铜或钼钛合金/铜。
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CN114512523A (zh) * 2022-02-15 2022-05-17 深圳市华星光电半导体显示技术有限公司 阵列基板及显示面板
CN115347001A (zh) * 2022-08-03 2022-11-15 武汉华星光电半导体显示技术有限公司 阵列基板及显示面板

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