WO2020206747A1 - 显示器 - Google Patents

显示器 Download PDF

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Publication number
WO2020206747A1
WO2020206747A1 PCT/CN2019/084165 CN2019084165W WO2020206747A1 WO 2020206747 A1 WO2020206747 A1 WO 2020206747A1 CN 2019084165 W CN2019084165 W CN 2019084165W WO 2020206747 A1 WO2020206747 A1 WO 2020206747A1
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WO
WIPO (PCT)
Prior art keywords
notch
edge portion
substrate
film transistor
thin film
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Application number
PCT/CN2019/084165
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English (en)
French (fr)
Inventor
李丽霞
王勐
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2020206747A1 publication Critical patent/WO2020206747A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays

Definitions

  • the invention relates to a display, in particular to a display with a new test pad arrangement design.
  • the conventional cell test pad is placed on the chip side.
  • the chip test pad is divided into source signals and GOA signals, as well as functional signals (Acom, Cfcom, etc.).
  • the gate signal is mainly a timing signal (CK).
  • CK timing signal
  • COF color film
  • TFT thin film transistor
  • FIG. 1 is a schematic diagram of the arrangement of chip test pads of a conventional display
  • FIG. 2 is a schematic diagram of the arrangement of chip test pads of another conventional display.
  • the display 100 shown in FIG. 1 includes a thin film transistor (TFT) substrate 110; a color film (CF) substrate 120 disposed on the TFT substrate 110 and exposing the edge portion of the upper surface of the TFT substrate 110; and a plurality of chips For the test pad 130, the display 100 shown in FIG.
  • TFT thin film transistor
  • CF color film
  • the display 200 shown in FIG. 2 includes a thin film transistor (TFT) substrate 210; a color film (CF) substrate 220 disposed on the TFT substrate 210 and exposing the edge portion of the upper surface of the TFT substrate 210; and There are two chip test pads 230, 200 shown in FIG. 2 has a two-dimensional code 240 arranged in the middle of the edge of the display so that the chip test pad 210 can be arranged close to the corner of the display.
  • TFT thin film transistor
  • CF color film
  • the present invention provides a display, including; a thin film transistor (TFT) substrate; a color film (CF) substrate, disposed on the TFT substrate and exposing the TFT substrate The first edge portion of the upper surface, wherein at least two corners of the CF substrate each have a notch, and the notch exposes the upper surface of the TFT substrate, forming at least two notch areas on the TFT substrate And a plurality of chip test pads are disposed on the first edge portion and the notch area.
  • TFT thin film transistor
  • CF color film
  • the first edge portion and the notch area constitute an outer lead bonding (OLB) area.
  • the shape of the notch area includes the following groups: rectangular, fan-shaped, and irregular.
  • the arrangement of the plurality of chip test pads on the first edge portion and the notch area is independently the same or different.
  • the arrangement of the plurality of chip test pads includes the following groups: single row, double row, and multiple rows.
  • the CF substrate is a glass substrate.
  • the at least two notch regions are respectively located at a second edge portion and a third edge portion of the upper surface of the TFT substrate, wherein the second edge portion and the third edge The part is adjacent to the first edge part.
  • the display further includes: a base substrate located under the TFT substrate.
  • the display further includes: a light source located between the base substrate and the TFT substrate, wherein the light source includes at least one of the following: a backlight source and a side light source.
  • the display further includes: a display area including a plurality of scan lines and a plurality of data lines interlaced vertically with each other; and a non-display area located at the periphery of the display area, wherein the plurality of scan lines The line and the data lines extend to the non-display area, and are respectively connected with a plurality of external pins one-to-one, and the non-display area includes the first edge portion and the notch area.
  • the display further includes a plurality of external pins, and the plurality of external pins and the plurality of chip test pads are located in the outer pin bonding (OLB) area and are mutually Alternate configuration.
  • OLB outer pin bonding
  • the present invention provides a new display that adopts a special design that can increase the space for the arrangement of test pads.
  • the color film glass is dug out one more area, that is, the area on the side of the chip is enlarged, and the chip test pads are respectively placed in this area.
  • FIG. 1 is a schematic diagram of the arrangement of chip test pads of a conventional display.
  • FIG. 2 is a schematic diagram showing the arrangement of chip test pads of another conventional display.
  • FIG. 3 is a schematic diagram of the arrangement of chip test pads of a display according to an embodiment of the invention.
  • FIG. 4 is a schematic diagram showing the arrangement of chip test pads of a display according to another embodiment of the invention.
  • FIG. 5 is a schematic diagram showing the arrangement of chip test pads of a display according to another embodiment of the present invention.
  • FIG. 6 is a schematic diagram showing the arrangement of chip test pads of a display according to another embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a display according to an embodiment of the invention.
  • the embodiment of the present invention provides a new display, which adopts a special design that can increase the space for the arrangement of test pads.
  • the color film glass is dug out one more area, that is, the area on the side of the chip is enlarged.
  • the chip test pads are respectively placed in this area to solve the problem of limited space in the corners of the chip, and the surface can be used as far as possible to cut three times, so as to achieve the effect of saving productivity and reducing process steps and time.
  • a display 300 see FIG. 3.
  • 3 is a schematic diagram of the arrangement of chip test pads of a display according to an embodiment of the invention.
  • a display 300 according to an embodiment of the present invention includes: a thin film transistor (TFT) substrate 310; a color film (CF) substrate 320, which is disposed on the TFT substrate 310 and exposes all of them.
  • TFT thin film transistor
  • CF color film
  • At least two corners of the CF substrate 320 each have a notch, and the notch exposes the upper surface of the TFT substrate 310 to form at least two Notch regions 312, 313 are on the upper surface of the TFT substrate 310; and a plurality of chip test pads 330 are disposed on the first edge portion 310a and the notch regions 312, 313.
  • the first edge portion 310a and the notch areas 312, 313 form an outer lead bonding (OLB) area O.
  • OLB outer lead bonding
  • the shape of the notch areas 312, 313 is rectangular.
  • the arrangement of the plurality of chip test pads 330 on the first edge portion 310a and the notch areas 312, 313 is a single row.
  • the at least two notch regions 312, 313 are respectively located at the second edge portion 310b and the third edge portion 310c of the upper surface of the TFT substrate 310, The second edge portion 310b and the third edge portion 310c are adjacent to the first edge portion 310a.
  • the plurality of outer pins 350 and the plurality of chip test pads 330 are located in the outer pin bonding (OLB) area O, and are alternately arranged with each other.
  • the display 300 further includes: a display area (not shown), including a plurality of scan lines (not shown) and a plurality of data lines (FIG. (Not shown); and a non-display area (not shown), located at the periphery of the display area, wherein the multiple scan lines and multiple data lines extend to the non-display area, and are paired with multiple external pins 350, respectively A bonding, and the non-display area (not shown) includes the first edge portion 310a and the notch areas 312, 313, that is, includes the outer lead bonding (OLB) area O.
  • a display area including a plurality of scan lines (not shown) and a plurality of data lines (FIG. (Not shown); and a non-display area (not shown), located at the periphery of the display area, wherein the multiple scan lines and multiple data lines extend to the non-display area, and are paired with multiple external pins 350, respectively A bonding, and the non-display area (not shown) includes the first edge portion
  • the display 300 may further include: a base substrate 301 located under the TFT substrate 310; and a light source 302 located between the base substrate 301 and the TFT substrate 310 , wherein the light source 302 may include at least one of the following: a backlight source and a side light source.
  • a display 400 includes: a thin film transistor (TFT) substrate 410; a color film (CF) substrate 420, which is disposed on the TFT substrate 410 and exposes all The first edge portion of the upper surface of the TFT substrate 410, wherein at least two corners of the CF substrate 420 each have a notch, and the notch exposes the upper surface of the TFT substrate 410, forming at least two The notch regions 412, 413 are on the upper surface of the TFT substrate 410; and a plurality of chip test pads 430 are disposed on the first edge portion 410a and the notch regions 412, 413.
  • TFT thin film transistor
  • CF color film
  • the arrangement of the plurality of chip test pads 430 on the first edge portion 410a is a single row; and the plurality of chip test pads 430 are arranged in a single row.
  • the arrangement of the notch areas 412, 413 are all double rows, and the setting conditions of other components are similar to those of embodiment 1, such as the shape of the notch areas 412, 413 and the film structure of the display 400 For the corresponding parts, please refer to the description of Embodiment 1, which will not be repeated here.
  • a display 500 includes: a thin film transistor (TFT) substrate 510; a color film (CF) substrate 520 disposed on the TFT substrate 510 and exposing all The first edge portion of the upper surface of the TFT substrate 510, wherein at least two corners of the CF substrate 520 each have a notch, and the notch exposes the upper surface of the TFT substrate 510, forming at least two The notch areas 512, 513 are on the upper surface of the TFT substrate 510; and a plurality of chip test pads 530 are disposed on the first edge portion 510a and the notch areas 512, 513.
  • TFT thin film transistor
  • CF color film
  • Embodiment 3 of the present invention except that the arrangement of the plurality of chip test pads 530 on the first edge portion 510a includes single row and double row; and the plurality of chip test pads Except that the arrangement of 530 on the notch areas 512, 513 is a single row, the setting conditions of other components are similar to those of Embodiment 1, such as the shape of the notch areas 512, 513 and the film of the display 500
  • the corresponding parts such as the layer structure, please refer to the description of Embodiment 1, which will not be repeated here.
  • a display 600 is a schematic diagram showing the arrangement of chip test pads of a display according to another embodiment of the present invention.
  • a display 600 according to an embodiment of the present invention includes: a thin film transistor (TFT) substrate 610; a color film (CF) substrate 620, which is disposed on the TFT substrate 610 and exposes all The first edge portion of the upper surface of the TFT substrate 610, wherein at least two corners of the CF substrate 620 each have a notch, and the notch exposes the upper surface of the TFT substrate 610 to form at least two The notch regions 612, 613 are on the upper surface of the TFT substrate 610; and a plurality of chip test pads 630 are disposed on the first edge portion 610a and the notch regions 612, 613.
  • TFT thin film transistor
  • CF color film
  • Embodiment 4 of the present invention except that the arrangement of the plurality of chip test pads 630 on the first edge portion 610a includes single row and double row; and the plurality of chip test pads Except for the arrangement of 630 on the notch areas 612, 613 in double rows, the setting conditions of other components are similar to those of Embodiment 1, such as the shape of the notch areas 612, 613 and the film of the display 600
  • the corresponding parts such as the layer structure, please refer to the description of Embodiment 1, which will not be repeated here.
  • the CF substrate may be a glass substrate.
  • the shape of the notch area is rectangular, in other embodiments, the notch area can also have other shapes, including the following group consisting of: rectangle, sector, and Irregular shape.
  • the arrangement of the plurality of chip test pads on the first edge portion and the notch area only presents a single row and/or double row, but in other embodiments
  • the arrangement of the plurality of chip test pads on the first edge portion and the notch area can also be other same or different arrangements independently of each other, including the following groups: Single row, double row, and multiple rows.
  • the embodiment of the present invention provides a new display, which adopts a special design that can increase the space for the arrangement of test pads.
  • the color film glass is dug out one more area, that is, the area on the side of the chip is enlarged, and the chip test pad They are placed in this area to solve the problem of limited space in the corners of the chip, and can avoid the use of the surface to three times as much as possible to achieve the effect of saving productivity and reducing the process and production steps and time.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种显示器(300,400,500,600)，包括薄膜晶体管TFT基板(310,410,510,610)；彩膜CF基板(320,420,520,620)，配置于TFT基板(310,410,510,610)上并暴露出TFT基板(310,410,510,610)的上表面的第一边缘部分(310a,410a,510a,610a)，其中CF基板(320,420,520,620)中至少两个边角处各具有一个缺口，缺口暴露出TFT基板(310,410,510,610)的上表面，形成至少两缺口区(312,313,412,413,512,513,612,613)于TFT基板(310,410,510,610)的上表面；以及多个芯片测试垫(330,430,530,630)配置于第一边缘部分(310a,410a,510a,610a)及缺口区(312,313,412,413,512,513,612,613)上。

Description

显示器 技术领域
本发明涉及一种显示器，尤其涉及一种具有新式测试垫排布设计的显示器。
 背景技术
常规的芯片测试垫(cell test pad)放置在芯片(chip)侧，芯片测试垫分源极(source)的讯号和数组上栅极(GOA)的讯号，以及功能讯号（Acom、Cfcom等），对于数组上栅极(GOA)的芯片，其栅极(gate)的讯号主要为时序信号(CK)。随着分辨率的增加和画素尺寸(pixel size)变小，彩膜(COF)到薄膜晶体管(TFT)边的距离减小，若要提高分辨率则需要增加时序讯号数目，因此导致芯片角落空间受限。
图1为一种习知显示器的芯片测试垫排布示意图；图2为另一种习知显示器的芯片测试垫排布示意图。如图1及图2所示，当芯片测试垫排布的空间受限时，习知的芯片测试垫排布设计方案从图1进展到图2。图1所示显示器100包括薄膜晶体管(TFT)基板110；彩膜(CF)基板120，配置于所述TFT基板110上并暴露出所述TFT基板110的上表面的边缘部分；以及多个芯片测试垫130，图1所示显示器100系将二维码140配置在显示器100角落，占用了部分的芯片测试垫110可排布位置。图2所示显示器200包括薄膜晶体管(TFT)基板210；彩膜(CF)基板220，配置于所述TFT基板210上并暴露出所述TFT基板210的所述上表面的边缘部分；以及多个芯片测试垫230，图2所示200则将二维码240配置在显示器边缘中段让芯片测试垫210可排布靠近显示器角落位置。
随着分辨率进一步的增加，已经使用扫描线减半数据线加倍(half gate double data, HG2D)的画素(pixel)设计，导致空间进一步减小，需要三次切割，增加工艺制程步骤和工艺时间，如此一来，虽然将芯片测试垫配置于源极的一侧，具有区域切割工艺简单的优点，却无法避免芯片空间受限时需使用三次切割，增加机台，增加制程步骤和工艺时间的缺点。
 技术问题
为了解决芯片角落空间受限，亟需开发一种新的显示器，采用可增加测试垫排布空间的特殊设计。
 技术解决方案
据此，依据本发明的一实施例，本发明提供了一种显示器，包括；薄膜晶体管(TFT)基板；彩膜(CF)基板，配置于所述TFT基板上并暴露出所述TFT基板的上表面的第一边缘部分，其中所述CF基板中至少两个边角处各具有一个缺口，所述缺口暴露出所述TFT基板的所述上表面，形成至少两缺口区于所述TFT基板的所述上表面；以及多个芯片测试垫配置于所述第一边缘部分及所述缺口区上。
在本发明的一实施例中，所述第一边缘部分及所述缺口区组成一外引脚接合(OLB)区。
在本发明的一实施例中，所述缺口区的形状包括下列所组成的群组：矩形、扇形、以及不规则形。
在本发明的一实施例中，所述多个芯片测试垫于所述第一边缘部分及所述缺口区上的排布方式各自独立地为相同或相异。
在本发明的一实施例中，所述多个芯片测试垫的排布方式包括下列所组成的群组：单排、双排、以及多排。
在本发明的一实施例中，所述CF基板为一玻璃基板。
在本发明的一实施例中，所述所述至少两缺口区分别位于所述TFT基板的所述上表面的第二边缘部分及第三边缘部分，其中所述第二边缘部分及第三边缘部分与所述第一边缘部分相邻。
在本发明的一实施例中，所述显示器更包括：衬底基板位于所述TFT基板下。
在本发明的一实施例中，所述显示器更包括：光源位于所述衬底基板及所述TFT基板之间，其中所述光源包括下列至少一者：背光源及侧光源。
在本发明的一实施例中，所述显示器还包括：显示区，包括彼此垂直交错的多条扫描线及多条数据线；以及非显示区，位于显示区的***，其中所述多条扫描线及多条数据线延伸至所述非显示区，分别与多个外引脚一对一接合，且所述非显示区包括所述第一边缘部分及所述缺口区。
在本发明的一实施例中，所述显示器更包括多个外引脚，所述多个外引脚与所述多个芯片测试垫共同位于所述外引脚接合(OLB)区内，彼此交替配置。
 有益效果
本发明提供一种新的显示器，采用可增加测试垫排布空间的特殊设计，将彩膜玻璃多挖出一个区域，即在芯片侧面的扩大了区域，将芯片测试垫分别放置在此区，以解决芯片角落空间受限的问题，且可尽量避面使用到三次切割，达到节省产能的效果和降低工艺制作步骤及时间。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种习知显示器的芯片测试垫排布示意图。
图2为另一种习知显示器的芯片测试垫排布示意图。
图3为依据本发明一实施例之显示器的芯片测试垫排布示意图。
图4为依据本发明另一实施例之显示器的芯片测试垫排布示意图。
图5为依据本发明又一实施例之显示器的芯片测试垫排布示意图。
图6为依据本发明再一实施例之显示器的芯片测试垫排布示意图。
图7为依据本发明一实施例之显示器的示意图。
 本发明的最佳实施方式
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式作详细说明。
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[纵向]、[横向]、[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
为了克服习知显示器的缺点，本发明实施例提供一种新的显示器，采用可增加测试垫排布空间的特殊设计，将彩膜玻璃多挖出一个区域，即在芯片侧面的扩大了区域，将芯片测试垫分别放置在此区，以解决芯片角落空间受限的问题，且可尽量避面使用到三次切割，达到节省产能的效果和降低工艺制作步骤及时间。
实施例1
据此，依据本发明的一实施例1，本发明提供了一种显示器300，参见图3。图3为依据本发明一实施例之显示器的芯片测试垫排布示意图。如图3所示，具体而言，依据本发明之一实施例的显示器300包括：薄膜晶体管(TFT)基板310；彩膜(CF)基板320，配置于所述TFT基板310上并暴露出所述TFT基板310的上表面的第一边缘部分，其中所述CF基板320中至少两个边角处各具有一个缺口，所述缺口暴露出所述TFT基板310的所述上表面，形成至少两缺口区312, 313于所述TFT基板310的所述上表面；以及多个芯片测试垫330配置于所述第一边缘部分310a及所述缺口区312, 313上。
继续参见图3，在实施例1中，所述第一边缘部分310a及所述缺口区312, 313组成一外引脚接合(OLB)区O。
继续参见图3，在本发明的实施例1中，所述缺口区312, 313的形状为矩形。
继续参见图3，在本发明的实施例1中，所述多个芯片测试垫330于所述第一边缘部分310a及所述缺口区312, 313上的排布方式皆为单排。
继续参见图3，在本发明的实施例1中，所述所述至少两缺口区312, 313分别位于所述TFT基板310的所述上表面的第二边缘部分310b及第三边缘部分310c，其中所述第二边缘部分310b及第三边缘部分310c与所述第一边缘部分310a相邻。
如图3所示，在本发明的实施例1中，所述多个外引脚350与所述多个芯片测试垫330共同位于所述外引脚接合(OLB)区O，彼此交替配置。
继续参见图3，在本发明的实施例1中，所述显示器300还包括：显示区(图未示)，包括彼此垂直交错的多条扫描线(图未示)及多条数据线(图未示)；以及非显示区(图未示)，位于显示区的***，其中所述多条扫描线及多条数据线延伸至所述非显示区，分别与多个外引脚350一对一接合，且所述非显示区(图未示)包括所述第一边缘部分310a及所述缺口区312, 313，亦即包括所述外引脚接合(OLB)区O。
参见图7，图7为依据本发明一实施例之显示器的示意图。具体而言，在本发明的实施例1中，所述显示器300可更包括：衬底基板301位于所述TFT基板310下；以及光源302位于所述衬底基板301及所述TFT基板310之，其中所述光源302可包括下列至少一者：背光源及侧光源。
实施例2
依据本发明的一实施例2，本发明提供了一种显示器400，参见图4。图4为依据本发明另一实施例之显示器的芯片测试垫排布示意图。如图4所示，具体而言，依据本发明之一实施例的显示器400包括：薄膜晶体管(TFT)基板410；彩膜(CF)基板420，配置于所述TFT基板410上并暴露出所述TFT基板410的上表面的第一边缘部分，其中所述CF基板420中至少两个边角处各具有一个缺口，所述缺口暴露出所述TFT基板410的所述上表面，形成至少两缺口区412, 413于所述TFT基板410的所述上表面；以及多个芯片测试垫430配置于所述第一边缘部分410a及所述缺口区412, 413上。
继续参见图4，在本发明的实施例2中，除了所述多个芯片测试垫430于所述第一边缘部分410a的排布方式皆为单排；而所述多个芯片测试垫430于所述缺口区412, 413上的排布方式皆为双排以外，其他组件的设定条件皆与实施例1相似，像是所述缺口区412, 413的形状、以及显示器400的膜层结构等对应的部分请参考实施例1的描述，于此不再赘述。
实施例3
依据本发明的一实施例3，本发明提供了一种显示器500，参见图5。图5为依据本发明另一实施例之显示器的芯片测试垫排布示意图。如图5所示，具体而言，依据本发明之一实施例的显示器500包括：薄膜晶体管(TFT)基板510；彩膜(CF)基板520，配置于所述TFT基板510上并暴露出所述TFT基板510的上表面的第一边缘部分，其中所述CF基板520中至少两个边角处各具有一个缺口，所述缺口暴露出所述TFT基板510的所述上表面，形成至少两缺口区512, 513于所述TFT基板510的所述上表面；以及多个芯片测试垫530配置于所述第一边缘部分510a及所述缺口区512, 513上。
继续参见图5，在本发明的实施例3中，除了所述多个芯片测试垫530于所述第一边缘部分510a的排布方式包括单排及双排；而所述多个芯片测试垫530于所述缺口区512, 513上的排布方式皆为单排以外，其他组件的设定条件皆与实施例1相似，像是所述缺口区512, 513的形状、以及显示器500的膜层结构等对应的部分请参考实施例1的描述，于此不再赘述。
实施例4
依据本发明的一实施例4，本发明提供了一种显示器600，参见图6。图6为依据本发明另一实施例之显示器的芯片测试垫排布示意图。如图6所示，具体而言，依据本发明之一实施例的显示器600包括：薄膜晶体管(TFT)基板610；彩膜(CF)基板620，配置于所述TFT基板610上并暴露出所述TFT基板610的上表面的第一边缘部分，其中所述CF基板620中至少两个边角处各具有一个缺口，所述缺口暴露出所述TFT基板610的所述上表面，形成至少两缺口区612, 613于所述TFT基板610的所述上表面；以及多个芯片测试垫630配置于所述第一边缘部分610a及所述缺口区612, 613上。
继续参见图6，在本发明的实施例4中，除了所述多个芯片测试垫630于所述第一边缘部分610a的排布方式包括单排及双排；而所述多个芯片测试垫630于所述缺口区612, 613上的排布方式皆为双排以外，其他组件的设定条件皆与实施例1相似，像是所述缺口区612, 613的形状、以及显示器600的膜层结构等对应的部分请参考实施例1的描述，于此不再赘述。
在本发明的上述实施例中，所述CF基板可为一玻璃基板。
虽然在本发明的上述实施例中，所述缺口区的形状为矩形，然而在其他实施例中，所述缺口区亦可为其他形状，包括：下列所组成的群组：矩形、扇形、以及不规则形。
虽然在本发明的上述实施例中，所述多个芯片测试垫于所述第一边缘部分及所述缺口区上的排布方式仅呈现单排及/或双排，然而在其他实施例中，所述多个芯片测试垫于所述第一边缘部分及所述缺口区上的排布方式亦可各自独立地为其他相同或相异的排布方式，包括：下列所组成的群组：单排、双排、以及多排。
据此，本发明实施例提供了一种新的显示器，采用可增加测试垫排布空间的特殊设计，将彩膜玻璃多挖出一个区域，即在芯片侧面的扩大了区域，将芯片测试垫分别放置在此区，以解决芯片角落空间受限的问题，且可尽量避面使用到三次切割，达到节省产能的效果和降低工艺制作步骤及时间。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种显示器，包括：
    薄膜晶体管基板；
    彩膜基板，配置于所述薄膜晶体管基板上并暴露出所述薄膜晶体管基板的上表面的第一边缘部分，其中所述彩膜基板中至少两个边角处各具有一个缺口，所述缺口暴露出所述薄膜晶体管基板的所述上表面，形成至少两缺口区于所述薄膜晶体管基板的所述上表面；以及
    多个芯片测试垫配置于所述第一边缘部分及所述缺口区上，
    其中所述缺口区的形状包括下列所组成的群组：矩形、扇形、以及不规则形，以及所述多个芯片测试垫的排布方式包括下列所组成的群组：单排、双排、以及多排。
  2. 根据权利要求1所述的显示器，其中所述第一边缘部分及所述缺口区组成外引脚接合区。
  3. 根据权利要求1所述的显示器，其中所述多个芯片测试垫于所述第一边缘部分及所述缺口区上的排布方式各自独立地为相同或相异。
  4. 根据权利要求1所述的显示器，其中所述彩膜基板为玻璃基板。
  5. 根据权利要求1所述的显示器，其中所述至少两缺口区分别位于所述薄膜晶体管基板的所述上表面的第二边缘部分及第三边缘部分，其中所述第二边缘部分及第三边缘部分与所述第一边缘部分相邻。
  6. 根据权利要求1所述的显示器，更包括：
    衬底基板位于所述薄膜晶体管基板下。
  7. 根据权利要求6所述的显示器，更包括：
    光源位于所述衬底基板及所述薄膜晶体管基板之间，其中所述光源包括下列至少一者：背光源及侧光源。
  8. 根据权利要求7所述的显示器，其中更包括多个外引脚，所述多个外引脚与所述多个芯片测试垫共同位于所述外引脚接合区内，彼此交替配置。
  9. 一种显示器，包括：
    薄膜晶体管基板；
    彩膜基板，配置于所述薄膜晶体管基板上并暴露出所述薄膜晶体管基板的上表面的第一边缘部分，其中所述彩膜基板中至少两个边角处各具有一个缺口，所述缺口暴露出所述薄膜晶体管基板的所述上表面，形成至少两缺口区于所述薄膜晶体管基板的所述上表面；以及
    多个芯片测试垫配置于所述第一边缘部分及所述缺口区上。
  10. 根据权利要求9所述的显示器，其中所述第一边缘部分及所述缺口区组成外引脚接合区。
  11. 根据权利要求9所述的显示器，其中所述缺口区的形状包括下列所组成的群组：矩形、扇形、以及不规则形。
  12. 根据权利要求9所述的显示器，其中所述多个芯片测试垫于所述第一边缘部分及所述缺口区上的排布方式各自独立地为相同或相异。
  13. 根据权利要求9所述的显示器，其中所述多个芯片测试垫的排布方式包括下列所组成的群组：单排、双排、以及多排。
  14. 根据权利要求9所述的显示器，其中所述彩膜基板为玻璃基板。
  15. 根据权利要求9所述的显示器，其中所述至少两缺口区分别位于所述薄膜晶体管基板的所述上表面的第二边缘部分及第三边缘部分，其中所述第二边缘部分及第三边缘部分与所述第一边缘部分相邻。
  16. 根据权利要求9所述的显示器，更包括：
    衬底基板位于所述薄膜晶体管基板下。
  17. 根据权利要求16所述的显示器，更包括：
    光源位于所述衬底基板及所述薄膜晶体管基板之间，其中所述光源包括下列至少一者：背光源及侧光源。
  18. 根据权利要求17所述的显示器，更包括多个外引脚，所述多个外引脚与所述多个芯片测试垫共同位于所述外引脚接合区内，彼此交替配置。
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