WO2020140469A1 - 比较器和模数转换器 - Google Patents
比较器和模数转换器 Download PDFInfo
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- WO2020140469A1 WO2020140469A1 PCT/CN2019/104546 CN2019104546W WO2020140469A1 WO 2020140469 A1 WO2020140469 A1 WO 2020140469A1 CN 2019104546 W CN2019104546 W CN 2019104546W WO 2020140469 A1 WO2020140469 A1 WO 2020140469A1
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- transistor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
Definitions
- the invention relates to the technical field of integrated circuits, in particular, to a comparator and a corresponding analog-to-digital converter.
- analog-to-digital converter has developed rapidly.
- the comparator is the core device, and its accuracy and speed play a vital role in the entire analog-to-digital converter.
- the accuracy of the comparator determines the subtlety of the difference between the two signals that the comparator can compare.
- the speed of the comparator determines the response time of the comparator. Comparators with high accuracy are usually more complicated, so the response speed is relatively slow. Some simplified comparators can achieve a faster response speed, but their accuracy may not meet product requirements.
- the embodiments described herein provide comparators and analog-to-digital converters.
- a comparator includes: a first current source circuit, a pre-amplifier circuit, an amplifier circuit, a comparison circuit, and an output circuit.
- the first current source circuit is coupled to the pre-amplifier circuit, and is configured to provide a first constant current to the pre-amplifier circuit.
- the pre-amplifier circuit is coupled to the amplifier circuit via a first node and a second node, and is configured to amplify the first input signal from the first input terminal into a first pre-amplified signal according to the first constant current, Amplify the second input signal from the second input terminal into a second pre-amplified signal, and provide the first pre-amplified signal and the second to the amplifier circuit via the first node and the second node, respectively Pre-amplified signal.
- the amplifier circuit includes a current mirror and a load circuit.
- the amplifier circuit is coupled to the comparison circuit via a third node and a fourth node, and is configured to generate a first mirror signal of the first pre-amplified signal and a second pre-amplified signal through the current mirror
- a second image signal based on the first image signal and the second image signal, respectively, generates a first amplified signal and a second amplified signal through the load circuit, and respectively passes through the third node and the fourth
- the node provides the first amplified signal and the second amplified signal to the comparison circuit.
- the load circuit includes differential diode-connected transistors.
- the comparison circuit is coupled to the output circuit via a fifth node and is configured to compare the first amplified signal and the second amplified signal and provide the comparison to the output circuit via the fifth node the result of.
- the output circuit is configured to output a first voltage or a second voltage based on the result of the comparison.
- the current mirror includes a first current mirror and a second current mirror.
- the first current mirror is coupled to the first node, the first voltage terminal, the load circuit, and the third node.
- the first current mirror is configured to generate the first image signal according to the first pre-amplified signal and provide the first image signal to the third node.
- the second current mirror is coupled to the second node, the first voltage terminal, the load circuit, and the fourth node.
- the second current mirror is configured to generate the second image signal according to the second pre-amplified signal and provide the second image signal to the fourth node.
- the first current mirror includes a first transistor and a third transistor.
- the second current mirror includes a second transistor and a fourth transistor.
- the second electrode of the first transistor is coupled to the control electrode of the first transistor and the first node.
- the first electrode of the first transistor is coupled to the first voltage terminal.
- the second electrode of the second transistor is coupled to the control electrode of the second transistor and the second node.
- the first electrode of the second transistor is coupled to the first voltage terminal.
- the control electrode of the third transistor is coupled to the control electrode of the first transistor.
- the first electrode of the third transistor is coupled to the first voltage terminal.
- the second electrode of the third transistor is coupled to the third node.
- the control electrode of the fourth transistor is coupled to the control electrode of the second transistor.
- the first electrode of the fourth transistor is coupled to the first voltage terminal.
- the second electrode of the fourth transistor is coupled to the fourth node.
- the differential diode-connected transistor includes a fifth transistor and a sixth transistor.
- the second electrode of the fifth transistor is coupled to the control electrode of the fifth transistor and the third node.
- the first electrode of the fifth transistor is coupled to the second voltage terminal.
- the second electrode of the sixth transistor is coupled to the control electrode of the sixth transistor and the fourth node.
- the first electrode of the sixth transistor is coupled to the second voltage terminal.
- the differential diode-connected transistor further includes a seventh transistor and an eighth transistor.
- the control electrode of the seventh transistor is coupled to the control electrode of the fifth transistor.
- the first electrode of the seventh transistor is coupled to the second voltage terminal.
- the second electrode of the seventh transistor is coupled to the second electrode of the sixth transistor.
- the control electrode of the eighth transistor is coupled to the control electrode of the sixth transistor.
- the first electrode of the eighth transistor is coupled to the second voltage terminal.
- the second electrode of the eighth transistor is coupled to the second electrode of the fifth transistor.
- the amplifier circuit further includes a second current source circuit.
- the second current source circuit is coupled to the current mirror and the load circuit, and is configured to provide a second constant current to the load circuit.
- the second current source circuit includes a ninth transistor and a tenth transistor.
- the control electrode of the ninth transistor is coupled to the second bias voltage terminal.
- the first electrode of the ninth transistor is coupled to the second voltage terminal.
- the second electrode of the ninth transistor is coupled to the third node.
- the control electrode of the tenth transistor is coupled to the second bias voltage terminal.
- the first electrode of the tenth transistor is coupled to the second voltage terminal.
- the second electrode of the tenth transistor is coupled to the fourth node.
- the first current source circuit includes an eleventh transistor.
- the control electrode of the eleventh transistor is coupled to the first bias voltage terminal.
- the first electrode of the eleventh transistor is coupled to the second voltage terminal.
- the second electrode of the eleventh transistor is coupled to the pre-amplifier circuit.
- the pre-amplifier circuit includes a twelfth transistor and a thirteenth transistor.
- the control electrode of the twelfth transistor is coupled to the first input terminal.
- the first electrode of the twelfth transistor is coupled to the first current source circuit.
- the second electrode of the twelfth transistor is coupled to the first node.
- the control electrode of the thirteenth transistor is coupled to the second input terminal.
- the first electrode of the thirteenth transistor is coupled to the first electrode of the twelfth transistor.
- the second electrode of the thirteenth transistor is coupled to the second node.
- the comparison circuit includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor.
- the control electrode of the fourteenth transistor is coupled to the fourth node.
- the first electrode of the fourteenth transistor is coupled to the first voltage terminal.
- the second pole of the fourteenth transistor is coupled to the second pole of the sixteenth transistor.
- the control electrode of the fifteenth transistor is coupled to the third node.
- the first electrode of the fifteenth transistor is coupled to the first voltage terminal.
- the second electrode of the fifteenth transistor is coupled to the fifth node.
- the first electrode of the sixteenth transistor is coupled to the second voltage terminal.
- the control electrode of the sixteenth transistor is coupled to the second electrode of the sixteenth transistor.
- the control electrode of the seventeenth transistor is coupled to the control electrode of the sixteenth transistor.
- the first electrode of the seventeenth transistor is coupled to the second voltage terminal.
- the second electrode of the seventeenth transistor is coupled to the fifth node.
- the output circuit includes an eighteenth transistor and a nineteenth transistor.
- the control electrode of the eighteenth transistor is coupled to the fifth node.
- the first electrode of the eighteenth transistor is coupled to the first voltage terminal.
- the second electrode of the eighteenth transistor is coupled to the output signal terminal.
- the control electrode of the nineteenth transistor is coupled to the fifth node.
- the first electrode of the nineteenth transistor is coupled to the second voltage terminal.
- the second electrode of the nineteenth transistor is coupled to the output signal terminal.
- the ratio of the first constant current to the second constant current is greater than 2.
- a comparator includes first to eighth transistors and eleventh to nineteenth transistors.
- the second electrode of the first transistor is coupled to the control electrode of the first transistor and the first node.
- the first electrode of the first transistor is coupled to the first voltage terminal.
- the second electrode of the second transistor is coupled to the control electrode and the second node of the second transistor.
- the first electrode of the second transistor is coupled to the first voltage terminal.
- the control electrode of the third transistor is coupled to the control electrode of the first transistor.
- the first electrode of the third transistor is coupled to the first voltage terminal.
- the second electrode of the third transistor is coupled to the third node.
- the control electrode of the fourth transistor is coupled to the control electrode of the second transistor.
- the first electrode of the fourth transistor is coupled to the first voltage terminal.
- the second electrode of the fourth transistor is coupled to the fourth node.
- the second electrode of the fifth transistor is coupled to the control electrode of the fifth transistor and the third node.
- the first electrode of the fifth transistor is coupled to the second voltage terminal.
- the second electrode of the sixth transistor is coupled to the control electrode of the sixth transistor and the fourth node.
- the first electrode of the sixth transistor is coupled to the second voltage terminal.
- the control electrode of the seventh transistor is coupled to the control electrode of the fifth transistor.
- the first electrode of the seventh transistor is coupled to the second voltage terminal.
- the second electrode of the seventh transistor is coupled to the second electrode of the sixth transistor.
- the control electrode of the eighth transistor is coupled to the control electrode of the sixth transistor.
- the first electrode of the eighth transistor is coupled to the second voltage terminal.
- the second electrode of the eighth transistor is coupled to the second electrode of the fifth transistor.
- the control electrode of the eleventh transistor is coupled to the first bias voltage terminal.
- the first electrode of the eleventh transistor is coupled to the second voltage terminal.
- the second pole of the eleventh transistor is coupled to the first pole of the twelfth transistor and the first pole of the thirteenth transistor.
- the control electrode of the twelfth transistor is coupled to the first input terminal.
- the second electrode of the twelfth transistor is coupled to the first node.
- the control electrode of the thirteenth transistor is coupled to the second input terminal.
- the second electrode of the thirteenth transistor is coupled to the second node.
- the control electrode of the fourteenth transistor is coupled to the fourth node.
- the first electrode of the fourteenth transistor is coupled to the first voltage terminal.
- the second pole of the fourteenth transistor is coupled to the second pole of the sixteenth transistor.
- the control electrode of the fifteenth transistor is coupled to the third node.
- the first electrode of the fifteenth transistor is coupled to the first voltage terminal.
- the second electrode of the fifteenth transistor is coupled to the fifth node.
- the first electrode of the sixteenth transistor is coupled to the second voltage terminal.
- the control electrode of the sixteenth transistor is coupled to the second electrode of the sixteenth transistor.
- the control electrode of the seventeenth transistor is coupled to the control electrode of the sixteenth transistor.
- the first electrode of the seventeenth transistor is coupled to the second voltage terminal.
- the second electrode of the seventeenth transistor is coupled to the fifth node.
- the gate electrode of the eighteenth transistor is coupled to the fifth node.
- the first electrode of the eighteenth transistor is coupled to the first voltage terminal.
- the second electrode of the eighteenth transistor is coupled to the output signal terminal.
- the gate of the nineteenth transistor is coupled to the fifth node.
- the comparator further includes a ninth transistor and a tenth transistor.
- the control electrode of the ninth transistor is coupled to the second bias voltage terminal.
- the first electrode of the ninth transistor is coupled to the second voltage terminal.
- the second electrode of the ninth transistor is coupled to the third node.
- the control electrode of the tenth transistor is coupled to the second bias voltage terminal.
- the first electrode of the tenth transistor is coupled to the second voltage terminal.
- the second electrode of the tenth transistor is coupled to the fourth node.
- an analog-to-digital converter including the comparator as described in the first and second aspects of the present invention.
- FIG. 1 is a schematic block diagram of a comparator according to an embodiment of the present invention
- FIG. 2 is a schematic block diagram of an amplifier circuit in a comparator according to an embodiment of the present invention
- FIG. 3 is an exemplary circuit diagram of a comparator according to an embodiment of the present invention.
- FIG. 4 is an exemplary circuit diagram of a comparator according to another embodiment of the present invention.
- FIG. 5 is an exemplary circuit diagram of a comparator according to still another embodiment of the present invention.
- FIG. 6 is a schematic block diagram of an analog-to-digital converter according to an embodiment of the present invention.
- the source and drain (emitter and collector) of the transistor are symmetrical, and the source and drain (emitter and collector) of the N-type transistor and the P-type transistor are The direction of the on-current between them is opposite. Therefore, in the embodiment of the present invention, the controlled intermediate terminal of the transistor is called the control electrode, and the remaining two ends of the transistor are called the first electrode and the second electrode, respectively.
- terms such as “first” and “second” are only used to distinguish one component (or part of a component) from another component (or another part of a component).
- the currently studied comparators mainly include multi-stage open-loop comparators, switched capacitor comparators and dynamic latch regenerative comparators.
- the multi-stage open-loop comparator has high accuracy, but due to the bandwidth limitation of the multi-stage amplifier, the response speed is difficult to increase.
- the switched capacitor comparator can use offset cancellation technology to eliminate offset voltage to improve accuracy.
- the switched capacitor comparator has serious charge injection and clock feedthrough effects. This increases the difficulty of designing a switched capacitor comparator.
- the dynamic latch comparator has a fast response speed, but the kick-back noise and offset voltage are large, which is not suitable for high-precision systems. For this reason, a comparator with high accuracy (low offset voltage) and high speed is desired.
- FIG. 1 shows a schematic block diagram of a comparator 100 according to an embodiment of the present invention.
- the comparator 100 may include a first current source circuit 110, a pre-amplifier circuit 120, an amplifier circuit 130, a comparison circuit 140 and an output circuit 150.
- the first current source circuit 110 may be coupled to the pre-amplifier circuit 120, the second voltage terminal V2, and the first bias voltage terminal Vb1.
- the first current source circuit 110 may be configured to provide the first constant current to the pre-amplification circuit 120.
- the first constant current can be used to maintain the total current flowing through the pre-amplifier circuit 120 constant.
- the pre-amplifier circuit 120 may be coupled to the first current source circuit 110, the amplifier circuit 130, the first voltage terminal V1, the first input terminal INP, and the second input terminal INN.
- the pre-amplification circuit 120 may be configured to amplify the first input signal from the first input terminal INP into a first pre-amplification signal according to the first constant current and provide the first pre-amplification signal to the amplification circuit 130 via the first node N1, And amplify the second input signal from the second input terminal INN into a second pre-amplified signal and provide the second pre-amplified signal to the amplifier circuit 130 via the second node N2.
- the amplifying circuit 130 may include a current mirror 131 and a load circuit 132.
- the current mirror 131 may be coupled to the pre-amplifier circuit 120, the comparison circuit 140, the load circuit 132, and the first voltage terminal V1.
- the load circuit 132 may be coupled to the current mirror 131, the comparison circuit 140, and the second voltage terminal V2.
- the load circuit 132 may include differential diode-connected transistors. Since the differential diode-connected transistor has a high impedance value, the load circuit 132 including such a transistor has a high impedance value, so that the amplifier circuit 130 has a higher gain.
- the amplifying circuit 130 may be configured to generate a first image signal of the first pre-amplified signal and a second image signal of the second pre-amplified signal through the current mirror 131, generate a first amplified signal through the load circuit 132 based on the first image signal, and The first amplified signal is supplied to the comparison circuit 140 via the third node N3, and the second amplified signal is generated by the load circuit 132 based on the second image signal, and the second amplified signal is supplied to the comparison circuit 140 via the fourth node N4.
- the comparison circuit 140 may be coupled to the amplifying circuit 130, the output circuit 150, the first voltage terminal V1 and the second voltage terminal V2.
- the comparison circuit 140 may be configured to compare the first amplified signal and the second amplified signal and provide the comparison result to the output circuit 150 via the fifth node N5.
- the output circuit 150 may be coupled to the comparison circuit 140, the first voltage terminal V1, the second voltage terminal V2, and the output signal terminal OUT.
- the output circuit 150 may be configured to output the first voltage V1 or the second voltage V2 from the output signal terminal OUT based on the result of the comparison.
- the first voltage V1 is, for example, a high level
- the second voltage V2 is a low level.
- the comparator 100 amplifies the voltage difference between the first input signal and the second input signal by amplifying the first input signal and the second input signal. Since the amplifier circuit 130 uses a differential diode-connected transistor having a high impedance value as a load, the amplifier circuit 130 can obtain a high gain. In this way, even if the voltage difference between the first input signal and the second input signal is small, the voltage difference between the first amplified signal and the second amplified signal can be made sufficiently large, so that the first input signal can be accurately compared with The size of the second input signal. Therefore, the offset of the comparator 100 according to the embodiment of the present invention is small.
- the embodiments of the present invention implement a low-offset high-speed comparator.
- FIG. 2 shows a schematic block diagram of the amplifier circuit 230 in the comparator 100 according to an embodiment of the present invention.
- the amplifier circuit 230 may include a first current mirror 234, a second current mirror 235 and a load circuit 132.
- the first current mirror 234 and the second current mirror 235 constitute the current mirror 131 shown in FIG. 1.
- the first current mirror 234 is coupled to the first node N1, the first voltage terminal V1, the load circuit 132, and the third node N3.
- the first current mirror 234 is configured to generate a first image signal according to the first pre-amplified signal and provide the first image signal to the third node N3.
- the second current mirror 235 is coupled to the second node N2, the first voltage terminal V1, the load circuit 132, and the fourth node N4.
- the second current mirror 235 is configured to generate a second image signal according to the second pre-amplified signal and provide the second image signal to the fourth node N4.
- the amplifier circuit 230 may further include a second current source circuit 236.
- the second current source circuit 236 is coupled to the first current mirror 234, the second current mirror 235 and the load circuit 132, and is configured to provide the second constant current to the load circuit 132.
- the ratio of the first constant current to the second constant current is N:1, and N>2.
- the current flowing through the load circuit 132 shown in FIG. 2 can be (0.5N-1)/0.5N of the current flowing through the load circuit 132 shown in FIG. 1. For example, if N is 2.5, the current flowing through the load circuit 132 shown in FIG. 2 is 1/5 of the current flowing through the load circuit 132 shown in FIG.
- the gain of the amplifier circuit 230 shown in FIG. 2 will become 5 times the gain of the amplifier circuit 130 shown in FIG. 1. Since the gain of the amplifying circuit 230 becomes larger, even if the voltage difference between the first input signal and the second input signal is small, the voltage difference between the first amplified signal and the second amplified signal can be made large enough to be accurate To compare the magnitude of the first input signal and the second input signal. Therefore, the offset of the comparator 100 according to the present embodiment is smaller.
- FIG. 3 shows an exemplary circuit diagram of the comparator 100 according to an embodiment of the present invention.
- the amplifying circuit 130 may include first to sixth transistors (M1-M6).
- the first transistor M1 and the third transistor M3 constitute a first current mirror 234, the second transistor M2 and the fourth transistor M4 constitute a second current mirror 235, and the fifth transistor M5 and the sixth transistor M6 constitute a differential diode-connected transistor as Load circuit 132.
- the second electrode of the first transistor M1 is coupled to the control electrode of the first transistor M1 and the first node N1.
- the first electrode of the first transistor M1 is coupled to the first voltage terminal V1.
- the second electrode of the second transistor M2 is coupled to the control electrode of the second transistor M2 and the second node N2.
- the first electrode of the second transistor M2 is coupled to the first voltage terminal V1.
- the control electrode of the third transistor M3 is coupled to the control electrode of the first transistor M1.
- the first electrode of the third transistor M3 is coupled to the first voltage terminal V1.
- the second electrode of the third transistor M3 is coupled to the third node N3.
- the control electrode of the fourth transistor M4 is coupled to the control electrode of the second transistor M2.
- the first electrode of the fourth transistor M4 is coupled to the first voltage terminal V1.
- the second electrode of the fourth transistor M4 is coupled to the fourth node N4.
- the second electrode of the fifth transistor M5 is coupled to the control electrode of the fifth transistor M5 and the third node N3.
- the first electrode of the fifth transistor M5 is coupled to the second voltage terminal V2.
- the second electrode of the sixth transistor M6 is coupled to the control electrode of the sixth transistor M6 and the fourth node N4.
- the first electrode of the sixth transistor M6 is coupled to the second voltage terminal V2.
- the first current source circuit 110 may include an eleventh transistor M11.
- the control electrode of the eleventh transistor M11 is coupled to the first bias voltage terminal Vb1.
- the first electrode of the eleventh transistor M11 is coupled to the second voltage terminal V2.
- the second electrode of the eleventh transistor M11 is coupled to the pre-amplifier circuit 120.
- the pre-amplifier circuit 120 may include a twelfth transistor M12 and a thirteenth transistor M13.
- the control electrode of the twelfth transistor M12 is coupled to the first input terminal INP.
- the first electrode of the twelfth transistor M12 is coupled to the second electrode of the eleventh transistor M11.
- the second electrode of the twelfth transistor M12 is coupled to the first node N1.
- the control electrode of the thirteenth transistor M13 is coupled to the second input terminal INN.
- the first electrode of the thirteenth transistor M13 is coupled to the first electrode of the twelfth transistor M12.
- the second electrode of the thirteenth transistor M13 is coupled to the second node N2.
- the comparison circuit 140 may include a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17.
- the gate of the fourteenth transistor M14 is coupled to the fourth node N4.
- the first electrode of the fourteenth transistor M14 is coupled to the first voltage terminal V1.
- the second pole of the fourteenth transistor M14 is coupled to the second pole of the sixteenth transistor M16.
- the control electrode of the fifteenth transistor M15 is coupled to the third node N3.
- the first electrode of the fifteenth transistor M15 is coupled to the first voltage terminal V1.
- the second electrode of the fifteenth transistor M15 is coupled to the fifth node N5.
- the first electrode of the sixteenth transistor M16 is coupled to the second voltage terminal V2.
- the control electrode of the sixteenth transistor M16 is coupled to the second electrode of the sixteenth transistor M16.
- the control electrode of the seventeenth transistor M17 is coupled to the control electrode of the sixteenth transistor M16.
- the first electrode of the seventeenth transistor M17 is coupled to the second voltage terminal V2.
- the second electrode of the seventeenth transistor M17 is coupled to the fifth node N5.
- the output circuit 150 may include an eighteenth transistor M18 and a nineteenth transistor M19.
- the gate electrode of the eighteenth transistor M18 is coupled to the fifth node N5.
- the first electrode of the eighteenth transistor M18 is coupled to the first voltage terminal V1.
- the second electrode of the eighteenth transistor M18 is coupled to the output signal terminal OUT.
- the gate of the nineteenth transistor M19 is coupled to the fifth node N5.
- the first electrode of the nineteenth transistor M19 is coupled to the second voltage terminal V2.
- the second electrode of the nineteenth transistor M19 is coupled to the output signal terminal OUT.
- the first to fourth transistors (M1-M4), the fourteenth transistor M14, the fifteenth transistor M15, and the eighteenth transistor M18 are P-type transistors.
- the fifth transistor M5, the sixth transistor M6, the eleventh to thirteenth transistors (M11-M13), the sixteenth transistor M16, the seventeenth transistor M17, and the nineteenth transistor M19 are N-type transistors.
- the first bias voltage Vb1 is supplied to the gate of the eleventh transistor M11.
- the first constant current can be output from the second electrode of the eleventh transistor M11.
- the size of the first constant current can be adjusted by setting the width-to-length ratio of the eleventh transistor M11.
- the first input signal and the second input signal are voltage signals.
- the first input signal is provided to the control electrode of the twelfth transistor M12.
- the twelfth transistor M12 amplifies the first input signal into a first pre-amplified signal and provides the first pre-amplified signal to the second electrode of the first transistor M1 via the first node N1.
- the second input signal is supplied to the gate of the thirteenth transistor M13.
- the thirteenth transistor M13 amplifies the second input signal into a second pre-amplified signal and provides the second pre-amplified signal to the second electrode of the second transistor M2 via the second node N2.
- the first pre-amplified signal and the second pre-amplified signal are current signals. The sum of the first pre-amplified signal and the second pre-amplified signal is equal to the first constant current.
- the first current mirror 234 generates a first image signal at the second electrode of the third transistor M3 according to the first pre-amplified signal, and provides the first image signal to the third node N3.
- the second current mirror 235 generates a second mirror signal at the second electrode of the fourth transistor M4 according to the second pre-amplified signal, and provides the second mirror signal to the fourth node N4.
- the first image signal and the second image signal are current signals.
- the third node N3 is coupled to the control electrode of the fifteenth transistor M15, the current flowing to the control electrode of the fifteenth transistor M15 is small and can be ignored. Therefore, it can be considered that the first mirror signal is all supplied to the second electrode of the fifth transistor M5. Since the third node N3 is coupled to the fifth transistor M5 as a load, a voltage signal corresponding to the first mirror signal is generated at the third node N3 (which is referred to as "first amplified signal" in this context). This voltage signal is inversely proportional to the transconductance of the fifth transistor M5. Similarly, although the fourth node N4 is coupled to the control electrode of the fourteenth transistor M14, the current flowing to the control electrode of the fourteenth transistor M14 is small and can be ignored.
- the second mirror signal is all supplied to the second electrode of the sixth transistor M6. Since the fourth node N4 is coupled to the sixth transistor M6 as a load, a voltage signal corresponding to the second mirror signal is generated at the fourth node N4 (which is referred to as “second amplified signal” in this context). This voltage signal is inversely proportional to the transconductance of the sixth transistor M6.
- the first amplified signal turns on the fifteenth transistor M15.
- the current flowing through the fifteenth transistor M15 generates a voltage signal at the fifth node N5 as the first comparison signal.
- the second amplified signal turns on the fourteenth transistor M14.
- the current flowing through the fourteenth transistor M14 is mirrored by the current mirror formed by the sixteenth transistor M16 and the seventeenth transistor M17 to the second pole of the seventeenth transistor M17, thereby generating another voltage signal at the fifth node N5 as The second comparison signal.
- the first pre-amplified signal is greater than the second pre-amplified signal. Therefore, the first amplified signal is greater than the second amplified signal.
- the first comparison signal is greater than the second comparison signal, thereby generating a positive voltage at the fifth node N5.
- the positive voltage turns on the nineteenth transistor M19 and turns off the eighteenth transistor M18, thereby outputting the second voltage V2 at the output signal terminal OUT.
- the first pre-amplified signal is smaller than the second pre-amplified signal. Therefore, the first amplified signal is smaller than the second amplified signal.
- the first comparison signal is smaller than the second comparison signal, thereby generating a negative voltage at the fifth node N5. This negative voltage turns on the eighteenth transistor M18 and turns off the nineteenth transistor M19, thereby outputting the first voltage V1 at the output signal terminal OUT.
- FIG. 4 shows an exemplary circuit diagram of a comparator according to another embodiment of the present invention.
- the amplifying circuit 130 further includes a seventh transistor M7 and an eighth transistor M8.
- the seventh transistor M7 and the eighth transistor M8 constitute another differential diode-connected transistor, and are coupled to the differential diode-connected transistor constituted by the fifth transistor M5 and the sixth transistor M6, and together constitute the load circuit 132.
- the seventh transistor M7 and the eighth transistor M8 are N-type transistors.
- the control electrode of the seventh transistor M7 is coupled to the control electrode of the fifth transistor M5.
- the first electrode of the seventh transistor M7 is coupled to the second voltage terminal V2.
- the second electrode of the seventh transistor M7 is coupled to the second electrode of the sixth transistor M6.
- the control electrode of the eighth transistor M8 is coupled to the control electrode of the sixth transistor M6.
- the first electrode of the eighth transistor M8 is coupled to the second voltage terminal V2.
- the second electrode of the eighth transistor M8 is coupled to the second electrode of the fifth transistor M5.
- the impedance value of the load of the amplifier circuit 130 shown in FIG. 4 is larger, and therefore, the amplifier circuit 130 has a larger gain. In this way, even if the voltage difference between the first input signal and the second input signal is small, the voltage difference between the first amplified signal and the second amplified signal can be made sufficiently large, so that the first input signal can be accurately compared with The size of the second input signal. Therefore, compared with FIG. 3, the offset of the comparator 100 shown in FIG. 4 is smaller.
- FIG. 5 shows an exemplary circuit diagram of a comparator according to still another embodiment of the present invention.
- the amplifying circuit 230 may further include a ninth transistor M9 and a tenth transistor M10.
- the ninth transistor M9 and the tenth transistor M10 constitute a second current source circuit 236.
- the ninth transistor M9 and the tenth transistor M10 are N-type transistors.
- the control electrode of the ninth transistor M9 is coupled to the second bias voltage terminal Vb2.
- the first electrode of the ninth transistor M9 is coupled to the second voltage terminal V2.
- the second electrode of the ninth transistor M9 is coupled to the third node N3.
- the control electrode of the tenth transistor M10 is coupled to the second bias voltage terminal Vb2.
- the first electrode of the tenth transistor M10 is coupled to the second voltage terminal V2.
- the second electrode of the tenth transistor M10 is coupled to the fourth node N4.
- the first bias voltage terminal Vb1 provides the first bias voltage Vb1.
- the second bias voltage terminal Vb2 provides the second bias voltage Vb2.
- the ratio of the first constant current to the second constant current can be made N:1.
- the second bias voltage Vb2 may be equal to the first bias voltage Vb1.
- the current flowing through the load circuit 132 can be reduced, and therefore, the transconductance of the transistor in the load circuit is reduced. Therefore, the impedance of the load circuit increases, thereby increasing the gain of the amplifier circuit. Therefore, the offset of the comparator shown in FIG. 5 is reduced.
- FIG. 6 shows a schematic block diagram of an analog-to-digital converter 600 according to an embodiment of the present invention.
- the analog-to-digital converter 600 may include one or more comparators (100, 200) as shown in any one of FIGS. 1-5.
- the analog-to-digital converter may include a comparator. The comparator receives the analog signal via the first input and the reference signal via the second input. If the amplitude of the analog signal is greater than or equal to the amplitude of the reference signal, the comparator outputs a logic "1" as the digital signal corresponding to the analog signal. If the amplitude of the analog signal is less than the amplitude of the reference signal, the comparator outputs a logic "0".
- the analog-to-digital converter may include multiple comparators to convert the analog signal into a multi-bit digital signal. The accuracy of the analog-to-digital converter 600 may depend on the number of comparators included in the analog-to-digital converter 600.
- the analog-to-digital converter 600 can be applied to a protection circuit of a display device, such as an overvoltage protection circuit or an overcurrent protection circuit.
- the overvoltage protection circuit may include an analog-to-digital converter 600 and a detection circuit. Through the analog-to-digital converter 600, the voltage input to the display device is converted into a digital signal and provided to the detection circuit. The detection circuit detects whether the digital signal exceeds the threshold, and activates the overvoltage protection of the display device when the digital signal exceeds the threshold.
- the display device can be applied to any product with a display function, for example, electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, wearable device, or navigator.
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Abstract
Description
Claims (15)
- 一种比较器,包括:第一电流源电路、预放大电路、放大电路、比较电路和输出电路;其中,所述第一电流源电路耦接所述预放大电路,并被配置为向所述预放大电路提供第一恒定电流;所述预放大电路经由第一节点和第二节点耦接所述放大电路,并被配置为根据所述第一恒定电流,将来自第一输入端的第一输入信号放大为第一预放大信号,将来自第二输入端的第二输入信号放大为第二预放大信号,并分别经由所述第一节点和所述第二节点向所述放大电路提供所述第一预放大信号和所述第二预放大信号;所述放大电路经由第三节点和第四节点耦接所述比较电路,其包括电流镜和负载电路,并被配置为通过所述电流镜产生所述第一预放大信号的第一镜像信号和所述第二预放大信号的第二镜像信号,分别基于所述第一镜像信号和所述第二镜像信号,通过所述负载电路产生第一放大信号和第二放大信号,并分别经由所述第三节点和所述第四节点向所述比较电路提供所述第一放大信号和所述第二放大信号,其中,所述负载电路包括差分的二极管连接的晶体管;所述比较电路经由第五节点耦接所述输出电路,并被配置为比较所述第一放大信号和所述第二放大信号,并经由所述第五节点向所述输出电路提供所述比较的结果;所述输出电路被配置为基于所述比较的所述结果,输出第一电压或第二电压。
- 根据权利要求1所述的比较器,其中,所述电流镜包括第一电流镜和第二电流镜;所述第一电流镜与所述第一节点、第一电压端、所述负载电路和所述第三节点耦接,并被配置为根据所述第一预放大信号产生所述第一镜像信号,以及向所述第三节点提供所述第一镜像信号;所述第二电流镜与所述第二节点、所述第一电压端、所述负载电路和 所述第四节点耦接,并被配置为根据所述第二预放大信号产生所述第二镜像信号,以及向所述第四节点提供所述第二镜像信号。
- 根据权利要求2所述的比较器,其中,所述第一电流镜包括第一晶体管和第三晶体管,所述第二电流镜包括第二晶体管和第四晶体管,其中,所述第一晶体管的第二极耦接所述第一晶体管的控制极和所述第一节点,所述第一晶体管的第一极耦接所述第一电压端;所述第二晶体管的第二极耦接所述第二晶体管的控制极和所述第二节点,所述第二晶体管的第一极耦接所述第一电压端;所述第三晶体管的控制极耦接所述第一晶体管的控制极,所述第三晶体管的第一极耦接所述第一电压端,所述第三晶体管的第二极耦接所述第三节点;所述第四晶体管的控制极耦接所述第二晶体管的控制极,所述第四晶体管的第一极耦接所述第一电压端,所述第四晶体管的第二极耦接所述第四节点。
- 根据权利要求1-3中任一项所述的比较器,其中,所述差分的二极管连接的晶体管包括第五晶体管和第六晶体管,其中,所述第五晶体管的第二极耦接所述第五晶体管的控制极和所述第三节点,所述第五晶体管的第一极耦接第二电压端;所述第六晶体管的第二极耦接所述第六晶体管的控制极和所述第四节点,所述第六晶体管的第一极耦接所述第二电压端。
- 根据权利要求4所述的比较器,其中,所述差分的二极管连接的晶体管还包括第七晶体管和第八晶体管,其中,所述第七晶体管的控制极耦接所述第五晶体管的控制极,所述第七晶体管的第一极耦接所述第二电压端,所述第七晶体管的第二极耦接所述第六晶体管的第二极;所述第八晶体管的控制极耦接所述第六晶体管的控制极,所述第八晶体管的第一极耦接所述第二电压端,所述第八晶体管的第二极耦接所述第五晶体管的第二极。
- 根据权利要求1-5中任一项所述的比较器,其中,所述放大电路还包括第二电流源电路,其中,所述第二电流源电路与所述电流镜和所述负载电路耦接,并被配置为向所述负载电路提供第二恒定电流。
- 根据权利要求6所述的比较器,其中,所述第二电流源电路包括第九晶体管和第十晶体管,其中,所述第九晶体管的控制极耦接第二偏置电压端,所述第九晶体管的第一极耦接第二电压端,所述第九晶体管的第二极耦接所述第三节点;所述第十晶体管的控制极耦接所述第二偏置电压端,所述第十晶体管的第一极耦接所述第二电压端,所述第十晶体管的第二极耦接所述第四节点。
- 根据权利要求1-7中任一项所述的比较器,其中,所述第一电流源电路包括第十一晶体管,其中,所述第十一晶体管的控制极耦接第一偏置电压端,所述第十一晶体管的第一极耦接第二电压端,所述第十一晶体管的第二极耦接所述预放大电路。
- 根据权利要求1-8中任一项所述的比较器,其中,所述预放大电路包括第十二晶体管和第十三晶体管,其中,所述第十二晶体管的控制极耦接所述第一输入端,所述第十二晶体管的第一极耦接所述第一电流源电路,所述第十二晶体管的第二极耦接所述第一节点;所述第十三晶体管的控制极耦接所述第二输入端,所述第十三晶体管的第一极耦接所述第十二晶体管的第一极,所述第十三晶体管的第二极耦接所述第二节点。
- 根据权利要求1-9中任一项所述的比较器,其中,所述比较电路包括第十四晶体管、第十五晶体管、第十六晶体管和第十七晶体管,其中,所述第十四晶体管的控制极耦接所述第四节点,所述第十四晶体管的第一极耦接第一电压端,所述第十四晶体管的第二极耦接所述第十六晶体管的第二极;所述第十五晶体管的控制极耦接所述第三节点,所述第十五晶体管的第一极耦接所述第一电压端,所述第十五晶体管的第二极耦接所述第五节点;所述第十六晶体管的第一极耦接第二电压端,所述第十六晶体管的控制极耦接所述第十六晶体管的第二极;所述第十七晶体管的控制极耦接所述第十六晶体管的控制极,所述第十七晶体管的第一极耦接所述第二电压端,所述第十七晶体管的第二极耦接所述第五节点。
- 根据权利要求1至10中任一项所述的比较器,其中,所述输出电路包括第十八晶体管和第十九晶体管,其中,所述第十八晶体管的控制极耦接所述第五节点,所述第十八晶体管的第一极耦接第一电压端,所述第十八晶体管的第二极耦接输出信号端;所述第十九晶体管的控制极耦接所述第五节点,所述第十九晶体管的第一极耦接第二电压端,所述第十九晶体管的第二极耦接所述输出信号端。
- 根据权利要求6所述的比较器,其中,所述第一恒定电流和所述第二恒定电流的比值大于2。
- 一种比较器,包括第一至第八晶体管和第十一至第十九晶体管;其中,第一晶体管的第二极耦接所述第一晶体管的控制极和第一节点,第一晶体管的第一极耦接第一电压端;第二晶体管的第二极耦接所述第二晶体管的控制极和第二节点,第二晶体管的第一极耦接所述第一电压端;第三晶体管的控制极耦接所述第一晶体管的控制极,所述第三晶体管的第一极耦接所述第一电压端,所述第三晶体管的第二极耦接第三节点;第四晶体管的控制极耦接所述第二晶体管的控制极,所述第四晶体管的第一极耦接所述第一电压端,所述第四晶体管的第二极耦接第四节点;第五晶体管的第二极耦接所述第五晶体管的控制极和所述第三节点,所述第五晶体管的第一极耦接第二电压端;第六晶体管的第二极耦接所述第六晶体管的控制极和所述第四节点,所述第六晶体管的第一极耦接所述第二电压端;第七晶体管的控制极耦接所述第五晶体管的控制极,所述第七晶体管的第一极耦接所述第二电压端,所述第七晶体管的第二极耦接所述第六晶体管的第二极;第八晶体管的控制极耦接所述第六晶体管的控制极,所述第八晶体管的第一极耦接所述第二电压端,所述第八晶体管的第二极耦接所述第五晶体管的第二极;第十一晶体管的控制极耦接第一偏置电压端,所述第十一晶体管的第一极耦接所述第二电压端,所述第十一晶体管的第二极耦接第十二晶体管的第一极和第十三晶体管的第一极;所述第十二晶体管的控制极耦接所述第一输入端,所述第十二晶体管的第二极耦接所述第一节点;所述第十三晶体管的控制极耦接所述第二输入端,所述第十三晶体管的第二极耦接所述第二节点;第十四晶体管的控制极耦接所述第四节点,所述第十四晶体管的第一极耦接所述第一电压端,所述第十四晶体管的第二极耦接第十六晶体管的第二极;第十五晶体管的控制极耦接所述第三节点,所述第十五晶体管的第一极耦接所述第一电压端,所述第十五晶体管的第二极耦接第五节点;所述第十六晶体管的第一极耦接所述第二电压端,所述第十六晶体管的控制极耦接所述第十六晶体管的第二极;所述第十七晶体管的控制极耦接所述第十六晶体管的控制极,所述第十七晶体管的第一极耦接所述第二电压端,所述第十七晶体管的第二极耦接所述第五节点;第十八晶体管的控制极耦接所述第五节点,所述第十八晶体管的第一极耦接所述第一电压端,所述第十八晶体管的第二极耦接输出信号端;第十九晶体管的控制极耦接所述第五节点,所述第十九晶体管的第一 极耦接所述第二电压端,所述第十九晶体管的第二极耦接所述输出信号端。
- 根据权利要求13所述的比较器,还包括第九晶体管和第十晶体管,其中,第九晶体管的控制极耦接第二偏置电压端,所述第九晶体管的第一极耦接所述第二电压端,所述第九晶体管的第二极耦接所述第三节点;第十晶体管的控制极耦接所述第二偏置电压端,所述第十晶体管的第一极耦接所述第二电压端,所述第十晶体管的第二极耦接所述第四节点。
- 一种模数转换器,包括根据权利要求1-14中任一项所述的比较器。
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CN103762962A (zh) * | 2014-01-03 | 2014-04-30 | 东南大学 | 一种低失调的预放大锁存比较器 |
CN104579202A (zh) * | 2014-12-30 | 2015-04-29 | 上海贝岭股份有限公司 | 一种三角波比较器电路 |
CN106067822A (zh) * | 2016-06-06 | 2016-11-02 | 东南大学 | 一种高速高精度的cmos锁存比较器 |
CN109728801A (zh) * | 2019-01-02 | 2019-05-07 | 京东方科技集团股份有限公司 | 比较器和模数转换器 |
Cited By (2)
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CN115441717A (zh) * | 2022-09-23 | 2022-12-06 | 圣邦微电子(北京)股份有限公司 | 适用于电压模环路的自适应加速电路 |
CN115441717B (zh) * | 2022-09-23 | 2024-05-03 | 圣邦微电子(北京)股份有限公司 | 适用于电压模环路的自适应加速电路 |
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CN109728801A (zh) | 2019-05-07 |
US20200266811A1 (en) | 2020-08-20 |
US10924099B2 (en) | 2021-02-16 |
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