WO2020133950A1 - 阵列基板、显示面板和显示装置 - Google Patents

阵列基板、显示面板和显示装置 Download PDF

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Publication number
WO2020133950A1
WO2020133950A1 PCT/CN2019/091283 CN2019091283W WO2020133950A1 WO 2020133950 A1 WO2020133950 A1 WO 2020133950A1 CN 2019091283 W CN2019091283 W CN 2019091283W WO 2020133950 A1 WO2020133950 A1 WO 2020133950A1
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Prior art keywords
electrode
light
pixel
sub
pixels
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PCT/CN2019/091283
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English (en)
French (fr)
Inventor
孙婕
楼均辉
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云谷（固安）科技有限公司
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Publication of WO2020133950A1 publication Critical patent/WO2020133950A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/822—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/828—Transparent cathodes, e.g. comprising thin metal layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a display panel, and a display device.
  • the present application provides an array substrate, a display panel, and a display device.
  • an array substrate including: a substrate, a first electrode layer, a light emitting layer, and a second electrode layer.
  • the first electrode layer is formed on the substrate.
  • the light emitting layer is formed on the first electrode layer, and includes: a transparent first light emitting region, the first light emitting region includes a plurality of first light emitting structures, and the first electrode layer includes a corresponding first A plurality of first electrodes of the light emitting area, the plurality of first light emitting structures are provided on the plurality of first electrodes, wherein, for each of the first electrodes, at least one of the first electrodes is provided on the first electrode
  • the first light emitting structure and the display color of the first light emitting structure provided on the first electrode are the same; and the non-transparent second light emitting area, the second light emitting area includes a plurality of second light emitting structures, wherein, The distribution density of the first light emitting structure in the first light emitting area is smaller than the distribution density of the second light
  • a display panel comprising: the array substrate as described above; and an encapsulation layer, the encapsulation layer is provided on a side where the second electrode layer of the array substrate is located, The area of the display panel corresponding to the first light-emitting area is configured to provide a photosensitive device.
  • a display device including: a device body having a device area; and a display panel as described above, the display panel being provided in a device of the device body On the side where the area is located; wherein, the transparent display area of the display panel covers the device area and the device area includes a photosensitive device that emits or collects light through the transparent display area of the display panel.
  • Fig. 1 is a schematic structural diagram of an array substrate according to an exemplary embodiment of the present application.
  • Fig. 2 is a cross-sectional view taken along line A-A of Fig. 1.
  • Fig. 3-5 is a schematic structural diagram of an array substrate according to an exemplary embodiment of the present application.
  • 6-7 are one of the structural schematic diagrams of a first light-emitting region on an array substrate according to an exemplary embodiment of the present application.
  • FIGS. 8-11 are the second schematic structural diagrams of a first light-emitting region on an array substrate according to an exemplary embodiment of the present application.
  • Fig. 12 is a partial schematic diagram of an array substrate according to an exemplary embodiment of the present application.
  • FIG. 13 is a third schematic structural diagram of a first light-emitting region on an array substrate according to an exemplary embodiment of the present application.
  • FIGS. 14-20 are schematic structural diagrams of a first electrode on an array substrate according to an exemplary embodiment of the present application.
  • Fig. 21 is a schematic cross-sectional view of another array substrate according to an exemplary embodiment of the present application.
  • 22-26 are the second structural diagrams of an array substrate according to an exemplary embodiment of the present application.
  • Fig. 27 is a schematic structural diagram of an OLED sub-pixel according to an exemplary embodiment of the present application.
  • FIG. 28 is an arrangement diagram of OLED sub-pixels of the same color in the first light-emitting area according to an exemplary embodiment of the present application.
  • FIG. 29 is a schematic circuit diagram of a passive driving mode of two rows and multiple columns of OLED sub-pixels of the same color in the first light-emitting area.
  • FIG. 30 is a circuit schematic diagram of another passive driving method of two rows and multiple columns of OLED sub-pixels of the same color in the first light-emitting area.
  • FIG. 31 is a schematic circuit diagram of an active driving mode of two rows and multiple columns of OLED sub-pixels of the same color in the first light-emitting area.
  • Figure 32 is a GIP circuit structure and timing diagram.
  • FIG. 33 is a schematic circuit diagram of another active driving method of two rows and multiple columns of OLED sub-pixels of the same color in the first light-emitting area.
  • 34 is a circuit diagram and a timing diagram of a pixel driving circuit having a function of compensating for the threshold voltage of a driving transistor.
  • Fig. 35 is another OLED sub-pixel arrangement diagram of the first light-emitting area according to an exemplary embodiment of the present application.
  • FIG. 36 is a circuit schematic diagram of a passive driving method of two columns and multiple rows of OLED sub-pixels of the same color in the first light-emitting area.
  • FIG. 37 is a circuit schematic diagram of another passive driving method of two columns and multiple rows of OLED sub-pixels of the same color in the first light-emitting area.
  • FIG. 38 is a schematic circuit diagram of an active driving method of two columns and multiple rows of OLED sub-pixels of the same color in the first light-emitting area.
  • FIG. 39 is a circuit schematic diagram of another active driving mode of two columns and multiple rows of OLED same-color sub-pixels in the first light-emitting area.
  • Fig. 40 is another OLED sub-pixel arrangement diagram of the first light-emitting area according to an exemplary embodiment of the present application.
  • FIG. 41 is a schematic circuit diagram of a passive driving method of OLED sub-pixels with different colors and two rows and multiple columns in the first light-emitting area.
  • FIG. 42 is a circuit schematic diagram of another passive driving method of OLED sub-pixels with different colors and two rows and multiple columns in the first light-emitting area.
  • FIG. 43 is a circuit schematic diagram of another passive driving method of OLED sub-pixels with different colors and two rows and multiple columns in the first light-emitting area.
  • FIG. 44 is a schematic circuit diagram of an active driving method of OLED sub-pixels with different colors in two rows and multiple columns in the first light-emitting area.
  • FIG. 45 is a schematic circuit diagram of a passive driving method of two columns and multiple rows of OLED sub-pixels with different colors in the first light-emitting area.
  • FIG. 46 is a schematic circuit diagram of an active driving mode of two columns and multiple rows of OLED sub-pixels of different colors in the first light-emitting area.
  • Fig. 47 is a schematic cross-sectional view of a display panel according to an exemplary embodiment of the present application.
  • Fig. 48 is a schematic cross-sectional view of a display device according to an exemplary embodiment of the present application.
  • Fig. 49 is a schematic structural diagram of a display device according to an exemplary embodiment of the present application.
  • the display of these electronic devices cannot achieve a good full-screen display, that is, the screen ratio of the display panel configured by the electronic device is not close to 100%, so that it cannot be displayed in various areas of the entire screen, such as in the camera area The screen cannot be displayed.
  • the screen ratio of the display panel configured by the electronic device is not close to 100%, so that it cannot be displayed in various areas of the entire screen, such as in the camera area The screen cannot be displayed.
  • FIG. 1 is a schematic structural diagram of an array substrate 100 according to an exemplary embodiment of the present application
  • FIG. 2 is a cross-sectional view taken along line AA of FIG. 1
  • FIG. 3 is an exemplary embodiment of the present application according to an exemplary embodiment.
  • the embodiment shows a schematic structural diagram of an array substrate.
  • the array substrate 100 may include a substrate 1, a first electrode layer 2, a light emitting layer 3, and a second electrode layer 4.
  • the substrate 1 may include a layer structure such as a substrate, an inorganic layer and an organic layer.
  • the substrate may include a flexible substrate or a rigid substrate.
  • the flexible substrate may be made of a flexible material, and the flexible material may be polyimide (Polyimide, PI for short) polymer, polycarbonate (Polycarbonate, PC for short) resin, also known as PC plastic, polyterephthalic acid (Polyethylene terephthalate, PET for short) plastic, etc.; rigid substrate can be made of plexiglass material.
  • the first electrode layer 2 is formed on the substrate 1, the light emitting layer 3 is formed on the first electrode layer 2, and the second electrode layer 4 is formed on the light emitting layer 3.
  • the light-emitting layer 3 may include a transparent first light-emitting region 31 and a non-transparent second light-emitting region 32, and the portion of the first electrode layer 2 corresponding to the first light-emitting region 31 includes a plurality of first electrodes 21 , 22 and 23.
  • the first light emitting region 31 may include a plurality of first light emitting structures 311 disposed on a plurality of first electrodes.
  • the second light emitting area 32 may include a plurality of second light emitting structures 321.
  • a plurality of first light emitting structures 311 may be provided on each first electrode, and the colors of the first light emitting structures 311 on the same first electrode are the same.
  • the distribution density of the plurality of first light emitting structures 311 in the first light emitting region 31 is smaller than the distribution density of the plurality of second light emitting structures 321 in the second light emitting region 32.
  • the distribution density of the first light-emitting structure in the transparent first light-emitting region is smaller than the distribution density of the second light-emitting structure in the non-transparent second light-emitting region, that is, in a unit area, the number of the first light-emitting structure Less than the number of second light-emitting structures, the number of gaps between the first light-emitting structures will be reduced, which can reduce the probability of light diffracting when passing through the first light-emitting area, and enhance the detection accuracy of the photosensitive device below the first light-emitting area, And achieve full-screen display.
  • All the first light-emitting structure 311 and the second light-emitting structure 321 are formed in the same process to reduce the number of masks and reduce production costs.
  • the first light emitting structure 311 and the second light emitting structure 321 have the same size, that is, the opening pattern used to form the first light emitting structure on the mask is the same size as the opening pattern used to form the second light emitting structure, so that the deformation of the mask can be reduced.
  • the plurality of first electrodes 21, 22, and 23 of the first electrode layer 2 are arranged along the first direction (X direction shown in FIG. 3), and each first electrode is along the second direction (shown in FIG. 3).
  • the Y direction shown) extends, and the second direction is perpendicular to the first direction.
  • the first direction may be a row direction in which all the light emitting structures on the array substrate 100 are arranged as shown in FIG. 3, and the second direction may be a column direction in which all the light emitting structures on the array substrate 100 are arranged as shown in FIG.
  • the first direction may be the column direction in which all the light emitting structures on the array substrate 100 are arranged as shown in FIG. 4
  • the second direction may be all the light in the array substrate 100 as shown in FIG.
  • the row direction of the structure arrangement may be a row direction in which all the light emitting structures on the array substrate 100 are arranged as shown in FIG. 3
  • the second direction may be a column direction in which all the light emitting structures on the array substrate 100 are arranged as shown in FIG.
  • the first direction may be the column direction in which all the light emitting structures on the array substrate 100 are arranged as shown in FIG. 4
  • the second direction may be all the light in the array substrate 100 as shown in FIG.
  • the row direction of the structure arrangement may be a row direction in which all the
  • the first electrode layer 2 may include a plurality of first electrodes 21, 22, and 23 corresponding to the first light emitting region 31, and the first electrodes 21, 22, and 23 respectively correspond to Two first light emitting structure 311.
  • the first light emitting structures 311 corresponding to the first electrodes 21 are all red patches
  • the first light emitting structures 311 corresponding to the first electrodes 22 are all green patches
  • the first light emitting structures 311 corresponding to the first electrodes 23 are all Blue color block.
  • each first electrode may further include three or more first light emitting structures 311, and the number of first light emitting structures 311 included in different first electrodes may be the same or different, This application is not restricted.
  • a plurality of first light emitting structures 311 and second light emitting structures 321 are vapor-deposited with one mask, and in this application, a plurality of first light emitting structures 311 may be formed on the same first electrode, corresponding to the mask A plurality of holes may be formed in the area corresponding to the first light-emitting region 31, so as to increase the strength of the mask, reduce the deformation of the mask, and reduce the probability of color mixing between adjacent first light-emitting structures 311.
  • the first light-emitting area 31 is a transparent area
  • the second light-emitting area 32 is a non-transparent area
  • the photosensitive device included in the electronic device equipped with the array substrate 100 may be provided corresponding to the first light emitting region 31 and the photosensitive device is provided directly below the light emitting layer 3.
  • the photosensitive device is, for example, a device that emits or collects light, such as a camera, a light sensor, or a light emitter. At this time, external light can be collected by the photosensitive device after passing through the first light-emitting area 31; similarly, internal light can be emitted through the first light-emitting area 31.
  • the area corresponding to the first light-emitting area 31 can be used to display an image, and the image shown in the corresponding area of the first light-emitting area 31 and the image showing the corresponding area of the second light-emitting area 32 It can be matched to ensure the integrity of the image display and improve the display effect.
  • the area corresponding to the first light-emitting area 31 may also be a static display, which is not limited in this application.
  • the distance between two adjacent first light emitting structures 311 may be greater than that of the adjacent two
  • the distance between the second light-emitting structures 321 decreases the probability of diffraction when light passes through the first light-emitting region 31 by increasing the distance.
  • the area of the first light emitting structure 311 may be larger than the area of the second light emitting structure 321.
  • the number of first light emitting structures 311 is smaller than the number of second light emitting structures 321 per unit area, so that the number of gaps between the first light emitting structures is reduced compared to the second light emitting structures, which can be more effectively reduced The probability that light will diffract when it passes through the first light-emitting area 31.
  • the first light-emitting area 31 may be surrounded by the second light-emitting area 32.
  • the first light-emitting area 31 may be completely surrounded by the second light-emitting area 32; or, one edge of the first light-emitting area 31 may be in contact with the opposite side edge of the second light-emitting area 32.
  • the first light-emitting area 31 may be shaped like a drop as shown in FIG. 1; or, in other embodiments, the first light-emitting area 31 may also be round, rectangular, or elliptical, etc., which is not limited in this application.
  • the second electrode layer 4 includes a second electrode provided corresponding to the first light emitting region 31, and the second electrode is a surface electrode.
  • the second electrode has a single-layer structure or a stacked structure.
  • the second electrode is a single-layer metal layer, a single-layer metal mixture layer, or a single-layer transparent metal oxide layer.
  • the second electrode has a stacked structure, the second electrode is a stacked layer of a transparent metal oxide layer and a metal layer, or the second electrode is a stacked layer of a transparent metal oxide layer and a metal mixture layer.
  • the second electrode material is doped with metal, and the thickness of the second electrode is greater than or equal to 100 angstroms, and less than or equal to 500 angstroms, the second electrode is an integral continuous surface electrode, and the The transparency of the second electrode is greater than 40%.
  • the second electrode when the material of the second electrode is doped with metal, and the thickness of the second electrode is greater than or equal to 100 angstroms, and less than or equal to 200 angstroms, the second electrode is an overall continuous surface electrode, and the The transparency of the second electrode is greater than 40%.
  • the second electrode material is doped with metal, and the thickness of the second electrode is greater than or equal to 50 angstroms, and less than or equal to 200 angstroms, the second electrode is an overall continuous surface electrode, and the The transparency of the second electrode is greater than 50%.
  • the second electrode material is doped with metal, and the thickness of the second electrode is greater than or equal to 50 angstroms, and less than or equal to 200 angstroms, the second electrode is an overall continuous surface electrode, and the The transparency of the second electrode is greater than 60%.
  • the single-layer metal layer material is Al, Ag
  • the single-layer metal mixture layer material is MgAg or an Al-doped metal mixed material
  • the transparent metal is oxidized
  • the object is ITO or IZO.
  • the X direction is the first direction and the Y direction is the second direction (ie, the extending direction of the first electrode) as an example.
  • Each first electrode may correspond to two columns of first light emitting structures 311 arranged along the second direction. Based on this, it is possible to reduce the number of first electrodes and reduce the processing difficulty while reducing the mask deformation amount while the distribution density of the plurality of first light-emitting structures of the first light-emitting region 31 is unchanged.
  • two adjacent first light emitting structures 311 on the same first electrode in the X direction shown in FIG. 6 are aligned; or, as shown in FIG. 7, in the direction shown in X, the same Two adjacent first light emitting structures 311 on one electrode are arranged in a misaligned manner.
  • the two light emitting structures 311 adjacent to each other on the same first electrode are aligned to improve the uniformity of the arrangement of the first light emitting structures 311 and improve the display effect.
  • the spacing between the central axes of two adjacent first light emitting structures 311 on the same first electrode in the Y direction is The size of the first light emitting structure 311 in this Y direction is 0.5-2 times.
  • the first light emitting structure 311A and the first light emitting structure 311B are misaligned in the direction indicated by X, and the distance D3 between the central axis of the first light emitting structure 311A and the central axis of the first light emitting structure 311B is equal to the first light emitting structure 311B The width of D4.
  • the first electrode 23 may include a connection portion 233 and a plurality of first sub-electrodes 231 and 232.
  • the plurality of first sub-electrodes are arranged in a misalignment in the first direction (the Y direction shown in FIGS. 8 and 9), each first sub-electrode 231 includes a plurality of electrode blocks 2311, and the first sub-electrode 232 includes a plurality of Electrode blocks 2321, and the connecting portion 233 electrically connects two adjacent electrode blocks in the first direction to obtain a wave extending in the second direction (X direction shown in FIGS. 8 and 9) Shaped first electrode (as shown in Figure 9). Specifically, as shown in FIG.
  • the first electrode 23 may include first sub-electrodes 231 and 232, and the first sub-electrode 231 includes a plurality of electrode blocks 2311, second sub
  • the electrode 232 includes a plurality of electrode blocks 2321; the first electrode 23 may further include a connecting portion 233 that connects two adjacent electrode blocks in the first direction, so that the edge shown in FIG. 9 can be obtained
  • the wavy first electrode 23 extends in the X direction.
  • the first light-emitting region 31 may be arranged in a structure of three rows and two columns as shown in FIG.
  • the first light emitting structures 311 corresponding to all the first electrodes may have the same color.
  • the first light-emitting structures 311 corresponding to all the first electrodes in the same column direction ie, from top to bottom or from bottom to top in FIG. 12
  • the first direction is the Y direction, that is, the column direction
  • the second direction is the X direction, that is, the row direction as an example for description.
  • the first direction may be the Y direction, that is, the column direction
  • the second direction is the X direction, which is not limited in this application.
  • the first light emitting structures 311 corresponding to the two adjacent first electrodes may be aligned in the first direction (Y direction).
  • the electrode block 2311 of the first sub-electrode 231 of the first electrode 23 in FIG. 8 and the first light-emitting structure of the electrode block 2211 of the first sub-electrode 221 of the first electrode 22 are aligned in the Y direction
  • the first The electrode blocks 2321 of the first sub-electrode 232 of one electrode 23 and the first light-emitting structures of the electrode blocks 2221 of the first sub-electrode 222 of the first electrode 22 are aligned in the Y direction.
  • the first light emitting structures 311 corresponding to the two adjacent first electrodes can also be arranged in a misaligned manner.
  • the first light-emitting structures of the electrode blocks 2321 of the first sub-electrode 232 of the first electrode 23 and the electrode blocks 2221 of the first sub-electrode 222 of the first electrode 22 are misaligned in the Y direction.
  • the first electrode may be wavy extending in the Y direction.
  • the first light-emitting region 31 can allow external light to pass through, and there is a gap between the adjacent first electrodes, diffraction is likely to occur when the light penetrates. Therefore, it is also proposed in the present application that, as shown in FIG. 14, in the extending direction of each first electrode, both sides of the first electrode in the X direction are wavy, and the peaks of the two sides Relative setting, valley relative setting. Therefore, the gap between the first electrodes of the two adjacent columns exhibits an intermittent change in the extending direction (the direction indicated by Y in FIG. 14).
  • the gap between two adjacent columns of first electrodes may be continuously changed in the extending direction, that is, a column of first electrodes includes one first electrode to cause the continuous change of the gap, as shown in FIG. 16.
  • Whether the width of the first electrode 21 changes continuously or intermittently may be a periodic change, and the length of one change period may correspond to the width of one pixel.
  • the first light-emitting area 31 is provided with a plurality of rows of the first electrodes, so that the width of the first electrode continuously changes or intermittently changes in the extending direction, so that there is a continuously varying spacing between two adjacent first electrodes Or intermittently changing spacing. Therefore, between different width positions of the first electrode and different distances between adjacent first electrodes, the positions of the generated diffraction fringes are different, so that the derivative effects at different positions cancel each other, which can effectively reduce the diffraction effect, which is beneficial to guarantee The photographing effect of the camera located below the first light-emitting area 31 is improved.
  • the first electrode is in the form of multiple rows and multiple columns as an example for description.
  • the Y direction is the second direction in which the first electrodes extend
  • the X direction is the first direction in which the first electrodes are arranged.
  • the shape of the two sides of each first electrode in the X direction may include one or more peaks and one or more valleys. Taking the first electrode 21 as an example, the position shown by T in FIG. 14 is a peak, and the position shown by B in FIG. 14 is a valley.
  • the width D5 between the peaks of the two sides is between 30um and (AX)um; the width D6 between the valleys of the two sides is greater than X and less than the width D5 of the peaks, where A is adjacent
  • the distance between the central axes of the two first electrodes in the Y direction, X is the minimum process size, and the A is greater than or equal to (30+X)um.
  • X is 4 microns, and in other embodiments it may be smaller.
  • the spacing between the first rows of adjacent two rows of electrodes also changes accordingly.
  • the peaks of two adjacent columns of first electrodes have a minimum distance W1 between opposite positions, and the valleys of two columns of first electrodes have a maximum distance W2 of opposite positions.
  • the minimum pitch W1 is (A-D5)
  • the maximum pitch W2 is (A-D6).
  • the shape of the first light emitting structure 311 provided corresponding to the first electrode 21 may be the same as the shape of the first electrode 21.
  • the shape of the first light emitting structure 311 provided corresponding to the first electrode 21 may be different from the shape of the first electrode 21.
  • the first light emitting structure 311 may be rectangular as shown in FIG. 15. Or in other embodiments, it may also be represented as a circle or an ellipse, etc., which is not limited in this application.
  • each column of first electrodes may include a plurality of pattern units, so that the above-mentioned peaks and troughs can be formed.
  • each first electrode includes a plurality of circular pattern cells.
  • the shape of the first electrode 21 may include a plurality of elliptical graphic units.
  • the shape of the first electrode 21 includes a plurality of dumbbell-shaped graphic elements. In some embodiments, two round shapes may be used to form a gourd shape, and multiple gourd shapes may be used to form an electrode block, as shown in FIGS. 14 and 15.
  • each column of the first electrodes 21 may also include a gourd-shaped pattern unit. As shown in FIG. 19, since the first electrode 21 includes an elliptical pattern unit, the first electrode 21 includes only the peak and not the trough, so that the width of the first electrode 21 at the position opposite the trough is not limited.
  • each column of the first electrodes 21 may also be provided in a rectangular shape, for example, may be square or rectangular, which is not limited in this application.
  • the first light emitting structure 311 disposed on the rectangular first electrode 21 may also be rectangular.
  • the first light emitting structure 31 disposed on the rectangular first electrode 21 may also be circular or elliptical.
  • the first electrode layer 2 may be made of a transparent material
  • the second electrode layer 4 may also be made of a transparent material
  • the first electrode layer 2 and the second electrode layer 4 Can be made of transparent materials.
  • the transmittance of the transparent material is greater than or equal to 90%, which further improves the light transmittance of the first light emitting area 31, and even makes the light transmittance of the entire first light emitting area 31 above 80%.
  • the transparent material may include one or more of indium tin oxide, indium zinc oxide, silver-doped indium tin oxide, and silver-doped indium zinc oxide.
  • the light emitting layer 3 may include an organic light emitting material layer and a common layer.
  • the organic light emitting material layer may exist in multiple independent individuals to form a corresponding organic light emitting structure.
  • the common layer may include a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.
  • the hole injection layer and the hole transport layer are provided between the organic light emitting material layer and the first electrode layer 2 as an anode (ie, providing holes), and the hole injection layer is closer to the first electrode than the hole transport layer Layer 2 is provided; an electron injection layer and an electron transport layer are provided between the organic light-emitting material layer and the second electrode layer 4 serving as a cathode (ie providing electrons), and the electron injection layer is closer to the second electrode layer than the electron transport layer 4 settings.
  • the hole injection layer covers the gap between the first electrode layer 2 and the adjacent two rows of first electrodes. Moreover, the first electrode layer 2 and the second electrode layer 4 are isolated by the hole injection layer and other layers of the common layer to avoid short circuits.
  • the array substrate 100 may further include a pixel defining layer 5.
  • the pixel defining layer 5 is formed on the first electrode layer 2 and includes a plurality of first pixel defining holes 51 provided corresponding to the first light emitting region 31.
  • a plurality of first light emitting structures 311 can be formed in each pixel defining hole 51; alternatively, a single first light emitting structure 311 can also be formed in each pixel defining hole 51 to reduce color mixing between adjacent first light emitting structures 311 Probability.
  • the pixel defining layer 5 may of course also include a plurality of second pixel defining holes 52 provided corresponding to the second light emitting area 32.
  • Second pixel-defining holes 52 There may be a one-to-one correspondence between the second pixel-defining holes 52 and the second light-emitting structures, or a plurality of second light-emitting structures may be formed in a single second pixel-defining hole, which will not be repeated here.
  • the size of the second pixel defining hole 52 is not larger than the size of the first pixel defining hole 51.
  • the size of the first pixel defining hole 51 and the second pixel defining hole 52 are equal, which can reduce the difficulty of processing the mask.
  • the size of the first pixel-defining hole 51 may be larger than the size of the second pixel-defining hole 52, so that the spacing between adjacent first pixel-defining holes 51 is equal to that between adjacent second pixel-defining holes 52 At the pitch, the distribution density of the first pixel-defining holes 51 is reduced, and the number of gaps between the first pixel-defining holes 51 is reduced, thereby reducing the probability of light diffraction.
  • the pixel defining layer 5 may be made of transparent organic material as a whole; or the pixel defining layer 5 may be made of transparent inorganic material; or, the portion of the pixel defining layer 5 corresponding to the first light-emitting area 31 is made of transparent material However, the portion corresponding to the second light-emitting area 32 is made of a non-transparent material, which is not limited in this application.
  • a plurality of first light-emitting structures and a plurality of second light-emitting structures are all arranged in multiple rows, and a row of first light-emitting structures corresponds to a row of second light-emitting structures.
  • the column direction in which the plurality of first light emitting structures and the plurality of second light emitting structures are arranged may be along the Y direction as shown in FIG. 24. In other embodiments, the column direction of the plurality of first light-emitting structures 31 and the plurality of second light-emitting structures may also be along the X direction.
  • the color of the first light emitting structure in the same row is the same as the color of a second light emitting structure disposed close to the first light emitting region 31 in the second light emitting structure in the same row to reduce Process requirements for the first light-emitting region 31, and reduce the risk of color mixing of the first light-emitting region 31 in the same column direction.
  • the light emitting structures 311C and 311D are in the same column.
  • the first light emitting structure 311C and the first light emitting structure 311D are both blue; or, when the second light emitting structure 321A is green, the first light emitting structure 311C and the first light emitting structure 311D Both are green; or, when the second light emitting structure 321A is red, both the first light emitting structure 311C and the first light emitting structure 311D are red.
  • One or more first light-emitting structures close to the second light-emitting area in the light-emitting structure constitute one pixel unit 7, for example, one sub-pixel R, one sub-pixel G and one sub-pixel B form one pixel unit 7.
  • the second light-emitting structure 321A, the first light-emitting structure 311C, and the first light-emitting structure 311D may form a pixel unit 7 including red, green, and blue color blocks (as shown by the dotted frame in FIG. 23); or As shown in FIG. 26, the second light-emitting structure 321A, the second light-emitting structure 321B, and the first light-emitting structure 311D may form a pixel unit 7 including red, green, and blue color blocks (as shown by the dotted frame in FIG. 24) ). Based on this, display transition can be performed at the junction of the first light-emitting area 31 and the second light-emitting area 32 to improve the display effect.
  • the one pixel unit may also include two primary colors, such as red and green; or red and blue.
  • one pixel unit may also include four or more primary colors, so that the number of first light-emitting structures and second light-emitting structures included in the one pixel unit may be adjusted accordingly.
  • one first electrode anode
  • all light-emitting structures on the first electrode and the second electrode layer 4 (cathode) can be combined into one organic A light-emitting diode (organic light-emitting diode, OLED for short) sub-pixel 6, the driving method of the OLED sub-pixel may be active or passive.
  • OLED organic light-emitting diode
  • the first electrode 21 is provided with first light emitting structures 311E, 311F, and 311G, and covers the first light emitting structures 311E, 311F, and 311G
  • There is a second electrode layer 4 the first electrode 21, the first light emitting structures 311E, 311F and 311G and the second electrode layer 4 are formed as one OLED sub-pixel 6.
  • the light emission driving method of the OLED sub-pixel 6 may be an active type or a passive type.
  • passively driven (passively driven) OLED Passive, Matrix, OLED, PMOLED
  • the cathode and anode are simply used to form a matrix, and the sub-pixels at the intersection of rows and columns in the array are illuminated in a scanning manner.
  • Each sub-pixel is Operating in short pulse mode, it emits light with high brightness instantly.
  • the external circuit can be controlled by a display driver integrated chip (DDIC).
  • DDIC display driver integrated chip
  • An active drive (active drive) OLED (Active Matrix OLED, AMOLED) includes a thin film transistor (TFT) array, and each thin film transistor unit includes a plurality of thin film transistors and at least one storage capacitor.
  • AMOLED uses an independent thin film transistor to control each sub-pixel to emit light, and each sub-pixel can emit light continuously and independently, and finally form the desired image. In other words, the addressing of each OLED sub-pixel is directly controlled by the thin film transistor array.
  • the row selection signal of the thin film transistor array can be derived from the GIP (Gate in Panel) circuit, and the column selection signal can be derived from the display driver integrated chip (DDIC).
  • the color of the first light emitting structure displayed on any two adjacent first electrodes is the same, thereby forming an OLED as a sub-pixel of the same color.
  • the first electrode 21 is adjacent to the first electrode 22, so that all the first light emitting structures provided on the first electrode 21 and the first electrode 22 display a red color, and are located on the first electrode 21 and the second electrode
  • the color displayed by the first light emitting structure provided on the first electrode on the right side of 22 is also red.
  • all the colors displayed by the first light-emitting structure corresponding to this first light-emitting area 31 are red.
  • the colors displayed by all the first light-emitting structures of the first light-emitting area 31 may be blue or green, which is not limited in this application.
  • FIG. 29 is a schematic circuit diagram of a passive driving method of two rows and multiple columns of OLED sub-pixels of the same color in the first light-emitting area 31.
  • the first electrode corresponding to the OLED sub-pixel 6 in the first row is connected to one data line
  • the first electrode corresponding to the OLED sub-pixel 6 in the second row is connected to another data line.
  • the cathodes of all OLED sub-pixels 6 are grounded.
  • the color data signals carried by the two data lines are consistent with the colors of the OLED sub-pixels in each column, and the data signals are provided by external circuits. Since there are only two rows, only one driving current needs to be applied to the first row, and another driving current needs to be applied to the second row.
  • the two driving current signals may be derived from two data signal channels of a display driving integrated chip (DDIC).
  • DDIC display driving integrated chip
  • FIG. 30 is a circuit schematic diagram of another passive driving method of OLED same-color sub-pixels with two rows and multiple columns in the first light-emitting area 31.
  • the first electrodes corresponding to the OLED sub-pixels 6 in each row and column are connected to different data lines, and the cathodes of all OLED sub-pixels 6 are grounded.
  • the color data signal carried by each data signal channel is consistent with the color of each OLED sub-pixel, and each data signal is also provided by an external circuit. Since there are only two rows, only the driving current needs to be applied to the first row and the second row.
  • the driving current of each column can be derived from several data signal channels of the display driving integrated chip.
  • the traces of the first electrode corresponding to the first row of OLED sub-pixels 6 are provided on the frame area above the first light-emitting area 31 (above the orientation shown in FIGS. 29 to 30) and the first The frame area (that is, the edge area) on the side of the light emitting area (left and right of the orientation shown in FIGS. 29 to 30).
  • the scheme in which the border area on the upper side and the side of the first light-emitting area can further reduce the number of OLED sub-pixels 6 in each column
  • the graphic film layer in the area further reduces the probability of diffraction in the light transmission mode.
  • FIG. 31 is a circuit diagram of an active driving mode of two rows and multiple columns of OLED sub-pixels of the same color in the first light-emitting area.
  • the first electrode corresponding to the first row of OLED sub-pixels 6 is connected to the drain of the driving transistor in one pixel driving circuit, and the first electrode corresponding to the second row of OLED sub-pixels 6 is connected to the other pixel driving circuit Drain of the drive transistor.
  • the cathodes of all OLED sub-pixels are grounded.
  • a pixel driving circuit includes a switching transistor X1, a driving transistor X2, and a storage capacitor C.
  • the pixel driving circuit connected to the first electrode corresponding to the first row of OLED sub-pixels 6 may be disposed in the frame area above the first light-emitting area 31.
  • the pixel driving circuit connected to the first electrode corresponding to the second row of OLED sub-pixels 6 may be disposed in the border area below the first light-emitting area 31.
  • the data line connected to the source of the switching transistor of the upper pixel driving circuit can be connected to a data signal channel of the display driving integrated chip; the data line connected to the source of the switching transistor of the lower driving circuit can be connected to the display driving Another data signal channel of the integrated chip.
  • the scanning lines connected to the gates of the switching transistors of the upper and lower driving circuits can be connected to a row of scanning signal channels of the GIP circuit.
  • Figure 32 is a GIP circuit structure and timing diagram.
  • the GIP circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5.
  • the first clock signal line XCK is connected to the gate of the first transistor T1 and the gate of the third transistor T3, and the second clock signal line CK is connected to the source of the second transistor T2.
  • the first gate line Vgh connects the source of the fourth transistor T4 and the source of the fifth transistor T5, and the second gate line Vgl connects the source of the third transistor T3.
  • the display panel 1 may include a multi-stage GIP circuit.
  • the source of the first transistor T1 of the n-th stage GIP circuit is connected to an input signal line, so that the data signal Dn is input to the n-th stage circuit.
  • the drain of the second transistor T2 of the n-th stage GIP circuit is connected to the output signal line of the n-th stage circuit.
  • the output signal of the n-th stage GIP circuit serves as the input signal Dn+1 of the source of the first transistor of the n+1-th stage GIP circuit.
  • the signal of the first gate line Vgh is a high level signal
  • the signal of the second gate line Vgl is a low level signal
  • the signal lines CK respectively output digital signals of opposite high and low levels.
  • the level of the first clock signal line XCK jumps to a low level
  • a low-level signal is input to the input signal line of the source of the first transistor of the first-stage GIP circuit
  • the power of the second clock signal line CK When the level jump becomes high level, the first-level GIP circuit outputs a low-level signal as a signal of the input signal line of the second-level GIP circuit.
  • the output signal of the nth stage circuit is used as the input signal of the n+1th stage circuit.
  • FIG. 33 is a circuit schematic diagram of another active driving method of two rows and multiple columns of OLED sub-pixels of the same color in the first light-emitting area 31.
  • the first electrodes corresponding to the OLED sub-pixels 6 in the first row are connected to the drains of corresponding driving transistors in different pixel drive circuits, and the first electrodes corresponding to the first OLED sub-pixels 6 in the second row are connected to different The drain of the corresponding driving transistor in the pixel driving circuit.
  • the cathodes of all OLED sub-pixels 6 are grounded.
  • a scan signal is input to the gate of the switching transistor in each pixel driving circuit, and the source of the driving transistor in each pixel driving circuit corresponds to the same power supply voltage.
  • a pixel driving circuit includes a transistor unit, and the transistor unit includes: a switching transistor X1, a driving transistor X2, and a storage capacitor C.
  • the pixel driving circuit connected to the first electrode corresponding to the first row of OLED sub-pixels 6 may be disposed in the border area above the first light-emitting area 31.
  • the pixel driving circuit connected to the first electrode corresponding to the second row of OLED sub-pixels 6 may be disposed in the border area below the first light-emitting area 31.
  • the data line connected to the source of the switching transistor in each pixel driving circuit provided above can be connected to a data signal channel of the display driving integrated chip.
  • the data line connected to the source of the switching transistor in each pixel driving circuit provided below can be connected to a data signal channel of the display driving integrated chip.
  • Each scanning line connected to the gate of the switching transistor in each pixel driving circuit above and below can be connected to a row of scanning signal channels of the GIP circuit. In other words, it occupies multiple data signal channels of the display driving integrated chip, and occupies one row of scanning signal channels of the GIP circuit.
  • the pixel drive circuit 34 is a schematic diagram and timing diagram of a pixel driving circuit having a function of compensating for the threshold voltage of a driving transistor.
  • the pixel drive circuit can also be as shown in FIG. 34, and the pixel drive circuit can also be a pixel that compensates for the threshold voltage of the drive transistor, such as 7T1C, 6T1C, etc. Drive circuit.
  • the 7T1C pixel drive circuit shown in FIG. 34 is divided into three working stages: reset, compensation, and light emission.
  • the working principle is: in the compensation stage, the threshold voltage Vth of the driving transistor first exists in its gate-source voltage Vgs, and in the light-emission stage, the voltage Vgs-Vth is converted into current. Because Vgs already contains Vth, the effect of Vth is offset when it is converted into current, thereby achieving current consistency.
  • the above circuit can improve the life span and display uniformity of each column of OLED sub-pixels 6.
  • a data signal is input to the gate of the driving transistor in the pixel driving circuit, and the driving transistor A source voltage signal is input to the source of.
  • another data signal is input to the gate of the driving transistor in the pixel driving circuit, and The source corresponds to a power supply voltage signal.
  • the data signal V DATA input to the source of the switching transistor in the pixel driving circuit of the OLED sub-pixel 6 in the first row described above may be a signal from one data signal channel of the display driving integrated chip.
  • the data signal V DATA input to the source of the switching transistor in the pixel driving circuit of the OLED sub-pixel 6 of the second row may be a signal from another data signal channel of the display driving integrated chip.
  • the scanning signals Gn-1 and Gn of the respective pixel driving circuits of the OLED pixels 6 of the first row and the second row may come from the two rows of scanning signal channels of the GIP circuit.
  • the transmission signal EM can come from a row of transmission signal channels of the GIP circuit.
  • the initial signal INIT can come from the display driver integrated chip.
  • the gates of the driving transistors in each pixel driving circuit correspond to the display driving A data signal of the chip, and the source of each driving transistor corresponds to the signal of the same or different power supply voltage.
  • the data signal V DATA of the pixel driving circuit of the OLED sub-pixel of the first row and each column and the sub-pixel of the OLED of the second row and each column may come from a data signal channel of the display driving integrated chip.
  • the scanning signals Gn-1 and Gn of the pixel driving circuits of the OLED sub-pixels of the first and second rows can be from the two rows of scanning signal channels of the GIP circuit, and the emission signal EM can be from the row of the emission signal channels of the GIP circuit, and the initial signal INIT can come from a display driver integrated chip.
  • the data signal V DATA of the pixel driving circuit of the OLED sub-pixels in the first row and the second row may come from multiple data signal channels of the display driving integrated chip.
  • the scanning signals Gn-1 and Gn can be from the two-line scanning signal channel of the GIP circuit, the transmitting signal EM can be from the one-line transmitting signal channel of the GIP circuit, and the initial signal INIT can be from the display driving integrated chip.
  • the first direction is the row direction of the light emitting structure arrangement on the array substrate 100 (ie, the X direction shown in FIG. 28), and the second direction is the light emission on the array substrate 100
  • the column direction of the structure arrangement ie, the Y direction shown in FIG. 28
  • the first direction may also be the light emitting structure arranged on the array substrate 100.
  • the column direction (ie, the Y direction shown in FIG. 35) and the second direction are the row directions where the light emitting structures are arranged on the array substrate 100 (ie, the X direction shown in FIG. 35).
  • FIG. 36 is a schematic circuit diagram of a passive driving method of two columns and multiple rows of OLED sub-pixels of the same color in the first light-emitting area 31.
  • the first electrode corresponding to the first column of OLED sub-pixels 6 is connected to one data line
  • the first electrode corresponding to the second column of OLED sub-pixels 6 is connected to another data line.
  • the cathodes of all OLED sub-pixels 6 are grounded.
  • the color data signals of the two data signal channels that input data signals to the first electrodes corresponding to the sub-pixels of both the first and second columns are consistent with the colors of the OLED sub-pixels 6 of each column.
  • the data lead corresponding to the first column of OLED pixels 6 may be in the border area on the left of the orientation shown in FIG. 36, and the data lead corresponding to the second column of OLED pixels 6 may be in the border area on the right of the orientation shown in FIG. 36.
  • FIG. 37 is a circuit schematic diagram of another passive driving method of two columns of multiple rows of OLED sub-pixels of the same color disposed in the first light-emitting area 31. Referring to FIG. 37, the same data signal is input to the first electrode corresponding to each row of OLED sub-pixels 6 in both the first column and the second column.
  • FIG. 38 is a schematic circuit diagram of an active driving mode of two columns and multiple rows of OLED sub-pixels of the same color in the first light-emitting area.
  • the first electrode corresponding to the OLED sub-pixel 6 in the first column is connected to the drain of a driving transistor of a pixel driving circuit, and a source voltage signal is input to the source of the driving transistor.
  • the first electrode corresponding to the second row of OLED sub-pixels 6 is connected to the drain of the driving transistor of another pixel driving circuit, and a source voltage signal is input to the source of the driving transistor.
  • the scanning lines connected to the gates of the switching transistors of the two pixel driving circuits are connected to the same scanning signal channel of the GIP circuit.
  • the pixel driving circuit in FIG. 38 takes 2T1C as an example, and in other alternatives, the pixel driving circuit may also be a pixel driving circuit such as 3T1C, 6T1C, and 7T1C.
  • the first electrode corresponding to the OLED sub-pixel 6 in both the first column and the second column is connected to the drain of a driving transistor of a pixel driving circuit, and a source voltage signal is input to the source of the driving transistor.
  • the scanning line connected to the gate of the switching transistor of the pixel driving circuit is connected to one scanning signal channel of the GIP circuit.
  • the pixel drive circuit in FIG. 39 takes 2T1C as an example, and in other alternatives, the pixel drive circuit may also be a pixel drive circuit such as 3T1C, 6T1C, 7T1C.
  • the driving method is described by taking each OLED sub-pixel included in the first light-emitting region 31 as a sub-pixel of the same color as an example.
  • the driving method when the OLED sub-pixels included in the first light-emitting area 31 are different colors will be described below.
  • one pixel unit includes three sub-pixels, corresponding to red, green, and blue, respectively.
  • the display colors of the first light emitting structures 311 disposed on the first electrode 21 are all red, and one OLED sub-pixel 61 includes three first light emitting structures.
  • the first light emitting structures 311 disposed on the first electrode 22 are all green, and one OLED sub-pixel 62 includes three first light emitting structures.
  • the first light emitting structures 311 arranged on the first electrode 23 are all blue, and an OLED sub-pixel 63 includes three first light emitting structures. Therefore, the sub-pixels 61, 62, and 63 may constitute a pixel unit 7.
  • the pixel unit including three primary colors is used as an example for description. In other embodiments, it may also include four primary colors or five primary colors, and details are not repeated herein.
  • the driving method will be described below for the pixel arrangement shown in FIG. 40.
  • FIG. 41 is a schematic circuit diagram of a passive driving method of an OLED sub-pixel with two rows and multiple columns in the first light-emitting area 31, and shows three sub-pixels of R, G, and B.
  • one sub-pixel R, one sub-pixel G, and one sub-pixel B form one pixel unit 7.
  • the first electrode corresponding to the OLED sub-pixels of the same color in the first row of pixel units is connected to one data line
  • the first electrode corresponding to the OLED sub-pixels of the same color in the second row of pixel units is connected to another data line;
  • the second electrodes corresponding to the same-color sub-pixels of all columns of OLEDs are grounded.
  • the same R data signal is input to all row red sub-pixels; the same G data signal is input to all row green sub-pixels; the same B data signal is input to all row blue sub-pixels.
  • the R, G, and B data signals are provided by external circuits.
  • the schematic diagram of FIG. 41 since there are only two rows and multiple columns, only one driving current needs to be applied to the three same-color sub-pixels in the first row, and the colors of the three same-color sub-pixels in the second row and the first row are the same The three same-color sub-pixels of the second row apply another drive current.
  • the three same-color sub-pixels R of the first row apply one drive current
  • the three same-color sub-pixels R of the second row apply another drive current.
  • the driving current applied by the sub-pixels in the first row can be derived from the three data signal channels of the display driving integrated chip
  • the driving current applied by the sub-pixels in the second row can be derived from the other three data of the display driving integrated chip Signal channel.
  • FIG. 42 is a circuit schematic diagram of another passive driving method of an OLED sub-pixel with two rows and multiple columns in the first light-emitting area. Referring to FIG. 42, one sub-pixel R, one sub-pixel G, and one sub-pixel B form one pixel unit 7.
  • the second electrodes of the OLED sub-pixels of each pixel unit in the first row and the second row are grounded, the first electrode corresponding to each sub-pixel in the first row is connected to the drain of the corresponding one of the switching transistors, and the The source of the switching transistor corresponding to the same-color sub-pixel of each row of pixel units is connected to a data line and the same data signal is input, and the gate of the switching transistor corresponding to the same-color sub-pixel of the first row is connected to a switching signal line and is Input the same switch signal.
  • the source of the switching transistor corresponding to the same color sub-pixel of each pixel unit in the second row is connected to another data line and the same data signal is input, and the gate of the switching transistor corresponding to the same color sub-pixel in the second row is connected to another switching signal And the same switch signal is input.
  • the same-color sub-pixels in the second row have the same color as the same-color sub-pixels in the first row. In addition to being able to uniformly control the display or non-display of a row of sub-pixels of the same color, and when the switch signal is "off", it can also control all columns of sub-pixels of the same color in a non-display state to prevent crosstalk of adjacent other color sub-pixels during display.
  • the anode of the sub-pixel of each pixel unit in each row is connected to the drain of a switching transistor, the source of the switching transistor corresponding to the same-color sub-pixel of each pixel unit in the first row is connected to a data line, and the gates are connected differently The line of the switching signal; the source of the switching transistor corresponding to the same color sub-pixel of each pixel unit in the second row is connected to another data line, and the gate is connected to the line of different switching signals.
  • FIG. 43 is a circuit schematic diagram of another passive driving mode of the two-row multi-column OLED sub-pixels of the first light-emitting area 31.
  • one sub-pixel R, one sub-pixel G, and one sub-pixel B form one pixel unit 7.
  • the anodes corresponding to the sub-pixels in each pixel unit of the first row and the second row can be connected to different data lines, that is, the corresponding One electrode is connected to one data line.
  • the data signal is also provided by an external circuit.
  • the driving current of each column can be derived from several data signal channels of the display driving integrated chip.
  • FIG. 44 is a schematic circuit diagram of an active driving method of an OLED sub-pixel with two rows and multiple columns in the first light-emitting area.
  • one sub-pixel R, one sub-pixel G, and one sub-pixel B form one pixel unit 7.
  • the second electrodes of the OLED sub-pixels of the same color in each pixel unit in the first row and the second row are grounded.
  • the first electrode corresponding to the OLED sub-pixel of the same color in each pixel unit of the first row is connected to the drain of a driving transistor in a pixel driving circuit.
  • the gate of the one driving transistor corresponds to one data signal.
  • the first electrode corresponding to the same-color sub-pixel of the OLED of each pixel unit in the second row is connected to the drain of one driving transistor in another pixel driving circuit, and the gate of the driving transistor corresponds to one data signal.
  • the pixel driving circuit may include a plurality of transistor units.
  • Each transistor unit corresponding to the OLED sub-pixels of the same color in each pixel unit in the first row and the second row may include: a switching transistor X1, a driving transistor X2, and a storage capacitor C.
  • the data line connected to each transistor unit can be connected to a data signal channel of the display driving integrated chip.
  • the scanning line connected to the transistor unit corresponding to the same color sub-pixel of each pixel unit in the upper and lower rows can be connected to a row of scanning signal channels of the GIP circuit.
  • each pixel unit of the first row occupies three data signal channels of the display driver integrated chip, and each pixel unit of the second row occupies the other three data signal channels of the display driver integrated chip; each pixel unit of the first row and the second row occupies One line of the GIP circuit scans the signal channel.
  • the first electrodes of the same-color sub-pixels of each column of OLEDs of each pixel unit are connected to the drains of driving transistors in different pixel driving circuits, and the gate of each driving transistor corresponds to a data signal.
  • the pixel driving circuit may include a transistor unit. Each transistor unit may include a switching transistor X1, a driving transistor X2, and a storage capacitor C.
  • the data line connected to each transistor unit can be connected to one data signal channel of the display driving integrated chip; each scan line connected to each transistor unit can be connected to one row of scanning signal channels of the GIP circuit. In other words, it occupies multiple data signal channels of the display driving integrated chip, and occupies one row of scanning signal channels of the GIP circuit.
  • the pixel driving circuit in addition to the above 2T1C, the pixel driving circuit may also be a pixel driving circuit such as 6T1C, 7T1C.
  • the data signal V DATA of each pixel driving circuit mentioned above may come from a plurality of data signal channels of the display driving integrated chip, and the scanning signals G n-1 and G n may come from the two rows of scanning signal channels of the GIP circuit.
  • the emission signal EM can come from a row of emission signal channels of the GIP circuit, and the initial signal INIT can come from the display driving integrated chip.
  • the first direction is the row direction of the light emitting structure arrangement on the array substrate 100 (ie, the X direction shown in FIG. 40 ), and the second direction is the light emission on the array substrate 100
  • the column direction of the structure arrangement ie, the Y direction shown in FIG. 40
  • the first direction may also be the light emitting structure arranged on the array substrate 100.
  • the column direction (ie, the Y direction shown in FIG. 45) and the second direction are the row directions where the light emitting structures are arranged on the array substrate 100 (ie, the X direction shown in FIG. 45).
  • FIG. 45 is a circuit schematic diagram of a passive driving mode of two columns and multiple rows of OLED sub-pixels in the first light-emitting area, and shows that one pixel unit includes three sub-pixels.
  • the first electrode corresponding to the OLED sub-pixels of the same color in the first column is connected to a data line.
  • the first electrode of the second column corresponding to the same-color sub-pixel of the same color of the same-color sub-pixel of the first column is connected to another data line.
  • the same-color sub-pixels in the second column are the same colors as the same-color sub-pixels in the first column.
  • each sub-pixel in the first column may correspond to a data signal; each sub-pixel in the second column corresponds to a data signal, so as to separately control the light emission of each row of sub-pixels.
  • FIG. 46 is a schematic circuit diagram of an active driving mode of two columns and multiple rows of OLED sub-pixels in the first light-emitting area, and shows that one pixel unit includes three sub-pixels.
  • the first electrode corresponding to the OLED sub-pixels of the same color in the first column is connected to the drain of a driving transistor of a pixel driving circuit.
  • the first electrode corresponding to the OLED sub-pixel of the same color in the second column is connected to the drain of the driving transistor of another pixel driving circuit.
  • the color of the same-color sub-pixel in the second column is the same as the color of the same-color sub-pixel in the first column.
  • the color of the same-color sub-pixel in the first column is R
  • the color of the same-color sub-pixel in the second column is also R.
  • the first-row OLED sub-pixels of the same color are controlled together
  • the second-row OLED sub-pixels of the same color are controlled together
  • the sub-pixels of different colors in the same column are independently controlled.
  • the first electrode corresponding to each OLED sub-pixel of the first column may also be connected to the drain of the driving transistor of a pixel driving circuit.
  • Each OLED sub-pixel in the second column corresponds to the drain of a driving transistor of a pixel driving circuit to individually control the light emission of each sub-pixel.
  • the three primary colors are red, green, and blue, and the arrangement order is red, green, and blue. In other embodiments, it may be arranged in the order of blue, red, and green, which is not limited in this application.
  • the display panel 200 may include an encapsulation layer 201 and the array substrate 100 described in any of the above embodiments.
  • the encapsulation layer 201 is located on the side where the second electrode layer of the array substrate 100 is located.
  • a transparent display area 204 provided corresponding to the first light emitting area 31 and a non-transparent display area 203 provided corresponding to the second light emitting area may be formed on the display panel 200.
  • a photosensitive device may be placed under the transparent display area, and the photosensitive device may collect external light through the transparent display area or emit light outward. Specifically, when the photosensitive device is in a working state, the transparent display area can be switched to a non-display state, and when the photosensitive device is in a closed state, the transparent display area can be switched to a display state.
  • the display panel can include a polarizer 205, which is The non-transparent display area 203 may be covered, and the transparent display area 204 is not covered, so as to prevent the polarizer from affecting external incident light or light emitted from the electronic device equipped with the display panel 200.
  • the first light emitting area 31 of the array substrate 100 is at least partially surrounded by the second light emitting area 32
  • the display panel 200 may further include a chip assembly 202.
  • the chip assembly 202 is disposed on the side of the array substrate 100 away from the packaging layer 201 and at a portion of the display panel corresponding to the non-transparent display area 203.
  • the chip assembly 202 can be used to control the display states of the first light emitting structure and the second light emitting structure, and can make the colors of the first light emitting structure and the second light emitting structure at the junction of the first light emitting area 31 and the second light emitting area 32 consistent
  • the difference between the transparent display area and the non-transparent display area is visually reduced, and the user's visual effect is improved.
  • the embodiment of the present application further provides a display device 300 as shown in FIG. 48.
  • the display apparatus 300 may include an apparatus body 301 provided with a device area 3011 and the above-mentioned display panel 200.
  • the display panel 200 is provided on the device body 301 and connected to the device body 301.
  • the transparent area 204 of the display panel 200 covers the device area 3011.
  • the display panel 200 may use the display panel in any of the foregoing embodiments to display static or dynamic images.
  • the device area 3011 may be provided with a photosensitive device such as a camera 400 (shown in FIG. 49) and a photosensor.
  • the transparent display area 204 of the display panel 200 is set corresponding to the device area 3011, so that the above-mentioned photosensitive devices such as the camera 400 and the photosensor can collect external light through the transparent display area. Since the first light-emitting area of the array substrate can effectively improve the diffraction phenomenon caused by external light transmitting through the first light-emitting area, the quality of the image captured by the camera 400 of the display device 300 can be effectively improved, and the image captured due to diffraction can be avoided Distortion, and at the same time can also improve the accuracy and sensitivity of the light sensor to sense external light.
  • the display device may be any product or component with a display function such as a liquid crystal display device, electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, and the like.
  • a display function such as a liquid crystal display device, electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, and the like.

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Abstract

本公开提供一种阵列基板、显示面板和显示装置。阵列基板，包括：衬底、第一电极层、发光层以及第二电极层。所述第一电极层形成于所述衬底上。所述发光层形成于所述第一电极层上，且包括：透明的第一发光区，其包括多个第一发光结构，所述第一电极层包括对应所述第一发光区的多个第一电极，所述多个第一发光结构设置在所述多个第一电极上，其中，针对各个所述第一电极，所述第一电极上设有至少一个所述第一发光结构且设置在所述第一电极上的所述第一发光结构的显示颜色相同；和非透明的第二发光区，其包括多个第二发光结构，其中，所述第一发光结构在所述第一发光区的分布密度小于所述第二发光结构在所述第二发光区的分布密度。所述第二电极层形成于所述发光层上。

Description

阵列基板、显示面板和显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板、显示面板和显示装置。
背景技术
随着电子设备的快速发展，用户对屏占比的要求越来越高，使得电子设备的全面屏显示受到业界越来越多的关注。
发明内容
为解决相关技术中的技术问题，本申请提供一种阵列基板、显示面板和显示装置。
根据本申请的实施例的第一方面，提供一种阵列基板，包括：衬底、第一电极层、发光层和第二电极层。所述第一电极层形成于所述衬底上。所述发光层形成于所述第一电极层上，且包括：透明的第一发光区，所述第一发光区包括多个第一发光结构，所述第一电极层包括对应所述第一发光区的多个第一电极，所述多个第一发光结构设置在所述多个第一电极上，其中，针对各个所述第一电极，所述第一电极上设有至少一个所述第一发光结构且设置在所述第一电极上的所述第一发光结构的显示颜色相同；和非透明的第二发光区，所述第二发光区包括多个第二发光结构，其中，所述第一发光结构在所述第一发光区的分布密度小于所述第二发光结构在所述第二发光区的分布密度。所述第二电极层形成于所述发光层上。
根据本申请的实施例的第二方面，提供一种显示面板，包括：如上所述的阵列基板；以及封装层，所述封装层设置于所述阵列基板的第二电极层所在的一侧，所述显示面板的对应于所述第一发光区的区域配置为设置感光器件。
根据本申请的实施例的第三方面，提供一种显示装置，包括：设备本体，所述设备本体具有器件区；以及如上所述的显示面板，所述显示面板设置在所述设备本体的器件区所在的一侧上；其中，所述显示面板的透明显示区域覆盖所述器件区且所述器件区包括透过所述显示面板的透明显示区域发射或者采集光线的感光器件。
附图说明
此处的附图被并入说明书中并构成本说明书的一部，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。
图1是本申请根据一示例性实施例示出的一种阵列基板的结构示意图。
图2是沿图1的A-A线剖切的截面图。
图3-5是本申请根据一示例性实施例示出的一种阵列基板的结构示意图之一。
图6-7是本申请根据一示例性实施例示出的一种阵列基板上第一发光区的结构示意图之一。
图8-11是本申请根据一示例性实施例示出的一种阵列基板上第一发光区的结构示意图之二。
图12是本申请根据一示例性实施例示出的一种阵列基板的局部示意图。
图13是本申请根据一示例性实施例示出的一种阵列基板上第一发光区的结构示意图之三。
图14-20是本申请根据一示例性实施例示出的一种阵列基板上的第一电极的结构示意图。
图21是本申请根据一示例性实施例示出的另一种阵列基板的截面示意图。
图22-26是本申请根据一示例性实施例示出的一种阵列基板上的结构示意图之二。
图27是本申请根据一示例性实施例示出的一种OLED亚像素的结构示意图。
图28是本申请根据一示例性实施例示出的一种第一发光区的OLED同色亚像素排布图。
图29是第一发光区两行多列OLED同色亚像素的一种被动驱动方式的电路示意图。
图30是第一发光区两行多列OLED同色亚像素的另一种被动驱动方式的电路示意图。
图31是第一发光区两行多列OLED同色亚像素的一种主动驱动方式的电路示意图。
图32是一种GIP电路结构及时序图。
图33是第一发光区两行多列OLED同色亚像素的另一种主动驱动方式的电路示意图。
图34是具有对驱动晶体管的阈值电压进行补偿功能的一种像素驱动电路的电路图以及时序图。
图35是本申请根据一示例性实施例示出的另一种第一发光区的OLED亚像素排布图。
图36是第一发光区两列多行OLED同色亚像素的一种被动驱动方式的电路示意图。
图37是第一发光区两列多行OLED同色亚像素的另一种被动驱动方式的电路示意图。
图38是第一发光区两列多行OLED同色亚像素的一种主动驱动方式的电路示意图。
图39是第一发光区两列多行OLED同色亚像素的另一种主动驱动方式的电路示意图。
图40是本申请根据一示例性实施例示出的又一种第一发光区的OLED亚像素排布图。
图41是第一发光区两行多列OLED不同色亚像素的一种被动驱动方式的电路示意图。
图42是第一发光区两行多列OLED不同色亚像素的另一种被动驱动方式的电路示意图。
图43是第一发光区两行多列OLED不同色亚像素的再一种被动驱动方式的电路示意图。
图44是第一发光区两行多列OLED不同色亚像素的一种主动驱动方式的电路示意图。
图45是第一发光区两列多行OLED不同色亚像素的一种被动驱动方式的电路示意图。
图46是第一发光区两列多行OLED不同色亚像素的一种主动驱动方式的电路示意图。
图47是本申请根据一示例性实施例示出的一种显示面板的截面示意图。
图48是本申请根据一示例性实施例示出的一种显示装置的截面示意图。
图49是本申请根据一示例性实施例示出的一种显示装置的结构示意图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
传统的电子设备如手机、平板电脑等，由于需要集成诸如前置摄像头、听筒以及红外感应元件等，故而可通过在显示面板上开槽(Notch)，在开槽区域设置摄像头、听筒以及红外感应元件等。但是，如刘海屏的显示面板上的开槽区域并不用来显示画面。或者，采用在显示面板的屏幕上开孔的方式来设置摄像头等，这样，对于实现摄像功能的电子设备来说，外界光线通过屏幕上的开孔处会进入位于屏幕下方的感光元件，引起不良的成像效果。如此，这些电子设备的显示均不能实现良好的全面屏显示，即，电子设备所配置的显示面板的屏占比未接近100％，从而不能在整个屏幕的各个区域均进行显示，如在摄像头区域不能显示画面。基于当前电子设备的全面屏发展趋势，如何在保证电子设备前置拍摄功能的同时，将电子设备所配置的显示面板屏占比提高至接近100％，已经成为本领域内亟待解决的问题。
基于此，图1是本申请根据一示例性实施例示出的一种阵列基板100的结构示意图、图2是沿图1的A-A线剖切的截面图、以及图3是本申请根据一示例性实施例示出的一种阵列基板的结构示意图。如图1-图3所示，该阵列基板100可以包括衬底1、第一电极层2、发光层3和第二电极层4。衬底1可以包括基板、无机层和有机层等层结构。该基板可以包括柔性基板或者刚性基板。柔性基板可以采用柔性材料制成，且该柔性材料可以为聚酰亚胺(Polyimide，简称PI)聚合物，聚碳酸酯(Polycarbonate，简称PC)树脂，也称为PC塑料，聚对苯二甲酸类(Polyethylene terephthalate，简称PET)塑料等；刚性基板可以采用有机玻璃材质制成。第一电极层2形成在衬底1上、发光层3形成于第一电极层2上、第二电极层4形成于发光层3上。
在本实施例中，发光层3可以包括透明的第一发光区31和非透明的第二发光区32，第一电极层2的对应于第一发光区31的部分包含多个第一电极21、22和23。第一发光区31可以包括设置在多个第一电极上的多个第一发光结构311。第二发光区32可以包括多个第二发光结构321。每一第一电极上可以设置多个第一发光结构311，并且，同一第一电极上的第一发光结构311的颜色相同。多个第一发光结构311在第一发光区31的分布密度小于多个第二发光结构321在第二发光区32的分布密度。
因此，在第一发光结构在透明的第一发光区域的分布密度小于第二发光结构在非透明的第二发光区域的分布密度的情况下，即，在单位面积内，第一发光结构的数量小于第二发光结构的数量，第一发光结构之间的间隙数量会减少，从而能够降低光线透过第一发光区时发生衍射的概率，加强位于第一发光区下方的感光器件的检测精度，并实现全屏显示。
所有的第一发光结构311和第二发光结构321是在同一个工艺中形成，以减少掩膜(mask)的张数，降低生产成本。
第一发光结构311和第二发光结构321的大小相同，即mask上的用于形成第一发光结构的开口图案与用于形成第二发光结构的开口图案大小相同，如此能够减少mask的形变。
进一步地，第一电极层2的多个第一电极21、22和23沿第一方向(图3中所示的X方向)排列、每一第一电极均沿第二方向(图3中所示的Y方向)延伸，该第二方向与第一方向垂直。
第一方向可以是如图3中所示为阵列基板100上所有发光结构排列的行方向、第二方向可以是如图3中所示为阵列基板100上所有发光结构排列的列方向。当然，在其他实施例中，第一方向可以是如图4中所示为阵列基板100上所有发光结构排列的列方向、第二方向可以是如图4中所示为阵列基板100上所有发光结构排列的行方向。
举例而言，仍以图3所示，假定第一电极层2可以包括对应于第一发光区31的多个第一电极21、22和23，并且，第一电极21、22和23分别对应两个第一发光结构311。且，第一电极21对应的第一发光结构311均为红色色块，第一电极22对应的第一发光结构311均为绿色色块，以及第一电极23对应的第一发光结构311均为蓝色色块。当然，在此仅以第一电极21、22和23分别对应两个第一发光结构311为例进行说明。然而，在其他实施例中，每个第一电极还可以包括三个或者三个以上的第一发光结构311，且不同第一电极所包括的第一发光结构311的数量可以相同也可以不同，本申请并不限制。
基于此，由于多个第一发光结构311和第二发光结构321采用一张mask进行蒸镀，而本申请中可以在同一第一电极上形成多个第一发光结构311，相应的在mask上对应于第一发光区31的区域可以形成多个孔，从而能够提高mask的强度，减少mask的形变，降低相邻第一发光结构311之间混色的概率。
进一步地，在本申请中，第一发光区31为透明区、第二发光区32为非透明区。并且配置有该阵列基板100的电子设备所包括的感光器件可以对应于第一发光区31设置且感光器件设置在发光层3的正下方。感光器件例如为摄像头、光线感应器或光线发射器等的发射或采集光线的器件。此时，外部光线可以透过第一发光区31后被感光器件采集；相类似的，内部光线可以透过第一发光区31而出射。基于此，可以在保证感光器件正常工作的同时，不影响电子设备的屏占比。其中，当感光器件处于关闭状态时，第一发光区31对应的区域可以用于显示图像，并且第一发光区31的对应区域示出的图像与第二发光区32的对应区域示出的图像之间可以吻合，以保证图像显示的完整性，提升显示效果。当然，在其他一些实施例中，第一发光区31对应的区域也可以是采用静态显示，本申请并不对此进行限制。
而且，在第一发光结构311的分布密度较小的情况下，在一些实施例中，如图3所示，可以是相邻的两个第一发光结构311之间的间距大于相邻的两个第二发光结构321之间的间距，以通过增大间距的方式，降低光线透过第一发光区31时发生衍射的概率。在另一些实施例中，如图5所示，也可以是第一发光结构311的面积大于第二发光结构321的面积。基于此，在单位面积内，第一发光结构311的数量小于第二发光结构321的数量，从而相比于第二发光结构，第一发光结构之间的间隙数量减少，这能够更加有效地降低光线透过第一发光区31时发生衍射的概率。
在一实施例中，仍以图1所示，第一发光区31的至少一部分可以被第二发光区32包围。例如，可以是第一发光区31全部被第二发光区32包围；或者也可以是第一发光区31的一侧边缘与第二发光区32的相对侧边缘接触。该第一发光区31可以如图1所示为水滴形；或者，在其他实施例中，该第一发光区31也可以为圆形或者矩形或者椭圆形等，本申请并不限制。
在上述实施例中，所述第二电极层4包括对应于所述第一发光区31设置的第二电极，所述第二电极为面电极。
优选的，所述第二电极为单层结构或叠层结构。所述第二电极为单层结构时，所述第二电极为单层金属层、或单层金属混合物层、或单层透明金属氧化物层。所述第二电极为叠层结构时，所述第二电极为透明金属氧化物层与金属层的叠层、或所述第二电极为透明金属氧化物层与金属混合物层的叠层。
优选的，所述第二电极材料中掺杂有金属，且所述第二电极的厚度大于或等于100埃，小于或等于500埃时，所述第二电极为整体连续的面电极，且所述第二电极的透明度大于40％。
优选的，所述第二电极材料中掺杂有金属，且所述第二电极的厚度大于或等于100埃，小于或等于200埃时，所述第二电极为整体连续的面电极，且所述第二电极的透明度大于40％。
优选的，所述第二电极材料中掺杂有金属，且所述第二电极的厚度大于或等于50埃，小于或等于200埃时，所述第二电极为整体连续的面电极，且所述第二电极的透明度大于50％。
优选的，所述第二电极材料中掺杂有金属，且所述第二电极的厚度大于或等于50埃，小于或等于200埃时，所述第二电极为整体连续的面电极，且所述第二电极的透明度大于60％。
优选的，所述第二电极为单层结构时，所述单层金属层材料为Al、Ag，所述单层金属混合物层材料为MgAg或掺杂Al的金属混合材料，所述透明金属氧化物为ITO或IZO。
基于本申请的技术方案，在一实施例中，如图6所示，以X方向为第一方向、Y方向为第二方向(即第一电极的延伸方向)为例。每一第一电极可以对应沿第二方向设置的两列第一发光结构311。基于此，可以在第一发光区31的多个第一发光结构的分布密度不变的情况下，在降低mask形变量的同时，减少第一电极的数量，降低加工难度。
在本实施例中，同一第一电极上在图6所示的X方向上相邻的两个第一发光结构311对齐设置；或者，如图7所示，在X所示方向上，同一第一电极上相邻的两个第一发光结构311错位设置。相对于图7所示的方式，同一第一电极上相邻两列的第一发光结构311对齐设置能够提高第一发光结构311排布的均匀性，提升显示效果。
进一步地，针对形成图7中所示第一发光结构311的排列方式，仍以图7所示，同一第一电极上相邻的两个第一发光结构311的中轴线在Y向上的间距为第一发光结构311在该Y向上尺寸的0.5-2倍。例如，第一发光结构311A与第一发光结构311B在X所示方向上错位，且第一发光结构311A的中轴线与第一发光结构311B的中轴线之间的间距D3等于第一发光结构311B的宽度D4。当然，在此仅以D3＝D4为例进行说明，而在其他实施例中，例如，如图8所示，D3＝1.5*D4。或者，在其他实施例中，例如，D3也可以是D4的0.5倍、0.8倍、1.2倍、1.5倍或者2倍，本申请并不进行限制。
进一步地，在本申请中，如图8、9所示，第一电极23可以包括连接部233和多个第一子电极231和232。该多个第一子电极在第一方向(如图8和图9所示的Y方向)上错位排列，每一第一子电极231包括多个电极块2311，以及第一子电极232包括多个电极块2321，且该连接部233电性连接在第一方向上相邻的两个电极块，以得到沿第二方向(如图8和图9所示的X方向)延伸的、呈波浪形的第一电极(如图9所示)。具体而言，如图8中所示，以第一电极23为例，该第一电极23可以包括第一子电极231和232，且第一子电极231包括多个电极块2311、第二子电极232包括多个电极块2321；该第一电极23还可以包括连接部233，该连接部233连接在第一方向上的相邻的两个电极块，从而能够得到如图9所示的沿X方向延伸的、呈波浪形的第一电极23。
针对图8、图9中所示的第一电极21、22、23的排列结构形状，在第一发光区31内可以排布成如图12所示的三行两列的结构。并且，在行方向上(即图12中由左至右或者由右至左的方向)，所有的第一电极所对应的第一发光结构311可以颜色相同。当然在此仅作示例性说明，在其他实施例中，也可以是排成两行两列、三行三列等，本申请并不限制。并且，也可以是同一列方向上(即图12中由上至下或者由下至上的方向)所有第一电极对应的第一发光结构311可以颜色相同。
在图8、图9所示实施例中，第一方向为Y方向、即为列方向，第二方向为X方向，即行方向为例进行说明。在其他实施例中，如图11所示，也可以是第一方向为Y方向、即为列方向，第二方向为X方向，本申请并不限制。
在一实施例中，仍以图8和图9所示，相邻的两个第一电极对应的第一发光结构311可以在第一方向(Y方向)对齐设置。示例地，图8中的第一电极23的第一子电极231的电极块2311与第一电极22的第一子电极221的电极块2211的第一发光结构在Y方向上对齐设置，而第一电极23的第一子电极232的电极块2321与第一电极22的第一子电极222的电极块2221的第一发光结构在Y方向上对齐设置。
如图10和图11所示，在第一电极为沿X方向延伸的、呈波浪形的情况下，相邻的两个第一电极对应的第一发光结构311也可以错位设置，本申请并不对此进行限制。示例地，图9中的第一电极23的第一子电极231的电极块2311的第一发光结构与第一电极22的第一子电极221的电极块2211的第一发光结构在Y方向上错位设置，而第一电极23的第一子电极232的电极块2321与第一电极22的第一子电极222的电极块2221的第一发光结构在Y方向上错位设置。
如图13所示，第一电极可为沿Y方向延伸的、呈波浪形。
基于本申请的技术方案，由于第一发光区31可以允许外部光线透过，而相邻的第一电极之间存在间隙，导致光线穿射时容易发生衍射。所以，本申请中还提出，如图14所示，在每一第一电极的延伸方向上，该第一电极的在X方向上的两条边均为波浪形，且该两条边的波峰相对设置、波谷相对设置。因此，相邻两列第一电极之间的间隙在延伸方向(图14中Y所示方向)呈现为间断变化。当然，相邻两列第一电极之间的间隙在延伸方向上可以为连续变化，即，一列第一电极包含一个第一电极而引起所述间隙的连续变化，如图16所示。第一电极21的宽度是连续变化还是间断变化都可以为周期性变化，而一个变化周期的长度可以对应于一个像素的宽度。
上述第一发光区31中设置有多列上述的第一电极，以在延伸方向上，第一电极的宽度连续变化或者间断变化，从而使得相邻两个第一电极之间具有连续变化的间距或者间断变化的间距。因此在第一电极的不同宽度位置以及相邻第一电极的不同间距之间，产生的衍射条纹的位置不同，从而不同位置处的衍生效应相互抵消，从而可以有效减弱衍射效应，进而有利于保证提高位于该第一发光区31下方摄像头的拍照效果。
具体而言，在一实施例中，仍以图14所示，以第一电极呈多行多列的形式为例进行说明。在该实施例中，Y方向为第一电极的延伸方向即第二方向、X方向为第一电极的排列方向即第一方向。每一第一电极的在X方向上的两条边的形状均可以包括一个或者多个波峰、一个或者多个波谷。以第一电极21为例，图14中T所示位置处为波峰、以图14中B所示位置处为波谷。在两条边的波峰相对处的宽度D5在30um～(A-X)um之间；两条边的波谷相对处的宽度D6大于X，且小于所述波峰相对处的宽度D5，其中A为相邻两个第一电极的沿Y方向的中轴线之间的间距，X为最小工艺尺寸，且所述A大于或等于(30+X)um。在本实施例中X为4微米，在其他的实施例中还可以更小。
进一步地，由于相邻两列第一电极的在X方向上的两条边呈波浪形延伸，从而导致相邻两列第一电极之间的间距亦随之产生变化。在本申请中，相邻两列第一电极的波峰相对处间具有最小间距W1，并在两列第一电极的波谷位置相对处具有最大间距W2。其中，最小间距W1为(A-D5)，最大间距W2为(A-D6)。
在本实施例中，以第一电极21为例，如图14所示，对应于第一电极21设置的第一发光结构311形状可以与该第一电极21的形状相同。或者，如图15所示，对应于第一电极21设置的第一发光结构311形状可以与该第一电极21的形状不同，例如，第一发光结构311可以如图15所示为长方形。或者在其他实施例中，也可以表现为圆形或者椭圆形等，本申请并不对此进行限制。
针对本申请中所述边缘为波浪形的第一电极，每列第一电极可以包含多个图形单元，从而能够形成上述的波峰和波谷。例如，如图14、图15中所示的，每一第一电极均包含多个圆形的图形单元。如图16所示，第一电极21的形状可以包含多个椭圆形的图形单元。如图17所示，第一电极21的形状包含多个哑铃形的图形单元。在一些实施例中，也可以是通过两个圆形组成一个葫芦形，并通过多个葫芦形组成电极块，可以参考图14、15所示的情况。
在一实施例中，如图18所示，每一列第一电极21也可以包含一个例如葫芦形的图形单元。如图19所示，由于第一电极21包含一个椭圆形的图形单元，因此第一电极21仅包括波峰，而不包括波谷，从而不对第一电极21在波谷相对处的宽度进行限定。
在另一实施例中，如图20所示，每一列第一电极21也可以呈矩形状设置，例如可以是正方形也可以是长方形，本申请并不限制。设置在呈矩形的第一电极21上的第一发光结构311也可以为矩形。在其他实施例中，设置在呈矩形的第一电极21上的第一发光结构31也可以是圆形或者椭圆形等。
在本申请所述的技术方案中，第一电极层2可以采用透明材质制成，第二电极层4也可以是采用透明材质制成，或者，该第一电极层2和第二电极层4可采用透明材质制成。该透明材质的透过率大于等于90％，进一步提高第一发光区31的透光率，甚至使得整个第一发光区31的透光率在80％以上。该透明材质可以包括氧化铟锡、氧化铟锌、掺杂银的氧化铟锡和掺杂银的氧化铟锌中的一种或者多种。
在一实施例中，发光层3可以包括有机发光材料层和公共层。有机发光材料层可以存在多个独立的个 体，以形成对应的有机发光结构。公共层可以包括空穴注入层、空穴传输层、电子传输层及电子注入层。空穴注入层、空穴传输层设置在有机发光材料层与作为阳极(即提供空穴)的第一电极层2之间，且空穴注入层相比于空穴传输层较靠近第一电极层2设置；电子注入层、电子传输层设置在有机发光材料层与作为阴极(即提供电子)的第二电极层4之间，且电子注入层相比于电子传输层较靠近第二电极层4设置。
由此，空穴注入层覆盖第一电极层2以及相邻两列第一电极之间的间隙。而且，通过空穴注入层以及公共层的其他层来隔离第一电极层2和第二电极层4，避免短路。
如图21所示，阵列基板100还可以包括像素限定层5。该像素限定层5形成于第一电极层2上，并且包括对应于第一发光区31设置的多个第一像素限定孔51。仍每一像素限定孔51内可以形成多个第一发光结构311；或者，每一像素限定孔51内也可以形成单个第一发光结构311，以降低相邻第一发光结构311之间的混色概率。如图22所示，该像素限定层5固然还可以包括对应于第二发光区32设置的多个第二像素限定孔52。该第二像素限定孔52与第二发光结构之间可以为一一对应，或者也可以是单个第二像素限定孔内形成多个第二发光结构，在此不再一一赘述。
在本实施例中，第二像素限定孔52的尺寸不大于第一像素限定孔51的尺寸。举例而言，如图22所示，第一像素限定孔51和第二像素限定孔52的尺寸相等，可以降低对mask的加工难度。如图23所示，该第一像素限定孔51的尺寸可以大于第二像素限定孔52的尺寸，从而在相邻第一像素限定孔51之间间距等于相邻第二像素限定孔52之间间距时，减小第一像素限定孔51的分布密度，并减少第一像素限定孔51之间的间隙数量，进而降低光线的衍射概率。该像素限定层5可以整体采用透明有机材质制成；或者，该像素限定层5也可以采用透明无机材质制成；或者，该像素限定层5对应第一发光区31的部分采用透明材质制成，而对应于第二发光区32的部分采用非透明材质制成，本申请并不对此进行限制。
基于本申请的技术方案，如图24所示，多个第一发光结构和多个第二发光结构均排成多列，并且一列第一发光结构对应一列第二发光结构。相比于多列第一发光结构对应一列第二发光结构，上述的一一对应的方式可以减小第一发光结构的分布密度。多个第一发光结构和多个第二发光结构排成的列方向可以如图24所示沿Y向。在其他实施例中，也可以是多个第一发光结构31和多个第二发光结构排成的列方向沿X向。
在本实施例中，仍以图24所示，同一列第一发光结构的颜色、与在同一列的第二发光结构中靠近第一发光区31设置的一个第二发光结构颜色一致，以降低对第一发光区31的工艺要求，且降低第一发光区31在同一列方向的混色风险。例如，图24所示方位的最左侧由第一发光结构311C和第一发光结构311D组成一列，而第二发光结构中的一个靠近第一发光区31的第二发光结构321A位于与第一发光结构311C和311D同一列。当第二发光结构321A为蓝色时，第一发光结构311C和第一发光结构311D均为蓝色；或者，当第二发光结构321A为绿色时，第一发光结构311C和第一发光结构311D均为绿色；或者，当第二发光结构321A为红色时，第一发光结构311C和第一发光结构311D均为红色。
在另一实施例中，如图25所示，一列第二发光结构中靠近第一发光区31设置的一个或者多个第二发光结构、和与所述一列第二发光结构同一列的第一发光结构中靠近第二发光区的一个或者多个第一发光结构组成一个像素单元7，例如一个亚像素R，一个亚像素G和一个亚像素B形成一个像素单元7。举例而言，可以是通过第二发光结构321A、第一发光结构311C和第一发光结构311D组成一个包括红色、绿色和蓝色色块的像素单元7(如图23中虚线框所示)；或者，如图26所示，可以是通过第二发光结构321A、第二发光结构321B和第一发光结构311D组成一个包括红色、绿色和蓝色色块的像素单元7(如图24中虚线框所示)。基于此，可以在第一发光区31和第二发光区32的交界处进行显示过渡，提升显示效果。
当然，在其他实施例中，该一个像素单元也可以是包括两个原色，例如红色和绿色；或者红色和蓝色。再例如，在一些实施例中，一个像素单元也可以是包括四个或者四个以上的原色，从而该一个像素单元所包含的第一发光结构和第二发光结构的数量可以相应进行调整。
基于上述各个实施例中所述的阵列基板100，如图27所示，可以将一个第一电极(阳极)、该第一电极上的所有发光结构和第二电极层4(阴极)组成一个有机发光二极管(organic light-emitting diode，简称为OLED)亚像素6，该OLED亚像素的驱动方式可以为主动式或者被动式。举例而言，仍以图27所示，以第一电极21为例，该第一电极21上设置有第一发光结构311E、311F和311G、且在第一发光结构311E、311F和311G上覆盖有第二电极层4，第一电极21、第一发光结构311E、311F和311G以及第二电极层4形成为一个OLED亚像素6。
OLED亚像素6的发光驱动方式可以为主动式，也可以为被动式。在被动驱动式(无源驱动式)OLED(Passive Matrix OLED，PMOLED)中，单纯地以阴极、阳极构成矩阵状，以扫描方式点亮阵列中行列交 叉点的亚像素，每个亚像素都是操作在短脉冲模式下，为瞬间高亮度发光。换言之，每个OLED亚像素的寻址直接受控于外部电路。该外部电路可以受控于显示驱动集成芯片(DDIC)。
主动驱动式(有源驱动式)OLED(Active Matrix OLED，AMOLED)包括薄膜晶体管(TFT)阵列，每一薄膜晶体管单元包含多个薄膜晶体管和至少一个存储电容器。AMOLED是采用独立的薄膜晶体管控制每个亚像素发光，且每个亚像素可以连续且独立发光，最终形成所需图像。换言之，每个OLED亚像素的寻址直接受控于薄膜晶体管阵列。薄膜晶体管阵列的行选择信号可以来源于GIP(Gate in Panel)电路，而列选择信号可以来源于显示驱动集成芯片(DDIC)。
在一实施例中，如图28所示，任意相邻的两个第一电极上第一发光结构显示的颜色相同，从而形成OLED为同色亚像素。例如，第一电极21与第一电极22相邻，从而该第一电极21和第一电极22上设置的所有第一发光结构显示的颜色均为红色，并且位于第一电极21和第二电极22右侧的第一电极上设置的第一发光结构显示的颜色亦为红色。依次类推，这个第一发光区31对应的第一发光结构显示的颜色全部为红色。在其他实施例中，也可以是第一发光区31的所有的第一发光结构显示的颜色都为蓝色或绿色，本申请并不限制。
在本实施例中，仍以图28所示，以第一方向为行方向(即X所示方向)、第二方向为列方向(即Y所示方向)。其中，图29是第一发光区31的两行多列OLED同色亚像素的一种被动驱动方式的电路示意图。参照图29，第一行的OLED亚像素6对应的第一电极连接一个数据线，第二行OLED亚像素6对应的第一电极连接另一个数据线。所有的OLED亚像素6的阴极接地。该两个数据线携带的颜色数据信号与各列OLED亚像素的颜色一致，且该数据信号由外部电路提供。由于仅具有两行，因而仅需向第一行施加一个驱动电流、第二行施加另一个驱动电流，该两个驱动电流信号可以来源于显示驱动集成芯片(DDIC)的两个数据信号通道。
图30是第一发光区31两行多列OLED同色亚像素的另一种被动驱动方式的电路示意图。参照图30，每行各列OLED亚像素6对应的第一电极连接不同的数据线，所有OLED亚像素6的阴极接地。各个数据信号通道携带的颜色数据信号与各个OLED亚像素的颜色一致，且各个数据信号也由外部电路提供。由于仅具有两行，因而仅需向第一行、第二行施加驱动电流。各列的驱动电流可以来源于显示驱动集成芯片的若干个数据信号通道。
图29与图30中，对于第一行OLED亚像素6对应的第一电极的走线设置在第一发光区31的上边(图29至图30所示方位的上方)的边框区以及第一发光区的侧边(图29至图30所示方位的左右)的边框区(即，边缘区域)。相对于走线设置在各列OLED亚像素6所在区域(即，第一发光区)的方案，设置在第一发光区的上边和侧边的边框区的方案能进一步减少各列OLED亚像素6所在区域的图形膜层，进一步降低透光模式下的衍射的概率。
图31是第一发光区的两行多列OLED同色亚像素的一种主动驱动方式的电路图。参照图31，第一行OLED亚像素6对应的第一电极连接至一个像素驱动电路中的驱动晶体管的漏极，第二行OLED亚像素6对应的第一电极连接至另一个像素驱动电路中的驱动晶体管的漏极。所有OLED亚像素的阴极接地。第一行OLED亚像素6对应的驱动晶体管的栅极通过一开关晶体管连接一个数据线，第二行的OLED亚像素6对应的驱动晶体管的栅极通过一开关晶体管连接另一个数据线，该两个驱动晶体管的源极分别被输入一电源电压VDD。图31中，一个像素驱动电路包括一开关晶体管X1、一驱动晶体管X2以及一存储电容C。
与第一行OLED亚像素6对应的第一电极连接的像素驱动电路可以设置在第一发光区31的上方的边框区。与第二行OLED亚像素6对应的第一电极连接的像素驱动电路可以设置在第一发光区31下方的边框区。
该上方的像素驱动电路的开关晶体管的源极所连接的数据线可以接入显示驱动集成芯片的一个数据信号通道；下方的驱动电路的开关晶体管的源极所连接的数据线可以接入显示驱动集成芯片的另一个数据信号通道。上下方的驱动电路的开关晶体管的栅极所连接的扫描线可以接入GIP电路的一行扫描信号通道。
图32是一种GIP电路结构及时序图。参照图32，GIP电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5。第一时钟信号线XCK连接第一晶体管T1的栅极和第三晶体管T3的栅极，第二时钟信号线CK连接第二晶体管T2的源极。第一栅极线Vgh连接第四晶体管T4的源极和第五晶体管T5的源极，第二栅极线Vgl连接第三晶体管T3的源极。显示面板1中可以包括多级GIP电路，第n级GIP电路的第一晶体管T1的源极连接一输入信号线，从而为第n级电路输入数据信号Dn。第n级GIP电路的第二晶体管T2的漏极连接第n级电路的输出信号线。第n级GIP电路的输出信号作为第n+1级GIP电路的第一晶体管的源极的输入信号Dn+1。
参照图32中的GIP电路驱动的时序图，第一栅极线Vgh的信号为高电平信号，第二栅极线Vgl的信号为低电平信号，第一时钟信号线XCK和第二时钟信号线CK分别输出高低电平相反的数字信号。在第一时钟信号线XCK的电平跳变为低电平时，第1级GIP电路的第一晶体管的源极的输入信号线被输入一低电平信号，在第二时钟信号线CK的电平跳变为高电平时，第1级GIP电路输出低电平信号，以作为第2级GIP电路的输入信号线的信号。并以此类推，第n级电路的输出信号作为第n+1级电路的输入信号。
图33是第一发光区31的两行多列OLED同色亚像素的另一种主动驱动方式的电路示意图。参照图33，第一行的OLED亚像素6对应的第一电极连接至不同像素驱动电路中的对应的驱动晶体管的漏极，第二行第一OLED亚像素6对应的第一电极连接至不同像素驱动电路中的对应的驱动晶体管的漏极。所有OLED亚像素6的阴极接地。每一像素驱动电路中的开关晶体管的栅极被输入一个扫描信号，各个像素驱动电路中的驱动晶体管的源极对应同一电源电压。
图33中，一个像素驱动电路包括一晶体管单元，且晶体管单元包括：一开关晶体管X1、一驱动晶体管X2以及一存储电容C。第一行OLED亚像素6对应的第一电极连接的像素驱动电路可以设置在第一发光区31上方的边框区。第二行OLED亚像素6对应的第一电极连接的像素驱动电路可以设置在第一发光区31下方的边框区。
设置在上方的各个像素驱动电路中的开关晶体管的源极所连接的数据线可以接入显示驱动集成芯片的一个数据信号通道。设置在下方的各个像素驱动电路中的开关晶体管的源极所连接的数据线可以接入显示驱动集成芯片的一个数据信号通道。上下方的各个像素驱动电路中的开关晶体管的栅极所连接的各个扫描线可以接入GIP电路的一行扫描信号通道。换言之，占据显示驱动集成芯片的多个数据信号通道，以及占据GIP电路的一行扫描信号通道。
图34是具有对驱动晶体管的阈值电压进行补偿功能的一种像素驱动电路的示意图以及时序图。像素驱动电路除了上述的2T1C(即，2个薄膜晶体管和一个电容器)形式，还可以为如图34所示的，像素驱动电路还可以为7T1C、6T1C等对驱动晶体管的阈值电压进行补偿的像素驱动电路。图34所示的7T1C像素驱动电路分为三个工作阶段：复位、补偿、发光。工作原理为：在补偿阶段中，把驱动晶体管的阈值电压Vth先存在在它的栅源电压Vgs内，以及在发光阶段中，把电压Vgs-Vth转换为电流。因为Vgs已经包含了Vth，因而在转化成电流时就把Vth的影响抵消了，从而实现了电流的一致性。上述电路可以提高各列OLED亚像素6的寿命以及显示均匀性。
在第一行的OLED亚像素6对应的第一电极连接至一个像素驱动电路中的驱动晶体管的漏极的情况下，像素驱动电路中的驱动晶体管的栅极被输入一个数据信号，且驱动晶体管的源极被输入一个电源电压信号。在第二行的OLED亚像素6对应的第一电极连接至另一个像素驱动电路中的驱动晶体管的漏极的情况下，像素驱动电路中的驱动晶体管的栅极被输入另一个数据信号，且源极对应一电源电压信号。向上述的第一行的OLED亚像素6的像素驱动电路中的开关晶体管的源极输入的数据信号V DATA可以来自显示驱动集成芯片的一个数据信号通道的信号。向第二行OLED亚像素6的像素驱动电路中的开关晶体管的源极输入的数据信号V DATA可以来自显示驱动集成芯片的另一个数据信号通道的信号。第一行与第二行OLED像素6的各自像素驱动电路的扫描信号Gn-1、Gn可以来自GIP电路的两行扫描信号通道。发射信号EM可以来自GIP电路的一行发射信号通道。初始信号INIT可以来自显示驱动集成芯片。
在第一行、第二行的OLED亚像素6对应的第一电极连接至不同像素驱动电路中的驱动晶体管的漏极的情况下，每一像素驱动电路中的驱动晶体管的栅极对应显示驱动芯片的一个数据信号，而各驱动晶体管的源极对应同一或不同电源电压的信号。第一行每列的OLED亚像素、第二行每列OLED的亚像素的像素驱动电路的数据信号V DATA可以来自显示驱动集成芯片的一个数据信号通道。第一行与第二行的OLED亚像素的像素驱动电路的扫描信号Gn-1、Gn可以来自GIP电路的两行扫描信号通道，发射信号EM可以来自GIP电路的一行发射信号通道，以及初始信号INIT可以来自显示驱动集成芯片。第一行、第二行的OLED亚像素的像素驱动电路的数据信号V DATA可以来自显示驱动集成芯片的多个数据信号通道。扫描信号Gn-1、Gn可以来自GIP电路的两行扫描信号通道，发射信号EM可以来自GIP电路的一行发射信号通道，初始信号INIT可以来自显示驱动集成芯片。
在上述图29-34所示实施例中，以第一方向为阵列基板100上发光结构排布的行方向(即图28中所示的X向)、第二方向为为阵列基板100上发光结构排布的列方向(即图28中所示的Y向)为例进行说明，在其他实施例中，如图35所示，也可以是第一方向为阵列基板100上发光结构排布的列方向(即图35中所示的Y向)、第二方向为阵列基板100上发光结构排布的行方向(即图35中所示的X向)。下述针对图35中所示的第一方向为列方向、第二方向为行方向时的驱动方式进行说明。
图36是第一发光区31的两列多行OLED同色亚像素的一种被动驱动方式的电路示意图。参照图36，第一列OLED亚像素6对应的第一电极连接一个数据线，而第二列OLED亚像素6对应的第一电极连接另一个数据线。所有OLED亚像素6的阴极接地。向第一列和第二列两者的亚像素对应的第一电极输入数据信号的两个数据信号通道的颜色数据信号与各列OLED亚像素6的颜色一致。示例地，第一列OLED像素6对应的数据引线可以在图36所示方位的左边的边框区，第二列OLED像素6对应的数据引线可以在图36所示方位的右边的边框区。
图37是设置在第一发光区31的两列多行OLED同色亚像素的另一种被动驱动方式的电路示意图。参照图37，第一列、第二列两者的各行OLED亚像素6对应的第一电极被输入同一个数据信号。
图38是第一发光区的两列多行OLED同色亚像素的一种主动驱动方式的电路示意图。参照图38，第一列的OLED亚像素6对应的第一电极连接一个像素驱动电路的驱动晶体管的漏极，该驱动晶体管的源极被输入一电源电压信号。第二列OLED亚像素6对应的第一电极连接另一个像素驱动电路的驱动晶体管的漏极，且该驱动晶体管的源极被输入一电源电压信号。两个像素驱动电路的开关晶体管的栅极所连接的扫描线连接GIP电路的同一扫描信号通道。
图38中的像素驱动电路以2T1C为例，而其它可选方案中，像素驱动电路也可以为3T1C、6T1C、7T1C等像素驱动电路。
图39是第一发光区的两列多行OLED同色亚像素的另一种主动驱动方式的电路示意图。参照图39，第一列、第二列两者的OLED亚像素6对应的第一电极连接一个像素驱动电路的一个驱动晶体管的漏极，而驱动晶体管的源极被输入一电源电压信号。像素驱动电路的开关晶体管的栅极所连接的扫描线连接GIP电路的一个扫描信号通道。
图39中的像素驱动电路以2T1C为例，而其它可选方案中，像素驱动电路也可以为3T1C、6T1C、7T1C等像素驱动电路。
在上述各个实施例中，以第一发光区31所包括的各个OLED亚像素为同色亚像素为例来对驱动方式进行说明。下面将针对第一发光区31所包括的OLED亚像素为不同颜色时的驱动方式进行说明。
如图40所示，一个像素单元包括三个亚像素，分别对应红色、绿色、和蓝色。第一电极21上布置的第一发光结构311的显示颜色均为红色，且一OLED亚像素61包含三个第一发光结构。第一电极22上布置的第一发光结构311均为绿色，且一OLED亚像素62包含三个第一发光结构。第一电极23上布置的第一发光结构311均为蓝色，且一OLED亚像素63包含三个第一发光结构。因此，亚像素61、62和63可以构成一像素单元7。在此仅以像素单元包括三原色为例进行说明，在其他实施例中，固然也可以是包括四原色或者五原色，在此不再一一赘述。
下述将针对图40所示的像素排布，对驱动方式进行说明。
图41是第一发光区31两行多列OLED亚像素的一种无源驱动方式的电路示意图，且示出了R、G、B三个亚像素。参照图41，一个亚像素R、一个亚像素G和一个亚像素B形成一个像素单元7。在此情况下，第一行像素单元中的OLED同色亚像素对应的第一电极连接至一个数据线，第二行像素单元中的OLED同色亚像素对应的第一电极连接至另一个数据线；所有列OLED同色亚像素对应的第二电极接地。换言之，所有行红色亚像素被输入同一R数据信号；所有行绿色亚像素被输入同一G数据信号；所有行蓝色亚像素被输入同一B数据信号。该R、G和B数据信号由外部电路提供。图41示意中，由于仅具有两行、多列，因而仅需向第一行的三个同色亚像素施加一个驱动电流，第二行与第一行的所述三个同色亚像素的颜色相同的三个同色亚像素施加另一个驱动电流，例如，第一行的三个同色亚像素R施加一个驱动电流，第二行的三个同色亚像素R施加另一个驱动电流。该第一行的亚像素所施加的驱动电流可以来源于显示驱动集成芯片的三个数据信号通道，该第二行的亚像素所施加的驱动电流可以来源于显示驱动集成芯片的另三个数据信号通道。
图42是第一发光区两行多列OLED亚像素的另一种被动驱动方式的电路示意图。参照图42，一个亚像素R，一个亚像素G以及一个亚像素B形成一个像素单元7。在此情况下，第一行与第二行各像素单元的OLED亚像素的第二电极接地，第一行的每一个亚像素对应的第一电极连接相应的一个开关晶体管的漏极，且第一行各像素单元的同色亚像素对应的开关晶体管的源极连接一个数据线且被输入同一个数据信号，而且第一行的同色亚像素对应的开关晶体管的栅极连接一个开关信号线且被输入同一个开关信号。第二行各像素单元的同色亚像素对应的开关晶体管的源极连接另一个数据线且被输入同一个数据信号，而第二行的同色亚像素对应的开关晶体管的栅极连接另一开关信号线且被输入同一个开关信号。第二行的同 色亚像素为与第一行的同色亚像素的颜色相同。除了能统一控制一行同色亚像素显示或不显示外，而且，在开关信号为“关”时，还能将所有列同色亚像素控制在不显示状态，防止相邻其它颜色亚像素显示时串扰。
其它可选方案中，每行各像素单元的亚像素的阳极连接一开关晶体管的漏极，第一行各像素单元的同色亚像素对应的开关晶体管的源极连接一个数据线，栅极连接不同开关信号的线；第二行各像素单元的同色亚像素对应的开关晶体管的源极连接另一个数据线，栅极连接不同开关信号的线。上述结构使得各列同色亚像素可以单独控制显示或透明。
图43是第一发光区31的两行多列OLED亚像素的再一种被动驱动方式的电路示意图。如图43所示，一个亚像素R，一个亚像素G，一个亚像素B形成一个像素单元7。为了使得每行的同色亚像素可以被单独地控制显示或透明，也可以第一行、第二行各像素单元中的亚像素对应的阳极连接至不同数据线，即每个亚像素对应的第一电极连接一个数据线。该数据信号也由外部电路提供。事实上，由于仅具有两行，因而仅需向各列施加驱动电流。各列的驱动电流可以来源于显示驱动集成芯片的若干个数据信号通道。
图44是第一发光区两行多列OLED亚像素的一种主动驱动方式的电路示意图。参照图44，一个亚像素R、一个亚像素G和一个亚像素B形成一个像素单元7。第一行与第二行各像素单元的OLED同色亚像素的第二电极接地。第一行各像素单元的OLED同色亚像素对应的第一电极连接至一个像素驱动电路中的一个驱动晶体管漏极。在该一个像素驱动电路中，该一个驱动晶体管的栅极对应一个数据信号。第二行各像素单元的OLED同色亚像素对应的第一电极连接至另一个像素驱动电路中的一个驱动晶体管的漏极，驱动晶体管的栅极对应一个数据信号。
图44中，像素驱动电路可以包括多个晶体管单元。第一行、第二行各像素单元的OLED同色亚像素对应的每一晶体管单元可以包括：一开关晶体管X1、一驱动晶体管X2以及一存储电容C。每一晶体管单元所连接的数据线可以接入显示驱动集成芯片的一个数据信号通道。上下两行各像素单元的同色亚像素对应的晶体管单元所连接的扫描线可以接入GIP电路的一行扫描信号通道。换言之，第一行各像素单元占据显示驱动集成芯片的三个数据信号通道，第二行各像素单元占据显示驱动集成芯片的另三个数据信号通道；第一行与第二行各像素单元占据GIP电路的一行扫描信号通道。
其它可选方案中，各像素单元的各列OLED同色亚像素的第一电极连接至不同像素驱动电路中的驱动晶体管漏极，每一驱动晶体管的栅极对应一个数据信号。像素驱动电路可以包括晶体管单元。每一晶体管单元可以包括：一开关晶体管X1、一驱动晶体管X2以及一存储电容C。各个晶体管单元所连接的数据线可以接入显示驱动集成芯片的一个数据信号通道；各晶体管单元所连接的各扫描线可以接入GIP电路的一行扫描信号通道。换言之，占据显示驱动集成芯片的多个数据信号通道，以及占据GIP电路的一行扫描信号通道。
在实施过程中，各像素单元的OLED同色亚像素的第一电极连接的像素驱动电路中，除了上述的2T1C，像素驱动电路还可以为6T1C、7T1C等像素驱动电路。上述各像素驱动电路的数据信号V DATA可以来自显示驱动集成芯片的多个数据信号通道，而扫描信号G n-1、G n可以来自GIP电路的两行扫描信号通道。发射信号EM可以来自GIP电路的一行发射信号通道，而初始信号INIT可以来自显示驱动集成芯片。
在上述图41至44所示的示例中，以第一方向为阵列基板100上发光结构排布的行方向(即图40中所示的X向)、第二方向为为阵列基板100上发光结构排布的列方向(即图40中所示的Y向)为例进行说明，在其他实施例中，如图45所示，也可以是第一方向为阵列基板100上发光结构排布的列方向(即图45中所示的Y向)、第二方向为阵列基板100上发光结构排布的行方向(即图45中所示的X向)。下述针对图45中所示的第一方向为列方向、第二方向为行方向时的驱动方式进行说明
图45是第一发光区两列多行OLED亚像素的一种被动驱动方式的电路示意图，且示出了一个像素单元包含三个亚像素。参照图45，第一列的OLED同色亚像素对应的第一电极连接一数据线。第二列的与第一列的同色亚像素颜色相同的OLED同色亚像素对应的第一电极连接另一数据线。第二列的同色亚像素为与第一列的同色亚像素的颜色相同的亚像素，例如，第一列的同色亚像素为R，而第二列的同色亚像素也为R。如此，第一列OLED同色亚像素同时发同样亮度的光、第二列同色亚像素同时发同样亮度的光。其它方案中，也可以第一列的每个亚像素对应一个数据信号；第二列的每个亚像素对应一个数据信号，以单独对每一行子像素的发光进行亮暗控制。
图46是第一发光区两列多行OLED亚像素的一种主动驱动方式的电路示意图，且示出了一个像素单元包含三个亚像素。参照图46，第一列的OLED同色亚像素对应的第一电极连接一个像素驱动电路的驱动晶体管的漏极。第二列的OLED同色亚像素对应的第一电极连接另一像素驱动电路的驱动晶体管的 漏极。第二列的同色亚像素的颜色与第一列的同色亚像素的颜色相同，例如第一列的同色亚像素的颜色为R，则第二列的同色亚像素的颜色也为R。如此，第一列OLED同色亚像素被一并控制，而第二列OLED同色亚像素被一并控制，且同一列的不同色的亚像素被独立地控制。其它方案中，也可以第一列的每个OLED亚像素对应的第一电极连接一个像素驱动电路的驱动晶体管的漏极。第二列的每个OLED亚像素对应一个像素驱动电路的驱动晶体管的漏极，以单独对每一个亚像素的发光进行控制。
其它可选方案中，除了2T1C，也可以选择3T1C、6T1C、7T1C等具体的像素驱动电路。
在上述各个实施例中，三原色为红色、绿色和蓝色，且其排列顺序为红色、绿色和蓝色。在其他实施例中，也可以是蓝色、红色和绿色这样的顺序进行排列，本申请并不限制。
本申请的实施例如图47所示，还提供一种显示面板200。该显示面板200可以包括封装层201和上述任一项实施例中所述的阵列基板100。该封装层201位于阵列基板100的第二电极层所在的一侧。
在显示面板200上可以形成对应于第一发光区31设置的透明显示区域204、和对应于第二发光区设置的非透明显示区域203。并且，在透明显示区域的下方可以放置感光器件，该感光器件可以通过该透明显示区域采集外部光线，或者向外发射光线。具体，在当感光器件处于工作状态时，透明显示区域可以切换至非显示状态，当感光器件处于关闭状态时，透明显示区域可以切换至显示状态该显示面板可以包括偏光片205，该偏光片205可以覆盖非透明显示区域203，且未覆盖透明显示区域204，以避免偏光片影响外部的入射光线，或者自配置有该显示面板200的电子设备发出的光线。
在本实施例中，阵列基板100的第一发光区31至少部分被第二发光区32包围，并且该显示面板200还可以包括芯片组件202。该芯片组件202设置在阵列基板100的远离封装层201的一侧，且设置在显示面板的对应于非透明显示区域203的部分处。该芯片组件202可以用于控制第一发光结构和第二发光结构的显示状态，并且能够使得位于第一发光区31和第二发光区32交界处的第一发光结构和第二发光结构颜色一致，从而在视觉上减弱透明显示区域和非透明显示区域之间的差异，提升用户的视觉效果。
本申请实施例还提供如图48所示的一种显示装置300。该显示装置300可以包括设置有器件区3011的设备本体301和上述的显示面板200。显示面板200设置在设备本体301上，且与该设备本体301相互连接。显示面板200的透明区204覆盖器件区3011。显示面板200可以采用前述任一实施例中的显示面板，用以显示静态或者动态画面。器件区3011可以设置有诸如摄像头400(如图49所示)以及光传感器等感光器件。
此时，显示面板200的透明显示区域204对应于器件区3011设置，以使得上述的诸如摄像头400及光传感器等感光器件能够透过该透明显示区域对外部光线进行采集等操作。由于阵列基板的第一发光区能够有效改善外部光线透射该第一发光区所产生的衍射现象，从而可有效提升显示装置300的摄像头400所拍摄图像的质量，避免因衍射而导致所拍摄的图像失真，以及同时也能提升光传感器感测外部光线的精准度和敏感度。
该显示装置可以为液晶显示装置、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本领域技术人员可以理解附图只是一个优选实施例的示意图，附图中的模块或流程并不一定是实施本申请所必须的。以上所述仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种阵列基板，包括：
    衬底；
    第一电极层，所述第一电极层形成于所述衬底上；
    发光层，所述发光层形成于所述第一电极层上，且包括：
    透明的第一发光区，所述第一发光区包括多个第一发光结构，所述第一电极层包括对应所述第一发光区的多个第一电极，所述多个第一发光结构设置在所述多个第一电极上，其中，针对各个所述第一电极，所述第一电极上设有至少一个所述第一发光结构且设置在所述第一电极上的所述第一发光结构的显示颜色相同；和
    非透明的第二发光区，所述第二发光区包括多个第二发光结构，其中，所述第一发光结构在所述第一发光区的分布密度小于所述第二发光结构在所述第二发光区的分布密度；以及
    第二电极层，所述第二电极层形成于所述发光层上。
  2. 根据权利要求1所述的阵列基板，其中，相邻两个第一发光结构之间的间距大于相邻两个所述第二发光结构之间间距；和/或
    每个所述第一发光结构的面积大于每个所述第二发光结构的面积。
  3. 根据权利要求1所述的阵列基板，其中，每个所述第一发光结构和每个所述第二发光结构的大小相同。
  4. 根据权利要求1所述的阵列基板，其中，所述第一发光区的至少部分被所述第二发光区包围。
  5. 根据权利要求1所述的阵列基板，其中，所述第一电极沿第一方向排列且沿垂直于所述第一方向的第二方向延伸，所述第一方向为列方向，所述第二方向为行方向；或所述第一方向为行方向，所述第二方向为列方向；
    所述第二电极层包括对应于所述第一发光区设置的第二电极，所述第二电极为面电极；
    所述第二电极为单层结构或叠层结构，所述第二电极为单层结构时，所述第二电极为单层金属层、或单层金属混合物层、或单层透明金属氧化物层；所述第二电极为叠层结构时，所述第二电极为透明金属氧化物层与金属层的叠层、或所述第二电极为透明金属氧化物层与金属混合物层的叠层；
    当所述第二电极材料中掺杂有金属，且所述第二电极的厚度大于或等于100埃，小于或等于500埃时所述第二电极为整体连续的面电极，且所述第二电极的透明度大于40％；
    所述第二电极材料中掺杂有金属，且所述第二电极的厚度大于或等于100埃，小于或等于200埃时，所述第二电极为整体连续的面电极，且所述第二电极的透明度大于40％；
    当所述第二电极材料中掺杂有金属，且所述第二电极的厚度大于或等于50埃，小于或等于200埃时，所述第二电极为整体连续的面电极，且所述第二电极的透明度大于50％；
    所述第二电极材料中掺杂有金属，且所述第二电极的厚度大于或等于50埃，小于或等于200埃时，所述第二电极为整体连续的面电极，且所述第二电极的透明度大于60％；
    所述第二电极为单层结构的状态中，所述单层金属层材料为Al、Ag，所述单层金属混合物层材料为Mg、Ag或掺杂Al的金属混合材料，所述透明金属氧化物为ITO或IZO。
  6. 根据权利要求1所述的阵列基板，其中，每一所述第一电极设置有沿平行于第一电极延伸方向的第二方向设置的多列所述第一发光结构，
    同一所述第一电极上的多列第一发光结构中的在与所述第二方向垂直的第一方向上相邻两个所述第一发光结构对齐设置或者错位设置。
  7. 根据权利要求6所述的阵列基板，其中，
    在所述相邻两个第一发光结构错位设置的状态中，同一所述第一电极上相邻两个所述第一发光结构的中轴线在所述第二方向上的间距为所述第一发光结构在所述第二方向上尺寸的0.5-2倍。
  8. 根据权利要求7所述的阵列基板，其中，
    每一所述第一电极包括：
    多个第一子电极，所述多个第一子电极在所述第一方向上错位排列，每一所述第一子电极设置有沿第二方向设置的一列第一发光结构，每一第一子电极包括多个电极块；以及
    连接部，所述连接部电性连接在所述第一方向上相邻的两个电极块，以得到沿第二方向延伸的、呈波浪形的所述第一电极。
  9. 根据权利要求8所述的阵列基板，其中，
    相邻两个所述第一电极对应的所述第一发光结构对齐设置或错位设置。
  10. 根据权利要求1所述的阵列基板，其中，
    所述第一电极在所述第一电极的延伸方向上的两条边均为波浪形，且所述两条边的波峰相对设置、以及波谷相对设置；
    每一所述第一电极在所述衬底上的正投影包含一个图形单元或多个图形单元。
  11. 根据权利要求10所述的阵列基板，其中，所述阵列基板还包括：
    形成于所述第一电极层上的像素限定层，所述像素限定层包括对应于所述第一发光区的多个第一像素限定孔，每一所述第一像素限定孔对应一个或者多个所述第一发光结构；以及
    对应于所述第二发光区的多个第二像素限定孔，所述第二像素限定孔的尺寸不大于所述第一像素限定孔的尺寸。
  12. 根据权利要求11所述的阵列基板，其中，
    多个所述第一发光结构和多个所述第二发光结构均排布成多列，且一一对应，且所述第一发光结构颜色与在同一列上的第二发光结构中靠近所述第一发光区设置的一个第二发光结构颜色一致。
  13. 根据权利要求11所述的阵列基板，其中，
    所述阵列基板还包括多个像素单元，一个所述像素单元包含一列所述第二发光结构中靠近所述第一发光区设置的一个或者多个所述第二发光结构、和对应列的所述第一发光结构中靠近第二发光区的一个或者多个所述第一发光结构。
  14. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括多个OLED亚像素，每个OLED亚像素包含一个第一电极、该一个第一电极上的所有第一发光结构和第二电极层，所述OLED亚像素的驱动方式为主动式或者被动式；
    每一OLED亚像素对应的像素驱动电路设置在所述阵列基板的所述第一发光区的边缘区域。
  15. 根据权利要求14所述的阵列基板，其中
    相邻的两个第一电极上第一发光结构的颜色相同，所述OLED亚像素为相同颜色的同色亚像素；
    在所述OLED亚像素的驱动方式为被动式，
    当与所述第一电极的延伸方向垂直的第一方向为列方向时，一列的OLED同色亚像素的第一电极连接至同一数据线；各列OLED同色亚像素的第一电极连接至同一数据线或不同数据线；
    当与所述第一电极的延伸方向垂直的所述第一方向为行方向时，一行OLED同色亚像素的第一电极连接至同一数据线；各行OLED同色亚像素的第一电极连接至同一数据线或不同数据线。
  16. 根据权利要求14所述的阵列基板，其中，
    相邻的两个第一电极上第一发光结构的颜色相同，所述OLED亚像素为相同颜色的同色亚像素；
    所述OLED亚像素的驱动方式为主动式，
    当与所述第一电极的延伸方向垂直的所述第一方向为列方向时，一列OLED同色亚像素的第一电极连接至同一像素驱动电路中的驱动晶体管的漏极，所述驱动晶体管的栅极对应一个数据信号；
    当与所述第一电极的延伸方向垂直的所述第一方向为行方向时，一行OLED同色亚像素的第一电极连接至同一像素驱动电路中的驱动晶体管的漏极，所述驱动晶体管的栅极对应一个数据信号。
  17. 根据权利要求1所述的阵列基板，其中
    相邻的两个第一电极上的第一发光结构的颜色不同；
    其中，所述阵列基板还包括多个像素单元，一个像素单元包含沿与第一电极延伸方向垂直的第一方向、连续的n个OLED亚像素，所述像素单元包括n个颜色，n≥3；
    所述像素单元的驱动方式为被动式，当所述第一方向为列方向时，各行的像素单元中OLED同色亚像素对应的第一电极连接至同一数据线或不同数据线；所述像素单元的驱动方式为被动式，当所述第一方向为行方向时，各列的像素单元中的OLED同色亚像素对应的第一电极连接至同一数据线或不同数据线；或
    所述像素单元的驱动方式为被动式，当所述第一方向为列方向时，各像素单元中的每个OLED亚像素的第一电极连接至一开关晶体管的漏极，所述开关晶体管的源极连接同一数据线或不同数据线，位于一列的部分或所有OLED同色亚像素对应的开关晶体管的栅极被输入同一扫描信号；当所述第一方向为行方向时，各像素单元中的每个OLED亚像素的第一电极连接至一开关晶体管的漏极，所述开关晶体管的源极连接同一数据线或不同数据信号，位于一行的部分或所有OLED同色亚像素对应的开关晶体管的栅极被输入同一扫描信号。
  18. 根据权利要求1所述的阵列基板，其中，
    相邻的两个第一电极上的第一发光结构的颜色不同；
    其中，所述阵列基板还包括多个像素单元，一个像素单元包含沿与第一电极延伸方向垂直的第一方向、连续的n个OLED亚像素，所述像素单元包括n个颜色，n≥3；
    所述像素单元的驱动方式为主动式，
    当所述第一方向为列方向时，一列像素单元中的OLED同色亚像素的第一电极连接至同一像素驱动电路或不同像素驱动电路中的驱动晶体管的漏极，每一所述驱动晶体管的栅极对应一个数据信号；或
    所述像素单元的驱动方式为主动式，当所述第一方向为行方向时，一行像素单元中的OLED同色亚像素的第一电极连接至同一像素驱动电路或不同像素驱动电路中的驱动晶体管的漏极，每一所述驱动晶体管的栅极对应一个数据信号。
  19. 一种显示面板，包括：
    如权利要求1所述的阵列基板；以及
    封装层，所述封装层设置于所述阵列基板的所述第二电极层所在的一侧。
  20. 一种显示装置，包括：
    设备本体，所述设备本体包括器件区；以及
    如权利要求19所述的显示面板，所述显示面板设置在所述设备本体的器件区所在的一侧上；
    所述显示面板对应于所述第一发光区的区域覆盖所述器件区且所述器件区包括透过所述显示面板对应于所述第一发光区的区域发射或者采集光线的感光器件。
PCT/CN2019/091283 2018-12-28 2019-06-14 阵列基板、显示面板和显示装置 WO2020133950A1 (zh)

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