WO2020133938A1 - 显示面板、显示面板制备方法、显示屏及显示终端 - Google Patents

显示面板、显示面板制备方法、显示屏及显示终端 Download PDF

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Publication number
WO2020133938A1
WO2020133938A1 PCT/CN2019/090869 CN2019090869W WO2020133938A1 WO 2020133938 A1 WO2020133938 A1 WO 2020133938A1 CN 2019090869 W CN2019090869 W CN 2019090869W WO 2020133938 A1 WO2020133938 A1 WO 2020133938A1
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Prior art keywords
layer
substrate
area
display panel
region
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PCT/CN2019/090869
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English (en)
French (fr)
Inventor
刘如胜
盛翠翠
徐琳
黄根茂
袁波
杜哲
楼均辉
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云谷（固安）科技有限公司
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Publication of WO2020133938A1 publication Critical patent/WO2020133938A1/zh
Priority to US17/159,122 priority Critical patent/US12004401B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/176—Passive-matrix OLED displays comprising two independent displays, e.g. for emitting information from two major sides of the display
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/102—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising tin oxides, e.g. fluorine-doped SnO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/103—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising indium oxides, e.g. ITO

Definitions

  • the present application relates to the field of display technology, in particular to a display panel, a preparation method of the display panel, a display screen, and a display terminal.
  • a display panel a display panel preparation method, a display screen, and a display terminal are provided.
  • a first aspect of the present application provides a display panel, including: a substrate, the substrate including a plurality of sub-pixel regions, each sub-pixel region includes a first region and a second region, the first region is provided with the substrate, A buffer layer and a pixel circuit layer, the second area is provided with the substrate; the first electrode is provided on the second area of each sub-pixel area, and the first electrode is directly connected to the substrate contact.
  • a second aspect of the present application provides a method for manufacturing a display panel, including the steps of providing a substrate, the substrate including a plurality of sub-pixel regions, each sub-pixel region including a first region and a second region, the first region and Each of the second regions is provided with the substrate; a buffer layer and a pixel circuit layer are prepared on the substrate in the first region; a first electrode is prepared on the substrate in the second region, and the first An electrode is in direct contact with the substrate in the second area.
  • a display screen which includes at least a first display area and a second display area, each of which is used to display a dynamic or static picture, and a photosensitive device may be provided below the first display area; wherein, A display panel according to any one of the first aspect of the present application is provided in the first display area, and the display panel provided in the second display area is a PMOLED (passive matrix light-emitting diode) display panel or AMOLED (active matrix) organic light-emitting diode display panel.
  • PMOLED passive matrix light-emitting diode
  • AMOLED active matrix organic light-emitting diode display panel
  • the display panel provided by the present application includes a substrate including a plurality of sub-pixel regions, each sub-pixel region includes a first region and a second region, the first region is provided with the substrate, the buffer layer and the pixel circuit Layer, the second area is provided with the substrate; the first electrode is provided on the second area of each sub-pixel area and the first electrode is in direct contact with the substrate.
  • each sub-pixel area is divided into a first area and a second area.
  • the first area is provided with a substrate, a buffer layer, and a pixel circuit layer
  • the second area is provided with a substrate and a first One electrode, no inorganic film layer is provided between the first electrode and the substrate, which reduces the coverage area of the inorganic film layer and improves the transparency of the display panel.
  • FIG. 1 is a cross-sectional view of a specific example of a display panel in an embodiment of this application;
  • FIG. 2 is a top view of a specific example of a display panel in an embodiment of this application.
  • FIG. 3 is a schematic diagram of a specific example of a display panel in the prior art
  • FIG. 4 is a schematic diagram of another specific example of a display panel in an embodiment of this application.
  • FIG. 5 is a schematic diagram of another specific example of the display panel in the embodiment of the present application.
  • FIG. 6 is a schematic diagram of another specific example of the display panel in the embodiment of the present application.
  • FIG. 7 is a schematic diagram of another specific example of the display panel in the embodiment of the present application.
  • FIG. 8 is a schematic diagram of a specific example of scanning lines of a display panel in an embodiment of the present application.
  • FIG. 9 is a schematic diagram of another specific example of the scan line of the display panel in the embodiment of the present application.
  • FIG. 10 is a schematic diagram of another specific example of the scan line of the display panel in the embodiment of the present application.
  • FIG. 11 is a schematic diagram of a specific example of the first electrode of the display panel in the embodiment of the present application.
  • FIG. 12 is a schematic diagram of another specific example of the first electrode of the display panel in the embodiment of the present application.
  • FIG. 13 is a schematic diagram of another specific example of the first electrode of the display panel in the embodiment of the present application.
  • FIG. 14 is a schematic diagram of a specific example of the pixel defining layer opening of the display panel in the embodiment of the present application.
  • 16 is a schematic diagram of a specific example of a display screen in an embodiment of this application.
  • 17 is a schematic diagram of a specific example of a display terminal in an embodiment of this application.
  • FIG. 18 is a schematic structural diagram of a device body in an embodiment of this application.
  • the display screen In order to achieve full-screen display, the display screen needs to achieve a certain transparency to meet the transparency requirements of cameras and the like. However, since the light transmittance of the materials constituting the inorganic film layer and the organic film layer in the pixel circuit is not 100%, these film layers reduce the transparency of the display screen and affect the overall consistency of the display screen.
  • the present application provides a display panel that does not cover the inorganic film layer and the organic film layer on the unnecessary area of the display panel, reduces the coverage area of the inorganic film layer and the organic film layer and other film layers, and improves the display panel
  • the transparency of the problem solves the above problems very well.
  • the display panel includes: a substrate 1 including a plurality of sub-pixel regions, each The sub-pixel area includes a first area 11 and a second area 12, the first area 11 is provided with a substrate 1, a buffer layer 4 and a pixel circuit layer 2, the second area 12 is provided with a substrate 1, a first electrode 3, and a second area 12.
  • the first electrode 3 is in direct contact with the substrate 1.
  • a pixel circuit layer is provided on the first region 11 of each sub-pixel region, and a corresponding first electrode 3 is provided on the second region 12 of each sub-pixel region,
  • the first electrode 3 and the pixel circuit 2 have a one-to-one correspondence.
  • the substrate 1 may be a substrate; the substrate 1 may be a flexible substrate, such as a PI film, etc.; or a rigid substrate, such as a transparent substrate such as a glass substrate, a quartz substrate, or a plastic substrate, to improve the transparency of the device.
  • each sub-pixel area is divided into a first area and a second area.
  • the first area is provided with a substrate, a buffer layer, and a pixel circuit layer
  • the second area is provided with a substrate and a first One electrode, no inorganic film layer is provided between the first electrode and the substrate, which reduces the coverage area of the inorganic film layer and improves the transparency of the display panel.
  • the pixel circuit layer 2 may include an active layer 21, a gate insulating layer 22, a gate layer 23, and an interlayer insulating layer 24 that are sequentially disposed on the first area substrate.
  • the gate insulating layer and the interlayer insulating layer are only provided on the first area, and the specific forming process may be: the buffer layer, the gate insulating layer and the interlayer insulating layer are prepared by a conventional process to form a film layer covering the entire surface of the substrate For example, if the entire buffer layer, gate insulating layer and interlayer insulating layer are formed by spin coating or deposition, these three inorganic film layers cover the first area and the second area, as shown in FIG.
  • the inorganic film layer is patterned through a mask plate, specifically, photoresist patterning, coating, exposure, and development steps are performed on the inorganic film layer, using dry etching ( Etching gas is CF4), or dry etching + wet etching (etching solution is BOE) to etch the inorganic film layer (buffer layer, gate insulating layer GI and interlayer insulating layer ILD) to remove the second area first Inorganic film layer on the electrode position.
  • dry etching Etching gas is CF4
  • dry etching + wet etching etching solution is BOE
  • the inorganic film layer at the position of the first electrode in the second region may be removed after the preparation of an inorganic film layer, or directly outside the position of the first electrode during manufacturing An inorganic film layer is formed on the area; the specific implementation method can be reasonably selected according to the actual situation, and this embodiment does not make any limitation on this.
  • a barrier layer (not shown) may also be provided on the substrate.
  • the first electrode is not covered with the barrier layer.
  • two barrier layers are prepared on the substrate at the same time during the formation of the substrate.
  • the first shield layer 111 is usually made of silicon nitride material
  • the second shield layer 112 is usually silicon oxide Materials, as shown in Figure 4.
  • the above-mentioned removal method in this embodiment may be used to partially or completely remove the two shielding layers at the position where the first electrode is provided in the second region, so as to further improve the transparency of the display panel.
  • the display panel further includes: a lead provided on the substrate 1, the lead including at least one of a scan line, a data line, and a connection line in the pixel circuit layer; the projections provided on the substrate overlap the projection
  • the inorganic film layer includes at least one of a gate insulating layer, an interlayer insulating layer, and a buffer layer.
  • the leads include scan lines, data lines, and connection lines in the pixel circuit layer.
  • the leads may be provided in the first area or in the second area, which may be set reasonably according to actual needs.
  • the second area 12 includes a light-emitting area and a non-light-emitting area, a first electrode 3 provided in the light-emitting area, a lead 4 provided in the non-light-emitting area directly contacts the substrate, and/or a lead located in the non-light-emitting area
  • An inorganic film layer is provided between the substrate 1 and the substrate 1.
  • the light-emitting area is not covered with an inorganic film layer
  • the first electrode 3 is provided on the light-emitting area
  • the non-light-emitting area may be entirely covered with the inorganic film layer, may not be covered with the inorganic film layer, or may be partially covered Inorganic film layer.
  • the lead located on the non-light-emitting region is directly in contact with the substrate.
  • an inorganic film layer is provided between the lead on the non-light emitting area and the substrate, and the inorganic film layer between the lead and the substrate differs according to the steps before and after preparing the lead, for example,
  • the lead is formed after the buffer layer is prepared before the gate insulating layer.
  • the inorganic film layer between the lead and the substrate is the buffer layer.
  • the lead is formed after the gate insulating layer is prepared and between the layers The insulating layer is formed before.
  • the inorganic film layer between the lead and the substrate is a buffer layer and a gate insulating layer.
  • the non-light emitting area includes a lead area for setting leads and a non-functional area, and the inorganic film layer is not covered above the non-functional area.
  • the inorganic film layer does not cover the non-functional area, the inorganic film layer is removed as much as possible, the coverage area of the inorganic film layer is reduced, and the transparency of the display panel is improved.
  • the pixel circuit layer is disposed on the first area of the substrate, the first electrode, the scan line, and the data line are disposed on the second area of the substrate, and only the first area is formed during the process of preparing the pixel circuit Inorganic film layers (such as a buffer layer, a gate insulating layer CI, an interlayer insulating layer ILD), an inorganic film layer is provided only on the second region where the projections of the leads on the substrate overlap.
  • the non-essential coverage area in the display panel does not cover the inorganic film layer and the organic film layer, which reduces the coverage area of the film layer and improves the transparency of the display panel.
  • both the first electrode and the lead are made of a transparent conductive material, and the light transmittance of the transparent conductive material is greater than 90%, thereby making the light transmittance of the entire display panel
  • the transparency of the display panel is higher.
  • the light transmittance of the transparent conductive material can also be set to other values, such as 80% or 95%, and the specific value can be set reasonably according to actual needs.
  • the transparent conductive material may be indium tin oxide (ITO), indium zinc oxide (IZO), or silver-doped indium tin oxide (Ag+ITO), or silver-doped indium zinc oxide ( Ag+IZO). Since the ITO process is mature and the cost is low, the conductive material is preferably indium zinc oxide. Further, in order to reduce the resistance of each conductive trace on the basis of ensuring high light transmittance, the transparent conductive material is made of aluminum-doped zinc oxide, silver-doped ITO, or silver-doped IZO.
  • the transparent conductive material may also use other materials, which can be set reasonably according to actual needs, which is not limited in this embodiment.
  • at least one of the first electrode, the data line, and the scan line is made of a transparent conductive material.
  • the lead includes a stacked first lead layer and a second lead layer, and the second lead layer is located above the first lead layer. Since the resistance of transparent conductive materials (such as ITO) is higher than that of metal wires, in order to achieve good electrical characteristics, metal wires are usually used as connecting wires, data lines, and scanning lines. These metal traces will seriously affect the display panel However, in this embodiment, the stacked arrangement of two lead layers made of a transparent conductive material can significantly reduce the resistance of the transparent conductive material and achieve high transparency while ensuring electrical characteristics. Of course, in other alternative embodiments, any one or any two of the scan lines, the data lines, and the connection lines in the pixel circuit layer may also be arranged in a stacked structure, which may be reasonably set according to actual needs.
  • FIG. 5 is a cross-sectional view of a specific example of the laminated structure.
  • the substrate 1, the first lead layer 102, and the second The lead layer 101, the inorganic film layer 103 below the first lead layer, and the organic film layer 104 above the first lead layer, the specific formation process can also use the above method of removing the inorganic film layer to remove the organic film layer, the difference is only in the choice
  • the etching gas or etching liquid in this embodiment will not be repeated here.
  • a stack of more layers also falls within the protection scope of this embodiment.
  • the first lead layer is a data line
  • the first lead layer is a transparent lead layer
  • the inorganic film layer 103 under the first lead layer includes GI-Si x O y , BL-Si x O y /Si x N y
  • the organic film layer 104 above the first lead layer may include CI-Si x N y , ILD-Si x O y /Si x N y , planarization-transparent/non-transparent organic glue.
  • the second lead layer and the first electrode layer are formed in the same process step.
  • the first electrode layer is an anode of an organic light-emitting diode (OLED), and is also made of a transparent conductive material.
  • the data lines and scanning lines in the first lead layer are made of ITO material; since other film layers are not covered above the first lead layer, when the first electrode layer is prepared in the subsequent process, the An additional layer of ITO is formed on top, and the layer of ITO is patterned to form a first electrode layer and a second lead layer covering the first lead layer.
  • the second lead layer is formed during the preparation of the first electrode layer, saving process steps and reducing production costs.
  • the second lead layer may also be formed in a separate step, and it may be properly arranged as needed.
  • the display panel further includes: a planarization layer, which is provided on the substrate and exposes the leads, so as to subsequently form stacked leads at the positions where the leads are exposed, reduce the resistance of the leads, and improve electrical characteristics.
  • the display panel further includes: a pixel defining layer disposed on the first electrode, disposed on the substrate and exposing the first electrode, specifically, the pixel defining layer has a plurality of openings, and the openings are exposed
  • the first electrode is used to prepare a light-emitting structure layer at this position.
  • the display panel further includes: a light-emitting structure layer, a second electrode, and a packaging layer that are sequentially stacked on the first electrode; the first area includes a pixel circuit area and a non-pixel circuit area, and the pixel circuit The inorganic film layer and the organic film layer are covered on the area and/or the light-emitting area.
  • a light-emitting structure layer is provided in the opening of the pixel defining layer to form a plurality of sub-pixels, and the sub-pixels correspond to the first electrode in one-to-one correspondence; the second electrode provided above the light-emitting structure layer, the first The two electrodes correspond one-to-one with the light emitting structure layer; the encapsulation layer is disposed on the second electrode and the pixel circuit layer.
  • the first area includes a pixel circuit area and a non-pixel circuit area, the pixel circuit area is covered with an inorganic film layer and an organic film layer, and the non-pixel area is not covered with an inorganic film layer and an organic film layer; and the second area includes a light emitting area and a non-light emitting area The inorganic film layer and the organic film layer on the light emitting area are not covered with the inorganic film layer and the organic film layer on the non-light emitting area.
  • the first area is divided into two parts (pixel circuit area and non-pixel circuit area), a pixel circuit layer is formed on the pixel circuit area, and the organic film layer and the inorganic film layer are not covered on the non-pixel circuit area; similarly, the second The area is also divided into two parts (light-emitting area and non-light-emitting area), the first electrode is formed on the light-emitting area, and the organic film layer and the inorganic film layer are not covered on the non-light-emitting area.
  • the coverage area of the inorganic film layer and the organic film layer is minimized, and the transparency of the display panel is improved. And it can also reduce the absorption of light by these layers and improve the light transmittance.
  • the photosensitive element such as a camera
  • it can increase the amount of light entering, increase the intensity of light reaching the photosensitive element, and enhance The photographing effect makes the image effect better.
  • the non-light-emitting area and the non-pixel circuit area are patterned, and the encapsulation layer, the planarization layer, the silicon oxide and the silicon nitride insulating layer at corresponding positions are etched away, and the resulting structure is shown in FIGS. 6 and 7. As shown in FIGS.
  • the pixel circuit 2 the light-emitting structure layer 63 and the encapsulation layer 61 on the substrate 1, as a schematic diagram of an application scenario of the structure, the photosensitive device 62 is disposed below the substrate, and the non-light-emitting area on the substrate
  • the non-pixel circuit area is not covered with the inorganic film layer and the organic film layer, the coverage area of the inorganic film layer and the organic film layer is further reduced, the transparency of the display panel is improved, and the absorption of light by these film layers can also be reduced, increasing The light intensity reaching the photosensitive device enhances the photographing effect.
  • the inorganic film layer includes an interlayer insulating layer, a gate insulating layer, a buffer layer, and a planarization layer.
  • the material of these inorganic film layers may be silicon oxide or silicon nitride, and may also be silicon oxide and nitrogen Of silicon dioxide; of course, in other embodiments, the inorganic film layer may also include some of the above film layers or other film layers other than the above, which can be reasonably determined according to needs, and this embodiment does not make any limitation on this .
  • the organic film layer includes an encapsulation layer, a pixel defining layer, and a planarization layer.
  • the scan line is connected to the gate.
  • the scan line and the gate can be formed in the same process step.
  • the scanning line and the gate may be made of ITO material.
  • a layer of ITO may be prepared first, and the ITO is patterned through the first mask plate to form the scanning line and Grid.
  • the scan lines may also be disposed above or below the gate, so that the gate and scan lines need to be formed separately.
  • the data line and the first electrode are formed in the same process step.
  • the data line and the first electrode are both made of ITO material, an entire surface of ITO is prepared, and the ITO is patterned through the second mask plate to form the data line and the first electrode at the same time;
  • the data line and the first electrode may also be formed separately.
  • the two sides of the scan line in its extending direction are wavy, and the two sides of the data line in its extending direction are also wavy.
  • the wavy data line and the scan line can produce different The diffraction fringes of the position and the diffusion direction weaken the diffraction effect, thereby ensuring that when the camera is arranged below the display panel, the graphics obtained by the photograph have high definition.
  • the width of the scan lines changes continuously or intermittently.
  • Continuously changing width means that the width at any two adjacent positions on the scan line is different.
  • the extending direction of the scanning line 7 is its longitudinal direction.
  • the width of the scanning line 7 continuously changes in the extending direction.
  • the discontinuous change in width means that the widths of two adjacent positions in the partial area on the scanning line 7 are the same, and the widths of the adjacent two positions in the partial area are not the same.
  • a plurality of scan lines 7 are regularly arranged on the substrate. Therefore, the gap between two adjacent scan lines 7 also shows a continuous change or an intermittent change in the direction parallel to the extending direction of the scan lines 7. In the extending direction of the scanning line 7, whether its width changes continuously or intermittently, it can be a periodic change.
  • the two sides of the scanning line 7 in the extending direction are both wavy, and the wave crests of the two sides are relatively arranged, and the wave troughs are also relatively arranged.
  • the peaks T of the two sides in the extending direction are relatively arranged and the valleys B are relatively arranged, the width between the peaks of the same scanning line 7 is W1, and the width between the valleys of the same scanning line 7 is W2,
  • the interval between the wave peaks of two adjacent scan lines 7 is D1, and the interval between the wave valleys of two adjacent scan lines 7 is D2.
  • both sides are formed by connecting the same arc-shaped side.
  • the two sides may also be formed by connecting the same elliptical side, as shown in FIG. 9.
  • both sides of the scanning line 7 into a wave shape formed by a circular arc or an ellipse, it can be ensured that the diffraction fringes generated on the scanning line 7 can be diffused in different directions, and thus no significant diffraction effect will be generated.
  • a second connection portion is formed at a position opposite to the valley of the wavy scanning line, and the second connection portion may be a straight line or a curved line.
  • the second connection portion is in the shape of a strip, and the second connection portion is an area where the scanning line 7 is electrically connected to the switching device, that is, a position where the control end of the switching device is connected to the second connection portion.
  • the second connection portion may also adopt other irregular structures, such as a shape with large middle ends and small ends, or a shape with large middle ends and small ends.
  • the second spacing continuously changes or intermittently changes; the width of the data lines continuously changes or intermittently changes.
  • the data line is similar to the scan line.
  • the data line can adopt any of the wavy shapes in Figure 8-10.
  • the two sides of the data line in the extending direction are wavy, the peaks of the two sides are oppositely arranged, and the valleys are relatively arranged; the third connection part is formed at the opposite side of the data line, and the third connection part is the data line and the switch
  • the settings of the data line and the scan line are similar. For details, see the settings of the scan line.
  • the scan lines and data lines on the display panel adopt any of the wavy shapes shown in FIGS. 8-10, which can ensure that the light passes through different width positions in the extension direction of the data line and the scan line alignment And at different gaps between adjacent traces, diffraction stripes with different positions can be formed, thereby reducing the diffraction effect, so that the photosensitive device placed under the display panel can work normally.
  • the shape of the first electrode may be a circle as shown in FIG. 11, or an ellipse as shown in FIG. 12, or a dumbbell shape as shown in FIG. 13, and the first electrode may be composed of other Curves with different radii of curvature.
  • obstacles such as slits, small holes, or discs
  • the distribution of diffraction fringes is affected by the size of obstacles, such as the width of the slit and the size of the small holes.
  • the positions of the diffraction fringes at the positions with the same width are consistent, so that a more obvious diffraction effect will occur. .
  • By changing the shape of the anode to a circle, ellipse or dumbbell it can be ensured that when light passes through the anode layer, diffraction stripes with different positions and diffusion directions can be generated at different width positions of the anode, thereby weakening the diffraction effect, and thus ensuring the camera
  • the graphics obtained by taking pictures have higher definition.
  • the sides of the projection of the opening on the pixel-defining layer on the substrate are not parallel to each other and each side is a curve, that is, the opening has a varying width in all directions and different directions of diffraction and diffusion at the same position, when external light passes
  • diffraction stripes with different positions and diffusion directions can be generated at different width positions, so that no more obvious diffraction effect is generated, thereby ensuring that the photosensitive element disposed under the display panel can work normally.
  • the openings on the conventional pixel-defining layer are all set to be rectangular or square according to the pixel size.
  • the rectangular opening is taken as an example for illustration. Since the rectangular shape has two sets of parallel sides, the rectangular shape has the same width in the length and width directions. Therefore, when external light passes through the opening, diffraction stripes with the same position and the same diffusion direction are generated at different positions in the length direction or the width direction, so that a significant diffraction effect occurs, making the photosensitive element located below the display panel unable to normal work.
  • the display panel in this embodiment can solve this problem well and ensure that the photosensitive element under the display panel can work normally.
  • the curve adopted by each side of the projection of the opening on the substrate may be at least one of a circle, an ellipse, and other curves with varying curvatures.
  • Each side of the opening is a curve, so when the light passes through the opening, the generated diffraction fringes will not spread in one direction, but in the direction of 360 degrees, which makes the diffraction extremely insignificant and has a better diffraction improvement effect. .
  • the projection graphic unit with an opening on the substrate is circular, elliptical, dumbbell-shaped or wavy, similar to the shape of the first electrode, please refer to the first electrode, see FIGS. 11-13.
  • the shape of the opening projected on the substrate can be determined according to the shape of the corresponding light emitting structure.
  • the number can be determined according to the aspect ratio of the light emitting structure.
  • the projection shape of the opening on the substrate may also be an axisymmetric structure, thereby ensuring that each pixel on the entire display panel has a uniform opening ratio, which does not affect the final display effect. Referring to FIG.
  • the corresponding light-emitting structure shape is a rectangle or a square with an aspect ratio of less than 1.5
  • the symmetry axis of the opening projection corresponds to the symmetry axis of the corresponding light-emitting structure.
  • the diameter of the circle in the projection is smaller than the minimum width of the light emitting structure.
  • the diameter of the projected circle can be determined according to the shape of the light emitting structure and the comprehensive aperture ratio. Since the determination process can be determined by a conventional method of determining the size of the opening, it will not be repeated here.
  • the length-to-width ratio of the light-emitting structure corresponding to the opening is between 1.5 and 2.5.
  • the projection is formed by two circular shapes communicating with each other to form a dumbbell shape.
  • the two circles are arranged along the length direction of the corresponding light emitting structure.
  • the length-to-width ratio of the light-emitting structure corresponding to the opening is greater than 2.5.
  • the projection is a wavy shape formed by three or more circles communicating with each other. Three or more circles are arranged along the length direction of the corresponding light emitting structure.
  • a connection portion is also formed in the projection.
  • the connection part is an arc, that is, the intersection of more than three circles is connected by an arc, so as to ensure that the light can diffuse in all directions when passing through the connection part, thereby improving the diffraction effect.
  • the projection When the length-to-width ratio of the light emitting structure corresponding to the opening is equal to 1.5, the projection may be a circle, or a dumbbell shape in which two circles communicate with each other. When the length-to-width ratio of the light emitting structure corresponding to the opening is equal to 2.5, the projection may be a dumbbell shape in which two circles communicate with each other, or a wave shape in which three circles communicate with each other, as shown in FIG. 14.
  • the shape of the sub-pixel is the same as the shape of the opening, that is, the sub-pixel is circular, elliptical, or dumbbell-shaped.
  • the shape design rules of the anode can also refer to the design rules of the openings, which can further improve the diffraction effect.
  • the anode can also adopt a conventional rectangular shape design.
  • This embodiment also provides a method for manufacturing a display panel, as shown in FIG. 15, including steps S1-S3.
  • Step S1 providing a substrate, the substrate includes a plurality of sub-pixel regions, each sub-pixel region includes a first region and a second region, and the first region and the second region are both provided with a substrate.
  • the substrate 1 may be a flexible substrate, such as a PI film, or a rigid substrate, such as a transparent substrate such as a glass substrate, a quartz substrate, or a plastic substrate, to improve the transparency of the device.
  • a flexible substrate such as a PI film
  • a rigid substrate such as a transparent substrate such as a glass substrate, a quartz substrate, or a plastic substrate, to improve the transparency of the device.
  • Step S2 preparing a buffer layer and a pixel circuit layer on the substrate in the first area.
  • the first insulating material may be deposited on the entire substrate by chemical vapor deposition, and the first insulating material may be patterned to form a buffer layer, and the buffer layer covers the substrate in the first region.
  • a pixel circuit layer is prepared on the buffer layer.
  • Step S3 A first electrode is prepared on the substrate in the second area, and the first electrode is in direct contact with the substrate in the second area.
  • each sub-pixel area is divided into a first area and a second area.
  • the first area is provided with a substrate, a buffer layer, and a pixel circuit layer.
  • the second area is provided with a substrate and a first One electrode, no inorganic film layer is provided between the first electrode and the substrate, which reduces the coverage area of the inorganic film layer and improves the transparency of the display panel.
  • the method further includes: preparing a lead on the substrate, and providing an inorganic film layer as an inter-lead insulating layer at the overlapping position of the lead projections, the inorganic film layer including a gate insulating layer, an inter-layer insulating layer, and a buffer layer
  • At least one of the lead wires includes at least one of a scan line, a data line, and a connection line in the pixel circuit. The coverage area of the inorganic film layer is reduced, and the display effect is improved.
  • This embodiment only uses data lines and scan lines as an example for description. Specifically, the data lines are prepared on the substrate, the inorganic film layer covering the entire substrate is prepared after the data lines are prepared, and the scan lines are prepared on the inorganic film layer. Finally, The inorganic film layer covering the entire substrate is removed, and only the inorganic film layer where the projection of the data line and the scanning line overlap is retained.
  • This embodiment is for illustrative purposes only, and is not limited thereto. The inorganic film layer can be removed or retained according to actual needs.
  • the second region includes a light-emitting region and a non-light-emitting region
  • the step S2 of preparing the buffer layer and the pixel circuit layer on the substrate of the first region includes the following steps S21-S6.
  • the buffer layer is made of a first insulating material, and a first insulating material covering the entire substrate is prepared on the substrate.
  • a chemical vapor deposition method is used to prepare the first insulating material covering the entire substrate.
  • other methods can also be used to form
  • the first insulating material covering the entire substrate is not limited in this embodiment.
  • the first insulating material may be an inorganic insulating material such as silicon oxide or silicon nitride, which is not limited thereto.
  • S22 preparing an active layer on the first insulating material.
  • a plasma enhanced chemical vapor deposition (PECVD) process may be used to prepare active materials (such as polycrystalline silicon and single crystal silicon), and the active materials cover the entire substrate; of course, in other embodiments, other methods may also be used
  • the active material is formed, which is not limited in this embodiment. After the active material is formed, the active material is patterned to form an active layer.
  • PECVD plasma enhanced chemical vapor deposition
  • the gate insulating layer is made of a second insulating material, and the second insulating material can be made by a chemical vapor deposition method, and the second insulating material covers the entire substrate.
  • the second insulating material may be an inorganic insulating material such as silicon oxide or silicon nitride; in other alternative embodiments, the second insulating material may also be composed of other inorganic insulating materials, which is not limited in this embodiment.
  • a gate layer is prepared on the second insulating material. Specifically, a second conductive material covering the entire substrate may be prepared on the second insulating material by sputtering, and the second conductive material may be patterned to form a gate layer. Of course, other methods may also be used to form the gate layer, which is not limited in this embodiment.
  • the second conductive material may be a metal material or a transparent conductive material, such as ITO or IZO; of course, in other embodiments, it may also be other conductive materials, which can be reasonably set as required.
  • a third insulating material is prepared on the gate layer, and the third insulating material covers the first region and the second region of the substrate.
  • the interlayer insulating layer is made of a third insulating material, and a third insulating material covering the entire substrate is formed on the gate layer.
  • the entire surface of the third insulating material can be obtained by chemical vapor deposition, of course, it can also be used
  • the third insulating material is formed by other methods, which is not limited in this embodiment.
  • the third insulating material may be an inorganic insulating material such as silicon oxide or silicon nitride; of course, in other alternative embodiments, the third insulating material may also be composed of other inorganic insulating materials, which is not limited in this embodiment.
  • the first insulating material, the second insulating material, and the third insulating material of the light emitting area are removed through the first mask. Specifically, the first insulating material, the second insulating material, and the third insulating material located on the light emitting area are removed through the first mask to expose the substrate of the light emitting area, so that the light emitting area is not covered with the buffer layer and the gate insulating layer And an interlayer insulating layer, so as to prepare a first electrode on the light emitting region later.
  • the first mask plate may be an ILD mask plate, and there is no need to add a new mask plate, and only a pattern needs to be added to the existing ILD mask plate to remove the first insulating material and the second insulating material in the light emitting area As well as the third insulating material, no additional process steps are required, and the production cost is low.
  • the method further includes: removing the first insulating material, the second insulating material, and the third insulating material of the non-light emitting area through the first mask plate so that the non-light emitting area is not covered with the inorganic film layer, further Reducing the area covered by the inorganic film layer improves the transparency of the display panel, and the overall consistency of the screen is better.
  • the non-light emitting area includes a lead area for setting the lead and a non-functional area.
  • the method further includes: removing the first insulating material, the second insulating material, and the second insulating material on the non-functional area through the first mask plate Three insulating materials, so that the inorganic film layer is not covered on the non-functional area, only the lead area is covered with the inorganic film layer, which further reduces the coverage area of the inorganic film layer, improves the transparency of the display panel, and the overall consistency of the screen is better.
  • step S2 includes steps S27-S29 in the step of preparing the buffer layer and the pixel circuit layer on the substrate in the first area.
  • Step S27 prepare a first lead layer on the substrate.
  • the first lead layer may be made of a transparent conductive material, such as ITO.
  • Step S28 forming a planarizing material on the substrate.
  • the planarizing material may use a material commonly used in the art to prepare a planarizing layer.
  • Step S29 Remove the planarizing material above the first lead layer through the second mask to expose the first lead layer.
  • the second mask plate may be a PLA mask plate. There is no need to add a new mask plate, and only a pattern needs to be added to the existing PLA mask plate to remove the planarization layer above the first lead layer, so that the first One lead layer is exposed, which facilitates the formation of the second lead layer on the first lead layer in the future, without additional process steps, and the production cost is low.
  • step S3 includes the steps S31-S32 in the step of preparing the first electrode on the substrate in the second region.
  • Step S31 A first conductive material is prepared on the substrate, and the first conductive material covers the first area and the second area.
  • the first conductive material covering the entire substrate may be prepared on the substrate by sputtering.
  • other methods may be used to form the first conductive material covering the entire substrate, which is not limited in this embodiment.
  • the first conductive material may be a transparent conductive material, such as ITO; of course, in other embodiments, it may also be other conductive materials, which can be reasonably set as required.
  • Step S32 pattern the first conductive material to form a first electrode and a second lead layer covering the first lead layer.
  • the first electrode and the second lead layer can be formed at the same time through a mask, the preparation process is simple, the process flow is saved, and the production cost is reduced.
  • the method further includes steps S5-S6.
  • Step S5 preparing a pixel defining layer on the substrate, the pixel defining layer exposing the first electrode.
  • the pixel defining layer has multiple openings, and the first electrodes are exposed at the openings.
  • Step S6 preparing a light-emitting structure layer, a second electrode, and an encapsulation layer that are sequentially stacked on the first electrode.
  • a light emitting structure layer may be formed on the first electrode exposed at the opening by evaporation
  • a second electrode may be prepared on the light emitting structure layer
  • an encapsulation layer may be prepared.
  • the first area includes a pixel circuit area and a non-pixel circuit area
  • the method further includes: patterning the encapsulation layer to remove the inorganic film layer and the organic layer on the non-pixel circuit area and/or the non-light emitting area ⁇ Film layer.
  • the inorganic and organic film layers on the non-pixel circuit area and the inorganic and organic film layers on the non-light emitting area can be simultaneously removed by patterning, so that the inorganic film layer and the organic film layer on the substrate cover only the necessary areas to increase the display
  • the transparency of the panel reduces the light absorption of these films, increases the light intensity reaching the photosensitive element placed under the display panel, and enhances the photographic effect.
  • This embodiment also provides a display screen, which includes at least a first display area and a second display area, each of which is used to display a dynamic or static picture.
  • a photosensitive device may be provided below the first display area;
  • the display area is provided with a display panel as mentioned in any of the above embodiments, and the display panel provided in the second display area is a PMOLED display panel or an AMOLED display panel. Since the first display area adopts the display panel in the foregoing embodiment, it has higher transparency and better overall consistency of the display screen.
  • the display screen includes a first display area 161 and a second display area 162, both of which are used to display static or dynamic pictures.
  • a display area 161 uses the display panel mentioned in any of the above embodiments, and the first display area 161 is located at the upper part of the display screen.
  • the display screen may further include three or more display areas, such as three display areas (first display area, second display area, and third display area), and the first display area uses
  • the display panel mentioned in any of the above embodiments, which display panel is used in the second display area and the third display area, which is not limited in this embodiment, may be a PMOLED display panel or an AMOLED display panel, of course
  • the display panel in this embodiment may also be used.
  • This embodiment also provides a display terminal, including the above display screen covered on the device body.
  • the above display terminal may be a product or component with a display function such as a mobile phone, a tablet, a TV, a display, a palmtop computer, an iPod, a digital camera, a navigator, and the like.
  • the display terminal includes a device body 810 and a display screen 820.
  • the display screen 820 is provided on the device body 810 and connected to the device body 810.
  • the display screen 820 may use the display screen in any of the foregoing embodiments to display static or dynamic images.
  • the device body 810 may be provided with a slotted area 812 and a non-slotted area 814.
  • the slotted area 812 photosensitive devices such as a camera 930, a light sensor, and a light sensor may be provided.
  • the display panel of the first display area of the display screen 820 is bonded together corresponding to the slotted area 812, so that the above-mentioned photosensitive devices such as the camera 930 and the light sensor can transmit external light through the first display area Collection and other operations.
  • the display panel in the first display area has higher transparency, the overall consistency of the screen is improved; at the same time, the above display panel can also effectively improve the diffraction phenomenon generated by the external light transmitting through the first display area, which can effectively improve
  • the quality of the image captured by the camera 930 on the display terminal can avoid the distortion of the captured image due to diffraction, and can also improve the accuracy and sensitivity of the light sensor to sense external light.

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Abstract

一种显示面板、显示面板制备方法、显示屏及显示终端，其中，显示面板包括：基板（1），所述基板（1）包括多个子像素区域，每一个子像素区域包括第一区域（11）和第二区域（12），所述第一区域（11）设置有基板（1）、缓冲层（4）和像素电路层（2），所述第二区域（12）设置有所述基板（1）；第一电极（3），设置在所述每一个子像素区域的所述第二区域（12）上并且与所述基板（1）直接接触。上述显示面板，将每一个子像素区域划分为第一区域（11）和第二区域（12），第一区域（11）上设置有基板（1）、缓冲层（4）、像素电路层（2），第二区域（12）上设置有基板（1）以及与基板（1）直接接触设置的第一电极（3），第一电极（3）与基板（1）之间不设置无机膜层，减少了无机膜层的覆盖面积，提高了显示面板的透明度。

Description

显示面板、显示面板制备方法、显示屏及显示终端 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板、显示面板制备方法、显示屏及显示终端。
背景技术
随着显示终端的快速发展，用户对屏幕占比的要求越来越高，全面屏显示受到业界越来越多的关注。由于屏幕上方需要安装摄像头、传感器、听筒等元件，因此屏幕上方通常会预留一部分区域用于安装上述元件，例如苹果手机iphoneX的前刘海区域，影响了屏幕的整体一致性。
发明内容
基于此，针对上述技术问题，提供一种显示面板、显示面板制备方法、显示屏以及显示终端。
本申请第一方面，提供一种显示面板，包括：基板，所述基板包括多个子像素区域，每一个子像素区域包括第一区域和第二区域，所述第一区域设置有所述基板、缓冲层和像素电路层，所述第二区域设置有所述基板；第一电极，设置在所述每一个子像素区域的所述第二区域上，并且所述第一电极与所述基板直接接触。
本申请第二方面，提供一种显示面板制备方法，包括如下步骤：提供基板，所述基板包括多个子像素区域，每一个子像素区域包括第一区域和第二区域，所述第一区域和所述第二区域均设置有所述基板；在所述第一区域的所述基板上制备缓冲层和像素电路层；在所述第二区域的所述基板上制备第一电极，所述第一电极与所述第二区域的所述基板直接接触。
本申请第三方面，提供一种显示屏，至少包括第一显示区和第二显示区，各显示区均用于显示动态或静态画面，所述第一显示区下方可设置感光器件；其中，在所述第一显示区设置有如本申请第一方面任一所述的显示面板，所述第二显示区设置的显示面板为PMOLED(passive matrix organic light-emitting diode)显示面板或AMOLED(active matrix organic light-emitting diode)显示面板。
本申请技术方案，具有如下优点：
本申请提供的显示面板，包括：基板，所述基板包括多个子像素区域，每一个子像素区域包括第一区域和第二区域，所述第一区域设置有所述基板、缓冲层和像素电路层，所述第二区域设置有所述基板；第一电极，设置在所述每一个子像素区域的所述第二区域上并且所述第一电极与所述基板直接接触。上述显示面板，将每一个子像素区域划分为第一区域和第二区域，第一区域上设置有基板、缓冲层、像素电路层，第二区域上设置有基板以及与基板直接接触设置的第一电极，第一电极与基板之间不设置无机膜层，减少了无机膜层的覆盖面积，提高了显示面板的透明度。
附图说明
为了更清楚地说明本申请具体实施方式的技术方案，下面将对具体实施方式描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例中显示面板的一个具体示例的剖视图；
图2为本申请实施例中显示面板的一个具体示例的俯视图；
图3为现有技术中的显示面板的一个具体示例的示意图；
图4为本申请实施例中显示面板的另一个具体示例的示意图；
图5为本申请实施例中显示面板的另一个具体示例的示意图；
图6为本申请实施例中显示面板的另一个具体示例的示意图；
图7为本申请实施例中显示面板的另一个具体示例的示意图；
图8为本申请实施例中显示面板的扫描线的一个具体示例的示意图；
图9为本申请实施例中显示面板的扫描线的另一个具体示例的示意图；
图10为本申请实施例中显示面板的扫描线的另一个具体示例的示意图；
图11为本申请实施例中显示面板的第一电极的一个具体示例的示意图；
图12为本申请实施例中显示面板的第一电极的另一个具体示例的示意图；
图13为本申请实施例中显示面板的第一电极的另一个具体示例的示意图；
图14为本申请实施例中显示面板的像素限定层开口的一个具体示例的示意图；
图15为本申请实施例中显示面板制备方法的一个具体示例的流程图；
图16为本申请实施例中显示屏的一个具体示例的示意图；
图17为本申请实施例中显示终端的一个具体示例的示意图；
图18为本申请实施例中设备本体的结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中 的实施例，本领域技术人员在没有付出创造性劳动的前提下所获得的所有其他实施例，都属于本申请保护的范围。
为了实现全面屏显示，需要显示屏达到一定的透明度，以满足摄像头等对透明度的需求。但是，由于构成像素电路中无机膜层和有机膜层的材料透光率并非100％，上述这些膜层使得显示屏的透明度降低，影响了显示屏的整体一致性。
基于此，本申请提供了一种显示面板，在显示面板中的非必要区域上不覆盖无机膜层和有机膜层，减少无机膜层和有机膜层等膜层的覆盖面积，提高了显示面板的透明度，很好地解决了上述问题。
图1为一实施例中显示面板的剖视图，图2为一实施例中显示面板的俯视图，如图1和图2所示，显示面板包括：基板1，该基板包括多个子像素区域，每一个子像素区域包括第一区域11和第二区域12，第一区域11设置有基板1、缓冲层4和像素电路层2，第二区域12设置有基板1、第一电极3，在第二区域12，第一电极3与基板1直接接触。
在一实施例中，具体地，在每一个子像素区域的第一区域11上设置像素电路层，在所述每一个子像素区域的第二区域12上设置与之对应的第一电极3，第一电极3与像素电路2为一一对应关系。
在一实施例中，基板1可以是衬底；基板1可以是柔性基板，如PI薄膜等；也可以是刚性基板，如玻璃基板、石英基板或者塑料基板等透明基板，以提高器件的透明度。
上述显示面板，将每一个子像素区域划分为第一区域和第二区域，第一区域上设置有基板、缓冲层、像素电路层，第二区域上设置有基板以及与基板直接接触设置的第一电极，第一电极与基板之间不设置无机膜层，减少了无机膜层的覆盖面积，提高了显示面板的透明度。
在一实施例中，如图1所示，像素电路层2可包括依次设置于第一区域基板上的有源层21、栅极绝缘层22、栅极层23以及层间绝缘层24。栅极绝缘层和层间绝缘层仅设置于第一区域上，其具体形成过程可以为：缓冲层、栅极绝缘层和层间绝缘层采用常规工艺制备成覆盖基板的一整面的膜层，如采用旋涂或者沉积方式形成整面的缓冲层、栅极绝缘层和层间绝缘层，这三层无机膜层均覆盖在第一区域和第二区域上，如图3所示；在制备完ILD层(层间绝缘层)之后，通过掩膜板对无机膜层进行图案化，具体为在无机膜层进行光刻胶图形化、涂布、曝光、显影工步，利用干刻(刻蚀气体为CF4)，或干刻+湿刻(刻蚀药液为BOE)进行无机膜层(缓冲层、栅极绝缘层GI和层间绝缘层ILD)刻蚀，去除第二区域第一电极位置上的无机膜层。当然，在其它实施例中，也可在制备完一层无机膜层后便去除第二区域第一电极位置上的该层无机膜层，还可以是在制作时直接在第一电极位置以外的区域上形成无机膜层；具体实现方式可根据实际情况合理选择，本实施例对此不作任何限制。
基板上还可设置有屏蔽层(Barrier)(图中未示出)，此种情况下，为了实现更高的透明度，第一电极位置上不覆盖屏蔽层。此外，现有工艺中在形成基板的过程中会同时在基板上方制备好两层屏蔽(Barrier)层，第一屏蔽层111通常为氮化硅材料制成，第二屏蔽层112通常为氧化硅材料，如图4所示。此种情况下，可采用本实施例中的上述去除方法将第二区域设置第一电极位置上的两层屏蔽层部分去除或者全部去除，以进一步提高显示面板的透明度。
在一实施例中，该显示面板还包括：设置于基板1上的引线，引线包括扫描线、数据线以及像素电路层中的连接线中的至少一个；设置于引线在基板上的投影交叠处的无机膜层，无机膜层包括栅极绝缘层、层间绝缘层以及缓冲层中的至少一个。
具体地，在本实施例中，引线包括扫描线、数据线以及像素电路层中的连接线，引线可设置在第一区域，还可设置在第二区域，可根据实际需要合理设 置。
在一实施例中，第二区域12包括发光区域和非发光区域，设置于发光区域的第一电极3，设置于非发光区域的引线4与基板直接接触，和/或位于非发光区域的引线和基板1之间设置有无机膜层。具体地，发光区域上不覆盖无机膜层，在发光区域上设置第一电极3；非发光区域上可以是全部覆盖无机膜层，也可以是全部不覆盖无机膜层，还可以是的部分覆盖无机膜层。
具体地，在非发光区域全部不覆盖无机膜层时，位于非发光区域上的引线直接与基板接触设置。在非发光区域全部覆盖无机膜层时，位于非发光区域上的引线与基板之间设置有无机膜层，引线与基板之间的无机膜层根据引线制备的前后步骤的不同而不同，例如，引线是在制备完缓冲层之后栅极绝缘层之前形成的，此种情况下，引线与基板之间的无机膜层为缓冲层，又例如，引线是在制备完栅极绝缘层之后、层间绝缘层之前形成的，此种情况下，引线与基板之间的无机膜层为缓冲层和栅极绝缘层。
在一实施例中，非发光区域包括用于设置引线的引线区域以及非功能区域，非功能区域的上方不覆盖无机膜层。无机膜层不覆盖非功能区域，尽可能多地去除无机膜层，减少无机膜层的覆盖面积，提高了显示面板的透明度。
在一实施例中，像素电路层设置在基板的第一区域上，第一电极、扫描线和数据线设置在基板的第二区域上，仅第一区域上覆盖在制备像素电路过程中所形成的无机膜层(如缓冲层、栅极绝缘层CI、层间绝缘层ILD)，第二区域上仅在引线在所述基板上的投影交叠处设置有无机膜层。在显示面板中的非必要覆盖区域上不覆盖无机膜层和有机膜层，减少膜层的覆盖面积，提高了显示面板的透明度。
在一实施例中，为了最大化地提高显示面板的整体透明度，第一电极和引线均采用透明导电材料制成，透明导电材料的透光率大于90％，从而使得整个 显示面板的透光率较佳，显示面板的透明度更高。当然，在其它可替换实施例中，透明导电材料的透光率还可设置为其它数值，如80％或者95％，具体数值可根据实际需要合理设置。
具体地，透明导电材料可为铟锡氧化物(ITO)，也可为铟锌氧化物(IZO)、或者掺杂银的氧化铟锡(Ag+ITO)、或者掺杂银的氧化铟锌(Ag+IZO)。由于ITO工艺成熟、成本低，导电材料优选为铟锌氧化物。进一步的，为了在保证高透光率的基础上，减小各导电走线的电阻，透明导电材料采用铝掺杂氧化锌、掺杂银的ITO或者掺杂银的IZO等材料。
在其它可替换实施例中，透明导电材料也可采用其它材料，根据实际需要合理设置即可，本实施例对此不作限定。在一可替换实施例中，第一电极、数据线以及扫描线中的至少一个采用透明导电材料制成。
在一实施例中，引线包括层叠的第一引线层和第二引线层，第二引线层位于第一引线层的上方。由于透明导电材料(如ITO)的电阻比金属导线的电阻大，为了实现良好的电特性，通常会采用金属线作为连接线、数据线以及扫描线等引线，这些金属走线会严重影响显示面板的透明度；然而，本实施例中采用由透明导电材料构成的两层引线层的叠层设置可显著降低透明导电材料的电阻，在保证电特性的基础上实现了高透明度。当然，在其它可替换实施例中，还可将扫描线、数据线以及像素电路层中的连接线中的任意一个或者任意两个设置为叠层结构，具体可根据实际需要合理设置。
本实施例中的叠层结构包括两层，但并不以此为限；图5为叠层结构的一个具体示例的剖视图，如图5所示，基板1、第一引线层102、第二引线层101、第一引线层下方的无机膜层103、以及第一引线层上层的有机膜层104，具体形成过程也可采用上述去除无机膜层的方法去除有机膜层，区别仅在于选用不同的刻蚀气体或刻蚀液，本实施例在此不再赘述。当然，在其它实施例中，更多 层的叠层(如三层或者三层以上)也落入本实施例的保护范围内。例如，第一引线层为数据线时，第一引线层为透明引线层，第一引线层下方的无机膜层103包括GI-Si xO y、BL-Si xO y/Si xN y，第一引线层上层的有机膜层104可包括CI-Si xN y、ILD-Si xO y/Si xN y、平坦化-透明/非透明有机胶。
在一实施例中，第二引线层与第一电极层在同一工艺步骤中形成。具体地，第一电极层为OLED(organic light-emitting diode)的阳极，也采用透明导电材料制成。第一引线层中的数据线、扫描线均采用ITO材料制备而成；由于在第一引线层的上方不覆盖其它膜层，在后续工艺中制备第一电极层时，在第一引线层的上方再形成一层ITO，对该层ITO图案化，形成第一电极层和覆盖第一引线层的第二引线层。在制备第一电极层的过程中形成第二引线层，节省工艺步骤、降低生产成本。当然，在其它可替换实施例中，第二引线层还可在一单独的步骤中形成，根据需要合理设置即可。
在上述显示面板的基础上，该显示面板还包括：平坦化层，设置于基板上并露出引线，以便后续在露出引线的位置上形成叠层设置的引线，降低引线的电阻，提高电特性。
在上述显示面板的基础上，该显示面板还包括：设置于第一电极上的像素限定层，设置于基板上并露出第一电极，具体地，像素限定层上具有多个开口，开口处露出第一电极，以便后续在该位置上制备发光结构层。
在上述显示面板的基础上，该显示面板还包括：设置于第一电极上的依次层叠的发光结构层、第二电极以及封装层；第一区域包括像素电路区域和非像素电路区域，像素电路区域上和/或发光区域上覆盖无机膜层及有机膜层。
在一实施例中，具体地，在像素限定层的开口内设置有发光结构层，以形成多个子像素，子像素与第一电极一一对应；设置于发光结构层上方的第二电极，第二电极与发光结构层一一对应；设置于第二电极和像素电路层上的封装 层。第一区域包括像素电路区域和非像素电路区域，像素电路区域上覆盖无机膜层和有机膜层，非像素区域上不覆盖无机膜层和有机膜层；并且第二区域包括发光区域和非发光区域，发光区域上无机膜层及有机膜层，非发光区域上不覆盖无机膜层和有机膜层。将第一区域分为两部分(像素电路区域和非像素电路区域)，像素电路区域上形成像素电路层，在非像素电路区域上不覆盖有机膜层和无机膜层；同样地，将第二区域也分为两部分(发光区域和非发光区域)，发光区域上形成第一电极，在非发光区域上不覆盖有机膜层和无机膜层。最大程度地减少无机膜层和有机膜层的覆盖面积，提高了显示面板的透明度。并且还能够减少这些膜层对光的吸收，提高了光的透过率，当感光元件(如摄像头)设置于显示面板的下方时，能够增大进光量，增加到达感光元件的光强，增强拍照效果，使得拍得的图像效果更优。
封装后，对非发光区域和非像素电路区域进行图形化，刻蚀掉相应位置的封装层、平坦化层、氧化硅和氮化硅绝缘层，得到的结构如图6和图7所示。如图6和7所示，基板1上的像素电路2、发光结构层63以及封装层61，作为该结构的一个应用场景的示意图，感光器件62设置于基板的下方，基板上的非发光区和非像素电路区上不覆盖无机膜层和有机膜层，无机膜层和有机膜层的覆盖面积进一步减少，提高了显示面板的透明度，并且还能够减少这些膜层对光的吸收，增加了到达感光器件的光强，增强拍照效果。
在一实施例中，无机膜层包括层间绝缘层、栅极绝缘层、缓冲层以及平坦化层，上述这些无机膜层的材料可为氧化硅或者氮化硅，还可为氧化硅和氮化硅的混合；当然，在其它实施例中，无机膜层还可包括上述中的部分膜层或者除上述之外的其它膜层，根据需要合理确定即可，本实施例对此不作任何限制。
在一实施例中，有机膜层包括封装层、像素限定层、平坦化层。
在一实施例中，扫描线与栅极连接，为了简化工艺步骤，节省工艺流程， 扫描线与栅极可在同一工艺步骤中形成。在一可选实施例中，具体可为扫描线和栅极均采用ITO材料构成，则在制作过程中可先制备一层ITO，通过第一掩膜板对ITO进行图案化同时形成扫描线和栅极。在一可替换实施例中，扫描线也可设置在栅极的上方或下方，这样便需要分别形成栅极和扫描线。
在一实施例中，为了简化工艺步骤，节省工艺流程，数据线与第一电极在同一工艺步骤中形成。在一可选实施例中，具体可为数据线与第一电极均采用ITO材料构成，制备一整面的ITO，通过第二掩膜板对ITO进行图案化同时形成数据线和第一电极；在一可替换实施例中，当数据线和第一电极材料不相同时，也可分别形成数据线和第一电极。
在一实施例中，扫描线在其延伸方向上的两条边为波浪形，并且数据线在其延伸方向上的两条边也为波浪形，波浪形的数据线和扫描线能够产生具有不同位置以及扩散方向的衍射条纹，从而弱化衍射效应，进而确保摄像头设置在该显示面板下方时，拍照得到的图形具有较高的清晰度。
在一可选实施例中，由于扫描线为波浪形，相邻的扫描线间具有第一间距，第一间距连续变化或间断变化；扫描线的宽度连续变化或间断变化。宽度连续变化是指扫描线上任意两个相邻位置处的宽度不相同。图8中，扫描线7的延伸方向为其长度方向。扫描线7在延伸方向上宽度连续变化。而宽度间断变化是指：扫描线7上部分区域内相邻两个位置的宽度相同，而部分区域内相邻两个位置的宽度不相同。在本实施例中，多个扫描线7在基板上规则排布，因此，相邻两个扫描线7之间的间隙在平行于扫描线7的延伸方向上也呈现为连续变化或者间断变化。扫描线7在延伸方向上，无论其宽度是连续变化还是间断变化都可以为周期性变化。
扫描线7在延伸方向上的两条边均为波浪形，两条边的波峰相对设置，且波谷也相对设置。如图8所示，延伸方向上的两条边的波峰T相对设置且波谷 B相对设置，同一个扫描线7波峰之间的宽度为W1，同一个扫描线7波谷之间的宽度为W2，相邻两个扫描线7波峰之间的间距为D1，相邻两个扫描线7波谷之间的间距为D2。本实施例中，两条边均由同一圆弧形边相连而成。在其它的实施例中，两条边也可以均由同一椭圆形边相连而成，如图9所示。通过将扫描线7的两边设置成由圆弧形或者椭圆形形成的波浪形，可以确保扫描线7上产生的衍射条纹能够向不同方向扩散，进而不会产生较为明显的衍射效应。
在一可选实施例中，在波浪形的扫描线的波谷相对处形成有第二连接部，第二连接部可为直线或者曲线。如图10所示，第二连接部为条状，第二连接部为扫描线7与开关器件电连接区域，即开关器件的控制端连接至第二连接部的位置。在其它的实施例中，第二连接部也可以采用其他不规则结构，如中间小两端大的形状，或者采用中间大两端小的形状。
在一实施例中，由于数据线为波浪形，相邻的数据线间具有第二间距，第二间距连续变化或间断变化；数据线的宽度连续变化或间断变化。数据线与扫描线类似，详见扫描线的具体描述，在此不再赘述。数据线可采用图8-10中的任意一种波浪形。数据线在延伸方向上的两条边均为波浪形，两条边的波峰相对设置，且波谷相对设置；数据线的波谷相对处形成有第三连接部，第三连接部为数据线与开关器件电连接区域，数据线与扫描线的设置类似，详见扫描线的设置。
在一实施例中，显示面板上的扫描线、数据线采用图8-10中的任意一种波浪形，可以确保在数据线和扫描线走线的延伸方向上，光线经过在不同宽度位置处以及相邻走线的不同间隙处时能够形成具有不同位置的衍射条纹，进而减弱衍射效应，以使得放置于显示面板下方的感光器件能够正常工作。
在一实施例中，第一电极的形状可为如图11所示的圆形，或者如图12所示的椭圆形，或者如图13所示的哑铃形，第一电极还可以由其它各处具有不同 曲率半径的曲线构成。由于光在穿过狭缝、小孔或者圆盘之类的障碍物时，会发生不同程度的弯散传播，从而偏离原来的直线传播，这种现象称之为衍射。衍射过程中，衍射条纹的分布会受到障碍物尺寸，例如狭缝的宽度、小孔的尺寸等的影响，具有相同宽度的位置处产生的衍射条纹的位置一致，从而会出现较为明显的衍射效应。通过将阳极形状改为圆形、椭圆形或者哑铃形，可以确保光线经过阳极层时，在阳极的不同宽度位置处能够产生具有不同位置以及扩散方向的衍射条纹，从而弱化衍射效应，进而确保摄像头设置在该显示面板下方时，拍照得到的图形具有较高的清晰度。
像素限定层上的开口在基板上的投影的各边互不平行且各边均为曲线，也即开口在各个方向上均具有变化的宽度且在同一位置具有不同衍射扩散方向，当外部光线经过该开口时，在不同宽度位置上能够产生具有不同位置和扩散方向的衍射条纹，进而不会产生较为明显的衍射效应，从而可以确保设置于该显示面板下方的感光元件能够正常工作。
传统的像素限定层上的开口均根据像素大小设置成长方形或者正方形。以长方形的开口为例进行说明，由于长方形存在两组相互平行的边，从而使得其在长度和宽度方向上均具有相同的宽度。因此，当外部光线经过该开口时，在长度方向或者宽度方向的不同位置均产生具有相同位置且扩散方向一致的衍射条纹，从而会出现明显的衍射效应，使得位于该显示面板下方的感光元件无法正常工作。本实施例中的显示面板可以很好的解决该问题，确保显示面板下方的感光元件能够正常工作。
在一实施例中，开口在基板上的投影的各边采用的曲线可以为圆形、椭圆形和其它具有变化曲率的曲线中的至少一种。开口的各边为曲线，因此，当光线经过开口时，产生的衍射条纹不会朝着一个方向扩散，而是朝着360度方向扩散，从而使得衍射极不明显，具有较佳的衍射改善效果。
在一实施例中，开口在基板上的投影图形单元为圆形、椭圆形或者哑铃形或者波浪形，与第一电极的形状类似，请参照第一电极，参见图11-13，在此不再赘述。开口在基板上投影的形状可以根据对应的发光结构的形状来确定。例如，可以根据发光结构的长宽比来确定个数。在一实施例中，开口在基板上的投影形状还可以为轴对称结构，从而确保整个显示面板上的各像素具有一致的开口率，不会影响最终的显示效果。参见图9，开口在基板上的投影为一个圆形时，对应的发光结构形状为长宽比小于1.5的长方形或者正方形，开口投影的对称轴与相应发光结构的对称轴对应。投影中的圆的直径小于发光结构的最小宽度。具体地，投影的圆的直径可以根据发光结构的形状并综合开口率进行确定。由于确定过程可以采用传统的确定开口的尺寸的方法来确定，此处不赘述。
开口对应的发光结构的长宽比在1.5到2.5之间。此时，投影为由两个圆形彼此连通形成哑铃形。两个圆分别沿对应的发光结构的长度方向排布。在一实施例中，两个圆之间有连接部，连接部的两边均为曲线，而确保光线经过连接部时，也能够向各个方向扩散，从而改善衍射效果。
开口对应的发光结构的长宽比大于2.5。此时，投影为由三个以上圆形彼此连通而成的波浪形。三个以上圆形分别沿对应的发光结构的长度方向排布。在一实施例中，投影中还形成有连接部。连接部为弧线，也即三个以上圆形的相交处采用弧线连接，从而确保光线经过连接部时，也能够向各个方向扩散，从而改善衍射效果。
当开口对应的发光结构的长宽比等于1.5时，投影可以为一个圆形，也可以为两个圆形彼此连通的哑铃形。当开口对应的发光结构的长宽比等于2.5时，投影可以为两个圆形彼此连通的哑铃形，也可以为由三个圆形彼此连通的波浪形，如图14所示。
在一可选实施例中，参见图11-13，子像素的形状与上述开口的形状相同，即子像素为圆形、椭圆形或者哑铃形。进一步的，阳极的形状设计规则也可参照上述开口的设计规则，可以进一步改善衍射效果。当然，阳极也可采用常规的矩形形状设计。
本实施例还提供了一种显示面板制备方法，如图15所示，包括步骤S1-S3。
步骤S1：提供基板，基板包括多个子像素区域，每一个子像素区域包括第一区域和第二区域，第一区域和第二区域均设置有基板。
本实施例中，基板1可以是柔性基板，如PI薄膜等；也可以是刚性基板，如玻璃基板、石英基板或者塑料基板等透明基板，以提高器件的透明度。
步骤S2：在第一区域的基板上制备缓冲层和像素电路层。
在一实施例中，具体地，可在整个基板上通过化学气相沉积第一绝缘材料，对第一绝缘材料进行图形化形成缓冲层，缓冲层覆盖在第一区域的基板上。在缓冲层上制备像素电路层。
步骤S3：在第二区域的基板上制备第一电极，第一电极与第二区域的基板直接接触。
该方法，通过将每一个子像素区域划分为第一区域和第二区域，第一区域上设置有基板、缓冲层、像素电路层，第二区域上设置有基板以及与基板直接接触设置的第一电极，第一电极与基板之间不设置无机膜层，减少了无机膜层的覆盖面积，提高了显示面板的透明度。
在一实施例中，该方法还包括：在基板上制备引线，在引线投影交叠处设置作为引线间绝缘层的无机膜层，无机膜层包括栅极绝缘层、层间绝缘层以及缓冲层中的至少一个，引线包括扫描线、数据线以及像素电路中的连接线中的至少一个。减少无机膜层的覆盖面积，提高了显示效果。
本实施例仅以数据线和扫描线为例进行说明，具体地，在基板上制备数据线，制备完数据线之后制备覆盖整个基板的无机膜层，在无机膜层上制备扫描线，最后，对覆盖整个基板的无机膜层进行去除，仅保留数据线和扫描线投影交叠处的无机膜层。本实施例仅作示例性说明，并不以此为限，无机膜层可根据实际需要进行去除或保留。
在一实施例中，第二区域包括发光区域和非发光区域，步骤S2在第一区域的基板上制备缓冲层和像素电路层的步骤中，包括如下步骤S21-S6。
S21：在基板上制备第一绝缘材料，第一绝缘材料覆盖基板的第一区域和第二区域。具体地，缓冲层采用第一绝缘材料制成，在基板上制备覆盖整个基板的第一绝缘材料，如采用化学气相沉积法制备覆盖整个基板的第一绝缘材料，当然，也可采用其它方法形成覆盖整个基板的第一绝缘材料，本实施例对此不作限定。在本实施例中，第一绝缘材料可为氧化硅或者氮化硅等无机绝缘材料，并不以此为限。
S22：在第一绝缘材料上制备有源层。具体地，可以采用等离子增强化学气相淀积(PECVD)工艺制备有源材料(例如多晶硅、单晶硅)，有源材料覆盖在整个基板上；当然，在其它实施例中，还可采用其它方法形成有源材料，本实施例对此不作限定。形成有源材料后，对有源材料图形化形成有源层。
S23：在有源层上制备第二绝缘材料，第二绝缘材料覆盖基板的第一区域和第二区域。具体地，栅极绝缘层采用第二绝缘材料制成，可采用化学气相沉积法制得第二绝缘材料，第二绝缘材料覆盖在整个基板上。当然，也可采用其它方法形成第二绝缘材料，本实施例对此不作限定。具体地，第二绝缘材料可为氧化硅或者氮化硅等无机绝缘材料；在其它可替换实施例中，第二绝缘材料也可采用其它无机绝缘材料构成，本实施例对此不作限定。
S24：在第二绝缘材料上制备栅极层。具体地，可通过溅射的方式在第二绝 缘材料上制备覆盖整个基板的第二导电材料，对第二导电材料图形化形成栅极层。当然，也可采用其它方法形成栅极层，本实施例对此不作限定。
在一实施例中，第二导电材料可以是金属材料或透明导电材料，如ITO或IZO；当然，在其它实施例中，也可以是其它导电材料，根据需要合理设置即可。
S25：在栅极层上制备第三绝缘材料，第三绝缘材料覆盖基板的第一区域和第二区域。具体地，层间绝缘层采用第三绝缘材料制成，在栅极层上形成覆盖整个基板的第三绝缘材料，可采用化学气相沉积法制得整面的第三绝缘材料，当然，也可采用其它方法形成第三绝缘材料，本实施例对此不作限定。第三绝缘材料可为氧化硅或者氮化硅等无机绝缘材料；当然，在其它可替换实施例中，第三绝缘材料也可采用其它无机绝缘材料构成，本实施例对此不作限定。
S26：通过第一掩膜板去除发光区域的第一绝缘材料、第二绝缘材料以及第三绝缘材料。具体地，通过第一掩膜板去除位于发光区域上的第一绝缘材料、第二绝缘材料以及第三绝缘材料以暴露出发光区域的基板，使得发光区域上不覆盖缓冲层、栅极绝缘层和层间绝缘层，以便后续在发光区域上制备第一电极。
具体地，第一掩膜板可以是ILD掩膜板，无需增加新的掩膜板，只需在现有的ILD掩膜板上增加图形，去除发光区域的第一绝缘材料、第二绝缘材料以及第三绝缘材料，无需增加额外的工艺步骤，生产成本低。
在一实施例中，该方法还包括：通过第一掩膜板去除非发光区域的第一绝缘材料、第二绝缘材料以及第三绝缘材料，使得非发光区域上也不覆盖无机膜层，进一步减少无机膜层的覆盖该面积，提高了显示面板的透明度，屏幕的整体一致性更好。
在一实施例中，非发光区域包括用于设置引线的引线区域以及非功能区域，该方法还包括：通过第一掩膜板去除非功能区域上的第一绝缘材料、第二绝缘材料以及第三绝缘材料，使得非功能区域上不覆盖无机膜层，仅引线区域覆盖 无机膜层，进一步减少无机膜层的覆盖面积，提高了显示面板的透明度，屏幕的整体一致性更好。
在一实施例中，步骤S2在第一区域的基板上制备缓冲层和像素电路层的步骤中，还包括步骤S27-S29。
步骤S27：在基板上制备第一引线层。具体地，第一引线层可采用透明导电材料制成，例如ITO。
步骤S28：在基板上形成平坦化材料。具体地，平坦化材料可采用本领域常用制备平坦化层的材料。
步骤S29：通过第二掩膜板去除第一引线层上方的平坦化材料，以露出第一引线层。具体地，第二掩膜板可以是PLA掩膜板，无需增加新的掩膜板，只需在现有的PLA掩膜板上增加图形，去除第一引线层上方的平坦化层，使得第一引线层暴露出来，便于在后续在第一引线层上形成第二引线层，无需增加额外的工艺步骤，生产成本低。
在一实施例中，步骤S3在第二区域的基板上制备第一电极的步骤中，包括步骤S31-S32。
步骤S31：在基板上制备第一导电材料，第一导电材料覆盖第一区域和第二区域。具体地，可通过溅射的方式在基板上制备覆盖整个基板的第一导电材料。当然，也可采用其它方法形成覆盖整个基板的第一导电材料，本实施例对此不作限定。
在一实施例中，第一导电材料可以是透明导电材料，如ITO；当然，在其它实施例中，也可以是其它导电材料，根据需要合理设置即可。
步骤S32：对第一导电材料图案化，形成第一电极和覆盖第一引线层的第二引线层。通过一次掩膜便可同时形成第一电极和第二引线层，制备过程简单、 节省工艺流程，降低生产成本。
在一实施例中，步骤S3在第二区域的基板上制备第一电极的步骤之后，该方法还包括步骤S5-S6。
步骤S5：在基板上制备像素限定层，像素限定层露出第一电极。具体地，像素限定层上具有多个开口，开口处露出第一电极。
步骤S6：在第一电极上制备依次层叠的发光结构层、第二电极以及封装层。在一实施例中，具体地，可通过蒸镀的方式在开口处露出的第一电极上形成发光结构层，在发光结构层上制备第二电极，之后再制备封装层。
在一实施例中，第一区域包括像素电路区域和非像素电路区域，该方法还包括：对封装层进行图案化，去除非像素电路区域上和/或非发光区域上的无机膜层及有机膜层。
具体地，可通过图案化同时去除非像素电路区域上的无机和有机膜层，以及非发光区域上的无机和有机膜层，使得基板上无机膜层和有机膜层仅覆盖必要区域，增加显示面板的透明度，减少这些膜层的光吸收，增加到达放置于显示面板下方的感光元件的光强，增强拍照效果。
本实施例还提供一种显示屏，至少包括第一显示区和第二显示区，各显示区均用于显示动态或静态画面，第一显示区下方可设置感光器件；其中，在第一显示区设置有如上述任一实施例中所提及的显示面板，第二显示区设置的显示面板为PMOLED显示面板或AMOLED显示面板。由于第一显示区采用了前述实施例中的显示面板，因此具有较高的透明度、显示屏的整体一致性较好。
在一实施例中，如图16所示，显示屏包括第一显示区161和第二显示区162，第一显示区161和第二显示区162均用于显示静态或者动态画面，其中，第一显示区161采用上述任一实施例中所提及的显示面板，第一显示区161位 于显示屏的上部。
在一可替换实施例中，显示屏还可包括三个甚至更多个显示区域，如包括三个显示区域(第一显示区域、第二显示区域和第三显示区域)，第一显示区域采用上述任一实施例中所提及的显示面板，第二显示区域和第三显示区域采用何种显示面板，本实施例对此不作限定，可以为PMOLED显示面板，也可为AMOLED显示面板，当然，也可以采用本实施例中的显示面板。
本实施例还提供一种显示终端，包括覆盖在设备本体上的上述显示屏。上述显示终端可以为手机、平板、电视机、显示器、掌上电脑、ipod、数码相机、导航仪等具有显示功能的产品或者部件。
图17为一实施例中的显示终端的结构示意图，该显示终端包括设备本体810和显示屏820。显示屏820设置在设备本体810上，且与该设备本体810相互连接。其中，显示屏820可以采用前述任一实施例中的显示屏，用以显示静态或者动态画面。
图18为一实施例中的设备本体810的结构示意图。在本实施例中，设备本体810上可设有开槽区812和非开槽区814。在开槽区812中可设置有诸如摄像头930以及光传感器、光线感应器等感光器件。此时，显示屏820的第一显示区的显示面板对应于开槽区812贴合在一起，以使得上述的诸如摄像头930及光传感器等感光器件能够透过该第一显示区对外部光线进行采集等操作。由于第一显示区中的显示面板具有较高的透明度，提高了屏幕的整体一致性；同时，上述显示面板还能够有效改善外部光线透射该第一显示区所产生的衍射现象，从而可有效提升显示终端上摄像头930所拍摄图像的质量，避免因衍射而导致所拍摄的图像失真，同时也能提升光传感器感测外部光线的精准度和敏感度。
虽然结合附图描述了本申请的实施例，但是本领域技术人员可以在不脱离 本申请的精神和范围的情况下作出各种修改和变型，这样的修改和变型均落入由所附权利要求所限定的范围之内。

Claims (20)

  1. 一种显示面板，包括：
    基板，所述基板包括多个子像素区域，每一个子像素区域包括第一区域和第二区域，所述第一区域设置有所述基板、缓冲层和像素电路层，所述第二区域设置有所述基板；
    第一电极，设置在所述每一个子像素区域的所述第二区域上，并且与所述基板直接接触。
  2. 根据权利要求1所述的显示面板，还包括：
    设置于所述基板上的引线，所述引线包括扫描线、数据线以及像素电路层中的连接线中的至少一个；
    设置于所述引线在所述基板上的投影交叠处的无机膜层，所述无机膜层包括栅极绝缘层、层间绝缘层以及缓冲层中的至少一个。
  3. 根据权利要求2所述的显示面板，其中，
    所述第二区域包括发光区域和非发光区域，设置于所述发光区域的所述第一电极，设置于所述非发光区域的所述引线与所述基板直接接触，和/或位于所述非发光区域的所述引线和所述基板之间设置有所述无机膜层。
  4. 根据权利要求3所述的显示面板，其中，所述非发光区域包括用于设置所述引线的引线区域以及非功能区域，所述非功能区域的上方不覆盖所述无机膜层。
  5. 根据权利要求2所述的显示面板，还包括：
    平坦化层，设置于所述基板上并露出所述引线。
  6. 根据权利要求2所述的显示面板，其中，所述引线包括层叠的第一引线层和第二引线层。
  7. 根据权利要求6所述的显示面板，其中，所述引线采用透明导电材料制成，所述透明导电材料的透光率大于90％，
    所述透明导电材料为氧化铟锡、氧化铟锌、掺杂银的氧化铟锡或者掺杂银的氧化铟锌。
  8. 根据权利要求2所述的显示面板，还包括：
    像素限定层，设置于所述基板上并露出所述第一电极。
  9. 根据权利要求8所述的显示面板，还包括：
    设置于所述第一电极上的依次层叠的发光结构层、第二电极以及封装层；
    所述第一区域包括像素电路区域和非像素电路区域，所述像素电路区域上和/或所述发光区域上覆盖所述无机膜层及有机膜层。
  10. 一种显示面板制备方法，包括如下步骤：
    提供基板，所述基板包括多个子像素区域，每一个子像素区域包括第一区域和第二区域，所述第一区域和所述第二区域均设置有所述基板；
    在所述第一区域的所述基板上制备缓冲层和像素电路层；
    在所述第二区域的所述基板上制备第一电极，所述第一电极与所述第二区域的所述基板直接接触。
  11. 根据权利要求10所述的显示面板制备方法，还包括：
    在所述基板上制备引线，在所述引线在所述基板上的投影交叠处设置作为 所述引线间绝缘层的无机膜层，所述无机膜层包括栅极绝缘层、层间绝缘层以及缓冲层中的至少一个，所述引线包括扫描线、数据线以及像素电路中的连接线中的至少一个。
  12. 根据权利要求10所述的显示面板制备方法，其中，所述第二区域包括发光区域和非发光区域，所述在所述第一区域的基板上制备缓冲层和像素电路层的步骤中，包括：
    在所述基板上制备第一绝缘材料，所述第一绝缘材料覆盖所述基板的第一区域和第二区域；
    在所述第一绝缘材料上制备有源层；
    在所述有源层上制备第二绝缘材料，所述第二绝缘材料覆盖所述基板的第一区域和第二区域；
    在所述第二绝缘材料上制备栅极层；
    在所述栅极层上制备第三绝缘材料，所述第三绝缘材料覆盖所述基板的第一区域和第二区域；
    通过第一掩膜板去除所述发光区域的所述第一绝缘材料、第二绝缘材料以及第三绝缘材料。
  13. 根据权利要求12所述的显示面板制备方法，其中，
    所述方法还包括：通过第一掩膜板去除所述非发光区域的所述第一绝缘材料、第二绝缘材料以及第三绝缘材料。
  14. 根据权利要求12所述的显示面板制备方法，其中，所述非发光区域包括用于设置引线的引线区域以及非功能区域，所述方法还包括：通过第一掩膜板去除所述非功能区域上的所述第一绝缘材料、第二绝缘材料以及第三绝缘材 料。
  15. 根据权利要求10所述的显示面板制备方法，其中，所述在所述第一区域的基板上制备缓冲层和像素电路层的步骤中，还包括：
    在所述基板上制备第一引线层；
    在所述基板上形成平坦化材料；
    通过第二掩膜板去除所述第一引线层上方的所述平坦化材料，以露出所述第一引线层。
  16. 根据权利要求15所述的显示面板制备方法，其中，所述在所述第二区域的基板上制备第一电极的步骤中，包括：
    在基板上制备第一导电材料，所述第一导电材料覆盖所述第一区域和第二区域；
    对所述第一导电材料图案化，形成所述第一电极和覆盖所述第一引线层的第二引线层。
  17. 根据权利要求10所述的显示面板制备方法，其中，在所述第二区域的基板上制备第一电极的步骤之后，还包括：
    在所述基板上制备像素限定层，所述像素限定层露出所述第一电极。
  18. 根据权利要求17所述的显示面板制备方法，其中，在所述基板上制备像素限定层的步骤之后，还包括：
    在所述第一电极上制备依次层叠的发光结构层、第二电极以及封装层。
  19. 根据权利要求18所述的显示面板制备方法，其中，所述第一区域包括像素电路区域和非像素电路区域，所述方法还包括：
    对所述封装层进行图案化，去除所述非像素电路区域上和/或所述非发光区域上的无机膜层及有机膜层。
  20. 一种显示屏，
    至少包括第一显示区和第二显示区，各显示区均用于显示动态或静态画面，所述第一显示区下方设置感光器件；
    其中，在所述第一显示区设置有如权利要求1-9任意一项所述的显示面板，所述第二显示区设置的显示面板为PMOLED显示面板或AMOLED显示面板。
PCT/CN2019/090869 2018-12-29 2019-06-12 显示面板、显示面板制备方法、显示屏及显示终端 WO2020133938A1 (zh)

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