WO2020098143A1 - Oled 显示面板及其制作方法 - Google Patents

Oled 显示面板及其制作方法 Download PDF

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Publication number
WO2020098143A1
WO2020098143A1 PCT/CN2019/071321 CN2019071321W WO2020098143A1 WO 2020098143 A1 WO2020098143 A1 WO 2020098143A1 CN 2019071321 W CN2019071321 W CN 2019071321W WO 2020098143 A1 WO2020098143 A1 WO 2020098143A1
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Prior art keywords
layer
display panel
oled display
heat preservation
film transistor
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PCT/CN2019/071321
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English (en)
French (fr)
Inventor
丁武
李松杉
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武汉华星光电半导体显示技术有限公司
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Priority to US16/319,474 priority Critical patent/US10861919B2/en
Publication of WO2020098143A1 publication Critical patent/WO2020098143A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8794—Arrangements for heating and cooling
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour

Definitions

  • the present application relates to a display technology, in particular to an OLED display panel and a manufacturing method thereof.
  • LTPS-TFT Low Temperature Polycrystalline Silicon Thin Film Transistors
  • three buffer layers of SiN x film and SiO x are deposited on the substrate continuously Film layer, amorphous silicon film (a-Si), and then using excimer laser annealing (Excimer Laser Anneal, ELA) to anneal and crystallize a-Si to form LTPS, but the formed LTPS grain size is more uniform Poor, with many grain boundaries, resulting in poor electrical uniformity of Switch TFT and Drive TFT, especially seriously affecting the electrical uniformity of Drive TFT, while Driver TFT directly affects organic light-emitting diodes (Organic Light Emitting Diode, OLED) The light emitting characteristics of the device seriously affect the yield of LTPS.
  • OLED Organic Light Emitting Diode
  • the embodiments of the present application provide an OLED display panel and a manufacturing method thereof to solve the problem of poor uniformity of LTPS grain size and many grain boundaries in the existing LTPS-TFT, resulting in Drive The technical problem of poor electrical uniformity of TFT.
  • An embodiment of the present application provides an OLED display panel, which includes:
  • the substrate includes a setting area for setting a driving thin film transistor that functions to drive the OLED device to emit light and a storage capacitor corresponding to the driving thin film transistor;
  • the heat preservation layer including at least one heat preservation sub-layer, is formed on the installation area;
  • a buffer layer is formed on the substrate and covers the thermal insulation layer
  • the driving thin film transistor is formed at a position of the buffer layer corresponding to the setting area;
  • the storage capacitor is formed at a position of the buffer layer corresponding to the setting area
  • both the driving thin film transistor and the storage capacitor include a polysilicon layer formed on the buffer layer, and the heat preservation layer is used to improve the thermal stability of amorphous silicon when crystallizing into a polysilicon layer;
  • the heat preservation layer includes a first heat preservation sub-layer provided on the substrate and a second heat preservation sub-layer provided on the first heat preservation sub-layer, the material of the first heat preservation sub-layer and the second heat preservation The material of the sublayer is different;
  • the thickness of the thermal insulation layer is between 50 nm and 100 nm.
  • the buffer layer includes a first buffer sublayer covering the second thermal insulation sublayer, wherein the material of the first buffer sublayer is SiN x , and the first thermal insulation The material of the sub-layer is SiO x , and the material of the second thermal insulation sub-layer is SiO x N y .
  • the content of oxygen element is greater than the content of nitrogen element.
  • the material of the heat preservation layer is one or a combination of SiO x and SiO x N y .
  • the OLED display panel includes a switching thin film transistor functioning as a switch, and the heat preservation layer is provided on an area of the substrate corresponding to the switching thin film transistor.
  • An embodiment of the present application further provides an OLED display panel, which includes:
  • the substrate includes a setting area for setting a driving thin film transistor that functions to drive the OLED device to emit light and a storage capacitor corresponding to the driving thin film transistor;
  • the heat preservation layer including at least one heat preservation sub-layer, is formed on the installation area;
  • a buffer layer is formed on the substrate and covers the thermal insulation layer
  • the driving thin film transistor is formed at a position of the buffer layer corresponding to the setting area;
  • the storage capacitor is formed at a position of the buffer layer corresponding to the setting area
  • the driving thin film transistor and the storage capacitor both include a polysilicon layer formed on the buffer layer, and the heat preservation layer is used to improve the thermal stability of amorphous silicon when crystallized into a polysilicon layer.
  • the heat preservation layer is composed of a heat preservation sub-layer.
  • the heat preservation layer includes a first heat preservation sub-layer provided on the substrate and a second heat preservation sub-layer provided on the first heat preservation sub-layer, so The material of the first thermal insulation sublayer is different from the material of the second thermal insulation sublayer.
  • the buffer layer includes a first buffer sublayer covering the second thermal insulation sublayer, wherein the material of the first buffer sublayer is SiN x , The material of the first insulation sublayer is SiO x , and the material of the second insulation sublayer is SiO x N y .
  • the content of oxygen element is greater than the content of nitrogen element.
  • the OLED display panel includes a switching thin-film transistor that functions as a switch, and the thermal insulation layer is provided on an area of the substrate corresponding to the switching thin-film transistor.
  • the thickness of the heat preservation layer is between 50 nm and 100 nm.
  • the material of the heat preservation layer is one or a combination of SiO x and SiO x N y .
  • the application also relates to a method for manufacturing an OLED display panel, which includes:
  • S1 providing a substrate, the substrate including a setting area for setting a driving thin film transistor for driving the OLED device to emit light and a storage capacitor corresponding to the driving thin film transistor;
  • S5 forming an insulating layer, a gate metal layer, an interlayer dielectric layer, a source-drain metal layer, and a passivation layer on the polysilicon layer in order to form the driving thin film transistor and the storage capacitor;
  • S6 A flat layer, an anode, a pixel definition layer, and a compartment are sequentially formed on the passivation layer.
  • the step of S2 includes:
  • S21 depositing a layer of SiO x film on the substrate by plasma-enhanced chemical vapor deposition method, and forming a first thermal insulation sub-layer using a photolithography process;
  • a plasma enhanced chemical vapor deposition method is used to deposit a SiO x N y film on the first thermal insulation sublayer, and a second thermal insulation sublayer is formed by a photolithography process.
  • step S21 the SiO x film is deposited at a temperature between 400 ° C and 440 ° C, an energy between 10 kw and 20 kw, and a pressure between 40 Pa and Between 80 Pa, reflecting the gas ratio of SiH 4 and N 2 O gas is between 1: 100 and 1:50, and reflecting time is between 20s and 40s;
  • the temperature is between 400 ° C and 440 ° C
  • the energy is between 10kw and 20kw
  • the pressure is between 40Pa and 80Pa
  • the gas ratio is between 1: 100: 80 and 1: 100: 120, reflecting the time between 20s and 40s.
  • the content of oxygen element is greater than the content of nitrogen element.
  • the thickness of the heat preservation layer is between 50 nm and 100 nm.
  • the OLED display panel and its manufacturing method of the present application prevent the heat of the amorphous silicon film layer from crystallizing during the annealing process by providing a thermal insulation layer on the installation area on the substrate
  • the rapid dissipation makes the amorphous silicon film at the driving thin film transistor and the storage capacitor fully crystallize, increasing the crystal grains and improving the uniformity of the crystal grains, thereby improving the electrical uniformity of the driving thin film transistors, thereby improving the OLED device Uniformity of luminescence; solves the technical problem of poor uniformity of LTPS grain size and many grain boundaries in the existing LTPS-TFT, resulting in poor electrical uniformity of Drive TFT.
  • FIG. 1 is a schematic structural diagram of a first embodiment of an OLED display panel of this application.
  • FIG. 2 is a schematic structural diagram of a second embodiment of an OLED display panel of this application.
  • FIG. 3 is a schematic structural diagram of a third embodiment of an OLED display panel of this application.
  • FIG. 5 is a flowchart of step S2 of an embodiment of the method for manufacturing an OLED display panel of the present application.
  • FIG. 1 is a schematic structural diagram of a first embodiment of an OLED display panel of the present application.
  • the OLED display panel 100 of the first embodiment includes a substrate 11, a thermal insulation layer 12, a buffer layer 13, a driving thin film transistor 1a, a storage capacitor 1b, a flat layer 15, an anode 16, a pixel definition layer 17, and a spacer 18.
  • the substrate 11 includes a setting area 11a for setting a driving thin film transistor 1a that functions to drive the OLED device to emit light and a storage capacitor 1b corresponding to the driving thin film transistor 1a.
  • the thermal insulation layer 12 includes at least one thermal insulation sub-layer, and the thermal insulation layer 12 is formed on the installation area 11a.
  • the buffer layer 13 is formed on the substrate 11 and covers the thermal insulation layer 12.
  • the driving thin film transistor 1a is formed at a position of the buffer layer 13 corresponding to the setting region 11a.
  • the storage capacitor 1b is formed at a position of the buffer layer 13 corresponding to the setting area 11a.
  • both the driving thin film transistor 1a and the storage capacitor 1b include a polysilicon layer 141 formed on the buffer layer 13, and the thermal insulation layer 12 is used to improve the thermal stability of amorphous silicon when crystallized into the polysilicon layer 141.
  • the heat preservation layer 12 is provided in the installation area 11a on the substrate 11 to prevent the rapid heat loss of the amorphous silicon film layer during crystallization during the annealing process, so that the thin film transistor 1a and the storage capacitor 1b are driven
  • the amorphous silicon film layer 141 is fully crystallized, increasing the crystal grains and improving the uniformity of the crystal grains, thereby improving the electrical uniformity of the driving thin film transistor 1a, thereby improving the uniformity of light emission of the OLED device.
  • the OLED display panel 100 of the first embodiment includes a polysilicon layer 141 provided on the buffer layer 13, an insulating layer 142 provided on the polysilicon layer, a gate metal layer 143 provided on the insulating layer 142, and a gate metal An interlayer dielectric layer 144 on the layer, a source-drain metal layer 145 provided on the interlayer dielectric layer 144, a passivation layer 146 provided on the source-drain metal layer 145, and a flat layer provided on the passivation layer 146 15 and the anode 16, the pixel definition layer 17, and the spacer 18 provided on the flat layer 15 in this order.
  • the polysilicon layer 141 includes an active layer corresponding to the driving thin film transistor 1a and a lower electrode plate constituting the storage capacitor 1b.
  • the lower electrode plate is formed by ion doping the polysilicon layer 141.
  • the gate metal layer 143 includes an upper electrode plate 1431 corresponding to the lower electrode plate and a gate 1432 corresponding to the driving thin film transistor 1a.
  • the source-drain electrodes of the active layer, the gate electrode 1432, and the source-drain metal layer 145 constitute the driving thin film transistor 1a, and the upper electrode plate 1431 and the lower electrode plate constitute the storage capacitor 1b.
  • the thermal insulation layer 12 is composed of a thermal insulation sublayer.
  • the thickness of the thermal insulation layer 12 is between 50 nm and 100 nm. This arrangement, on the one hand, ensures the thermal insulation effect of the thermal insulation layer 12, on the other hand, it does not affect the stress relationship between the adjacent layers, and improves the stability between the thermal insulation layer 12 and the adjacent layer.
  • the material of the thermal insulation layer is one or a combination of SiO x and SiO x N y . It should be noted that x and y both represent numerical values, such as 1, 2 and so on.
  • the manufacturing process of the polysilicon layer of the first embodiment is: depositing a layer of SiO x film on the substrate 11 (the thermal insulation layer 12 of the first embodiment is described by taking SiO x material as an example), and then set up by a photolithography process An insulating layer 12 is formed on the region 11a; then, a buffer layer 13 and an amorphous silicon layer are sequentially formed on the insulating layer 12; finally, the amorphous silicon layer is subjected to excimer laser annealing to crystallize the amorphous silicon layer to form a polycrystalline silicon layer 141.
  • the thermal insulation layer 12 plays a role in preventing the rapid loss of heat, so that the polycrystalline silicon layer corresponding to the thermal insulation layer 12 is fully crystallized, which improves the uniformity of the crystal grains and further improves the driving of the thin film transistor 1a Sexual homogeneity.
  • FIG. 2 is a schematic structural diagram of a second embodiment of an OLED display panel of the present application.
  • the OLED display panel 200 of the second embodiment includes a substrate 21, an insulating layer 22, a buffer layer 23, a driving thin film transistor 2a, a storage capacitor 2b, a flat layer 25, an anode 26, a pixel definition layer 27, and a spacer 28.
  • the difference between this second embodiment and the first embodiment lies in:
  • the thermal insulation layer 22 includes a first thermal insulation sublayer 221 disposed on the substrate 21 and a second thermal insulation sublayer 222 disposed on the first thermal insulation sublayer 221, the material of the first thermal insulation sublayer 221 and the second thermal insulation sublayer 222 The material is different.
  • the buffer layer 23 includes a first buffer sublayer 231 covering the second thermal insulation sublayer 222 and a second buffer sublayer 232 disposed on the first buffer sublayer 231.
  • the material of the first buffer sublayer 231 is SiN x
  • the material of the second buffer sublayer 232 is SiO x
  • the material of the first insulation sublayer 221 is SiO x
  • the material of the second insulation sublayer 222 is SiO x N y .
  • the second thermal insulation sublayer 222 is disposed between the first thermal insulation sublayer 221 and the first buffer sublayer 231, which improves the stability of the combination of the thermal insulation layer 22 and the buffer layer 23. Because the stress of the first buffer sub-layer 231 and the stress of the first thermal insulation sub-layer 221 are relatively large, and the stress of the second thermal insulation sub-layer 222 is between the two, it acts as a transition and improves the thermal insulation layer 22 Stability in combination with buffer layer 23.
  • the content of oxygen element is greater than the content of nitrogen element.
  • the second thermal insulation sublayer 222 is formed by plasma enhanced chemical vapor deposition (PECVD) deposition, and the oxygen content and nitrogen content can be adjusted by adjusting the flow ratio and energy of the film-forming gas.
  • PECVD plasma enhanced chemical vapor deposition
  • the difference between the third embodiment and the first embodiment is:
  • the OLED display panel 300 further includes a switching thin film transistor 3a functioning as a switch, and a thermal insulation layer 32 is provided on an area of the substrate 31 corresponding to the switching thin film transistor 3a.
  • the thermal insulation layer 32 is provided at the same time directly under the driving thin film transistor 3a, and the storage capacitor 3b and the switching thin film transistor 3c, which improves the uniformity of the crystal grains of the three polysilicon layers 341 during crystallization, and improves the driving thin film transistor 3a and the switching film
  • the electrical uniformity of the transistor 3c further improves the uniformity of light emission of the OLED device.
  • the switching thin film transistor 3c includes an active layer of the polysilicon layer 341, a gate of the gate metal layer 343, and a source-drain electrode of the source-drain metal layer 345.
  • the present application also relates to a method for manufacturing an OLED display panel, which includes:
  • S1 providing a substrate, the substrate including a setting area for setting a driving thin film transistor for driving the OLED device to emit light and a storage capacitor corresponding to the driving thin film transistor;
  • S5 forming an insulating layer, a gate metal layer, an interlayer dielectric layer, a source-drain metal layer, and a passivation layer on the polysilicon layer in order to form the driving thin film transistor and the storage capacitor;
  • S6 A flat layer, an anode, a pixel definition layer, and a compartment are sequentially formed on the passivation layer.
  • the heat preservation layer plays a role in preventing rapid heat loss, so that the thin film transistor and The amorphous silicon layer of the storage capacitor is sufficiently crystallized to form larger crystal grains, and the uniformity of the crystal grains is improved, the electrical uniformity of the driving thin film transistor is improved, and the uniformity of light emission of the OLED light emitting device is improved.
  • the step of S2 includes:
  • S21 depositing a layer of SiO x film on the substrate by plasma-enhanced chemical vapor deposition method, and forming a first thermal insulation sub-layer using a photolithography process;
  • a plasma enhanced chemical vapor deposition method is used to deposit a SiO x N y film on the first thermal insulation sublayer, and a second thermal insulation sublayer is formed by a photolithography process.
  • step S21 the SiO x film is deposited at a temperature between 400 ° C and 440 ° C, an energy between 10kw and 20kw, and a pressure between 40Pa Between ⁇ 80 Pa, the gas ratio of SiH 4 to N 2 O is between 1: 100 and 1:50, and the reflection time is between 20s and 40s.
  • the temperature is between 400 ° C and 440 ° C
  • the energy is between 10kw and 20kw
  • the pressure is between 40Pa and 80Pa
  • the gas ratio is between 1: 100: 80 and 1: 100: 120, reflecting the time between 20s and 40s.
  • the content of oxygen element is greater than the content of nitrogen element.
  • the thickness of the heat preservation layer is between 50 nm and 100 nm.
  • the structure of the OLED display panel manufactured by the method for manufacturing an OLED display panel of this embodiment is the same as the structure of the second embodiment of the OLED display panel of the present application.
  • the OLED display panel and its manufacturing method of the present application prevent the heat of the amorphous silicon film layer from crystallizing during the annealing process by providing a thermal insulation layer on the installation area on the substrate
  • the rapid dissipation makes the amorphous silicon film at the driving thin film transistor and the storage capacitor fully crystallize, increasing the crystal grains and improving the uniformity of the crystal grains, thereby improving the electrical uniformity of the driving thin film transistors, thereby improving the OLED device Uniformity of luminescence; solves the technical problem of poor uniformity of LTPS grain size and many grain boundaries in the existing LTPS-TFT, resulting in poor electrical uniformity of Drive TFT.

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Abstract

一种OLED显示面板(100)及其制作方法，其包括基板(11)、保温层(12)、缓冲层(13)、驱动薄膜晶体管(1a)和存储电容(1b)，基板包括设置区域(11a)；保温层(12)形成在设置区域(11a)上；缓冲层(13)形成在基板(11)上；驱动薄膜晶体管(1a)和存储电容(1b)均形成在缓冲层(13)对应于设置区域(11a)的位置上。通过保温层(12)的设置，防止了非晶硅膜层在退火处理进行结晶时热量快速散失。

Description

OLED显示面板及其制作方法 技术领域
本申请涉及一种显示技术，特别涉及一种OLED显示面板及其制作方法。
 背景技术
随着在传统的低温多晶硅薄膜晶体管（Low Temperature Polycrystalline Silicon Thin Film Transistors ，LTPS-TFT）的制作过程中，在基板上会连续沉积3个膜层的缓冲层，分别为SiN x膜层、SiO x膜层、非晶硅膜层（amorphous silicon，a-Si），接着利用准分子镭射退火（Excimer Laser Anneal，ELA）对a-Si进行退火结晶形成LTPS，但是形成的LTPS晶粒大小均一性较差，晶界较多，导致开关薄膜晶体管（Switch TFT）和驱动薄膜晶体管（Drive TFT）的电性均一性较差，尤其严重影响Drive TFT的电性均一性，而Driver TFT直接影响有机发光二极管（Organic Light Emitting Diode，OLED）器件的发光特性，进行严重影响LTPS的良率。
技术问题
本申请实施例提供一种OLED显示面板及其制作方法，以解决现有的LTPS-TFT中LTPS晶粒大小均一性差，晶界较多，导致Drive TFT的电性均一性差的技术问题。
 技术解决方案
本申请实施例提供一种OLED显示面板，其包括：
基板，包括用于设置起到驱动OLED器件发光作用的驱动薄膜晶体管和所述驱动薄膜晶体管对应的存储电容的设置区域；
保温层，包括至少一层保温子层，形成在所述设置区域上；
缓冲层，形成在所述基板上，并覆盖所述保温层；
所述驱动薄膜晶体管，形成在所述缓冲层对应于所述设置区域的位置上；以及
所述存储电容，形成在所述缓冲层对应于所述设置区域的位置上；
其中，所述驱动薄膜晶体管和存储电容均包括形成在所述缓冲层上的多晶硅层，所述保温层用于提高非晶硅在结晶成为多晶硅层时热量的稳定性；
所述保温层包括设置在所述基板上的第一保温子层和设置在所述第一保温子层上的第二保温子层，所述第一保温子层的材质和所述第二保温子层的材质不同；
所述保温层的厚度介于50纳米~100纳米之间。
在本申请的OLED显示面板中，所述缓冲层包括覆盖所述第二保温子层上的第一缓冲子层，其中，所述第一缓冲子层的材质是SiN x，所述第一保温子层的材质是SiO x，所述第二保温子层的材质是SiO xN y。
在本申请的OLED显示面板中，在所述第二保温子层中，氧元素的含量大于氮元素的含量。
在本申请的OLED显示面板中，所述保温层的材料是SiO x和SiO xN y中的一种或两种材料的组合。
在本申请的OLED显示面板中，所述OLED显示面板包括起到开关作用的开关薄膜晶体管，所述基板对应于所述开关薄膜晶体管的区域上设置有所述保温层。
本申请实施例还提供一种OLED显示面板，其包括：
基板，包括用于设置起到驱动OLED器件发光作用的驱动薄膜晶体管和所述驱动薄膜晶体管对应的存储电容的设置区域；
保温层，包括至少一层保温子层，形成在所述设置区域上；
缓冲层，形成在所述基板上，并覆盖所述保温层；
所述驱动薄膜晶体管，形成在所述缓冲层对应于所述设置区域的位置上；以及
所述存储电容，形成在所述缓冲层对应于所述设置区域的位置上；
其中，所述驱动薄膜晶体管和存储电容均包括形成在所述缓冲层上的多晶硅层，所述保温层用于提高非晶硅在结晶成为多晶硅层时热量的稳定性。
在本申请的OLED显示面板的第一实施例中，所述保温层由一层保温子层构成。
在本申请的OLED显示面板的第二实施例中，所述保温层包括设置在所述基板上的第一保温子层和设置在所述第一保温子层上的第二保温子层，所述第一保温子层的材质和所述第二保温子层的材质不同。
在本申请的OLED显示面板的第二实施例中，所述缓冲层包括覆盖所述第二保温子层上的第一缓冲子层，其中，所述第一缓冲子层的材质是SiN x，所述第一保温子层的材质是SiO x，所述第二保温子层的材质是SiO xN y。
在本申请的OLED显示面板的第二实施例中，在所述第二保温子层中，氧元素的含量大于氮元素的含量。
在本申请的第三实施例中，所述OLED显示面板包括起到开关作用的开关薄膜晶体管，所述基板对应于所述开关薄膜晶体管的区域上设置有所述保温层。
在本申请的OLED显示面板中，所述保温层的厚度介于50纳米~100纳米之间。
在本申请的OLED显示面板中，所述保温层的材料是SiO x和SiO xN y中的一种或两种材料的组合。
本申请还涉及一种OLED显示面板的制作方法，其包括：
S1：提供一基板，所述基板包括用于设置起到驱动OLED器件发光作用的驱动薄膜晶体管和所述驱动薄膜晶体管对应的存储电容的设置区域；
S2：在所述基板的设置区域形成一保温层，用于防止非晶硅在结晶时热量快速流失；
S3：在所述基板上依次形成缓冲层和非晶硅层；
S4：对所述非晶硅层进行镭射退火处理，以形成多晶硅层，并图案化所述多晶硅层；
S5：在所述多晶硅层上依次形成绝缘层、栅极金属层、层间介电层、源漏金属层和钝化层，以形成所述驱动薄膜晶体管和所述存储电容；
S6：在所述钝化层上依次形成平坦层、阳极、像素定义层和隔间部。
在本申请的OLED显示面板的制作方法中，在所述S2的步骤包括：
S21：在所述基板上采用等离子体增强化学的气相沉积法沉积一层SiO x膜，并采用光刻工艺形成第一保温子层；
S22：在所述第一保温子层上采用等离子体增强化学的气相沉积法沉积一层SiO xN y膜，并采用光刻工艺形成第二保温子层。
在本申请的OLED显示面板的制作方法中，在步骤S21中，沉积所述SiO x膜，温度介于400℃~440℃之间，能量介于10kw~20 kw之间，压强介于40Pa~80 Pa之间，反映气体SiH 4和N 2O的气体比为1:100到1:50之间，反映时间20s~40s之间；
沉积所述SiO xN y膜时，温度介于400℃~440℃之间，能量介于10kw~20 kw之间，压强介于40Pa~80 Pa之间，SiH 4：N 2O：NH 3的气体比为1:100:80到1:100:120之间，反映时间20s~40s之间。
在本申请的OLED显示面板的制作方法中，在所述第二保温子层中，氧元素的含量大于氮元素的含量。
在本申请的OLED显示面板的制作方法中，所述保温层的厚度介于50纳米~100纳米之间。
 有益效果
相较于现有技术的OLED显示面板及其制作方法，本申请的OLED显示面板及其制作方法通过在基板上的设置区域设置保温层，防止了非晶硅膜层在退火处理进行结晶时热量快速散失，使得驱动薄膜晶体管和存储电容处的非晶硅膜层充分结晶，增大晶粒和提高了晶粒的均一性，从而提高了驱动薄膜晶体管电性的均一性，进而提高了OLED器件发光均一性；解决了现有的LTPS-TFT中LTPS晶粒大小均一性差，晶界较多，导致Drive TFT的电性均一性差的技术问题。
 附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面对实施例中所需要使用的附图作简单的介绍。下面描述中的附图仅为本申请的部分实施例，对于本领域普通技术人员而言，在不付出创造性劳动的前提下，还可以根据这些附图获取其他的附图。
图1为本申请的OLED显示面板的第一实施例的结构示意图；
图2为本申请的OLED显示面板的第二实施例的结构示意图；
图3为本申请的OLED显示面板的第三实施例的结构示意图；
图4为本申请的OLED显示面板的制作方法的实施例的流程图；
图5为本申请的OLED显示面板的制作方法的实施例的步骤S2的流程图。
 本发明的实施方式
请参照附图中的图式，其中相同的组件符号代表相同的组件。以下的说明是基于所例示的本申请具体实施例，其不应被视为限制本申请未在此详述的其它具体实施例。
请参照图1，图1为本申请的OLED显示面板的第一实施例的结构示意图。本第一实施例的OLED显示面板100，其包括基板11、保温层12、缓冲层13、驱动薄膜晶体管1a、存储电容1b、平坦层15、阳极16、像素定义层17和间隔部18。
基板11包括用于设置起到驱动OLED器件发光作用的驱动薄膜晶体管1a和驱动薄膜晶体管1a对应的存储电容1b的设置区域11a。保温层12包括至少一层保温子层，保温层12形成在设置区域11a上。缓冲层13形成在基板11上，并覆盖保温层12。驱动薄膜晶体管1a形成在缓冲层13对应于设置区域11a的位置上。存储电容1b形成在缓冲层13对应于设置区域11a的位置上。
其中，驱动薄膜晶体管1a和存储电容1b均包括形成在缓冲层13上的多晶硅层141，保温层12用于提高非晶硅在结晶成为多晶硅层141时热量的稳定性。
本第一实施例的OLED显示面板通过在基板11上的设置区域11a设置保温层12，防止了非晶硅膜层在退火处理进行结晶时热量快速散失，使得驱动薄膜晶体管1a和存储电容1b处的非晶硅膜层141充分结晶，增大晶粒和提高了晶粒的均一性，从而提高了驱动薄膜晶体管1a电性的均一性，进而提高了OLED器件发光均一性。
本第一实施例的OLED显示面板100包括设置在缓冲层13上的多晶硅层141、设置在多晶硅层上的绝缘层142、设置在绝缘层142上的栅极金属层143、设置在栅极金属层上的层间介电层144、设置在层间介电层144上的源漏金属层145，设置在源漏金属层145上的钝化层146、设置在钝化层146上的平坦层15和依次设置在平坦层15上的阳极16、像素定义层17和间隔部18。
其中，多晶硅层141包括对应于驱动薄膜晶体管1a的有源层和组成存储电容1b的下电极板。下电极板通过对多晶硅层141进行离子掺杂形成。栅极金属层143包括对应于下电极板的上电极板1431和对应于驱动薄膜晶体管1a的栅极1432。
因此，有源层、栅极1432、源漏金属层145的源漏电极组成驱动薄膜晶体管1a，上电极板1431和下电极板组成存储电容1b。
在第一实施例中，保温层12由一层保温子层构成。保温层12的厚度介于50纳米~100纳米之间。这样的设置，一方面确保保温层12的保温效果，另一方面不影响相邻层之间的应力关系，提高保温层12和相邻层之间的稳定性。
其中，可选的，保温层的材料是SiO x和SiO xN y中的一种或两种材料的组合。需要说明的是：x和y均代表数值，比如1、2等。
本第一实施例的多晶硅层的制作过程是：在基板11上沉积一层SiO x膜（本第一实施例的保温层12以SiO x材质为例进行说明），随后通过光刻工艺在设置区域11a上形成保温层12；接着，依次在保温层12上形成缓冲层13和非晶硅层；最后，对非晶硅层进行准分子镭射退火处理，以使非晶硅层结晶形成多晶硅层141。
在非晶硅层进行结晶的过程中，保温层12起到防止热量快速散失的作用，使得保温层12对应的多晶硅层充分结晶，提高了晶粒的均一性，进而提高了驱动薄膜晶体管1a电性的均一性。
请参照图2，图2为本申请的OLED显示面板的第二实施例的结构示意图。本第二实施例的OLED显示面板200包括基板21、保温层22、缓冲层23、驱动薄膜晶体管2a、存储电容2b、平坦层25、阳极26、像素定义层27和间隔部28。本第二实施例与第一实施例的不同之处在于：
保温层22包括设置在基板21上的第一保温子层221和设置在第一保温子层221上的第二保温子层222，第一保温子层221的材质和第二保温子层222的材质不同。
缓冲层23包括覆盖第二保温子层222上的第一缓冲子层231和设置在所述第一缓冲子层231上的第二缓冲子层232。第一缓冲子层231的材质是SiN x，第二缓冲子层232的材质为SiO x，第一保温子层221的材质是SiO x，第二保温子层222的材质是SiO xN y。
其中，将第二保温子层222设置在第一保温子层221和第一缓冲子层231之间，提高了保温层22和缓冲层23结合的稳定性。因为第一缓冲子层231的应力和第一保温子层221的应力相差相对较大，而第二保温子层222的应力介于二者之间，起到过渡的作用，提高了保温层22和缓冲层23结合的稳定性。
另外，在第二保温子层222中，氧元素的含量大于氮元素的含量。这样的设置，提高第二保温子层222对有机/无机层的粘附性，进一步提高了保温层22与缓冲层23粘结的稳定性。
第二保温子层222采用等离子体增强化学的气相沉积法（PECVD）沉积形成，氧含量和氮含量可以通过调节成膜气体的流量比和能量进行调控。
请参照图3，在本第三实施例和第一实施例的不同之处在于：
OLED显示面板300还包括起到开关作用的开关薄膜晶体管3a，基板31对应于开关薄膜晶体管3a的区域上设置保温层32。将保温层32同时设置在驱动薄膜晶体管3a、和存储电容3b和开关薄膜晶体管3c的正下方，提高了三者的多晶硅层341结晶时晶粒的均一性，提高了驱动薄膜晶体管3a和开关薄膜晶体管3c的电性均一性，进一步提高OLED器件发光的均匀性。
开关薄膜晶体管3c包括多晶硅层341的有源层、栅极金属层343的栅极、源漏金属层345的源漏电极。
请参照图4，本申请还涉及一种OLED显示面板的制作方法，其包括：
S1：提供一基板，所述基板包括用于设置起到驱动OLED器件发光作用的驱动薄膜晶体管和所述驱动薄膜晶体管对应的存储电容的设置区域；
S2：在所述基板的设置区域形成一保温层，用于防止非晶硅在结晶时热量快速流失；
S3：在所述基板上依次形成缓冲层和非晶硅层；
S4：对所述非晶硅层进行镭射退火处理，以形成多晶硅层，并图案化所述多晶硅层；
S5：在所述多晶硅层上依次形成绝缘层、栅极金属层、层间介电层、源漏金属层和钝化层，以形成所述驱动薄膜晶体管和所述存储电容；
S6：在所述钝化层上依次形成平坦层、阳极、像素定义层和隔间部。
在本实施例的OLED显示面板的制作方法中，当对非晶硅层进行镭射退火处理，使非晶硅层结晶的过程中，保温层起到防止热量快速散失的作用，使得驱动薄膜晶体管和存储电容的非晶硅层充分结晶，形成较大的晶粒，且提高了晶粒的均一性，改善了驱动薄膜晶体管电性的均一性，进而提高了OLED发光器件的发光的均匀性。
在本实施例的OLED显示面板的制作方法中，请参照图5，在所述S2的步骤包括：
S21：在所述基板上采用等离子体增强化学的气相沉积法沉积一层SiO x膜，并采用光刻工艺形成第一保温子层；
S22：在所述第一保温子层上采用等离子体增强化学的气相沉积法沉积一层SiO xN y膜，并采用光刻工艺形成第二保温子层。
在本实施例的OLED显示面板的制作方法中，在步骤S21中，沉积所述SiO x膜，温度介于400℃~440℃之间，能量介于10kw~20 kw之间，压强介于40Pa~80 Pa之间，反映气体SiH 4和N 2O的气体比为1:100到1:50之间，反映时间20s~40s之间。
沉积所述SiO xN y膜时，温度介于400℃~440℃之间，能量介于10kw~20 kw之间，压强介于40Pa~80 Pa之间，SiH 4：N 2O：NH 3的气体比为1:100:80到1:100:120之间，反映时间20s~40s之间。
在本实施例的OLED显示面板的制作方法中，在所述第二保温子层中，氧元素的含量大于氮元素的含量。
在本实施例的OLED显示面板的制作方法中，所述保温层的厚度介于50纳米~100纳米之间。
本实施例的OLED显示面板的制作方法制作的OLED显示面板的结构和本申请的OLED显示面板的第二实施例的结构相同，具体请参照第二实施例的内容。
相较于现有技术的OLED显示面板及其制作方法，本申请的OLED显示面板及其制作方法通过在基板上的设置区域设置保温层，防止了非晶硅膜层在退火处理进行结晶时热量快速散失，使得驱动薄膜晶体管和存储电容处的非晶硅膜层充分结晶，增大晶粒和提高了晶粒的均一性，从而提高了驱动薄膜晶体管电性的均一性，进而提高了OLED器件发光均一性；解决了现有的LTPS-TFT中LTPS晶粒大小均一性差，晶界较多，导致Drive TFT的电性均一性差的技术问题。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (18)

  1. 一种OLED显示面板，其包括：
    基板，包括用于设置起到驱动OLED器件发光作用的驱动薄膜晶体管和所述驱动薄膜晶体管对应的存储电容的设置区域；
    保温层，包括至少一层保温子层，形成在所述设置区域上；
    缓冲层，形成在所述基板上，并覆盖所述保温层；
    所述驱动薄膜晶体管，形成在所述缓冲层对应于所述设置区域的位置上；以及
    所述存储电容，形成在所述缓冲层对应于所述设置区域的位置上；
    其中，所述驱动薄膜晶体管和存储电容均包括形成在所述缓冲层上的多晶硅层，所述保温层用于提高非晶硅在结晶成为多晶硅层时热量的稳定性；
    所述保温层包括设置在所述基板上的第一保温子层和设置在所述第一保温子层上的第二保温子层，所述第一保温子层的材质和所述第二保温子层的材质不同；
    所述保温层的厚度介于50纳米~100纳米之间。
  2. 根据权利要求1所述的OLED显示面板，其中，所述缓冲层包括覆盖所述第二保温子层上的第一缓冲子层，其中，所述第一缓冲子层的材质是SiN x，所述第一保温子层的材质是SiO x，所述第二保温子层的材质是SiO xN y。
  3. 根据权利要求2所述的OLED显示面板，其中，在所述第二保温子层中，氧元素的含量大于氮元素的含量。
  4. 根据权利要求1所述的OLED显示面板，其中，所述保温层的材料是SiO x和SiO xN y中的一种或两种材料的组合。
  5. 根据权利要求1所述的OLED显示面板，其中，所述OLED显示面板包括起到开关作用的开关薄膜晶体管，所述基板对应于所述开关薄膜晶体管的区域上设置有所述保温层。
  6. 一种OLED显示面板，其包括：
    基板，包括用于设置起到驱动OLED器件发光作用的驱动薄膜晶体管和所述驱动薄膜晶体管对应的存储电容的设置区域；
    保温层，包括至少一层保温子层，形成在所述设置区域上；
    缓冲层，形成在所述基板上，并覆盖所述保温层；
    所述驱动薄膜晶体管，形成在所述缓冲层对应于所述设置区域的位置上；以及
    所述存储电容，形成在所述缓冲层对应于所述设置区域的位置上；
    其中，所述驱动薄膜晶体管和存储电容均包括形成在所述缓冲层上的多晶硅层，所述保温层用于提高非晶硅在结晶成为多晶硅层时热量的稳定性。
  7. 根据权利要求6所述的OLED显示面板，其中，所述保温层由一层保温子层构成。
  8. 根据权利要求6所述的OLED显示面板，其中，所述保温层包括设置在所述基板上的第一保温子层和设置在所述第一保温子层上的第二保温子层，所述第一保温子层的材质和所述第二保温子层的材质不同。
  9. 根据权利要求7所述的OLED显示面板，其中，所述缓冲层包括覆盖所述第二保温子层上的第一缓冲子层，其中，所述第一缓冲子层的材质是SiN x，所述第一保温子层的材质是SiO x，所述第二保温子层的材质是SiO xN y。
  10. 根据权利要求8所述的OLED显示面板，其中，在所述第二保温子层中，氧元素的含量大于氮元素的含量。
  11. 根据权利要求6所述的OLED显示面板，其中，所述保温层的厚度介于50纳米~100纳米之间。
  12. 根据权利要求6所述的OLED显示面板，其中，所述保温层的材料是SiO x和SiO xN y中的一种或两种材料的组合。
  13. 根据权利要求6所述的OLED显示面板，其中，所述OLED显示面板包括起到开关作用的开关薄膜晶体管，所述基板对应于所述开关薄膜晶体管的区域上设置有所述保温层。
  14. 一种OLED显示面板的制作方法，其包括：
    S1：提供一基板，所述基板包括用于设置起到驱动OLED器件发光作用的驱动薄膜晶体管和所述驱动薄膜晶体管对应的存储电容的设置区域；
    S2：在所述基板的设置区域形成一保温层，用于防止非晶硅在结晶时热量快速流失；
    S3：在所述基板上依次形成缓冲层和非晶硅层；
    S4：对所述非晶硅层进行镭射退火处理，以形成多晶硅层，并图案化所述多晶硅层；
    S5：在所述多晶硅层上依次形成绝缘层、栅极金属层、层间介电层、源漏金属层和钝化层，以形成所述驱动薄膜晶体管和所述存储电容；
    S6：在所述钝化层上依次形成平坦层、阳极、像素定义层和隔间部。
  15. 根据权利要求14所述的OLED显示面板的制作方法，其中，在所述S2的步骤包括：
    S21：在所述基板上采用等离子体增强化学的气相沉积法沉积一层SiO x膜，并采用光刻工艺形成第一保温子层；
    S22：在所述第一保温子层上采用等离子体增强化学的气相沉积法沉积一层SiO xN y膜，并采用光刻工艺形成第二保温子层。
  16. 根据权利要求15所述的OLED显示面板的制作方法，其中，在步骤S21中，沉积所述SiO x膜，温度介于400℃~440℃之间，能量介于10kw~20 kw之间，压强介于40Pa~80 Pa之间，反映气体SiH 4和N 2O的气体比为1:100到1:50之间，反映时间20s~40s之间；
    沉积所述SiO xN y膜时，温度介于400℃~440℃之间，能量介于10kw~20 kw之间，压强介于40Pa~80 Pa之间，SiH 4：N 2O：NH 3的气体比为1:100:80到1:100:120之间，反映时间20s~40s之间。
  17. 根据权利要求15所述的OLED显示面板的制作方法，其中，在所述第二保温子层中，氧元素的含量大于氮元素的含量。
  18. 根据权利要求14所述的OLED显示面板的制作方法，其中，所述保温层的厚度介于50纳米~100纳米之间。
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Families Citing this family (3)

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Publication number Priority date Publication date Assignee Title
CN109860239B (zh) * 2018-12-13 2021-03-16 武汉华星光电半导体显示技术有限公司 阵列基板及其制作方法、显示装置
CN110571241B (zh) * 2019-08-09 2021-02-26 武汉华星光电半导体显示技术有限公司 阵列基板及其制作方法
US11244994B2 (en) * 2019-10-23 2022-02-08 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Thin film transistor array substrate and organic light emitting diode panel

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1540602A (zh) * 2003-04-24 2004-10-27 ����Sdi��ʽ���� 具有薄膜晶体管的平板显示器
CN101022096A (zh) * 2007-03-28 2007-08-22 友达光电股份有限公司 液晶显示器的半导体结构及其制作方法
CN103296034A (zh) * 2013-05-28 2013-09-11 京东方科技集团股份有限公司 一种阵列基板、制备方法以及显示装置
CN103681776A (zh) * 2013-12-24 2014-03-26 京东方科技集团股份有限公司 低温多晶硅薄膜及其制备方法、薄膜晶体管和显示装置
CN106548980A (zh) * 2017-02-09 2017-03-29 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示基板和显示装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100696200B1 (ko) * 2005-10-14 2007-03-20 한국전자통신연구원 능동 구동 표시 장치 및 그 제조방법
KR100796654B1 (ko) * 2006-06-02 2008-01-22 삼성에스디아이 주식회사 유기 발광 표시 장치 및 그 제조 방법
JP2014032983A (ja) * 2012-08-01 2014-02-20 Sony Corp 半導体装置、表示装置および電子機器
CN103700706B (zh) * 2013-12-16 2015-02-18 京东方科技集团股份有限公司 薄膜晶体管制备方法和阵列基板制备方法
KR102139355B1 (ko) * 2013-12-31 2020-07-29 엘지디스플레이 주식회사 유기전계발광표시장치 및 그 제조방법
CN104078621B (zh) * 2014-06-20 2016-09-07 京东方科技集团股份有限公司 低温多晶硅薄膜晶体管、其制备方法及阵列基板与显示装置
KR102435156B1 (ko) * 2015-10-13 2022-08-24 삼성디스플레이 주식회사 투명 표시 기판 및 투명 표시 장치
CN105374882A (zh) 2015-12-21 2016-03-02 武汉华星光电技术有限公司 一种低温多晶硅薄膜晶体管及其制备方法
JP2017174946A (ja) * 2016-03-23 2017-09-28 株式会社ジャパンディスプレイ 半導体装置の製造方法
US9985082B2 (en) * 2016-07-06 2018-05-29 Lg Display Co., Ltd. Organic light emitting display device comprising multi-type thin film transistor and method of manufacturing the same
KR102626961B1 (ko) * 2016-07-27 2024-01-17 엘지디스플레이 주식회사 하이브리드 타입의 박막 트랜지스터 및 이를 이용한 유기발광 표시장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1540602A (zh) * 2003-04-24 2004-10-27 ����Sdi��ʽ���� 具有薄膜晶体管的平板显示器
CN101022096A (zh) * 2007-03-28 2007-08-22 友达光电股份有限公司 液晶显示器的半导体结构及其制作方法
CN103296034A (zh) * 2013-05-28 2013-09-11 京东方科技集团股份有限公司 一种阵列基板、制备方法以及显示装置
CN103681776A (zh) * 2013-12-24 2014-03-26 京东方科技集团股份有限公司 低温多晶硅薄膜及其制备方法、薄膜晶体管和显示装置
CN106548980A (zh) * 2017-02-09 2017-03-29 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示基板和显示装置

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