WO2015180450A1 - 低温多晶硅薄膜晶体管及其制备方法和显示器件 - Google Patents

低温多晶硅薄膜晶体管及其制备方法和显示器件 Download PDF

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WO2015180450A1
WO2015180450A1 PCT/CN2014/093770 CN2014093770W WO2015180450A1 WO 2015180450 A1 WO2015180450 A1 WO 2015180450A1 CN 2014093770 W CN2014093770 W CN 2014093770W WO 2015180450 A1 WO2015180450 A1 WO 2015180450A1
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thin film
film transistor
low temperature
layer
polysilicon thin
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PCT/CN2014/093770
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English (en)
French (fr)
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田慧
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京东方科技集团股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • Embodiments of the present invention relate to a low temperature polysilicon thin film transistor, a method of fabricating the same, and a display device.
  • LTPS TFT Low Temperature Poly-silicon Thin Film Transistor
  • ADSL Active Matrix Organic Light Emitting Diode
  • AMOLED Active Matrix Organic Light Emitting Diode
  • AMLCD Active Matrix Liquid Crystal Display
  • Embodiments of the present invention provide a method of fabricating a low temperature polysilicon thin film transistor, including:
  • a source/drain metal layer is formed, and a source and a drain are obtained through patterning.
  • a buffer layer is formed on the base substrate before forming the active layer.
  • the active layer, the gate insulating layer, and the gate are sequentially formed on a base substrate, and forming the source and drain regions includes:
  • a gate metal layer is formed over the gate insulating layer, and the gate electrode is formed by patterning.
  • the source and drain regions are formed by ion implantation.
  • the buffer layer is formed using plasma enhanced chemical vapor deposition.
  • the amorphous silicon layer is formed using plasma enhanced chemical vapor deposition.
  • the gate insulating layer is formed using plasma enhanced chemical vapor deposition.
  • the crystallization process is processed using an excimer laser annealing apparatus.
  • the material of the gate metal layer and the source/drain metal layer includes one of molybdenum, aluminum, titanium, or a composite material of any two or more of molybdenum, aluminum, and titanium.
  • the ions implanted during the ion implantation are boron ions or phosphorus ions.
  • the buffer layer comprises a composite film of silicon oxide or silicon nitride or both.
  • the interlayer dielectric layer comprises a composite film of silicon oxide or silicon nitride or both.
  • the simultaneous ion activation and hydrogenation treatments include:
  • Low temperature annealing is performed while performing nitrogen plasma treatment.
  • the temperature of the low temperature annealing is 350-500 °C.
  • the low temperature annealing time is 20-40 minutes.
  • Embodiments of the present invention also provide a low temperature polysilicon thin film transistor prepared by the method for preparing a low temperature polysilicon thin film transistor described above, the low temperature polysilicon thin film transistor including an active layer, a gate insulating layer, a gate, and an interlayer dielectric Layer, source and drain.
  • the low temperature polysilicon thin film transistor further includes a buffer layer.
  • the buffer layer comprises a single layer of silicon oxide or silicon nitride or a composite film layer of both.
  • the gate insulating layer or interlayer dielectric layer comprises a single layer of silicon oxide or silicon nitride or a composite film layer of both.
  • Embodiments of the present invention also provide a display device including the low temperature polysilicon thin film transistor described above.
  • FIG. 1 is a flow chart showing the steps of a method for preparing a low temperature polysilicon thin film transistor according to Embodiment 1 of the present invention
  • FIG. 2 is a flow chart showing the steps of a part of an example of the first embodiment of the present invention
  • FIG. 3 shows a schematic structural view of a low temperature polysilicon thin film transistor fabricated in accordance with one embodiment of the present invention.
  • the preparation process of the low-temperature polysilicon thin film transistor is generally to deposit an amorphous silicon layer on the substrate, and then melt-crystallize the amorphous silicon by heat treatment to form a polycrystalline silicon layer having a grain structure, and then use the polysilicon layer as a channel of the thin film transistor.
  • the layer, silicon oxynitride is used as the gate insulating layer, the metal is used as the gate, and then the metal gate is used as a mask for self-aligned ion implantation to form the source and drain, and finally the fabrication of the polysilicon thin film transistor is completed.
  • the lattice damage of the polysilicon is caused after the ion implantation, and the subsequent activation process is required to activate the implanted ions and repair the lattice damage of the polysilicon layer.
  • the interface between the polysilicon film and the gate oxide layer has a dangling bond of an unbonded orbital, which is an important factor for increasing the interface state density of the polycrystalline silicon grain boundary, thereby causing a decrease in carrier mobility, a threshold voltage increase, and the like.
  • the subsequent process also passes through the hydrogenation process to passivate defects in the interior and interface of the polysilicon film.
  • a commonly used method of activating a damaged crystal lattice of polysilicon is to perform a rapid thermal annealing after forming an interlayer dielectric layer.
  • the method generally needs to heat the substrate to more than 600 degrees. This high temperature process easily causes deformation of the glass substrate and causes cracks in the interlayer insulating layer, thereby seriously affecting the characteristics of the thin film transistor.
  • the most common method of the hydrogenation process is to perform annealing in a hydrogen atmosphere after forming a thin film transistor (TFT) or heat treatment to diffuse hydrogen to the gate oxide layer and the polysilicon layer by using a silicon nitride film as a hydrogen source.
  • TFT thin film transistor
  • the preparation of the low-temperature polysilicon thin film transistor requires a multi-step heat treatment process including ion activation after the interlayer dielectric layer and hydrogenation treatment after completion of the TFT fabrication, wherein the commonly used activation method is rapid thermal annealing, and the hydrogenation treatment is in the device.
  • the commonly used activation method is rapid thermal annealing, and the hydrogenation treatment is in the device.
  • the thermal cost and time cost of the low-temperature polysilicon thin film transistor is high, and the electrical characteristics of the device Promotion will also be limited.
  • Embodiment 1 of the present invention provides a method for preparing a low temperature polysilicon thin film transistor.
  • the flow chart is as shown in FIG. 1 and includes the following steps:
  • step S1 a buffer layer, an active layer, a gate insulating layer and a gate are sequentially formed on the base substrate to form a source/drain region.
  • Step S2 forming an interlayer dielectric layer, and forming a contact hole of the source/drain region through a patterning process.
  • step S3 ion activation and hydrogenation treatment are simultaneously performed.
  • Step S4 forming a source/drain metal layer, and performing pattern processing to obtain a source and a drain.
  • the ion activation process and the hydrogenation process which are originally performed twice are combined into one process, and the whole process of the low-temperature polysilicon thin film transistor is shortened, thereby avoiding
  • the two processes separately perform deformation of the substrate substrate in the ion activation process due to the high temperature process, and further, it is also possible to avoid the characteristics of the device due to the occurrence of cracks in the interlayer insulating layer.
  • the step S1 in this embodiment is to sequentially form a buffer layer, an active layer, a gate insulating layer and a gate on the base substrate to form a source/drain region.
  • the flow is as shown in FIG. 2, and includes the following steps:
  • Step S11 depositing a buffer layer on the base substrate.
  • Step S12 depositing an amorphous silicon layer over the buffer layer, and crystallization treatment to become polycrystalline silicon, and then patterning the polycrystalline silicon to form an active layer.
  • Step S13 depositing a gate insulating layer over the active layer.
  • Step S14 depositing a gate metal layer over the gate insulating layer, and forming a gate by patterning.
  • Step S15 forming a source/drain region by ion implantation.
  • step S11 may also be omitted, that is, an amorphous silicon layer is directly formed on the base substrate.
  • the buffer layer, the amorphous silicon layer, and the gate insulating layer formed in the above steps S11 to S14 are all formed by plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the crystallization process in embodiments of the invention may be processed using an excimer laser annealing apparatus.
  • the crystallization of a polycrystalline silicon film is a method for fabricating a polycrystalline silicon film, and the atoms in disordered arrangement are turned into short-range ordered atoms by means of thermal annealing, photo annealing, high-energy atomic irradiation, and the like.
  • the amorphous structure is changed to a polycrystalline structure.
  • Solid phase crystallization refers to a temperature at which the crystallization temperature is lower than that of the amorphous solid after melting, and there are doped or undoped solid phase crystallization, metal induced crystallization, and microwave induced crystallization.
  • the doped or undoped solid phase crystallization process is simple, but the required temperature is relatively high, and needs to reach 600 to 1000 ° C.
  • the metal induced crystallization may cause the resulting polycrystalline silicon thin film transistor to contain metal atoms due to metal contamination.
  • Microwave-induced crystallization is performed on the amorphous silicon film by microwave irradiation, which requires microwave generating equipment and has high cost.
  • the laser crystallization is to laser the laser beam on the amorphous silicon film for a short time, so that it melts and crystallizes at a high temperature. Due to the short time, the temperature of the substrate has not changed, that is, the temperature remains unchanged, therefore, it will not be due to The substrate substrate is too hot to cause problems such as deformation and the like, and damage to the substrate substrate is avoided.
  • the excimer laser annealing apparatus used in the embodiment of the present invention uses an excimer laser beam to irradiate the amorphous silicon film on the substrate for a short time to recrystallize into a polysilicon film.
  • the material of the gate metal layer and the source/drain metal layer in this embodiment is one of molybdenum, aluminum, titanium, or a composite material composed of any two or more of molybdenum, aluminum, and titanium.
  • the ions implanted during ion implantation are boron (B) ions or phosphorus (P) ions.
  • B boron
  • P phosphorus
  • the principle of ion implantation is that after the B ion beam or the P ion beam is irradiated to the solid material, the speed is gradually reduced by the resistance of the solid material, and finally stays in the solid material.
  • the buffer layer is a composite film of silicon oxide or silicon nitride or both.
  • the interlayer dielectric layer is a composite film of silicon oxide or silicon nitride or both.
  • step S3 includes:
  • Low temperature annealing is performed while performing nitrogen plasma treatment. Immediately after the formation of the contact holes, ion activation and hydrogenation are carried out without a time interval therebetween, i.e., simultaneously in a one-step process.
  • the temperature for the low temperature annealing is, for example, 350 to 500 ° C, and the time for the low temperature annealing is 20 to 40 minutes.
  • the process of the low temperature polysilicon thin film transistor can be shortened, thereby reducing the heat cost and time cost of the device fabrication.
  • the ion activation and hydrogenation processes are formed after the contact holes are formed, which greatly shortens the path of ion activation and hydrogenation, and the nitrogen plasma treatment can effectively repair the dangling bonds in the interior and interface of the polysilicon film, improve the interface characteristics of the polysilicon film, and thus can enhance the ions.
  • the activation efficiency and hydrogenation effect can effectively improve the device mobility and switching ratio and other electrical characteristics.
  • the second embodiment of the present invention further provides a low temperature polysilicon thin film transistor obtained by the method for preparing a low temperature polysilicon thin film transistor of the first embodiment, the low temperature polysilicon thin film transistor comprising an active layer, a gate insulating layer, a gate, a source and a drain pole.
  • the low temperature polysilicon thin film transistor includes a buffer layer 20, a polysilicon active layer 30, a gate insulating layer 40, a gate 50, and an interlayer dielectric layer 60 formed on the base substrate 10. Source 51 and drain 52.
  • the substrate base 10 can be, for example, a glass, quartz or plastic substrate.
  • the buffer layer 20 deposited on the base substrate 10 may be a single layer of the silicon oxide 21 or the silicon nitride 22 or a composite film layer 20 of both.
  • the gate insulating layer 40 may also be a single layer of silicon oxide 41 or silicon nitride 42 or a composite film layer 40 of both.
  • the interlayer dielectric layer 60 can be a single layer of silicon oxide 61 or silicon nitride 62 or a composite film layer 60 of both.
  • FIG. 3 is merely a schematic structure of a polysilicon thin film transistor according to an embodiment of the present invention, but the present invention is not intended to be limited to the embodiment of the example. It should be understood by those skilled in the art that, as needed, the formed transistor may not be limited to the structural details shown in the figure, and some structures or details may be omitted or added, for example, a buffer layer or a gate insulating layer or an interlayer dielectric layer may be used. Make a single layer structure, or omit one or both of them or omit them.
  • top gate structure is taken as an example, it may also be a bottom gate structure. When it is a bottom-grid structure, the position of the corresponding features will also change corresponding positional relationship.
  • the low-temperature polysilicon thin film transistor in this embodiment can also achieve the beneficial effects of the first embodiment described above, and details are not described herein again.
  • Embodiment 3 of the present invention further provides a display device, including the low temperature polysilicon thin film transistor of Embodiment 2.
  • the display device may be: an array substrate, a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any product or component having a display function.
  • a method for fabricating a low-temperature polysilicon thin film transistor includes sequentially forming a buffer layer, an active layer, a gate insulating layer and a gate on a substrate to form a source/drain region; forming an interlayer dielectric layer
  • the patterning process forms a contact hole of the source and drain regions; simultaneously performing ion activation and hydrogenation treatment; forming a source/drain metal layer, and performing patterning to obtain a source and a drain.
  • the ion activation and the hydrogenation treatment are combined into one process at the same time, the low temperature polysilicon can be shortened.
  • the process of the film transistor reduces the thermal and time cost of device fabrication.
  • ion activation and hydrogenation treatment are performed, which greatly shortens the path of ion activation and hydrogenation.
  • Nitrogen plasma treatment can effectively repair the dangling bonds inside and at the interface of the polysilicon film, improve the interface characteristics of the polysilicon film, and thus can enhance the ions.
  • the activation efficiency and hydrogenation effect can effectively improve the device mobility and switching ratio and other electrical characteristics.

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Abstract

一种低温多晶硅薄膜晶体管及其制备方法和显示器件，该低温多晶硅薄膜晶体管的制备方法包括在衬底基板（10）上依次制作缓冲层（20）、有源层（30）、栅绝缘层（40）和栅极（50），形成源漏区域；沉积层间介质层（60），经过图案化处理形成源漏区域的接触孔；同时进行离子激活和氢化处理；沉积源漏金属层，经过图形化处理得到源极（51）和漏极（52）。由于离子激活和氢化处理同时进行，可以缩短制程，从而降低了器件制作的热成本和时间成本。

Description

低温多晶硅薄膜晶体管及其制备方法和显示器件 技术领域
本发明的实施例涉及一种低温多晶硅薄膜晶体管及其制备方法和显示器件。
背景技术
低温多晶硅薄膜晶体管(Low Temperature Poly-silicon Thin Film Transistor，简称LTPS TFT)由于具有较高的迁移率和稳定性等优点，已经普遍应用在有源矩阵有机发光显示器(Active Matrix Organic Light Emitting Diode，简称AMOLED)、有源矩阵液晶显示器(Active Matrix Liquid Crystal Display，简称AMLCD)等显示器上。
发明内容
本发明的实施例提供了一种低温多晶硅薄膜晶体管的制备方法，包括：
在衬底基板上依次形成有源层、栅绝缘层和栅极，形成源漏区域；
形成层间介质层，经过图案化处理形成源漏区域的接触孔；
同时进行离子激活和氢化处理；以及
形成源漏金属层，经过图形化处理得到源极和漏极。
在一个示例中，在形成所述有源层之前，在所述衬底基板上形成缓冲层。
在一个示例中，在衬底基板上依次形成所述有源层、所述栅绝缘层和所述栅极，形成所述源漏区域包括：
在所述缓冲层上方形成非晶硅层，并使所述非晶硅层经过晶化处理成为多晶硅层，再对所述多晶硅层进行图案化处理形成所述有源层；
在所述有源层上方形成栅绝缘层；以及
在所述栅绝缘层上方形成栅极金属层，经过图案化处理形成所述栅极。
在一个示例中，所述源漏区域通过离子注入形成。
在一个示例中，所述缓冲层采用等离子体增强化学气相沉积法形成。
在一个示例中，所述非晶硅层采用等离子体增强化学气相沉积法形成。
在一个示例中，所述栅绝缘层采用等离子体增强化学气相沉积法形成。
在一个示例中，所述晶化处理采用准分子激光退火设备进行处理。
在一个示例中，所述栅极金属层和所述源漏金属层的材料包括钼、铝、钛之一，或者钼、铝、钛中任意两者以上构成的复合材料。
在一个示例中，所述离子注入时注入的离子为硼离子或者磷离子。
在一个示例中，所述缓冲层包括氧化硅或氮化硅或二者的复合薄膜。
在一个示例中，所述层间介质层包括氧化硅或氮化硅或二者的复合薄膜。
在一个示例中，所述同时进行离子激活和氢化处理包括：
进行氮等离子处理的同时进行低温退火。
在一个示例中，所述低温退火的温度为350-500℃。
在一个示例中，所述低温退火的时间为20-40分钟。
本发明的实施例还提供了一种采用以上所述的低温多晶硅薄膜晶体管的制备方法制备的低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管包括有源层、栅绝缘层、栅极、层间介质层、源极和漏极。
在一个示例中，所述低温多晶硅薄膜晶体管还包括缓冲层。
在一个示例中，所述缓冲层包括单层的氧化硅或氮化硅或两者的复合膜层。
在一个示例中，所述栅绝缘层或层间介质层包括单层的氧化硅或氮化硅或两者的复合膜层。
本发明的实施例还提供了一种显示器件，包括以上所述的低温多晶硅薄膜晶体管。
附图说明
图1是本发明实施例一提供的一种低温多晶硅薄膜晶体管的制备方法的步骤流程图；
图2是本发明实施例一的部分示例的步骤流程图；以及
图3显示根据本发明的一个实施例制造的低温多晶硅薄膜晶体管结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在无需创 造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，本文使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“上”、“下”、等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
低温多晶硅薄膜晶体管的制备过程一般是在基板上沉积非晶硅层，再通过热处理等方式使非晶硅熔融结晶以形成具有晶粒结构的多晶硅层，接下来利用多晶硅层作为薄膜晶体管的沟道层，硅的氮氧化物作为栅绝缘层，金属作为栅极，然后以金属栅极为掩膜进行自对准的离子注入形成源漏极，最终完成多晶硅薄膜晶体管的制作。在多晶硅薄膜晶体管的制备过程中，离子注入后会造成多晶硅的晶格损伤，需要后续的激活工艺对注入的离子进行激活并修复多晶硅层的晶格损伤。另外，多晶硅薄膜与栅氧化层的界面存在未成键轨道的悬挂键，是多晶硅晶界的界面态密度增加的很重要的因素，从而导致载流子迁移率下降，阈值电压升高等显示器件的性能退化问题，后续工艺还要通过氢化工艺钝化多晶硅薄膜内部和界面的缺陷。
常用的对多晶硅的受损晶格进行激活的方法为形成层间介质层后进行快速热退火。该方法通常需要将基板加热到600度以上，这种高温工艺容易导致玻璃基板变形并造成层间绝缘层出现裂纹，从而严重影响薄膜晶体管的特性。氢化工艺最常用的方法是制作完成薄膜晶体管(TFT,Thin Film Transistor)后在氢气氛中进行退火或者以氮化硅薄膜为氢来源进行热处理使氢扩散至栅氧化层和多晶硅层。由于这些方法通常需要穿过多层薄膜进入有源层，使得氢的扩散距离很长，因此，为了充分进行氢化，就需要很长的时间进行热处理，增加了工艺成本和时间。同时，长时间的热处理会对TFT器件造成一定的影响，特别是在TFT的尺寸很大的情况下，这种影响会更大。
也就是说，制备低温多晶硅薄膜晶体管需要经过多步热处理工艺包括层间介质层后的离子激活以及TFT制作完成后的氢化处理等，其中常用的激活方法为快速热退火，氢化处理则是在器件完成后进行较长时间的退火，使得低温多晶硅薄膜晶体管的热成本和时间成本较高，而且对于器件的电学特性 提升也会受到限制。
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。
实施例一
本发明实施例一提供了一种低温多晶硅薄膜晶体管的制备方法，流程图如图1所示，包括以下步骤：
步骤S1、在衬底基板上依次形成缓冲层、有源层、栅绝缘层和栅极，形成源漏区域。
步骤S2、形成层间介质层，经过图案化处理形成源漏区域的接触孔。
步骤S3、同时进行离子激活和氢化处理。
步骤S4、形成源漏金属层，经过图形化处理得到源极和漏极。
与一般的低温多晶硅薄膜晶体管的制备方法相比，本发明实施例的制备方法中，将原本分两次进行的离子激活工艺和氢化工艺合并为一个工艺，缩短整个低温多晶硅薄膜晶体管的制程，避免两个工艺分开进行在离子激活工艺由于高温工艺导致的衬底基板变形，此外，还能避免由于层间绝缘层出现裂纹影响器件的特性。也不再需要氢化工艺单独进行时需要很长的时间进行热处理，节省时间和热源。
在一个示例中，本实施例中步骤S1是在衬底基板上依次形成缓冲层、有源层、栅绝缘层和栅极，形成源漏区域，流程如图2所示，包括以下步骤：
步骤S11、在衬底基板上沉积缓冲层。
步骤S12、在缓冲层上方沉积非晶硅层，并使非晶硅层经过晶化处理成为多晶硅，再对多晶硅进行图案化处理形成有源层。
步骤S13、在有源层上方沉积形成栅绝缘层。
步骤S14、在栅绝缘层上方沉积栅极金属层，经过图案化处理形成栅极。
步骤S15、通过离子注入形成源漏区域。
需要说明的是步骤S11也可以没有，即直接在衬底基板上形成非晶硅层。
在一个示例中，上述步骤S11～S14中形成缓冲层、非晶硅层以及栅绝缘层均采用等离子体增强化学气相沉积法(PECVD,Plasma Enhanced Chemical Vapor Deposition)制作。
在一个示例中，本发明的实施例中的晶化处理可以采用准分子激光退火设备进行处理。多晶硅薄膜的晶化是一种多晶硅薄膜制作的方法，将无序排列的原子经热退火、光退火、高能原子照射等手段变成短程有序排列的原子， 即将非晶结构变成多晶结构。
晶化的方法包括固相晶化和激光晶化。固相晶化是指晶化温度低于非晶固体熔融后结晶的温度，有掺杂或非掺杂固相晶化、金属诱导晶化以及微波诱导晶化等。掺杂或非掺杂固相晶化工艺简单，但是需要的温度较高，需达到600～1000℃，金属诱导晶化由于金属的污染会导致制作得到的多晶硅薄膜晶体管含有金属原子。微波诱导晶化利用微波作用在非晶硅薄膜上使之晶化，需要微波发生设备，成本较高。而激光晶化就是将激光束短时间打在非晶硅薄膜上，使其高温熔化结晶，由于时间很短，衬底基板的温度还没发生变化，即温度保持不变，因此，不会由于衬底基板温度过高导致其变形等问题的出现，避免对衬底基板造成损伤。本发明实施例中采用的准分子激光退火设备采用准分子激光束对基板上的非晶硅膜进行短时间照射，使其再结晶变成多晶硅膜。
在一个示例中，本实施例中的栅极金属层和源漏金属层的材料为钼、铝、钛之一，或者为钼、铝、钛中任意两者以上构成的复合材料。
在一个示例中，离子注入时注入的离子为硼(B)离子或者磷(P)离子。离子注入原理为B离子束或P离子束照射到固体材料以后，受到固体材料的抵抗而速度慢慢减低下来，并最终停留在固体材料中。
在一个示例中，缓冲层为氧化硅或氮化硅或两者的复合膜。
在一个示例中，层间介质层为氧化硅或氮化硅或两者的复合膜。
在一个示例中，步骤S3包括：
进行氮等离子处理的同时进行低温退火。接触孔形成之后紧接着进行离子激活和氢化，中间没有时间间隔，即在一步工艺中同时进行。
低温退火的温度例如为350-500℃，低温退火的时间为20-40分钟。
采用本发明实施例提供的低温多晶硅薄膜晶体管的制备方法，由于将离子激活和氢化工艺合并为一步同时进行，可以缩短低温多晶硅薄膜晶体管的制程，从而降低器件制作的热成本和时间成本。而且，接触孔形成后进行离子激活和氢化工艺，大大缩短了离子激活和氢化的路径，同时氮等离子处理能够有效修补多晶硅薄膜内部和界面的悬挂键，改善多晶硅薄膜的界面特性，因此可以提升离子的激活效率和氢化效果，从而能够有效提高器件的迁移率和开关比等电学特性。
实施例二
本发明实施例二还提供了一种采用实施例一中低温多晶硅薄膜晶体管的制备方法得到的低温多晶硅薄膜晶体管，该低温多晶硅薄膜晶体管包括有源层、栅绝缘层、栅极、源极和漏极。
根据一个实施例，如图3所示，该低温多晶硅薄膜晶体管包括在衬底基板10上形成的缓冲层20、多晶硅有源层30、栅绝缘层40、栅极50、层间介质层60、源极51和漏极52。
衬底基本10例如可以为玻璃、石英或塑料基板。
在衬底基板10上沉积形成的缓冲层20可以为单层的氧化硅21或氮化硅22或两者的复合膜层20。类似地，栅绝缘层40也可以为单层的氧化硅41或氮化硅42或两者的复合膜层40。同样类似地，层间介质层60可以为单层的氧化硅61或氮化硅62或两者的复合膜层60。
图3仅是根据本发明一个实施例的多晶硅薄膜晶体管的示意结构，但是，本发明无意受限于该示例的实施例。本领域技术人员应该理解，根据需要，形成的晶体管可以不限于图中显示的结构细节，还可以是省略或增加某些结构或者细节，例如，缓冲层或栅绝缘层或层间介质层都可以使单层的结构，或者省略其中的一个或两个或者都省略。
此外，虽然本文是以顶栅形结构为例进行说明的，但是，还可以是底栅形结构。当是底栅形结构时，相应的各特征的位置也会做相应的位置关系变化。
本实施例中的低温多晶硅薄膜晶体管也能够实现上述实施例一的有益效果，此处不再赘述。
实施例三
本发明实施例三还提供了一种显示器件，包括实施例二中的低温多晶硅薄膜晶体管。所述显示器件可以为：阵列基板、液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明实施例提供的一种低温多晶硅薄膜晶体管的制备方法，包括在衬底基板上依次形成缓冲层、有源层、栅绝缘层和栅极，形成源漏区域；形成层间介质层，经过图案化处理形成源漏区域的接触孔；同时进行离子激活和氢化处理；形成源漏金属层，经过图形化处理得到源极和漏极。一方面，由于将离子激活和氢化处理合并为一个工艺同时进行，可以缩短低温多晶硅薄 膜晶体管的制程，从而降低了器件制作的热成本和时间成本。另一方面，接触孔形成后进行离子激活和氢化处理，大大缩短离子激活和氢化的路径，氮等离子处理能够有效修补多晶硅薄膜内部和界面的悬挂键，改善多晶硅薄膜的界面特性，因此可以提升离子的激活效率和氢化效果，从而能够有效提高器件的迁移率和开关比等电学特性。
以上实施例仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，而这样的变化和变形以及等同的技术方案也应属于本发明的范围，本发明的专利保护范围由权利要求限定。
本申请要求于2014年05月27日提交的名称为“一种低温多晶硅薄膜晶体管及其制备方法和显示器件”的中国专利申请No.201410227982.8的优先权，其全文以引用方式合并于本文。

Claims (20)

  1. 一种低温多晶硅薄膜晶体管的制备方法，包括：
    在衬底基板上依次形成有源层、栅绝缘层和栅极；
    形成源漏区域；
    形成层间介质层，经过图案化处理形成源漏区域的接触孔；
    同时进行离子激活和氢化处理；以及
    形成源漏金属层，经过图形化处理得到源极和漏极。
  2. 如权利要求1所述的低温多晶硅薄膜晶体管的制备方法，还包括：
    在形成所述有源层之前，在所述衬底基板上形成缓冲层。
  3. 如权利要求1所述的低温多晶硅薄膜晶体管的制备方法，其中，在所述衬底基板上依次形成所述有源层、所述栅绝缘层和栅极包括：
    在所述衬底基板上方形成非晶硅层，并使所述非晶硅层经过晶化处理成为多晶硅层，再对所述多晶硅层进行图案化处理形成所述有源层；
    在所述有源层上方形成栅绝缘层；
    在所述栅绝缘层上方形成栅极金属层，经过图案化处理形成所述栅极。
  4. 如权利要求1所述的低温多晶硅薄膜晶体管的制备方法，其中所述源漏区域：
    通过离子注入形成。
  5. 如权利要求2所述的低温多晶硅薄膜晶体管的制备方法，其中所述缓冲层采用等离子体增强化学气相沉积法形成。
  6. 如权利要求2-5任一项所述的低温多晶硅薄膜晶体管的制备方法，其中所述非晶硅层采用等离子体增强化学气相沉积法形成。
  7. 如权利要求2-6任一项所述的低温多晶硅薄膜晶体管的制备方法，其中所述栅绝缘层采用等离子体增强化学气相沉积法形成。
  8. 如权利要求3-7任一项所述的低温多晶硅薄膜晶体管的制备方法，其中所述晶化处理采用准分子激光退火设备进行。
  9. 如权利要求3-8任一项所述的低温多晶硅薄膜晶体管的制备方法，其中所述栅极金属层和源漏金属层的材料包括钼、铝、钛之一，或者钼、铝、钛中任意两者以上构成的复合材料。
  10. 如权利要求4-9任一项所述的低温多晶硅薄膜晶体管的制备方法，其中所述离子注入过程中注入的离子包括硼离子或者磷离子。
  11. 如权利要求2-10中任一项所述的低温多晶硅薄膜晶体管的制备方法，其中所述缓冲层包括氧化硅或氮化硅或两者的复合膜。
  12. 如权利要求1-11中任一项所述的低温多晶硅薄膜晶体管的制备方法，其中所述层间介质层包括氧化硅或氮化硅或两者的复合膜。
  13. 如权利要求1-12任一项所述的低温多晶硅薄膜晶体管的制备方法，其中，所述同时进行离子激活和氢化处理包括：
    进行氮等离子处理的同时进行低温退火。
  14. 如权利要求1-13任一项所述的低温多晶硅薄膜晶体管的制备方法，其中所述低温退火的温度为350-500℃。
  15. 如权利要求1-14任一项所述的低温多晶硅薄膜晶体管的制备方法，其中所述低温退火的时间为20-40分钟。
  16. 一种采用权利要求1-15任一项所述的低温多晶硅薄膜晶体管的制备方法制备的低温多晶硅薄膜晶体管，其中所述低温多晶硅薄膜晶体管包括有源层、栅绝缘层、栅极、层间介质层、源极和漏极。
  17. 如权利要求16所述的低温多晶硅薄膜晶体管，其中所述低温多晶硅薄膜晶体管还包括缓冲层。
  18. 如权利要求17所述的低温多晶硅薄膜晶体管，其中所述缓冲层包括单层的氧化硅或氮化硅或两者的复合膜层。
  19. 如权利要求17或18所述的低温多晶硅薄膜晶体管，其中所述栅绝缘层或层间介质层包括单层的氧化硅或氮化硅或两者的复合膜层。
  20. 一种显示器件，包括权利要求16或19所述的低温多晶硅薄膜晶体管。
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