WO2020088236A1 - 基板及其制作方法以及透明显示装置 - Google Patents

基板及其制作方法以及透明显示装置 Download PDF

Info

Publication number
WO2020088236A1
WO2020088236A1 PCT/CN2019/111176 CN2019111176W WO2020088236A1 WO 2020088236 A1 WO2020088236 A1 WO 2020088236A1 CN 2019111176 W CN2019111176 W CN 2019111176W WO 2020088236 A1 WO2020088236 A1 WO 2020088236A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
film transistor
insulating layer
thin film
light
Prior art date
Application number
PCT/CN2019/111176
Other languages
English (en)
French (fr)
Inventor
孙宏达
刘凤娟
谢蒂旎
顾鹏飞
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/649,854 priority Critical patent/US11239259B2/en
Publication of WO2020088236A1 publication Critical patent/WO2020088236A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a substrate and a manufacturing method thereof, and a transparent display device.
  • LCD liquid crystal display
  • OLED organic light-emitting display
  • TV televisions
  • novel display technologies such as transparent display devices; among them, transparent display devices have obtained a good user experience and have broad Market prospects.
  • the current transparent display device still needs to be improved.
  • an object of the present disclosure is to propose a simple structure, easy to implement, good device performance, high yield, or high temperature illumination negative bias stability (NBTIS) of the active layer in the thin film transistor during use A substrate or transparent display device that does not deteriorate.
  • NTIS high temperature illumination negative bias stability
  • the present disclosure provides a substrate.
  • the substrate includes: a plurality of pixel units, at least part of the pixel units including a light emitting region and a transparent region, the light emitting region includes a thin film transistor; a light blocking member, the light blocking member is provided in In the light-emitting area, it is used to block the light incident on the thin film transistor through the transparent area.
  • the structure of the substrate is simple and easy to implement, and the light blocking member can effectively reduce the exposure of light to the thin film transistor, and is particularly suitable for blocking the side light from the transparent area to the thin film transistor, so that the active layer in the thin film transistor is effectively protected , Significantly reduce the problem of NBTIS deterioration of the active layer due to the irradiation of light (especially ultraviolet light), thereby effectively ensuring the stability of the thin film transistor, so that the transparent display device containing the substrate can be used in the process of long-term use Maintaining a high yield rate is conducive to satisfying consumers' consumption experience.
  • the light blocking member includes a reflective layer
  • the thin film transistor includes a multilayer insulating layer
  • the reflective layer at least covers at least a portion of the insulating layer in the multilayer insulating layer toward the transparent region On the side.
  • the insulating layer includes an interlayer insulating layer and a gate insulating layer, or the insulating layer includes an interlayer insulating layer.
  • the orthographic projection of the reflective layer on the substrate overlaps with the orthographic projection of the interlayer insulating layer on the substrate.
  • the material forming the reflective layer includes metal.
  • the light blocking member further includes an ultraviolet blocking wall, the ultraviolet blocking wall is located in the light emitting area, and is located on a side of the reflective layer close to the transparent area.
  • a blocking wall is further provided in the light-emitting area, the blocking wall is located on a side of the reflective layer close to the transparent area, and the ultraviolet blocking wall is located on the reflective layer and the blocking In the gap between the walls.
  • the retaining wall includes a first sublayer, a second sublayer, and a third sublayer from bottom to top.
  • the distance between the reflective layer and the retaining wall is 2-3 microns.
  • the reflective layer covers at least part of the side of the barrier wall facing the thin film transistor.
  • the light-emitting region further includes a flat layer covering the thin film transistor and the reflective layer, and at least a portion of the flat layer constitutes the ultraviolet blocking wall.
  • the material forming the ultraviolet blocking wall includes a material having a transmittance lower than 20%.
  • the material forming the ultraviolet blocking wall includes a polyimide-based organic material.
  • the light blocking member further includes a second reflective layer covering at least a portion of the insulating layer in the multilayer insulating layer toward the transparent area in the adjacent pixel unit On the side.
  • the present disclosure provides a transparent display device.
  • the transparent display device includes the aforementioned substrate. The inventor found that the transparent display device can maintain a very high display quality during long-term use, and the product yield is high, which can satisfy the consumer's consumption experience.
  • the present disclosure provides a method of manufacturing the aforementioned substrate.
  • the method includes: forming the plurality of pixel units; wherein forming at least part of the pixel unit includes forming a thin film transistor and a light blocking member in the light emitting region.
  • the inventor found that the manufacturing method is simple, convenient, easy to implement, and low in cost, and it can obtain a substrate having all the features and advantages described above.
  • the reflective layer and the source and drain in the thin film transistor are formed through a patterning process.
  • forming at least part of the pixel unit further includes the step of forming a barrier wall, wherein the first sub-layer and the buffer layer in the thin film transistor are formed by a patterning process; the second sub-layer The layer and the gate insulating layer in the thin film transistor are formed by one patterning process; the third sublayer and the interlayer insulating layer in the thin film transistor are formed by one patterning process.
  • forming at least part of the pixel unit further includes the step of forming a flat layer, a part of the flat layer is filled in the gap between the reflective layer and the retaining wall, and is filled in the The part of the flat layer in the gap constitutes an ultraviolet blocking wall.
  • FIG. 1 is a schematic structural diagram of a substrate in the prior art.
  • FIG 2 is a top view of a substrate in some embodiments of the present disclosure.
  • Fig. 3 is a schematic diagram of the cross-sectional structure of Fig. 2 along the AA 'direction.
  • FIG. 4 is a schematic structural diagram of a substrate in some embodiments of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a substrate in some embodiments of the present disclosure.
  • FIG. 6 is a top view of a substrate in some embodiments of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a substrate in some embodiments of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a substrate in some embodiments of the present disclosure.
  • a transparent display device As shown in FIG. 1, due to the presence of the transparent area 120 and the environment in which the transparent display device is used, a large amount of external light will enter the light-emitting area 110 from the transparent area 120, which may cause lateral light (Eg, UV) causes the electron migration of the active layer 60 (ACT layer) in the thin-film transistor 111 in the light-emitting region to be affected, and eventually the stability of the thin-film transistor (TFT) 111 device is impaired.
  • a light blocking member can be provided in the light emitting area to block the influence of the light from the outside toward the transparent area on the thin film transistor.
  • the present disclosure provides a substrate.
  • the substrate includes: a plurality of pixel units 100, at least part of which include a light emitting region 110 and a transparent region 120, and the light emitting region 110 includes a thin film transistor 111; A light blocking member 112, which is disposed in the light emitting region 110, and is used for blocking light incident on the thin film transistor through the transparent region.
  • the structure of the substrate is simple and easy to implement, and the light blocking member can effectively reduce the exposure of light to the thin film transistor, and is particularly suitable for blocking external light from the transparent area to the thin film transistor, so that the active layer in the thin film transistor Protection, significantly reducing the problem of NBTIS deterioration of the active layer due to the irradiation of light (especially ultraviolet light), thereby effectively ensuring the light stability of the thin film transistor, and the substrate can maintain a high level during long-term use Yield is conducive to satisfying consumers' consumption experience.
  • the gate line 2 and the data line 1 are intersected to define a plurality of pixel units 100.
  • the “light-emitting area” described in this document includes a thin-film transistor and a light-emitting element, where the arrangement of the thin-film transistor and the light-emitting element is the same as the arrangement of the thin-film transistor and the light-emitting element in a conventional pixel unit, that is, light
  • the element corresponds to the opening area of the conventional pixel unit
  • the thin film transistor corresponds to the area outside the opening area of the conventional pixel unit, and no light-emitting element is shown in the drawings herein; at least part of the pixel unit includes a light-emitting area and transparent
  • the area refers to: 1. All pixel units include a light emitting area and a transparent area; 2.
  • a part of the pixel unit includes a light emitting area and a transparent area, and another part of the pixel unit does not include a transparent area; for example, in a pixel unit arranged in an array, where One row of pixel units includes a light-emitting area and a transparent area, and the other row of pixel units does not include a transparent area.
  • the material of the active layer in the thin film transistor is an oxide semiconductor
  • it is extremely vulnerable to damage caused by light, causing electron migration, which degrades the performance of the thin film transistor.
  • the structure is beneficial to reduce the external light from entering the thin film transistor, thereby ensuring the performance of the thin film transistor.
  • the thin film transistor may be a top gate (Top Gate) thin film transistor, a bottom gate thin film transistor, a back channel etch type (BCE) thin film transistor, an etch barrier structure (ESL) thin film transistor, etc.
  • Top Gate top gate
  • BCE back channel etch type
  • ESL etch barrier structure
  • the light blocking member includes a reflective layer
  • the thin film transistor includes a multilayer insulating layer
  • the reflective layer at least covers at least a portion of the insulating layer in the multilayer insulating layer toward the transparent region On the side.
  • the insulating layer includes an interlayer insulating layer and a gate insulating layer or an interlayer insulating layer, that is, the reflective layer may cover at least the interlayer insulating layer in the thin film transistor toward The side of the transparent region or the reflective layer may cover at least the side of the interlayer insulating layer and the gate insulating layer of the thin film transistor facing the transparent region.
  • the thin film transistor may be a top gate type thin film transistor.
  • the light blocking member 112 includes a reflective layer 1121, and the reflective layer 1121 is provided at least on the thin film transistor 111 The interlayer insulating layer 30 and the gate insulating layer 20 in the side facing the transparent region 120.
  • the gate insulating layer of the top-gate thin film transistor is formed by etching using the gate as a reticle. In this case, the reflective layer is disposed on the interlayer insulating layer toward the transparent region On the side.
  • the thin film transistor may be a bottom-gate thin film transistor, and the reflective layer is disposed on the side of the interlayer insulating layer and the gate insulating layer facing the transparent region.
  • the reflective layer can reflect external light (including visible light and ultraviolet light) irradiated from the transparent area to the thin film transistor, significantly reducing the influence of light on the thin film transistor, and when the material forming the active layer includes an oxide semiconductor The electron migration of the active layer is hardly affected by light, which effectively guarantees the stability of the thin film transistor.
  • FIGS. 3 to 5 illustrate the present application by taking the top-gate thin film transistor as an example, and cannot be understood as a limitation to the present application.
  • the orthographic projection of the reflective layer 1121 on the substrate and the interlayer insulating layer 30 partially overlap, so that the structural stability of the reflective layer is higher, the service life is longer, and the reflection effect is better.
  • the thin film transistor 110 has two sides facing the transparent region 120, and the interlayer insulating layer and the gate insulating layer in the thin film transistor 110 may be provided with reflective layers facing the sides of the transparent region 120 on both sides 1121, to reduce the effect of light on the thin film transistor.
  • the material forming the reflective layer includes metal.
  • the reflective layer can be formed from a wide range of materials, which can effectively reflect visible light, ultraviolet light (UV), etc., thereby significantly reducing the impact of light on the active layer, so that the thin film transistor can maintain a high yield during long-term use .
  • the above metals include gold, silver, aluminum, copper, and the like. As a result, the material source is wide and the effect of reflecting light is excellent.
  • the light blocking member 112 further includes an ultraviolet blocking wall 1122 that is disposed on the outer peripheral wall of the reflective layer 1121. Therefore, since the ultraviolet blocking wall has the function of absorbing ultraviolet light, it can effectively absorb ultraviolet light, making the light blocking member block ultraviolet light more effectively, realize the all-round protection of the active layer, and protect the thin film transistor better and more effectively. The service life of the thin film transistor can be prolonged, which is more conducive to extending the service life of the substrate.
  • the material forming the ultraviolet blocking wall includes a material having a transmittance lower than 20% (for example, 20%, 15%, 10%, 5%, etc.). Therefore, the ultraviolet barrier wall has a low transmittance of ultraviolet light, which is beneficial to block ultraviolet light from irradiating the thin film transistor, and the effect of protecting the active layer is better.
  • the material forming the ultraviolet blocking wall includes a polyimide-based organic material. Therefore, the materials have a wide range of sources, the transmittance of ultraviolet light is low, the effect of blocking ultraviolet light from irradiating the thin film transistor is better, and the effect of protecting the thin film transistor is better.
  • a blocking wall 113 is further provided in the light emitting area 110, the blocking wall 113 is located on a side of the reflective layer 1121 near the transparent area 120, and the ultraviolet blocking wall 1122 is located in the gap between the reflective layer 1121 and the retaining wall 113.
  • the retaining wall can reduce defect intrusion or water vapor intrusion. More specifically, the retaining wall can reduce the intrusion of defects or moisture intrusion caused by the incomplete curing of the outer encapsulant, so that the problems generated when the encapsulant is not fully cured can reach the light emitting area as little as possible, reducing the loss of the light emitting area. And filling the gap between the reflective layer and the barrier wall with the ultraviolet barrier wall can further reduce the damage of the ultraviolet light to the thin film transistor.
  • the width of the retaining wall is less than 3 microns (for example, 3 microns, 2.5 microns, 2 microns, 1.5 microns, etc.), thereby, the retaining wall reduces defect intrusion or moisture intrusion caused by incomplete curing of the external encapsulant In this way, the problems caused when the encapsulant is not cured completely reach the light emitting area as little as possible, and the effect of reducing the loss of the light emitting area is better.
  • the width of the retaining wall is too large, it will affect the transparency effect of the substrate.
  • the retaining wall 113 includes a first sublayer 1131, a second sublayer 1132 and a third sublayer 1133 from bottom to top.
  • the retaining wall can reduce the intrusion of defects or moisture intrusion caused by the incomplete curing of the external encapsulant, so that the problems caused by the incomplete curing of the encapsulant can reach the light emitting area as little as possible, and the effect of reducing the loss of the light emitting area is better.
  • the first sublayer, the second sublayer, and the third sublayer may be formed separately, or may be formed simultaneously with other processes, respectively.
  • the first sublayer 1131 of the retaining wall and the buffer layer 10 in the thin film transistor 111 are formed by one patterning process, and / or the second sublayer 1132 and the gate insulating layer 20 are formed by one patterning process , And / or the third sublayer 1133 and the interlayer insulating layer 30 are formed by one patterning process.
  • the manufacturing process of the retaining wall can be effectively simplified by one patterning process, which is beneficial to reduce the production cost.
  • materials for forming the buffer layer include but are not limited to silicon oxide, etc .; materials for forming the gate insulating layer include but are not limited to polymethyl methacrylate, polyvinyl phenol, etc .; Materials include but are not limited to resin and the like. Therefore, the materials are widely available, the price is low, and the performance is good. It should be noted that the description “upper” used herein refers to the direction of the substrate toward the user during use, and “lower” refers to the direction of the substrate away from the user during use.
  • the distance L1 between the reflective layer 1121 and the retaining wall 113 is 2-3 microns (eg, 2 microns, 2.2 microns, 2.4 microns, 2.6 microns, 2.8 microns, 3 Micron, etc.).
  • the distance between the reflective layer and the retaining wall is too large, it will reduce the area occupied by the transparent area and reduce the overall transmittance of the pixel.
  • the distance between the reflective layer and the retaining wall refers to the maximum distance between the reflective layer and the retaining wall in the direction from the light-emitting area to the transparent area.
  • the blocking wall 113 is formed after etching the buffer layer 10, the gate insulating layer 20 and the interlayer insulating layer 30, and is formed between the thin film transistor 111 and the blocking wall 113 ⁇ 114 ⁇ The groove 114.
  • the grooves are arranged to make the width of the light-emitting area wider than the width of the light-emitting area in the prior art (for example, 5 microns)
  • the groove can be used to separate the light-emitting area and the transparent area, and Filling the groove with a material with low transmittance can block the light from entering the thin film transistor, reduce the loss of the thin film transistor, improve the product yield, and extend the product life.
  • the shape of the groove is not particularly limited, as long as the requirements can be met, those skilled in the art can flexibly choose according to actual needs.
  • the cross-sectional shape of the groove may be rectangular or trapezoidal.
  • the method of forming the groove includes but is not limited to etching, etc. The operation is simple, convenient, and easy to implement.
  • the shape of the retaining wall is not particularly limited, as long as the requirements can be met, those skilled in the art can flexibly choose according to actual needs.
  • the cross-sectional shape of the retaining wall may be rectangular or trapezoidal.
  • the reflective layer 1121 may also cover at least a part of the side surface of the barrier wall 113 toward the thin film transistor 111, whereby the reflective layer reflects the external light better and protects the active layer better .
  • the light emitting region further includes: a flat layer 130 covering the thin film transistor 111 and the reflective layer 1121, and at least a part of the flat layer 130 is formed
  • the ultraviolet blocking wall 1122 is formed through a one-step process, which effectively simplifies the manufacturing process and reduces the production cost; and the entire flat layer and the UV blocking wall are formed of the same material, which can further improve the effect of blocking UV light transmission and effectively achieve The effect of protecting the active layer in all directions.
  • the light emitting region 1 further includes a passivation layer 140 that is located between the flat layer 130 and the thin film transistor 111 and covers the source 81 of the thin film transistor 111, The drain 82 and the partially reflective layer 1121.
  • the passivation layer can effectively block water and oxygen, and effectively protect the thin film transistor.
  • the structure of the substrate is explained by taking the thin-film transistor in the light-emitting region as a top-gate thin-film transistor as an example. It should be noted that the following description is only used to explain the present application and cannot be understood as a Application restrictions. Specifically, referring to FIG.
  • the substrate includes: a plurality of pixel units, where each pixel unit includes a light-emitting region 110 and a transparent region 120, wherein the light-emitting region 110 includes: a substrate 40; and a shield layer (shield) 50 disposed on the substrate 40 Buffer layer (buffer) 10, which is disposed on the first surface of the substrate 40 and covers the barrier layer 50; active layer (ACT) 60, which is disposed on the surface of the buffer layer 10 away from the substrate 40; gate insulation A layer (GI) 20 is provided on the surface of the buffer layer away from the substrate 40 and covers the active layer 60; a gate (Gate) 70 is provided on the surface of the gate insulating layer 20 away from the substrate 40; an interlayer insulating layer (ILD) 30, disposed on the surface of the gate insulating layer 20 away from the substrate 40 and covering the gate 70; the source 81 and the drain 82, disposed on the surface of the interlayer insulating layer 30 away from the substrate 40, the source 81 and the drain 82 pass The
  • the blocking layer (the forming material may be metal, etc.) can effectively block the external light incident from the substrate side, reduce the impact on the active layer, and the light incident from the transparent region has less effect on the thin film transistor.
  • the source electrode and the drain electrode are electrically connected to the conductive region of the active layer, and the conductive region of the active layer is not shown in the figure.
  • the light-emitting area further includes a pixel-defining layer (PDL) disposed on a surface of the flat layer away from the substrate; an anode (Anode) is provided in the light-emitting area and is located in a gap defined by the pixel-defining layer; The layer is provided on the surface of the anode away from the substrate; the cathode is provided on the surface of the light-emitting layer away from the substrate and covers the light-emitting layer and the pixel defining layer.
  • PDL pixel-defining layer
  • Anode anode
  • the layer is provided on the surface of the anode away from the substrate
  • the cathode is provided on the surface of the light-emitting layer away from the substrate and covers the light-emitting layer and the pixel defining layer.
  • the present disclosure provides a transparent display device.
  • the transparent display device includes the aforementioned substrate. The inventor found that the transparent display device can maintain a very high display quality during long-term use, and the product yield is high, which can satisfy the consumer's consumption experience.
  • the transparent display device may also include a structure such as a package structure, a wiring, and the like, which will not be described in detail here.
  • the present disclosure provides a method of manufacturing the aforementioned substrate.
  • the method includes: forming a plurality of pixel units, at least part of the pixel units including a light emitting region and a transparent region; wherein forming at least part of the pixel units includes forming a thin film transistor in the light emitting region And a light-blocking component, the light-blocking component is used to block the influence of external light on the thin film transistor toward the transparent area.
  • the light blocking member includes a reflective layer, and the reflective layer may be formed separately or simultaneously with other processes.
  • the reflective layer and the source and drain in the thin film transistor are formed by one patterning process.
  • the manufacturing process can be simplified and the production cost can be reduced.
  • the reflective layer may not be formed by a patterning process with the source and drain of the thin film transistor, specifically, the source and drain may be formed first and then the reflective layer may be formed, or may be formed first The reflective layer then forms the source and drain. Thereby, there are various methods for preparing the reflective layer, and the prepared reflective layer is excellent in protecting the active layer.
  • forming at least part of the pixel unit further includes the step of forming a barrier wall in the light-emitting area, the barrier wall including a first sublayer, a second sublayer, and a third sublayer from bottom to top, wherein, the first sublayer and the buffer layer in the thin film transistor are formed by one patterning process; the second sublayer and the gate insulating layer in the thin film transistor are formed by one patterning process; and the third sublayer The interlayer insulating layer in the thin film transistor is formed by one patterning process.
  • the manufacturing process can be simplified and the production cost can be reduced.
  • forming at least part of the pixel unit further includes a step of forming a flat layer in the light-emitting area, the flat layer and the ultraviolet blocking wall in the light blocking member are formed by a one-step process, specifically , Coating the material forming the flat layer on the surface of the thin film transistor and the reflective layer, and filling the material in the gap between the reflective layer and the retaining wall and covering the retaining wall, the flat layer can be obtained after drying the material .
  • the manufacturing process can be simplified and the production cost can be reduced; and the entire flat layer is formed of the same material as the ultraviolet blocking wall, which can further improve the effect of blocking ultraviolet light transmission and effectively realize the effect of protecting the active layer in all directions.
  • the thin-film transistor in the light-emitting region as a top-gate thin-film transistor as an example to describe the steps of forming the light-emitting region
  • the steps of forming the pixel unit include:
  • a whole layer of first metal layer is deposited on the first surface of the substrate in the thin film transistor, and the first metal layer is etched to obtain a barrier layer;
  • a whole layer of first insulating layer is coated on the first surface of the substrate, and the first insulating layer is dried to form a buffer layer, and the buffer layer covers the barrier layer;
  • a whole layer of semiconductor layer is formed on the surface of the buffer layer away from the substrate by deposition or sputtering, and the semiconductor layer is etched to obtain an active layer;
  • a whole layer of a second insulating layer is coated on the surface of the buffer layer away from the substrate, the second insulating layer is dried to form a gate insulating layer, and the gate insulating layer covers the active layer;
  • a third insulating layer is coated on the surface of the gate insulating layer away from the substrate, and the third insulating layer is dried to form an interlayer insulating layer, and the interlayer insulating layer covers the gate;
  • a whole third metal layer is formed on the surface of the interlayer insulating layer away from the substrate by deposition or sputtering.
  • the metal material is connected to the active layer through the via
  • the third metal layer covers the side of the buffer layer, the gate insulating layer and the interlayer insulating layer of the thin film transistor facing the transparent region, and the third metal layer is etched to obtain the source electrode, the drain electrode and the reflective layer, and the The reflective layer covers the side of the buffer layer, the gate insulating layer and the interlayer insulating layer of the thin film transistor facing the transparent region and extends to a part of the surface of the interlayer insulating layer away from the substrate;
  • a whole layer of a fourth insulating layer is coated on the surface of the interlayer insulating layer away from the substrate, and the fourth insulating layer is dried to form a passivation layer;
  • a whole layer of a fifth insulating layer is coated on the surface of the passivation layer away from the substrate, the fifth insulating layer is dried to form a flat layer, and the flat layer covers the source electrode, the drain electrode, and the reflective layer And the retaining wall, and fill the gap between the reflective layer and the retaining wall.
  • the step of forming the pixel unit includes:
  • a whole layer of first metal layer is deposited on the first surface of the substrate in the thin film transistor, and the first metal layer is etched to obtain a barrier layer;
  • a whole layer of a first insulating layer is coated on the first surface of the substrate, and the first insulating layer is dried to form a buffer layer, and the buffer layer covers the barrier layer;
  • a whole layer of semiconductor layer is formed on the surface of the buffer layer away from the substrate by deposition or sputtering, and the semiconductor layer is etched to obtain an active layer;
  • a whole layer of a second insulating layer is coated on the surface of the buffer layer away from the substrate, the second insulating layer is dried to form a gate insulating layer, and the gate insulating layer covers the active layer;
  • a third insulating layer is coated on the surface of the gate insulating layer away from the substrate, and the third insulating layer is dried to form an interlayer insulating layer, and the interlayer insulating layer covers the gate;
  • a whole third metal layer is formed on the surface of the interlayer insulating layer away from the substrate by deposition or sputtering.
  • the metal material is connected to the active layer through the via
  • the third metal layer covers the side of the buffer layer, the gate insulating layer and the interlayer insulating layer of the thin film transistor facing the transparent region, and the third metal layer is etched to obtain the source electrode, the drain electrode and the reflective layer, and the The reflective layer covers the side of the buffer layer, the gate insulating layer and the interlayer insulating layer of the thin film transistor facing the transparent region and extends to a part of the surface of the interlayer insulating layer away from the substrate;
  • a whole layer of a fourth insulating layer is coated on the surface of the interlayer insulating layer away from the substrate, and the fourth insulating layer is dried to form a passivation layer;
  • a whole layer of a fifth insulating layer is coated on the surface of the passivation layer away from the substrate, the fifth insulating layer is dried to form a flat layer, and the flat layer covers the source electrode, the drain electrode and the reflective layer .
  • external light irradiated from the transparent area to the light-emitting area may affect the electron migration of the active layer of the thin film transistor, thereby making the thin film transistor less stable in light, Short service life.
  • the transparent display device in this application Under the premise of ensuring the area of the transparent area, as many light blocking materials as possible, such as blocking layers, light blocking components, etc., can be selected to further improve the product yield and performance of the transparent display device.
  • first and second are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.
  • the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more, unless otherwise specifically limited.
  • first feature "above” or “below” the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly intermediary contact.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Geometry (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

提供了基板及其制作方法以及透明显示装置。其中，基板包括：多个像素单元，至少部分所述像素单元包括发光区（110）和透明区（120），所述发光区（110）包括薄膜晶体管（111）；挡光部件（112），所述挡光部件（112）设置在所述发光区（110）中，用于阻挡通过所述透明区（120）射向所述薄膜晶体管（111）的光线。

Description

基板及其制作方法以及透明显示装置
相关申请的交叉引用
本申请要求于2018年11月1日提交的名称为“基板及其制作方法以及透明显示装置”的中国专利申请第201811296849.2号的优先权，该申请的公开通过引用被全部结合于此。
技术领域
本公开涉及显示技术领域，具体的，涉及基板及其制作方法以及透明显示装置。
背景技术
目前，显示装置正以日益多样化和新颖的形式出现在显示市场和大众的日常生活中，例如正在向超高分辨率发展的液晶显示(LCD)装置，广泛用于手机、Pad等便携设备的中小尺寸有机发光显示(OLED)装置，日趋成熟的用于电视(TV)的大尺寸OLED显示装置，以及新颖的显示技术如透明显示装置等；其中透明显示装置获得了良好的用户体验，具有广阔的市场前景。
发明内容
然而，在制作透明显示装置时，为追求透明的显示效果，会在保证发光区面积的前提下，尽可能的使透明区面积最大化，或采用透过率较高的材料，因此，难免遇到选材与器件性能相矛盾的情况，如何取舍一直在困扰制造商。
因而，目前的透明显示装置仍有待改进。
本公开旨在至少在一定程度上解决相关技术中的技术问题之一。为此，本公开的一个目的在于提出一种结构简单、易于实现，器件性能佳，良率高，或者在使用过程中薄膜晶体管中的有源层的高温光照负偏压稳定性(NBTIS)几乎不会变差的基板或透明显示装置。
在本公开的一个方面，本公开提供了一种基板。根据本公开的实施例，该基板包括：多个像素单元，至少部分所述像素单元包括发光区和透明区，所述发光区中包括薄膜晶体管；挡光部件，所述挡光部件设置在所述发光区中，用于阻挡通过所述透明区射向所述薄膜晶体管的光线。发明人发现，该基板结构简单、易于实现，挡光部件可以有效减少光线照射到薄膜晶体管，尤其适于阻挡光线从透明区侧向照射到薄膜晶体管，使得薄膜晶体管中的有源层得到有效保护，显著减少由于光线(尤其是紫外光)的照射造成的有源层的NBTIS变差的问题，从而有效保证了薄膜晶体管的稳定性，使得含有该基板的透明显示装置在长期使用过程中均能保持较高的良率，利于满足消费者的消费体验。
根据本公开的实施例，所述挡光部件包括反射层，所述薄膜晶体管包括多层绝缘层，所述反射层至少覆盖在所述多层绝缘层中至少部分绝缘层朝向所述透明区的侧面上。
根据本公开的实施例，所述绝缘层包括层间绝缘层和栅极绝缘层，或者所述绝缘层包括层间绝缘层。
根据本公开的实施例，所述反射层在基板上的正投影与层间绝缘层在基板上的正投影部分交叠。
根据本公开的实施例，形成所述反射层的材料包括金属。
根据本公开的实施例，所述挡光部件还包括紫外阻挡墙，所述紫外阻挡 墙位于所述发光区中，且位于所述反射层靠近所述透明区的一侧。
根据本公开的实施例，所述发光区中还设置有挡墙，所述挡墙位于所述反射层靠近所述透明区的一侧，所述紫外阻挡墙位于所述反射层和所述挡墙之间的间隙中。
根据本公开的实施例，所述挡墙由下至上包括第一亚层、第二亚层和第三亚层。
根据本公开的实施例，所述反射层与所述挡墙之间的间距为2-3微米。
根据本公开的实施例，所述反射层覆盖所述挡墙朝向所述薄膜晶体管的至少部分侧面。
根据本公开的实施例，所述发光区还包括：平坦层，所述平坦层覆盖所述薄膜晶体管和所述反射层，所述平坦层的至少一部分构成所述紫外阻挡墙。
根据本公开的实施例，形成所述紫外阻挡墙的材料包括透过率低于20％的材料。
根据本公开的实施例，形成所述紫外阻挡墙的材料包括聚酰亚胺类有机材料。
根据本公开的实施例，所述挡光部件还包括第二反射层，所述第二反射层至少覆盖在所述多层绝缘层中至少部分绝缘层朝向相邻的像素单元中的透明区的侧面上。
在本公开的另一方面，本公开提供了一种透明显示装置。根据本公开的实施例，该透明显示装置包括前面所述的基板。发明人发现，该透明显示装置在长期使用过程中均能保持很高的显示质量，产品良率高，可以满足消费者的消费体验。
在本公开的另一方面，本公开提供了一种制作前面所述的基板的方法。 根据本公开的实施例，该方法包括：形成所述多个像素单元；其中，形成至少部分所述像素单元包括：在所述发光区中形成薄膜晶体管和挡光部件。发明人发现，该制作方法操作简单、方便，易于实现，成本低，其可以获得具备前面所有所述的特征和优点的基板。
根据本公开的实施例，所述反射层与所述薄膜晶体管中的源极和漏极通过一次构图工艺形成。
根据本公开的实施例，形成至少部分所述像素单元还包括形成挡墙的步骤，其中，所述第一亚层与所述薄膜晶体管中的缓冲层通过一次构图工艺形成；所述第二亚层与所述薄膜晶体管中的栅绝缘层通过一次构图工艺形成；所述第三亚层与所述薄膜晶体管中的层间绝缘层通过一次构图工艺形成。
根据本公开的实施例，形成至少部分所述像素单元还包括形成平坦层的步骤，所述平坦层的一部分填充在所述反射层与所述挡墙之间的间隙中，且填充在所述间隙中的所述平坦层的所述一部分构成紫外阻挡墙。
附图说明
图1是现有技术中基板的结构示意图。
图2是本公开一些实施例中的基板的俯视图。
图3是图2中沿AA’方向的剖面结构示意图。
图4是本公开一些实施例中的基板的结构示意图。
图5是本公开一些实施例中的基板的结构示意图。
图6是本公开一些实施例中的基板的俯视图。
图7是本公开一些实施例中的基板的结构示意图。
图8是本公开一些实施例中的基板的结构示意图。
具体实施方式
下面详细描述本公开的实施例。下面描述的实施例是示例性的，仅用于解释本公开，而不能理解为对本公开的限制。实施例中未注明具体技术或条件的，按照本领域内的文献所描述的技术或条件或者按照产品说明书进行。
本公开是根据发明人的以下认识和发现而完成的：
在透明显示装置中，如图1所示，由于透明区120的存在，以及透明显示装置使用的环境，会有大量的外界光线从透明区120射入发光区110，进而会造成侧向的光线(例如UV)导致发光区中薄膜晶体管111中的有源层60(ACT层)电子迁移受影响，最终使得薄膜晶体管(TFT)111器件稳定性受损。针对上述技术问题，发明人进行了深入的研究，研究后发现，可以在发光区中设置挡光部件，以阻挡外界射向透明区的光线对薄膜晶体管的影响。
有鉴于此，在本公开的一个方面，本公开提供了一种基板。根据本公开的实施例，参照图2和图3，该基板包括：多个像素单元100，至少部分所述像素单元100包括发光区110和透明区120，所述发光区110包括薄膜晶体管111；挡光部件112，所述挡光部件112设置在所述发光区110中，用于阻挡通过所述透明区射向所述薄膜晶体管的光线。发明人发现，该基板结构简单、易于实现，挡光部件可以有效减少光线照射到薄膜晶体管，尤其适于阻挡外界光线从透明区侧向照射到薄膜晶体管，使得薄膜晶体管中的有源层得到有效保护，显著减少由于光线(尤其是紫外光)的照射造成的有源层的NBTIS变差的问题，从而有效保证了薄膜晶体管的光照稳定性，且基板在长期使用过程中均能保持较高的良率，利于满足消费者的消费体验。可以理解的是，参照图2，栅线2和数据线1交叉设置限定出多个像素单元100。需要说明的 是，本文中采用的描述方式“发光区”包括薄膜晶体管和发光元件，其中，薄膜晶体管与发光元件的设置方式与常规像素单元中的薄膜晶体管与发光元件的设置方式相同，即发光元件对应常规像素单元的开口区设置，而薄膜晶体管对应常规像素单元中的开口区之外的区域设置，在本文的附图中均未示出发光元件；上述至少部分像素单元包括发光区和透明区指的是：1、全部像素单元均包括发光区和透明区；2、一部分像素单元包括发光区和透明区，另一部分像素单元不包括透明区；例如在阵列排布的像素单元中，其中一排像素单元包括发光区和透明区，另一排像素单元不包括透明区。
根据本公开的实施例，薄膜晶体管中的有源层的形成材料为氧化物半导体时，其极易受到光线的损伤造成电子迁移，使得薄膜晶体管的性能下降，因此，本申请的上述发光区的结构有利于减少外界光线进入薄膜晶体管，从而保证薄膜晶体管的使用性能。
根据本公开的实施例，薄膜晶体管可以为顶栅(Top Gate)型薄膜晶体管、底栅型薄膜晶体管、背沟道刻蚀型(BCE)薄膜晶体管以及刻蚀阻挡结构(ESL)薄膜晶体管等，由此，使用范围较广。
根据本公开的实施例，所述挡光部件包括反射层，所述薄膜晶体管包括多层绝缘层，所述反射层至少覆盖在所述多层绝缘层中至少部分绝缘层朝向所述透明区的侧面上。在本公开的一些实施例中，所述绝缘层包括层间绝缘层和栅极绝缘层或层间绝缘层，也就是说，反射层可以至少覆盖在所述薄膜晶体管中层间绝缘层朝向所述透明区的侧面上，或者反射层可以至少覆盖在所述薄膜晶体管中层间绝缘层和栅绝缘层朝向所述透明区的侧面上。在本公开的一些实施例中，薄膜晶体管可以是顶栅型薄膜晶体管，参照图3-图5，所述挡光部件112包括反射层1121，所述反射层1121至少设置在所述薄膜晶 体管111中的层间绝缘层30和栅绝缘层20朝向透明区120的侧面上。在本公开的一些具体实施例中，顶栅型薄膜晶体管的栅绝缘层是以栅极为掩模版进行刻蚀形成的，在这种情况下，反射层设置在层间绝缘层朝向所述透明区的侧面上。在本公开的另一些实施例中，薄膜晶体管可以为底栅型薄膜晶体管，反射层设置在层间绝缘层和栅绝缘层朝向所述透明区的侧面上。由此，反射层可以反射从透明区照射向薄膜晶体管的外界光线(包括可见光和紫外光等)，显著降低光线对薄膜晶体管的影响，进而当形成有源层的材料包括氧化物半导体时可以使得有源层的电子迁移几乎不受光线的影响，有效保证了薄膜晶体管的稳定性。需要说明的是，图3-图5是以顶栅型薄膜晶体管为例进行说明本申请的，而不能理解为对本申请的限制。
根据本公开的实施例，参照图3-图5，为了使得反射层1121在使用过程中具备较佳的结构稳定性，所述反射层1121在基板上的正投影与所述层间绝缘层30在基板上的正投影部分地交叠，由此，反射层的结构稳定性更高，使用寿命更长，反射效果也更好。
在本公开的一些实施例中，参照图6，薄膜晶体管110有两侧朝向透明区120，薄膜晶体管110中的层间绝缘层和栅绝缘层朝向两侧透明区120的侧面均可设置反射层1121，以减少光线对薄膜晶体管的影响。
根据本公开的实施例，为了使得反射层反射光线的效果更好，形成所述反射层的材料包括金属。由此，反射层的形成材料来源广泛，可以有效反射可见光、紫外光(UV)等，进而显著降低光线对有源层的影响，使得薄膜晶体管在长期使用过程中均能保持较高的良率。在本公开的一些实施例中，上述金属包括金、银、铝、铜等。由此，材料来源广泛，反射光线的效果优异。
根据本公开的实施例，参照图5，所述挡光部件112还包括紫外阻挡墙 1122，所述紫外阻挡墙1122设置在所述反射层1121的外周壁上。由此，由于紫外阻挡墙具有吸收紫外光的作用，可以有效吸收紫外光，使得挡光部件阻挡紫外光的效果更佳，实现有源层的全方位保护，保护薄膜晶体管的效果更佳，更能延长薄膜晶体管的使用寿命，进而更有利于延长基板的使用寿命。
根据本公开的实施例，形成所述紫外阻挡墙的材料包括透过率低于20％(例如20％、15％、10％、5％等)的材料。由此，紫外阻挡墙对紫外光的透过率较低，有利于阻挡紫外光照射到薄膜晶体管，保护有源层的效果较佳。
根据本公开的实施例，形成所述紫外阻挡墙的材料包括聚酰亚胺类有机材料。由此，材料来源广泛，对紫外光的透过率较低，阻挡紫外光照射到薄膜晶体管的效果更佳，保护薄膜晶体管的效果更佳。
根据本公开的实施例，参照图5，所述发光区110中还设置有挡墙113，所述挡墙113位于所述反射层1121靠近所述透明区120的一侧，所述紫外阻挡墙1122位于所述反射层1121和所述挡墙113之间的间隙中。由此，挡墙可以减少缺陷入侵或者水汽入侵。更具体而言，挡墙可以减少外部封装(filler)胶未完全固化导致的缺陷入侵或者水汽入侵，使得封装胶未固化完全时产生的问题尽量少的波及到发光区，减少发光区的损失。并且将紫外阻挡墙填充入反射层和挡墙之间的间隙可以进一步降低紫外光对薄膜晶体管的损害。
根据本公开的实施例，挡墙的宽度为小于3微米(例如3微米、2.5微米、2微米、1.5微米等)，由此，挡墙减少外部封装胶未完全固化导致的缺陷入侵或者水汽入侵，使得封装胶未固化完全时产生的问题尽量少的波及到发光区，减少发光区的损失的效果更佳。当挡墙的宽度过大时，则影响基板的透明效果。
根据本公开的实施例，参照图5，挡墙113由下至上包括第一亚层1131， 第二亚层1132和第三亚层1133。由此，挡墙可以减少外部封装胶未完全固化导致的缺陷入侵或者水汽入侵，使得封装胶未固化完全时产生的问题尽量少的波及到发光区，减少发光区的损失的效果更佳。根据本公开的实施例，第一亚层、第二亚层以及第三亚层可以单独形成，也可以分别与其他工艺同步形成。在本公开的一些实施例中，挡墙的第一亚层1131与薄膜晶体管111中的缓冲层10通过一次构图工艺形成，和/或第二亚层1132与栅绝缘层20通过一次构图工艺形成，和/或第三亚层1133与层间绝缘层30通过一次构图工艺形成。由此，通过一次构图工艺可以有效简化挡墙的制作工艺，有利于降低生产成本。在本公开的一些实施例中，形成缓冲层的材料包括但不限于氧化硅等；形成栅绝缘层的材料包括但不限于聚甲基丙烯酸甲酯和聚乙烯苯酚等；形成层间绝缘层的材料包括但不限于树脂等。由此，材料来源广泛，价格较低，使用性能佳。需要说明的是，本文中采用的描述“上”指的是使用时基板朝向用户的方向，“下”指的是使用时基板远离用户的方向。
根据本公开的实施例，参照图5，所述反射层1121与所述挡墙113之间的间距L1为2-3微米(例如2微米、2.2微米、2.4微米、2.6微米、2.8微米、3微米等)。由此，反射层与挡墙之间可以填充入尽量多的紫外阻挡墙，阻挡紫外光照射到反射层的效果更佳，进一步降低光线对有源层的影响，实现对有源层的全方位保护。当反射层与挡墙之间的间距过大时，则会减小透明区所占的面积，减少像素整体的透过率，当反射层与挡墙之间的间距过小时，则会使得挡墙的阻挡效果相对不佳。需要说明的是，反射层与挡墙之间的间距指的是在沿发光区至透明区的方向上反射层与挡墙之间连线的最大距离。
在本公开的一些实施例中，参照图5，挡墙113是将缓冲层10、栅绝缘层20和层间绝缘层30刻蚀之后形成的，且在薄膜晶体管111与挡墙113之 间形成凹槽114。由此，虽然凹槽的设置会使得发光区的宽度比现有技术中的发光区的宽度宽(例如5微米)，但是通过凹槽可以在发光区与透明区之间做出分隔，并将透过率低的材料填入凹槽中可以阻挡光线射入薄膜晶体管，减少薄膜晶体管的损失，提高产品良率，延长产品使用寿命。根据本公开的实施例，凹槽的形状没有特别限制，只要能够满足要求，本领域技术人员可以根据实际需要灵活选择。例如凹槽的截面形状可以为长方形、梯形等。根据本公开的实施例，形成凹槽的方法包括但不限于刻蚀等，操作简单、方便，易于实现。
根据本公开的实施例，挡墙的形状没有特别限制，只要能够满足要求，本领域技术人员可以根据实际需要灵活选择。例如挡墙的截面形状可以为长方形、梯形等。
根据本公开的实施例，参照图8，反射层1121还可以覆盖挡墙113朝向薄膜晶体管111的至少部分侧面，由此，反射层反射外界光线的效果更好，保护有源层的效果更佳。
根据本公开的实施例，参照图7，所述发光区中还包括：平坦层130，所述平坦层130覆盖所述薄膜晶体管111和所述反射层1121，所述平坦层130的至少一部分构成所述紫外阻挡墙1122。由此，紫外阻挡墙与平坦层可以通过一步工艺形成，有效简化制作工艺，降低生产成本；且整个平坦层与紫外阻挡墙的形成材料相同，可以进一步提高阻挡紫外光透过的效果，有效实现全方位保护有源层的效果。
根据本公开的实施例，参照图7，所述发光区1中还包括钝化层140，所述钝化层140位于平坦层130和薄膜晶体管111之间且覆盖薄膜晶体管111的源极81、漏极82和部分反射层1121。由此，钝化层可以有效起到阻隔水、 氧的作用，有效保护薄膜晶体管。
在本公开的一些具体实施例中，以发光区中的薄膜晶体管为顶栅型薄膜晶体管为例进行说明基板的结构，需要说明的是，以下描述仅用于解释本申请，而不能理解为对本申请的限制。具体的，参照图7，基板包括：多个像素单元，其中每个像素单元包括发光区110和透明区120，其中，发光区110包括：基底40；阻挡层(shield)50，设置在基底40的第一表面上；缓冲层(buffer)10，设置在基底40的第一表面上且覆盖阻挡层50；有源层(ACT)60，设置在缓冲层10远离基底40的表面上；栅绝缘层(GI)20，设置在缓冲层远离基底40的表面上且覆盖有源层60；栅极(Gate)70，设置在栅绝缘层20远离基底40的表面上；层间绝缘层(ILD)30，设置在栅绝缘层20远离基底40的表面上且覆盖栅极70；源极81和漏极82，设置在层间绝缘层30远离基底40的表面上，源极81和漏极82通过过孔与有源层60电连接；反射层1121，设置在层间绝缘层30远离基底40的表面上，其中反射层1121与源极81和漏极82通过一次构图工艺形成；挡墙113，包括第一亚层1131、第二亚层1132和第三亚层1133，其中第一亚层1131与缓冲层10通过一次构图工艺形成，第二亚层1132与栅绝缘层20通过一次构图工艺形成，第三亚层1133与层间绝缘层30通过一次构图工艺形成；钝化层(PVX)140，设置在层间绝缘层30远离基底40的表面上且覆盖源极81、漏极82和反射层1121的部分表面；平坦层(或者树脂层)130，设置在基底40的第一表面上且覆盖钝化层140、反射层1121的部分表面和挡墙113，其中填充入反射层1121与挡墙113之间的间隙中的部分平坦层130同时作为紫外阻挡墙1122。由此，阻挡层(形成材料可以为金属等)可以有效阻挡从基底侧入射的外界光线，减少对有源层的影响，且从透明区入射的光线对薄膜晶体管的影响较小。需要说明的是， 源极、漏极与有源层的导体化区域电连接，图中未示出有源层的导体化区域。
根据本公开的实施例，发光区还包括像素界定层(PDL)，设置在平坦层远离基底的表面上；阳极(Anode)，设置在发光区中且位于像素界定层限定出的空隙中；发光层，设置在阳极远离基底的表面上；阴极，设置在发光层远离基底的表面上，且覆盖发光层和像素界定层。由此，可以有效实现发光区的发光功能。
在本公开的另一方面，本公开提供了一种透明显示装置。根据本公开的实施例，该透明显示装置包括前面所述的基板。发明人发现，该透明显示装置在长期使用过程中均能保持很高的显示质量，产品良率高，可以满足消费者的消费体验。
根据本公开的实施例，透明显示装置除了包括前面所述的基板之外，还可以包括封装结构、走线等结构，在此不再过多赘述。
在本公开的另一方面，本公开提供了一种制作前面所述的基板的方法。根据本公开的实施例，该方法包括：形成多个像素单元，至少部分所述像素单元包括发光区和透明区；其中，形成至少部分所述像素单元包括：在所述发光区中形成薄膜晶体管和挡光部件，所述挡光部件用于阻挡外界射向所述透明区的光线对所述薄膜晶体管的影响。发明人发现，该制作方法操作简单、方便，易于实现，成本低，且可以获得具备前面所有所述的特征和优点的基板。
根据本公开的实施例，所述挡光部件包括反射层，反射层可以单独形成，也可以与其他工艺同步形成。在本公开的一些实施例中，所述反射层与所述薄膜晶体管中的源极和漏极通过一次构图工艺形成。由此，可以简化制作工艺，降低生产成本。在本公开的另一些实施例中，反射层可以不与薄膜晶体 管中的源极和漏极通过一次构图工艺形成，具体的，可以先形成源极和漏极再形成反射层，或者可以先形成反射层再形成源极和漏极。由此，制备反射层的方法多样，且制备得到的反射层保护有源层的效果优异。
根据本公开的实施例，形成至少部分所述像素单元还包括在所述发光区中形成挡墙的步骤，所述挡墙由下至上包括第一亚层、第二亚层和第三亚层，其中，所述第一亚层与所述薄膜晶体管中的缓冲层通过一次构图工艺形成；所述第二亚层与所述薄膜晶体管中的栅绝缘层通过一次构图工艺形成；所述第三亚层与所述薄膜晶体管中的层间绝缘层通过一次构图工艺形成。由此，可以简化制作工艺，降低生产成本。需要说明的是，第一亚层、第二亚层、第三亚层与前面的描述一致，在此不再过多赘述。
根据本公开的实施例，形成至少部分所述像素单元还包括在所述发光区中形成平坦层的步骤，所述平坦层与所述挡光部件中的紫外阻挡墙通过一步工艺形成，具体的，将形成平坦层的材料涂覆在薄膜晶体管和反射层的表面上，并将该材料填充在反射层与挡墙之间的间隙中并覆盖挡墙，将该材料干燥之后即可得到平坦层。由此，可以简化制作工艺，降低生产成本；且整个平坦层与紫外阻挡墙的形成材料相同，可以进一步提高阻挡紫外光透过的效果，有效实现全方位保护有源层的效果。
在本公开的一些具体实施例中，以发光区中的薄膜晶体管为顶栅型薄膜晶体管为例进行说明形成发光区的步骤，需要说明的是，以下描述仅用于解释本申请，而不能理解为对本申请的限制。形成像素单元的步骤包括：
1、在薄膜晶体管中的基底的第一表面上沉积整层第一金属层，对所述第一金属层进行刻蚀处理以便得到阻挡层；
2、在所述基底的所述第一表面上涂覆整层第一绝缘层，所述第一绝缘层 干燥之后形成缓冲层，所述缓冲层覆盖所述阻挡层；
3、在所述缓冲层远离所述基底的表面上通过沉积或者溅射方法形成整层半导体层，对所述半导体层进行刻蚀处理得到有源层；
4、在所述缓冲层远离所述基底的表面上涂覆整层第二绝缘层，所述第二绝缘层干燥之后形成栅绝缘层，所述栅绝缘层覆盖所述有源层；
5、在所述栅绝缘层远离所述基底的表面上通过沉积或者溅射方法形成整层第二金属层，对所述第二金属层进行刻蚀处理得到栅极；
6、在所述栅绝缘层远离所述基底的表面上涂覆整层第三绝缘层，所述第三绝缘层干燥之后形成层间绝缘层，所述层间绝缘层覆盖所述栅极；
7、通过刻蚀方法形成贯穿所述层间绝缘层和所述栅绝缘层的两个过孔；
8、通过刻蚀方法形成贯穿所述缓冲层、所述栅绝缘层和所述层间绝缘层的凹槽，以形成挡墙；
9、在所述层间绝缘层远离所述基底的表面上通过沉积或者溅射方法形成整层第三金属层，在形成第三金属层的过程中，金属材料通过过孔与有源层连接，且第三金属层覆盖薄膜晶体管中缓冲层、栅绝缘层和层间绝缘层朝向透明区的侧面，对所述第三金属层进行刻蚀处理得到源极、漏极和反射层，且所述反射层覆盖所述薄膜晶体管中缓冲层、栅绝缘层和层间绝缘层朝向透明区的侧面并延伸至层间绝缘层远离基底的部分表面上；
10、在所述层间绝缘层远离所述基底的表面上涂覆整层第四绝缘层，所述第四绝缘层干燥之后形成钝化层；
11、在所述钝化层远离所述基底的表面上涂覆整层第五绝缘层，所述第五绝缘层干燥之后形成平坦层，且所述平坦层覆盖源极、漏极、反射层和挡墙，并填满反射层与挡墙之间的间隙。
在本公开的另一些具体实施例中，形成像素单元的步骤包括：
1、在薄膜晶体管中的基底的第一表面上沉积整层第一金属层，对所述第一金属层进行刻蚀处理以便得到阻挡层；
2、在所述基底的所述第一表面上涂覆整层第一绝缘层，所述第一绝缘层干燥之后形成缓冲层，所述缓冲层覆盖所述阻挡层；
3、在所述缓冲层远离所述基底的表面上通过沉积或者溅射方法形成整层半导体层，对所述半导体层进行刻蚀处理得到有源层；
4、在所述缓冲层远离所述基底的表面上涂覆整层第二绝缘层，所述第二绝缘层干燥之后形成栅绝缘层，所述栅绝缘层覆盖所述有源层；
5、在所述栅绝缘层远离所述基底的表面上通过沉积或者溅射方法形成整层第二金属层，对所述第二金属层进行刻蚀处理得到栅极；
6、在所述栅绝缘层远离所述基底的表面上涂覆整层第三绝缘层，所述第三绝缘层干燥之后形成层间绝缘层，所述层间绝缘层覆盖所述栅极；
7、通过刻蚀方法形成贯穿所述层件绝缘层和所述栅绝缘层的两个过孔；
8、在所述层间绝缘层远离所述基底的表面上通过沉积或者溅射方法形成整层第三金属层，在形成第三金属层的过程中，金属材料通过过孔与有源层连接，且第三金属层覆盖薄膜晶体管中缓冲层、栅绝缘层和层间绝缘层朝向透明区的侧面，对所述第三金属层进行刻蚀处理得到源极、漏极和反射层，且所述反射层覆盖所述薄膜晶体管中缓冲层、栅绝缘层和层间绝缘层朝向透明区的侧面并延伸至层间绝缘层远离基底的部分表面上；
9、在所述层间绝缘层远离所述基底的表面上涂覆整层第四绝缘层，所述第四绝缘层干燥之后形成钝化层；
10、在所述钝化层远离所述基底的表面上涂覆整层第五绝缘层，所述第 五绝缘层干燥之后形成平坦层，且所述平坦层覆盖源极、漏极和反射层。
根据本公开的实施例，在一般的透明显示装置中，从透明区照射至发光区的外界光线会使得薄膜晶体管的有源层的电子迁移受到影响，进而使得薄膜晶体管的光照稳定性不佳，使用寿命较短。而在本申请中，通过在发光区中设置挡光部件，可以有效降低外界光线对薄膜晶体管的影响，使得薄膜晶体管的光照稳定性强，使用性能优异，寿命长；且本申请中透明显示装置的结构可以在保证透明区面积的前提下，选用尽可能多的挡光材料，例如阻挡层、挡光部件等，进一步提高透明显示装置的产品良率和使用性能。
在本公开的描述中，需要理解的是，术语“宽度”、“上”、“下”、“前”、“后”、“左”、“右”、“顶”、“底”“内”、“外”、等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本公开中，除非另有明确的规定和限定，第一特征在第二特征“上”或“下”可以是第一和第二特征直接接触，或第一和第二特征通过中间媒介间接接触。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说 明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (19)

  1. 一种基板，包括：
    多个像素单元，至少部分所述像素单元包括发光区和透明区，所述发光区包括薄膜晶体管；
    挡光部件，所述挡光部件设置在所述发光区中，用于阻挡通过所述透明区射向所述薄膜晶体管的光线。
  2. 根据权利要求1所述的基板，其中，所述挡光部件包括反射层，所述薄膜晶体管包括多层绝缘层，所述反射层至少覆盖在所述多层绝缘层中至少部分绝缘层朝向所述透明区的侧面上。
  3. 根据权利要求2所述的基板，其中，所述绝缘层包括层间绝缘层和栅极绝缘层，或者所述绝缘层包括层间绝缘层。
  4. 根据权利要求3所述的基板，其中，所述反射层在所述基板上的正投影与所述层间绝缘层在所述基板上的正投影部分交叠。
  5. 根据权利要求2所述的基板，其中，形成所述反射层的材料包括金属。
  6. 根据权利要求2-5任一项所述的基板，其中，所述挡光部件还包括紫外阻挡墙，所述紫外阻挡墙位于所述发光区中，且位于所述反射层靠近所述透明区的一侧。
  7. 根据权利要求6所述的基板，其中，所述发光区中还设置有挡墙，所述挡墙位于所述反射层靠近所述透明区的一侧，所述紫外阻挡墙位于所述反射层和所述挡墙之间的间隙中。
  8. 根据权利要求7所述的基板，其中，所述挡墙由下至上包括第一亚层、第二亚层和第三亚层。
  9. 根据权利要求7所述的基板，其中，所述反射层与所述挡墙之间的间距为2-3微米。
  10. 根据权利要求7所述的基板，其中，所述反射层覆盖所述挡墙朝向所述薄膜晶体管的至少部分侧面。
  11. 根据权利要求6所述的基板，其中，所述发光区还包括：
    平坦层，所述平坦层覆盖所述薄膜晶体管和所述反射层，所述平坦层的至少一部分构成所述紫外阻挡墙。
  12. 根据权利要求6或者11所述的基板，其中，形成所述紫外阻挡墙的材料包括透过率低于20％的材料。
  13. 根据权利要求12所述的基板，其中，形成所述紫外阻挡墙的材料包括聚酰亚胺类有机材料。
  14. 根据权利要求2所述的基板，其中，所述挡光部件还包括第二反射层，所述第二反射层至少覆盖在所述多层绝缘层中至少部分绝缘层朝向相邻的像素单元中的透明区的侧面上。
  15. 一种透明显示装置，包括权利要求1-14任一项所述的基板。
  16. 一种制作权利要求1-14任一项所述的基板的方法，包括：
    形成所述多个像素单元；
    其中，形成至少部分所述像素单元包括：在所述发光区中形成薄膜晶体管和挡光部件。
  17. 根据权利要求16所述的方法，其中，所述反射层与所述薄膜晶体管中的源极和漏极通过一次构图工艺形成。
  18. 根据权利要求17所述的方法，其中，形成至少部分所述像素单元还包括形成挡墙的步骤，
    其中，所述第一亚层与所述薄膜晶体管中的缓冲层通过一次构图工艺形成；
    所述第二亚层与所述薄膜晶体管中的栅绝缘层通过一次构图工艺形成；
    所述第三亚层与所述薄膜晶体管中的层间绝缘层通过一次构图工艺形成。
  19. 根据权利要求18所述的方法，其中，形成至少部分所述像素单元还包括形成平坦层的步骤，所述平坦层的一部分填充在所述反射层与所述挡墙之间的间隙中，且填充在所述间隙中的所述平坦层的所述一部分构成紫外阻挡墙。
PCT/CN2019/111176 2018-11-01 2019-10-15 基板及其制作方法以及透明显示装置 WO2020088236A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/649,854 US11239259B2 (en) 2018-11-01 2019-10-15 Substrate, manufacturing method thereof and transparent display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811296849.2A CN109360849B (zh) 2018-11-01 2018-11-01 基板及其制作方法以及透明显示装置
CN201811296849.2 2018-11-01

Publications (1)

Publication Number Publication Date
WO2020088236A1 true WO2020088236A1 (zh) 2020-05-07

Family

ID=65343852

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/111176 WO2020088236A1 (zh) 2018-11-01 2019-10-15 基板及其制作方法以及透明显示装置

Country Status (3)

Country Link
US (1) US11239259B2 (zh)
CN (1) CN109360849B (zh)
WO (1) WO2020088236A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109360849B (zh) * 2018-11-01 2021-01-29 京东方科技集团股份有限公司 基板及其制作方法以及透明显示装置
CN109859649B (zh) 2019-04-09 2021-01-26 京东方科技集团股份有限公司 一种透明显示面板及其制备方法和显示装置
CN110265583B (zh) * 2019-07-26 2022-08-12 京东方科技集团股份有限公司 一种显示面板及其制备方法、显示装置
CN110808276A (zh) * 2019-11-27 2020-02-18 深圳市华星光电半导体显示技术有限公司 一种oled显示面板及其制备方法、oled显示装置
CN110957346B (zh) * 2019-11-29 2022-09-23 维沃移动通信有限公司 显示模组及电子设备
KR20210074494A (ko) * 2019-12-12 2021-06-22 엘지디스플레이 주식회사 폴리이미드 기판 및 디스플레이 장치

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140069896A (ko) * 2012-11-30 2014-06-10 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 그를 이용한 디스플레이 장치
CN106887523A (zh) * 2015-11-20 2017-06-23 三星显示有限公司 有机发光显示器及其制造方法
US20180013092A1 (en) * 2016-07-05 2018-01-11 Samsung Display Co., Ltd. Flexible display apparatus
CN107706208A (zh) * 2016-08-08 2018-02-16 三星显示有限公司 有机发光二极管显示器
CN107958916A (zh) * 2016-10-14 2018-04-24 三星显示有限公司 显示装置
CN109360849A (zh) * 2018-11-01 2019-02-19 京东方科技集团股份有限公司 基板及其制作方法以及透明显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10205122B2 (en) 2015-11-20 2019-02-12 Samsung Display Co., Ltd. Organic light-emitting display and method of manufacturing the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140069896A (ko) * 2012-11-30 2014-06-10 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 그를 이용한 디스플레이 장치
CN106887523A (zh) * 2015-11-20 2017-06-23 三星显示有限公司 有机发光显示器及其制造方法
US20180013092A1 (en) * 2016-07-05 2018-01-11 Samsung Display Co., Ltd. Flexible display apparatus
CN107706208A (zh) * 2016-08-08 2018-02-16 三星显示有限公司 有机发光二极管显示器
CN107958916A (zh) * 2016-10-14 2018-04-24 三星显示有限公司 显示装置
CN109360849A (zh) * 2018-11-01 2019-02-19 京东方科技集团股份有限公司 基板及其制作方法以及透明显示装置

Also Published As

Publication number Publication date
CN109360849A (zh) 2019-02-19
US20200235138A1 (en) 2020-07-23
CN109360849B (zh) 2021-01-29
US11239259B2 (en) 2022-02-01

Similar Documents

Publication Publication Date Title
WO2020088236A1 (zh) 基板及其制作方法以及透明显示装置
US10930887B2 (en) Flexible organic light emitting display device having a dam in a folding region
US10930719B2 (en) Array substrate, method of making array substrate and display device having sub-pixels with transparent etching layer
WO2019223682A1 (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
WO2019109674A1 (zh) 阵列基板、显示面板、显示装置及其制作方法
US9331309B2 (en) Display apparatus, method for manufacturing display apparatus, and method for designing display apparatus
WO2020206721A1 (zh) 显示面板及制作方法、显示模组
EP3242341A1 (en) Array substrate and manufacturing method therefor, display panel and display device
US11785802B2 (en) Display panel and display device provided with heat conducting layer
US8895971B2 (en) Organic light emitting display device and method for fabricating the same
US20160334682A1 (en) Color Filter on Array Substrate and Method for Manufacturing the same, as well as Display Device
CN110968218B (zh) 触控显示面板及其制备方法
US8183769B2 (en) Organic electroluminescent display unit and method for fabricating the same
US10062868B2 (en) Pixel structure and manufacturing method thereof
KR102182482B1 (ko) 산화물 반도체 박막 트랜지스터 및 이를 구비한 표시장치용 어레이 기판
KR102651358B1 (ko) 미러 기판의 제조 방법 및 이를 갖는 표시 장치
WO2020056865A1 (zh) 显示面板及显示装置
US9608118B2 (en) Array substrate, display device and manufacturing method of array substrate
US20150129857A1 (en) Organic light emitting diode display device and method of fabricating the same
US10693015B2 (en) Thin film transistor, method for manufacturing the same and display device comprising the same
KR20150042989A (ko) 유기 발광 다이오드 디스플레이 장치 및 이의 제조 방법
TW201322430A (zh) 薄膜電晶體陣列及其線路結構
CN111415963B (zh) 显示面板及其制备方法
TWI297210B (en) System for displaying images including electroluminescent device and method for fabricating the same
CN110137233B (zh) 阵列基板及其制备方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19879920

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19879920

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 19879920

Country of ref document: EP

Kind code of ref document: A1