WO2020077718A1 - 一种阵列基板及其制作方法、显示模组 - Google Patents

一种阵列基板及其制作方法、显示模组 Download PDF

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Publication number
WO2020077718A1
WO2020077718A1 PCT/CN2018/115617 CN2018115617W WO2020077718A1 WO 2020077718 A1 WO2020077718 A1 WO 2020077718A1 CN 2018115617 W CN2018115617 W CN 2018115617W WO 2020077718 A1 WO2020077718 A1 WO 2020077718A1
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region
array substrate
ion
layer
source
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PCT/CN2018/115617
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English (en)
French (fr)
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王威
黄情
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武汉华星光电半导体显示技术有限公司
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Priority to US16/619,458 priority Critical patent/US11309335B2/en
Publication of WO2020077718A1 publication Critical patent/WO2020077718A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present application relates to the field of display, in particular to an array substrate, a manufacturing method thereof, and a display module.
  • Array substrates prepared using Low Temperature Poly-silicon (LTPS) technology have higher carrier mobility, and therefore have become the first choice for driving backplanes of flexible display panels.
  • LTPS Low Temperature Poly-silicon
  • the thin film transistor device structure of the array substrate uses a patterned active layer as the active layer. This type of structure has the following defects: under the action of bending stress, stress concentration will occur on the edge of the channel of the active layer, It adversely affects the electrical properties of the thin film transistor device, which in turn affects the normal display of the display panel.
  • an active layer of the thin film transistor includes:
  • the first region includes a source-drain doped region doped with first ions and a channel region disposed between the source-drain doped regions without ion doping;
  • the first region and the second region have different conductivity types.
  • the element types of the first ion and the second ion are different.
  • the first area and the second area have the same thickness.
  • the thin film transistor further includes a gate insulating layer disposed on the active layer and a gate layer disposed on the gate insulating layer;
  • the pattern of the gate layer covers the pattern of the channel region.
  • the second region is connected to a metal line with a constant voltage.
  • the second area surrounds the first area.
  • a method for manufacturing an array substrate including:
  • Step S10 Provide a substrate, and form a polysilicon layer on the substrate, the polysilicon layer includes a first region and a second region;
  • Step S20 implanting second ions into the second region
  • Step S30 a gate insulating layer and a gate layer are sequentially formed on the polysilicon layer after the first ion implantation, the gate layer covers the channel region;
  • Step S40 Perform a first ion implantation on the channel region and the second region of the first region, and the region in the first region that has undergone the ion implantation twice forms a source-drain doped region;
  • Step S50 electrically connecting a metal line with a constant voltage to the second area to form an active layer
  • the first region includes the source and drain doped regions and the channel region between the source and drain doped regions, and the second region at least surrounds the channel region On the side contacting the source-drain doped region, the second region forms a PN junction with the first region.
  • the element types of the first ion and the second ion are different.
  • the second ion concentration when the second ion is implanted is greater than the first ion concentration when the first ion is implanted.
  • the step S20 includes:
  • Forming a photoresist layer on the polysilicon layer exposing and developing the photoresist layer to obtain the pattern of the second region, performing second ion implantation on the second region, and stripping the patterned ⁇ ⁇ ⁇ Photoresist layer.
  • it further includes forming an insulating layer and a gate layer on the active layer;
  • the pattern of the gate layer covers the pattern of the channel region.
  • the second area surrounds the first area.
  • a display module which includes an array substrate and a polarizer and a cover plate disposed above the array substrate, the array substrate includes a substrate and a thin film disposed on the substrate Transistor, the active layer of the thin film transistor includes:
  • the first region includes a source-drain doped region doped with first ions and a channel region disposed between the source-drain doped regions without ion doping;
  • the first region and the second region have different conductivity types.
  • the element types of the first ion and the second ion are different.
  • the first area and the second area have the same thickness.
  • the thin film transistor further includes a gate insulating layer disposed on the active layer and a gate layer disposed on the gate insulating layer;
  • the pattern of the gate layer covers the pattern of the channel region.
  • the second area surrounds the first area.
  • the second region is connected to a metal line with a constant voltage.
  • a second region surrounding at least the side of the channel region that is not in contact with the source and drain doped regions is provided to reduce the bending stress on the channel region and improve the bending resistance of the thin film transistor.
  • FIG. 1 is a schematic structural diagram of an active layer in an array substrate provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a partial structure of an active layer provided by an embodiment of this application.
  • FIG. 3 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a part of an array substrate provided by another embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a method for manufacturing an array substrate according to another embodiment of the application.
  • 6a and 6b are schematic structural diagrams of a method for manufacturing an array substrate provided by yet another embodiment of the present application.
  • the present application provides an array substrate including a substrate 11 and a thin film transistor 12 disposed on the substrate 11.
  • the substrate 11 is a flexible substrate, and the preparation material of the flexible substrate includes polyimide.
  • the substrate 11 and the thin film transistor 12 may further be provided with a barrier layer and a buffer layer, which may be specifically designed according to actual requirements.
  • FIG. 1 is a schematic structural diagram of an active layer in an array substrate according to an embodiment of the present application.
  • the active layer 121 of the thin film transistor 12 includes a first region 1211 and a second region 1212.
  • the first region 1211 includes a source-drain doped region 1211b doped with first ions and a channel region 1211a disposed between the source-drain doped region 1211b without ion doping;
  • a second region 1212, the second region 1212 at least surrounds the side of the channel region 1211a not in contact with the source and drain doped regions 1211b, the second region 1212 is doped with second ions, the The second region 1212 and the first region 1211 form a PN junction.
  • the edge of the channel region 1211a is likely to cause damage to the channel region 1211a due to stress concentration. Therefore, in this application, the second region 1212 surrounding the side of the channel region 1211a is provided at the side of the channel region 1211a, so as to alleviate the bending stress at the channel region 1211a, thereby achieving the purpose of protecting the channel region 1211a.
  • the thin film transistor 12 is an energized device, it is necessary to avoid the electrical performance of the second region 1212 from causing electrical interference to the first region 1211, so as to define the second region 1212 and the first region 1211 to form a PN junction.
  • the first ions and the second ions have different element types, and by setting the second region 1212 and the source-drain doped region 1211b, the doped regions have different ion element types, so that the source and drain A PN junction is formed between the polar doped region 1211b, the second region 1212, and the channel region 1211a, which becomes a barrier to carrier diffusion, and the source and drain doped region 1211b, the second region 1212, and the channel region 1211a Electrical barriers.
  • the first region 1211 and the second region 1212 have different conductivity types.
  • the first ion and the second ion are both P-type ions and N-type ions, and the element types of the first and second ions are different.
  • the second region 1212 is connected to a metal line with a constant voltage, thereby applying a constant bias voltage to the second region 1212 to enhance the electrical barrier between the source and drain doped regions 1211b, the second region 1212, and the channel region 1211a .
  • the thicknesses of the first region 1211 and the second region 1212 are equal, so as to prevent the first region 1211 and the second region 1212 from generating film breaks due to the difference in thickness, Affect the electrical performance of thin film transistors. It can also be understood that the first region 1211 and the second region 1212 are disposed in the same layer.
  • FIG. 3 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • the thin film transistor 12 further includes a gate insulating layer 122 disposed on the active layer 121 and a gate layer 123 disposed on the gate insulating layer 122.
  • the pattern of the gate layer 123 covers the pattern of the channel region 1212a. It can be understood that the pattern of the gate layer 123 covers the pattern of the channel region 1212a, but the region corresponding to the region covered by the pattern of the gate layer 123 is not limited to the channel region 1212a.
  • the second area 1212 surrounds the first area 1211, that is, the second area 1212 completely surrounds the first area 1211.
  • this application also provides a method for manufacturing an array substrate, including:
  • a substrate 11 is provided, and a polysilicon layer is formed on the substrate.
  • the polysilicon layer includes a first region 1211 and a second region 1212.
  • Step S20 implanting second ions into the second region 1212.
  • a photoresist layer is formed on the polysilicon layer, the photoresist layer is exposed and developed to obtain a pattern of the second region 1212, and a second ion implantation is performed on the second region 1212.
  • the patterned photoresist layer is peeled off.
  • a gate insulating layer 122 and a gate layer 123 are sequentially formed on the polysilicon layer after the first ion implantation, and the gate layer 123 covers the channel region 1211a.
  • Step S40 the first ion implantation is performed on the channel region and the second region of the first region. Due to the blocking of the gate layer 123, the polysilicon layer under the gate layer 123 is not ion implanted, thereby forming a channel In the region 1211a, ions can be implanted normally in the region blocked by the gate layer 123, and the region in the first region that has undergone the ion implantation twice forms the source-drain doped region 1211b.
  • the first ion and the second ion have different conductivity types.
  • the second ion concentration during the second ion implantation is greater than the first ion concentration during the first ion implantation, thereby making the second region 1212 and the source-drain doped region 1211b With different conductivity types, the second region 1212 is electrically insulated from the first region 1211.
  • Step S50 electrically connecting a metal line with a constant voltage to the second region 1212 to form an active layer 121.
  • the conductivity of the active layer 121 can be adjusted by the implantation dose of the first ion and the second ion.
  • the first region 1211 includes the source and drain doped regions 1211b and a channel region 1211a between the source and drain doped regions 1211b, and the second region 1211b at least surrounds the channel region 1211a is the side not in contact with the source-drain doped region 1211b, and the second region 1212 is electrically insulated from the first region 1211.
  • the manufacturing method of the array substrate further includes, but is not limited to: sequentially forming an interlayer insulating layer, a source-drain metal layer, an organic layer, an anode layer, a pixel definition layer, and a support layer on the gate layer , Organic light emitting device and encapsulation layer.
  • the present application proposes an array substrate, a manufacturing method thereof, and a display module.
  • the present application reduces the channel region by providing a second region that at least surrounds the side of the channel region that is not in contact with the source and drain doped regions The bending stress received improves the bending resistance of the thin film transistor.

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Abstract

一种阵列基板及其制作方法、显示模组。所述阵列基板包括衬底(11)以及薄膜晶体管(12)。所述薄膜晶体管(12)的有源层(121)包括：第一区域(1211)，包括源漏极掺杂区(1211b)和沟道区(1211a)。第二区域(1212)，所述第二区域(1212)至少包围所述沟道区(1211a)未与所述源漏极掺杂区(1211b)接触的侧边，所述第一区域(1211)与所述第二区域(1212)形成PN结。

Description

一种阵列基板及其制作方法、显示模组 技术领域
本申请涉及显示领域，特别涉及一种阵列基板及其制作方法、显示模组。
 背景技术
采用低温多晶硅技术（Low Temperature Poly-silicon， LTPS）制备的阵列基板具有较高的载流子迁移率，因此成为柔性显示面板的驱动背板的首选。然而，阵列基板的薄膜晶体管器件结构中采用经过图案化的有源层作为主动层，这类结构具有如下缺陷：在受到弯曲应力的作用下，有源层的沟道的边缘会发生应力集中，对薄膜晶体管器件电性产生不良的影响，进而影响显示面板的正常显示。
因此，目前亟需一种阵列基板及其制作方法、显示模组以解决上述问题。
 技术问题
解决现有阵列基板在受到弯曲应力时，有源层的沟道的边缘会发生应力集中，进而对薄膜晶体管器件电性产生不良的影响。
 技术解决方案
为实现上述目的，本发明提供的技术方案如下：
本申请提供了一种阵列基板，包括衬底以及设置在所述衬底上的薄膜晶体管，所述薄膜晶体管的有源层包括：
第一区域，包括掺杂有第一离子的源漏极掺杂区和设置在所述源漏极掺杂区之间的未进行离子掺杂的沟道区；以及
第二区域，所述第二区域至少包围所述沟道区未与所述源漏极掺杂区接触的侧边，所述第二区域掺杂有第二离子，所述第一区域与所述第二区域形成PN结。
根据本申请一实施例，所述第一区域与所述第二区域的导电类型不同。
根据本申请一实施例，所述第一离子与所述第二离子的元素种类不同。
根据本申请一实施例，所述第一区域与所述第二区域的厚度相等。
根据本申请一实施例，所述薄膜晶体管还包括设置在所述有源层上的栅绝缘层以及设置在所述栅绝缘层上的栅极层；
在俯视条件下，所述栅极层的图案覆盖所述沟道区的图案。
根据本申请一实施例，所述第二区域与具有恒定电压的金属线连接。
根据本申请一实施例，所述第二区域包围所述第一区域。
根据本申请的另一个方面，还提供了一种阵列基板的制作方法，包括：
步骤S10、提供一衬底，并在所述衬底上形成多晶硅层，所述多晶硅层包括第一区域和第二区域；
步骤S20、对所述第二区域进行第二离子的植入；
步骤S30、在经过第一次离子植入的所述多晶硅层上依次形成栅绝缘层和栅极层，所述栅极层覆盖沟道区；
步骤S40、对所述第一区域的所述沟道区和第二区域进行第一离子植入，所述第一区域中经过两次离子植入的区域形成源漏极掺杂区；
步骤S50、将具有恒定电压的金属线与所述第二区域电连接，形成有源层；
其中，所述第一区域包括所述源漏极掺杂区以及位于所述源漏极掺杂区之间的所述沟道区，所述第二区域至少包围所述沟道区未与所述源漏极掺杂区接触的侧边，所述第二区域与所述第一区域形成PN结。
根据本申请一实施例，所述第一离子与所述第二离子的元素种类不同。
根据本申请一实施例，所述第二离子植入时的第二离子浓度大于所述第一离子植入时的第一离子的浓度。
根据本申请一实施例，所述步骤S20包括：
在所述多晶硅层上形成光阻层，对所述光阻层进行曝光、显影以获取所述第二区域的图案，对所述第二区域进行第二离子植入，剥离经图案化的所述光阻层。
根据本申请一实施例，还包括在所述有源层上形成绝缘层以及栅极层；
在俯视条件下，所述栅极层的图案覆盖所述沟道区的图案。
根据本申请一实施例，所述第二区域包围所述第一区域。
根据本申请的又一个方面，提供了一种显示模组，其包括阵列基板以及设置在阵列基板上方的偏光片和盖板，所述阵列基板包括衬底以及设置在所述衬底上的薄膜晶体管，所述薄膜晶体管的有源层包括：
第一区域，包括掺杂有第一离子的源漏极掺杂区和设置在所述源漏极掺杂区之间的未进行离子掺杂的沟道区；以及
第二区域，所述第二区域至少包围所述沟道区未与所述源漏极掺杂区接触的侧边，所述第二区域掺杂有第二离子，所述第一区域与所述第二区域形成PN结。
根据本申请一实施例，所述第一区域与所述第二区域的导电类型不同。
根据本申请一实施例，所述第一离子与所述第二离子的元素种类不同。
根据本申请一实施例，所述第一区域与所述第二区域的厚度相等。
根据本申请一实施例，所述薄膜晶体管还包括设置在所述有源层上的栅绝缘层以及设置在所述栅绝缘层上的栅极层；
在俯视条件下，所述栅极层的图案覆盖所述沟道区的图案。
根据本申请一实施例，所述第二区域包围所述第一区域。
根据本申请一实施例，所述第二区域与具有恒定电压的金属线连接。
 有益效果
本申请通过设置一至少包围沟道区未与源漏极掺杂区接触的侧边的第二区域，以减小沟道区所受到的弯曲应力，提高薄膜晶体管的抗弯曲特性。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施例提供的一种阵列基板中有源层的结构示意图；
图2为本申请一实施例提供的有源层的部分结构示意图；
图3为本申请一实施例提供的一种阵列基板的结构示意图；
图4所示为本申请另一实施例提供的一种阵列基板的部分结构示意图；
图5所示为本申请又一实施例提供的一种阵列基板的制作方法的流程示意图；
图6a和6b所示为本申请又一实施例提供的一种阵列基板的制作方法的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
请参阅图1-4所示。本申请提供了一种阵列基板，包括衬底11以及设置在所述衬底11上的薄膜晶体管12。
所述衬底11为柔性衬底，所述柔性衬底的制备材料包括聚酰亚胺。
在一种实施例中，所述衬底11和薄膜晶体管12中还可设置阻挡层和缓冲层，具体可根据实际需求进行设计。
有源层121的结构请参阅图1，图1本申请一实施例提供的一种阵列基板中有源层的结构示意图。
所述薄膜晶体管12的有源层121包括第一区域1211和第二区域1212。
第一区域1211，包括掺杂有第一离子的源漏极掺杂区1211b和设置在所述源漏极掺杂区1211b之间的未进行离子掺杂的沟道区1211a；以及
第二区域1212，所述第二区域1212至少包围所述沟道区1211a未与所述源漏极掺杂区1211b接触的侧边，所述第二区域1212掺杂有第二离子，所述第二区域1212与所述第一区域1211形成PN结。
在一种实施例中，在受到弯曲应力时，在沟道区1211a的边缘处容易因为应力集中导致沟道区1211a发生断层受损。因此本申请通过在沟道区1211a的侧边位置设置将沟道区1211a边侧包围的第二区域1212，进而将沟道区1211a处的弯曲应力缓解，达到保护沟道区1211a的目的。但是，由于薄膜晶体管12为通电器件，因此需要避免第二区域1212的电学性能对第一区域1211产生电学干扰，进而限定第二区域1212与第一区域1211形成PN结。
在一种实施例中，所述第一离子与所述第二离子的元素种类不同，通过设置第二区域1212和源漏极掺杂区1211b掺杂区的离子元素种类不同，从而在源漏极掺杂区1211b、第二区域1212以及沟道区1211a之间形成PN结，成为阻挡载流子扩散的势垒，实现源漏极掺杂区1211b、第二区域1212以及沟道区1211a之间的电学阻挡。
在一种实施例中，所述第一区域1211与所述第二区域1212的导电类型不同。
在一种实施例中，所述第一离子和所述第二离子均为P型离子和N型离子，所述第一离子和第二离子的元素种类不同。
在一种实施例中，为了防止第一区域1211与第二区域1212形成PN结影响有源层内的电性传导。所述第二区域1212与具有恒定电压的金属线连接，从而对第二区域1212施加一恒定偏压，增强源漏极掺杂区1211b、第二区域1212以及沟道区1211a之间的电学阻挡。
在一种实施例中，所述第一区域1211与所述第二区域1212的厚度相等，进而避免所述第一区域1211与所述第二区域1212由于厚度的差异产生膜层的断层，会影响薄膜晶体管的电学性能。也可以理解为所述第一区域1211与所述第二区域1212同层设置。
请参阅图3，图3本申请一实施例提供的一种阵列基板的结构示意图。
在一种实施例中，所述薄膜晶体管12还包括设置在所述有源层121上的栅绝缘层122以及设置在所述栅绝缘层122上的栅极层123。
在俯视条件下，所述栅极层123的图案覆盖所述沟道区1212a的图案。可以理解的是，所述栅极层123的图案覆盖所述沟道区1212a的图案，但被所述栅极层123的图案覆盖区所对应的区域并不仅限于所述沟道区1212a。
在一种实施例中，所述第二区域1212包围所述第一区域1211，即所述第二区域1212将所述第一区域1211完全包围。
请参阅图1-6b所示，本申请还提供了一种阵列基板的制作方法，包括：
请参阅图6a，步骤S10、提供一衬底11，并在所述衬底上形成多晶硅层，所述多晶硅层包括第一区域1211和第二区域1212。
步骤S20、对所述第二区域1212进行第二离子的植入。
在一种实施例中，在所述多晶硅层上形成光阻层，对所述光阻层进行曝光、显影获取第二区域1212的图案，对所述第二区域1212进行第二离子植入，剥离经图案化的所述光阻层。
请参阅图6b，步骤S30、在经过第一次离子植入的所述多晶硅层上依次形成栅绝缘层122和栅极层123，所述栅极层123覆盖沟道区1211a。
步骤S40、对所述第一区域的所述沟道区和第二区域进行第一离子植入，由于栅极层123的阻挡，栅极层123下方的多晶硅层无离子注入，进而形成沟道区1211a，而在无栅极层123阻挡的区域，离子能够正常植入，所述第一区域中经过两次离子植入的区域形成源漏极掺杂区1211b。
在一种实施例中，所述第一离子与所述第二离子的导电类型不同。
在一种实施例中，所述第二离子植入时的第二离子浓度大于所述第一离子植入时的第一离子的浓度，进而使得第二区域1212与源漏极掺杂区1211b具有不同的导电类型，实现所述第二区域1212与所述第一区域1211电学绝缘。
步骤S50、将具有恒定电压的金属线与所述第二区域1212电连接，形成有源层121。
在一种实施例中，有源层121的电导率可以通过第一离子和第二离子的植入剂量进行调整。
其中，所述第一区域1211包括所述源漏极掺杂区1211b以及位于所述源漏极掺杂区1211b之间的沟道区1211a，所述第二区域1211b至少包围所述沟道区1211a未与所述源漏极掺杂区1211b接触的侧边，所述第二区域1212与所述第一区域1211电学绝缘。
在一种实施例中，所述阵列基板的制作方法还包括但不仅限于：在栅极层上依次形成层间绝缘层、源漏极金属层、有机层、阳极层、像素定义层、支撑层、有机发光器件以及封装层。
本申请提出了一种阵列基板及其制作方法、显示模组，本申请通过设置一至少包围沟道区未与源漏极掺杂区接触的侧边的第二区域，以减小沟道区所受到的弯曲应力，提高薄膜晶体管的抗弯曲特性。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，其包括衬底以及设置在所述衬底上的薄膜晶体管，所述薄膜晶体管的有源层包括：
    第一区域，包括掺杂有第一离子的源漏极掺杂区和设置在所述源漏极掺杂区之间的未进行离子掺杂的沟道区；以及
    第二区域，所述第二区域至少包围所述沟道区未与所述源漏极掺杂区接触的侧边，所述第二区域掺杂有第二离子，所述第一区域与所述第二区域形成PN结。
  2. 根据权利要求1所述的阵列基板，其中，所述第一区域与所述第二区域的导电类型不同。
  3. 根据权利要求1所述的阵列基板，其中，所述第一离子与所述第二离子的元素种类不同。
  4. 根据权利要求1所述的阵列基板，其中，所述第一区域与所述第二区域的厚度相等。
  5. 根据权利要求1所述的阵列基板，其中，所述薄膜晶体管还包括设置在所述有源层上的栅绝缘层以及设置在所述栅绝缘层上的栅极层；
    在俯视条件下，所述栅极层的图案覆盖所述沟道区的图案。
  6. 根据权利要求1所述的阵列基板，其中，所述第二区域包围所述第一区域。
  7. 根据权利要求1所述的阵列基板，其中，所述第二区域与具有恒定电压的金属线连接。
  8. 一种阵列基板的制作方法，其包括：
    步骤S10、提供一衬底，并在所述衬底上形成多晶硅层，所述多晶硅层包括第一区域和第二区域；
    步骤S20、对所述第二区域进行第二离子的植入；
    步骤S30、在经过第一次离子植入的所述多晶硅层上依次形成栅绝缘层和栅极层，所述栅极层覆盖沟道区；
    步骤S40、对所述第一区域的所述沟道区和第二区域进行第一离子植入，所述第一区域中经过两次离子植入的区域形成源漏极掺杂区；
    步骤S50、将具有恒定电压的金属线与所述第二区域电连接，形成有源层；
    其中，所述第一区域包括所述源漏极掺杂区以及位于所述源漏极掺杂区之间的所述沟道区，所述第二区域至少包围所述沟道区未与所述源漏极掺杂区接触的侧边，所述第二区域与所述第一区域形成PN结。
  9. 根据权利要求8所述的阵列基板的制作方法，其中，所述第一离子与所述第二离子的元素种类不同。
  10. 根据权利要求9所述的阵列基板的制作方法，其中，所述第二离子植入时的第二离子浓度大于所述第一离子植入时的第一离子的浓度。
  11. 根据权利要求8所述的阵列基板的制作方法，其中，所述步骤S20包括：
    在所述多晶硅层上形成光阻层，对所述光阻层进行曝光、显影以获取所述第二区域的图案，对所述第二区域进行第二离子植入，剥离经图案化的所述光阻层。
  12. 根据权利要求8所述的阵列基板的制作方法，其中，还包括在所述有源层上形成绝缘层以及栅极层；
    在俯视条件下，所述栅极层的图案覆盖所述沟道区的图案。
  13. 根据权利要求8所述的阵列基板的制作方法，其中，所述第二区域包围所述第一区域。
  14. 一种显示模组，其包括阵列基板以及设置在阵列基板上方的偏光片和盖板，所述阵列基板包括衬底以及设置在所述衬底上的薄膜晶体管，所述薄膜晶体管的有源层包括：
    第一区域，包括掺杂有第一离子的源漏极掺杂区和设置在所述源漏极掺杂区之间的未进行离子掺杂的沟道区；以及
    第二区域，所述第二区域至少包围所述沟道区未与所述源漏极掺杂区接触的侧边，所述第二区域掺杂有第二离子，所述第一区域与所述第二区域形成PN结。
  15. 根据权利要求14所述的显示模组，其中，所述第一区域与所述第二区域的导电类型不同。
  16. 根据权利要求14所述的显示模组，其中，所述第一离子与所述第二离子的元素种类不同。
  17. 根据权利要求14所述的显示模组，其中，所述第一区域与所述第二区域的厚度相等。
  18. 根据权利要求14所述的显示模组，其中，所述薄膜晶体管还包括设置在所述有源层上的栅绝缘层以及设置在所述栅绝缘层上的栅极层；
    在俯视条件下，所述栅极层的图案覆盖所述沟道区的图案。
  19. 根据权利要求14所述的显示模组，其中，所述第二区域包围所述第一区域。
  20. 根据权利要求14所述的显示模组，其中，所述第二区域与具有恒定电压的金属线连接。
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