WO2020073574A1 - 相位检测方法、装置、存储介质及电子装置 - Google Patents

相位检测方法、装置、存储介质及电子装置 Download PDF

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WO2020073574A1
WO2020073574A1 PCT/CN2019/075658 CN2019075658W WO2020073574A1 WO 2020073574 A1 WO2020073574 A1 WO 2020073574A1 CN 2019075658 W CN2019075658 W CN 2019075658W WO 2020073574 A1 WO2020073574 A1 WO 2020073574A1
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Prior art keywords
phase
phase interval
clock signal
interval
sampling
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PCT/CN2019/075658
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English (en)
French (fr)
Inventor
庞瑞
王博明
杨琴
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中兴通讯股份有限公司
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Priority to US17/292,475 priority Critical patent/US11381248B2/en
Priority to EP19871970.0A priority patent/EP3865884A4/en
Publication of WO2020073574A1 publication Critical patent/WO2020073574A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R25/00—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/0413—MIMO systems

Definitions

  • the present disclosure relates to the field of communications, and in particular, to a phase detection method, device, storage medium, and electronic device.
  • the large-scale multiple-input multiple-output (Massive MIMO, Massive Multiple In Multiple) technology in multi-array antenna base stations is a key technology in 4.5G and 5G communications.
  • space division multiplexing SDMA, Space, Multiple, Access
  • Space Division Multiple Access uses beamforming beamforming technology to concentrate signal energy in a specific direction, thereby increasing spectrum utilization efficiency and reducing interference to other receivers.
  • Beamforming has strict requirements on the phase difference of signals between multiple channels of transceivers. For example, the phase difference between multiple channels of 5G base station transceivers of sub-6G should be less than 5 °. Therefore, the wireless base station system will adopt a series of phase detection and adjustment measures to reduce the phase error between the channels, thereby aligning the phase of the multi-channel signal.
  • phase synchronization mechanism In the phase synchronization mechanism, the detection of the phase of the RF clock signal is the first step, and its phase detection accuracy directly affects the effect of multi-channel synchronization. At present, there is no good high-precision phase detection solution for radio frequency clock signals. In addition, there is no good high-precision phase detection solution for other types of clock signals.
  • Embodiments of the present disclosure provide a phase detection method, device, storage medium, and electronic device to at least solve the problem of low accuracy of clock signal phase detection in the related art.
  • a phase detection method which includes: sampling a clock signal to be detected to obtain a binary sequence; and determining a phase of the clock signal to be detected in an initial sampling period according to the binary sequence An interval as a first phase interval; using the reference phase interval included in the first phase interval to normalize other phase intervals included in the first phase interval to obtain a second phase interval, wherein the reference phase The interval is the phase interval determined in the first sampling period after the sampling operation is triggered, and the other phase interval is the phase determined in the sampling period after the first sampling period after the sampling operation is triggered Interval; converge the second phase interval, and obtain phase information of the clock signal to be detected according to the second phase interval after convergence.
  • a phase detection device including: a sampling module configured to perform sampling operation on a clock signal to be detected to obtain a binary sequence; and a phase interval determination module configured to be based on the binary sequence Determine the phase interval of the clock signal to be detected in the initial sampling period as the first phase interval; the normalization module is set to use the reference phase interval included in the first phase interval to determine the phase interval included in the first phase interval Perform standardization operation on other phase intervals to obtain a second phase interval, wherein the reference phase interval is a phase interval determined within the first sampling period after the sampling operation is triggered, and the other phase interval is during the sampling The phase interval determined in the sampling period after the first sampling period after the operation is triggered; the phase interval convergence module is configured to converge the second phase interval and obtain the The phase information of the clock signal to be detected.
  • a storage medium in which a computer program is stored, wherein the computer program is configured to execute the steps in any one of the above method embodiments during runtime.
  • an electronic device including a memory and a processor, the memory stores a computer program, the processor is configured to run the computer program to perform any of the above The steps in the method embodiment.
  • a series of binary sequences are obtained by sampling the clock signal to be detected, and based on these digital sampling information, the phase interval of the clock signal to be detected is determined in each sampling period, and finally a series of phase interval normalization operations To converge the phase information of the clock signal to be detected.
  • the solution in the embodiment of the present disclosure can make the phase detection algorithm simple, the circuit implementation difficulty is low, the phase convergence speed is fast, and the phase detection accuracy is high.
  • FIG. 1 is a flowchart of a phase detection method according to an embodiment of the present disclosure
  • FIG. 2 is a system architecture diagram of a phase detection scheme according to an embodiment of the present disclosure
  • phase difference accumulation module is a schematic diagram of a phase difference accumulation module according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a sampling module according to an embodiment of the present disclosure.
  • phase interval determination module is a schematic diagram of a phase interval determination module according to an embodiment of the present disclosure.
  • phase interval normalization module is a schematic diagram of a phase interval normalization module according to an embodiment of the present disclosure
  • phase interval convergence module 7 is a schematic diagram of a phase interval convergence module according to an embodiment of the present disclosure.
  • FIG. 8 is a functional schematic diagram of a sampling module according to an embodiment of the present disclosure.
  • FIG. 9 is an overlay diagram of sampling points in a normal mode and a high-precision mode according to an embodiment of the present disclosure.
  • FIG. 10 is an error analysis diagram of a normal mode and a high-precision mode according to an embodiment of the present disclosure
  • phase interval decision module 11 is a functional schematic diagram of a phase interval decision module according to an embodiment of the present disclosure.
  • phase interval normalization module 12 is a functional schematic diagram of a phase interval normalization module according to an embodiment of the present disclosure
  • phase interval convergence module 13 is a functional schematic diagram of a phase interval convergence module according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of an example of detecting the phase of a single-ended clock according to an embodiment of the present disclosure
  • 15 is a schematic diagram of an example of detecting a quadrature clock phase according to an embodiment of the present disclosure.
  • 16 is a schematic diagram of an example of a high-precision phase detection mode according to an embodiment of the present disclosure.
  • FIG. 17 is a schematic diagram of an example of a high-reliability phase detection mode according to an embodiment of the present disclosure.
  • FIG. 18 is a phase convergence curve according to an embodiment of the present disclosure.
  • a frequency discriminator (PFD, Phase and Frequency Detector) is a commonly used circuit for discriminating the frequency and phase difference between two input clock signals.
  • the PFD consists of two D flip-flops and a NAND gate. The D flip-flop outputs a high level after receiving the rising edge of the input clock, and resets when both D flip-flop outputs reach a high level. Therefore, the PFD can output pulse signals that characterize the frequency or phase difference of the two input clock signals.
  • the application of PFD in the phase detection of transceiver channels or other scenarios will have the following difficulties and problems:
  • PFD phase detection will dramatically increase the complexity of the original system.
  • the number of transceiver channels has reached tens or even hundreds.
  • the PFD to identify the two-channel signals the same number of PFDs will be used.
  • the MIMO system is generally composed of multiple chips. The connection between the chips and the existing PFD will make the PCB layout very complicated and reduce the circuit reliability.
  • PFD cannot directly or hardly give the phase information of the input clock signal.
  • PFD characterizes the frequency or phase difference of two input clock signals as a pulse signal of a certain width, rather than a series of high and low levels or binary sequences, and it is difficult for later digital circuits to convert it into pure phase information. In scenarios where phase values need to be detected directly, PFD cannot meet application requirements.
  • the frequency and phase discrimination capabilities of PFD are greatly challenged.
  • communication technologies have continuously evolved, and wireless communication frequency bands have developed towards high frequencies and large bandwidths.
  • the frequency and phase discrimination capabilities of PFD are already stretched, not to mention the 5G high frequency band up to 24.25 ⁇ 29.5GHz.
  • such a high-frequency clock signal is no longer a simple square wave or a square-like wave. After receiving these signals, the PFD can no longer show its frequency and phase discrimination capabilities normally or reliably.
  • the numerically controlled oscillator NCO and digital circuit modules that implement the arc tangent function are used.
  • the precision that these digital circuit modules can achieve is limited. If the number of operation iterations is small, the phase detection accuracy will be greatly limited. If the number of iterations is large Although the phase detection accuracy can be improved to a certain extent, it will significantly increase the computational resource overhead.
  • FIG. 1 is a flowchart of a phase detection method according to an embodiment of the present disclosure. As shown in FIG. 1, the process includes the following steps:
  • Step S12 Perform sampling operation on the clock signal to be detected to obtain a binary sequence
  • Step S14 determining the phase interval of the clock signal to be detected in the initial sampling period as the first phase interval according to the binary sequence
  • Step S16 using the reference phase interval included in the first phase interval to normalize other phase intervals included in the first phase interval to obtain a second phase interval, wherein the reference phase interval is A phase interval determined in the first sampling period after the sampling operation is triggered, and the other phase interval is a phase interval determined in the sampling period after the first sampling period after the sampling operation is triggered;
  • step S18 the second phase interval is converged, and the phase information of the clock signal to be detected is obtained according to the converged second phase interval.
  • the phase detection device may perform the above operation.
  • the binary sequence obtained above may be a discrete binary sequence.
  • a series of binary sequences can be obtained by sampling the clock signal to be detected. Based on the digital sampling information, the phase interval of the clock signal to be detected is determined in each sampling period, and finally through a series of phase interval normalization operations, the convergence The phase information of the clock signal to be detected.
  • the operation resource overhead will not be increased.
  • the solution in the present disclosure is adopted without excessive operation iterations In the case of the number of times, the phase detection accuracy can also be ensured. Compared with the related art, when the number of operation iterations is small, the phase detection accuracy will be greatly limited, and when the number of operation iterations is large, the operation resource overhead will be increased.
  • the solution in the embodiment of the present disclosure can be achieved by reducing the operation The accuracy of phase detection can also be ensured on the premise of the number of iterations.
  • the aforementioned related patents also include complex matrix multiplication and complex conjugate operations. Due to the complexity of the algorithm, it is not conducive to reducing the circuit scale and power consumption of the application system. In addition, the aforementioned patents have quadrature requirements for the two signals to be detected, so that only the phase detection of the quadrature signals can be achieved. However, in the embodiments of the present disclosure, excessively complex matrix multiplication and complex conjugate operations are not involved. Therefore, the circuit scale of the application system and the power consumption of the reference system can be effectively reduced.
  • the solution in the embodiment of the present disclosure can make the phase detection algorithm simple, the circuit implementation difficulty is low, the phase convergence speed is fast, and the phase detection accuracy is high.
  • the sampling operation of the clock signal to be detected to obtain a binary sequence includes: sampling the clock signal to be detected by using a sampling clock signal to obtain a binary sequence, wherein the sampling The least common multiple of the frequency of the clock signal and the frequency of the clock signal to be detected exceeds a predetermined threshold.
  • the frequency value of the sampling clock signal should be reasonably selected so that the frequency value of the clock signal to be detected and the sampling clock signal have a larger least common multiple.
  • determining the phase interval of the clock signal to be detected in the initial sampling period according to the binary sequence, as the first phase interval includes: determining the rising edge of each sampling clock signal according to the binary sequence The phase interval of the clock signal to be detected; determining the clock signal interval to be detected at the initial sampling time according to the determined phase interval and the accumulated phase difference value of the clock signal to be detected relative to the sampling clock signal, As the first phase interval, the sampling clock signal is used to perform the sampling operation on the clock signal to be detected.
  • determining the phase interval of the clock signal to be detected on the rising edge of each sampling clock signal according to the binary sequence includes: determining a phase interval judgment condition corresponding to the type of the binary sequence; The binary sequence and the phase interval decision condition determine the phase interval of the clock signal to be detected at the rising edge of each sampling clock signal.
  • the type of the binary sequence includes at least one of the following: a differential type, a single-ended type, and an orthogonal type.
  • a differential type ie, differential, single-ended, or orthogonal
  • the configuration of the phase interval judgment conditions is different. According to the requirements of fast sampling or high reliability sampling, the phase interval judgment conditions Configuration is different.
  • using the reference phase interval included in the first phase interval to normalize other phase intervals included in the first phase interval to obtain the second phase interval includes: using the reference The phase interval is a standard, and the other phase interval is transformed into the phase period in which the reference phase interval is located to obtain the second phase interval.
  • transforming the other phase intervals into the phase period in which the reference phase interval is located, and obtaining the second phase interval includes: When there is no intersection between other phase intervals and the reference phase interval, the other phase intervals are repeatedly reversed until the intersection between the other phase intervals and the reference phase interval occurs, and the reference phase interval is summed. The other phase interval after inversion is used as the second phase interval.
  • the flipping includes a left shift of 2 ⁇ or a right shift of 2 ⁇ .
  • the method further includes: when determining that there is an intersection between the other phase interval and the reference phase interval, On the premise that the normalization operation is performed on the phase interval, the first phase interval is directly converged, and the phase information of the clock signal to be detected is obtained according to the converged first phase interval.
  • the method further includes: sequentially obtaining an intersection of the second phase interval in the current sampling period until the second phase interval is in the current Until the difference between the upper limit and the lower limit of the intersection of the sampling period is less than a predetermined value, wherein the intersection of the second phase interval in the current sampling period is determined by Obtained by taking the intersection of the second phase interval at the intersection of the previous sampling period; converging the second phase interval, and obtaining the phase information of the clock signal to be detected according to the second phase interval after convergence includes: Averaging the upper and lower limits of the difference less than the predetermined value to obtain the initial phase of the clock signal to be detected at the time of initial sampling; the sum of the initial phase and the phase difference is used to obtain the current phase of the current sampling period The phase of the clock signal to be detected, wherein the phase difference value is based on the frequency of the clock signal to be detected and performing the sampling operation Relationship between the clock signal frequency sampling clock signal used for a current sampling period is calculated to be the detected phase difference
  • the phase difference between the clock signal to be detected and the sample clock signal since the sampling operation is triggered may be counted based on the frequency relationship between the clock signal to be detected and the sampling clock signal and the number of sampling cycles experienced based on the adder or multiplier value.
  • the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware, but in many cases the former is Better implementation.
  • the technical solution of the present disclosure can be embodied in the form of a software product in essence or part that contributes to the existing technology, and the computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk,
  • the CD-ROM includes several instructions to enable a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the embodiments of the present disclosure.
  • a phase detection device is also provided.
  • the device is used to implement the above-mentioned embodiments and preferred implementation modes, and those that have already been described will not be repeated.
  • the term "module” may implement a combination of software and / or hardware that performs predetermined functions.
  • the devices described in the following embodiments are preferably implemented in software, implementation of hardware or a combination of software and hardware is also possible and conceived.
  • FIG. 2 is a structural block diagram of a phase detection device according to an embodiment of the present disclosure. As shown in FIG. 2, the device includes:
  • the sampling module 101 is set to perform sampling operation on the clock signal to be detected to obtain a binary sequence; the phase interval determination module 102 is set to determine the phase interval of the clock signal to be detected in the initial sampling period according to the binary sequence as the first A phase interval; a normalization module 103 (which may also be referred to as a phase interval normalization module) is configured to use the reference phase interval included in the first phase interval to normalize other phase intervals included in the first phase interval, A second phase interval is obtained, wherein the reference phase interval is a phase interval determined in the first sampling period after the sampling operation is triggered, and the other phase interval is the first phase interval after the sampling operation is triggered The phase interval determined within the sampling period after one sampling period; the phase interval convergence module 104 is configured to converge the second phase interval and obtain the clock signal to be detected according to the converged second phase interval Phase information.
  • FIG. 2 can include the cumulative phase difference calculation module 100 and the control module 105 in addition to the above-mentioned modules.
  • FIG. 2 shows the above-mentioned six modules. The connection relationship between them can refer to FIG. 2. Among them, each parameter in FIG. 2 will be described in detail in the embodiment described later.
  • the cumulative phase difference calculation module 100 may be based on an adder or a multiplier, based on the frequency relationship between the clock signal to be detected and the sampling clock signal and the number of sampling cycles experienced, statistics of the clock signal to be detected since the sampling operation is triggered The phase difference value relative to the sampling clock signal.
  • the input clk sig of the sampling module 101 may be a differential, single-ended or quadrature type square wave, square wave-like or sinusoidal signal, and the output is a binary sequence in a corresponding form.
  • the module 101 may be composed of a core sampler (which may also be simply referred to as a sampler) and a post-stage waveform shaper. The purpose is to convert the input analog amplitude information into a discrete digital signal (ie, a binary sequence).
  • the core sampler can be implemented by flip-flops in the form of True Single Phase Clock (TSPC) or Current Mode Logic (CML).
  • TSPC True Single Phase Clock
  • CML Current Mode Logic
  • the post-stage waveform shaper can be realized by a Schmitt trigger or inverter circuit, and is set to signal swing amplification and waveform shaping.
  • the sampler can be selected as differential, single-ended or quadrature.
  • a sampling clock with a certain frequency can be selected to weaken the correlation between the clock signal to be detected and the frequency of the sampling clock signal, that is, to increase the least common multiple of the frequency of the clock signal to be detected and the frequency of the sampling clock signal.
  • the sampling module may include a sampler configured to use a sampling clock signal to perform sampling operation on the clock signal to be detected to obtain a binary sequence, wherein the frequency of the sampling clock signal and the frequency to be detected The least common multiple of the frequency of the clock signal exceeds a predetermined threshold.
  • the phase interval determination module 102 may determine the phase interval of the clock signal to be detected at the rising edge of each sampling clock signal according to the binary sequence output by the sampling module 101, and determine the initial sampling time to be detected according to the phase relationship between the sampling clock signal and the clock signal to be detected The phase interval of the clock signal.
  • the phase interval determination module 102 may include: a phase interval determiner configured to determine the phase interval of the clock signal to be detected on the rising edge of each sampling clock signal according to the binary sequence; an adder configured to determine The phase interval and the accumulated phase difference of the clock signal to be detected relative to the sampling clock signal determine the clock signal interval to be detected at the initial sampling time as the first phase interval, wherein the sampling The clock signal is used to perform the sampling operation on the clock signal to be detected.
  • the phase interval determination module 102 will be described in detail later.
  • the above-mentioned phase interval determiner can determine the phase interval judgment condition corresponding to the type of the binary sequence; according to the binary sequence and the phase interval judgment condition, determine the phase interval of each sampling clock signal rising edge of the clock signal to be detected .
  • the configuration of the phase interval decision conditions is also different. According to the requirements of fast sampling or high reliability sampling, the configuration of the judgment conditions of the phase interval is different.
  • the above-mentioned normalization module 103 may be set to use the reference phase interval as a standard, transform the other phase intervals into the phase period in which the reference phase interval is located, and obtain the second phase interval.
  • the normalization module 103 includes a phase scaler configured to repeatedly invert the other phase intervals until it is determined that there is no intersection between the other phase intervals and the reference phase interval until the other phase intervals Until there is an intersection with the reference phase interval, the reference phase interval and the other phase interval after inversion are used as the second phase interval.
  • the above flipping includes a left shift of 2 ⁇ or a right shift of 2 ⁇ .
  • the above device is further configured to: after determining the first phase interval, when determining that there is an intersection between the other phase interval and the reference phase interval, On the premise that the normalization operation is performed on the phase interval, the first phase interval is directly converged, and the phase information of the clock signal to be detected is obtained according to the converged first phase interval.
  • the above-mentioned phase interval convergence module 104 includes: an interval seeking intersection module, which is configured to sequentially obtain the intersection of the second phase interval in the current sampling period after obtaining the second phase interval, Until the difference between the upper and lower limits of the intersection of the second phase interval in the current sampling period is less than a predetermined value, where the intersection of the second phase interval in the current sampling period is determined by Obtained by taking the intersection of the phase interval of the current sampling period and the second phase interval at the intersection of the previous sampling period; the averaging module is set to obtain the waiting value by averaging the upper and lower limits of the difference less than the predetermined value The initial phase of the detected clock signal at the time of initial sampling; the adder is set to obtain the phase of the clock signal to be detected in the current sampling period by summing the initial phase and the phase difference value, wherein the phase The difference is related to the frequency of the clock signal to be detected and the frequency of the sampling clock signal used in the sampling operation Clock signal sample period the calculated current to be detected of the retardation
  • the phase interval convergence module 104 is set to obtain the intersection of the phase intervals output by the phase interval normalization module 103.
  • the module 104 may be composed of a simple comparator, and updates the intersection phase interval of the current sampling period by comparing the input phase interval of the current sampling period with the upper and lower limits of the intersection phase interval of the previous sampling period.
  • the phase interval convergence module can directly output the phase value of the clock signal to be detected at the initial sampling time, and on the basis of this phase value, increase the phase difference value of the current clock signal to be detected relative to the sampling clock signal to obtain the current sampling The phase value of the clock signal.
  • control module 105 is configured to control each module in the phase detection scheme in the embodiments of the present disclosure, through which the number of sampling cycles can be configured to trigger or terminate the phase detection operation and reset the phase detection Process and other functions.
  • the disclosed phase detection scheme can achieve very high accuracy.
  • FIG. 3 is a structural diagram of a cumulative phase difference calculation module 100.
  • the cumulative phase difference calculation module 100 may include a single sampling period phase difference calculator 1001 and an accumulator 1002, wherein the single sampling period phase difference
  • FIG. 4 is a structural diagram of the sampling module 101. As shown in FIG. 4, the sampling module 101 samples the clock signal to be detected under the sampling clock signal, and converts the analog amplitude information clk sig into a discrete digital signal bin.
  • the sampling module 101 may include a sampler 1011 and a waveform shaper 1012.
  • the sampler 1011 is a sampler composed of a trigger such as TSPC or CML.
  • 1012 performs swing amplification and waveform shaping on the signal output by 1011, and outputs an ideal digital pulse signal bin.
  • the sampler 101 samples the clock signal to be detected at the rising edge of the clock of each sampling clock signal clk ref , if the sampling level is higher than or equal to the common mode level 0 is output, and 1 is output if the sampling level is lower than the common mode level.
  • the sampling point can be covered over the entire [ 0,2 ⁇ ) phase interval, increase the diversity of sampling samples, and significantly improve the phase detection accuracy of the overall phase detection scheme.
  • FIG. 5 is a structural diagram of the phase interval determination module 102.
  • the module can determine the phase interval of the clock signal to be detected in the current sampling period according to the input binary sequence bin and the judgment condition written by reg.
  • the phase interval [ ⁇ lk , ⁇ hk ) of the clock signal to be detected at the initial sampling time is determined according to the cumulative phase difference ⁇ k of the clock signal to be detected relative to the sampling clock signal, where the subscript k is the number of sampling cycles experienced.
  • the judgment conditions of the phase interval can be configured according to the form of the clock signal to be detected (such as single-ended, differential, quadrature, etc.) and detection reliability requirements.
  • the phase interval judgment condition of the phase interval judgment module 102 can be configured as shown in FIG. 11.
  • FIG. 6 shows the structure of the standardized module 103.
  • this module uses the phase interval [ ⁇ l0 , ⁇ h0 ) determined in the first sampling period after the sampling operation is triggered as the reference interval to determine the subsequent sampling period Whether [ ⁇ lk , ⁇ hk ) overlaps with [ ⁇ l0 , ⁇ h0 ). If there is no interval overlap, the interval reversal of [ ⁇ lk , ⁇ hk ), that is, the left or right shift 2 ⁇ operation, until the interval overlap occurs with [ ⁇ l0 , ⁇ h0 ); if there is an interval overlap, then [ ⁇ lk , ⁇ hk ) does not perform interval inversion.
  • the 103 module outputs the normalized phase interval [ ⁇ ' lk , ⁇ ' hk ).
  • the module may include a phase interval overlap decider 1031 and a phase scaler 1032, where the phase interval overlap decider 1031 is a phase interval [ ⁇ l0 , ⁇ h0 ) determined by the first sampling period after the sampling operation is triggered With reference to the interval, it is determined whether [ ⁇ lk , ⁇ hk ) of the subsequent sampling period overlaps with [ ⁇ l0 , ⁇ h0 ).
  • phase scaler 1032 inverts [ ⁇ lk , ⁇ hk ) to the interval, that is, shifts left or right by 2 ⁇ until it intersects with [ ⁇ l0 , ⁇ h0 ); if there is an interval If they overlap, then [ ⁇ lk , ⁇ hk ) is not inverted.
  • FIG. 7 is a structural diagram of the phase interval convergence module 104. As shown in FIG. 7, this module obtains the intersection of [ ⁇ ′ lk , ⁇ ′ hk ) input for each sampling period, continuously narrowing the interval range. After a sufficient number of sampling cycles k, the phase information of the clock signal to be detected at the initial sampling time is converged through the mean calculation method, and the clock to be detected in the current sampling cycle is calculated according to the phase difference ⁇ k of the clock signal to be detected relative to the sampling clock signal The phase of the signal ⁇ sig .
  • the module may include an interval intersection module 1041, a delay module 1042, an averaging module 1043, and an adder 1044, where 1041 compares the input phase interval [ ⁇ ' lk , ⁇ ' hk ) with the previous sampling period intersection phase by comparing the current sampling period The upper and lower limits of the interval [ ⁇ lik-1 , ⁇ hik-1 ), update the intersection phase interval [ ⁇ lik , ⁇ hik ] of the current sampling period, [ ⁇ lik-1 , ⁇ hik-1 ] delay a single sampling period by 1042 get.
  • the clock signal to be detected is a single-ended signal, its frequency is set to 2 GHz, and a clock signal with a frequency of 122.88 MHz commonly used in the system is used for sampling.
  • the val ref of the 100 module is 122.88x10 6 and the val sig is 2x10 9.
  • the phase difference between the clock signal to be detected and the sampling clock signal in a single sampling period can be calculated as:
  • the cumulative phase difference between the clock signal to be detected and the sampling clock signal is:
  • the bin output from each sampling period 101 is 1-bit data
  • the phase interval judgment conditions of the 102 module are shown in Table 1:
  • phase of the clock signal to be detected is 130 ° at the initial sampling time, and the sampling period number val sum of the 105 module is 300.
  • the initial phase ⁇ avg of the clock signal to be detected converges to 130.275 °, and the phase detection error is 0.275 °.
  • the block diagram of this embodiment is shown in FIG. 15.
  • the clock signal to be detected is a quadrature signal, its frequency is set to 2 GHz, and a clock signal with a frequency of 122.88 MHz commonly used in the system is used for sampling.
  • the val ref of the 100 module is 122.88x10 6 and the val sig is 2x10 9.
  • the phase difference between the clock signal to be detected and the sampling clock signal in a single sampling period can be calculated as:
  • the cumulative phase difference between the clock signal to be detected and the sampling clock signal is:
  • the bin output from each sampling period 101 is 2 bits of data
  • the phase interval judgment conditions of the 102 module are shown in Table 2:
  • bin_i bin_q Phase interval 0 0 (0, ⁇ / 2) 0 1 ( ⁇ / 2, ⁇ ) 1 0 (3 ⁇ / 2,2 ⁇ ) 1 1 ( ⁇ , 3 ⁇ / 2)
  • phase of the clock signal to be detected is 130 ° at the initial sampling time, and the sampling period number val sum of the 105 module is 300.
  • the initial phase ⁇ avg of the clock signal to be detected converges to 130.275 °, and the phase detection error is 0.275 °.
  • This mode is dedicated to improving the phase detection accuracy of the disclosed solution.
  • the block diagram of this embodiment is shown in FIG. 16.
  • the clock signal to be detected is a quadrature signal, and its frequency is set to 2 GHz.
  • the 122.881MHz clock signal is used for sampling.
  • the val ref of the 100 module is 122.881x10 6 and the val sig is 2x10 9.
  • the phase difference between the clock signal to be detected and the sampling clock signal in a single sampling period can be calculated as:
  • the cumulative phase difference between the clock signal to be detected and the sampling clock signal is:
  • the bin output from each sampling period 101 is 2 bits of data
  • the phase interval judgment conditions of the 102 module are shown in Table 3:
  • bin_i bin_q Phase interval 0 0 (0, ⁇ / 2) 0 1 ( ⁇ / 2, ⁇ ) 1 0 (3 ⁇ / 2,2 ⁇ ) 1 1 ( ⁇ , 3 ⁇ / 2)
  • phase of the clock signal to be detected is 130 ° at the initial sampling time, and the sampling period number val sum of the 105 module is 300.
  • the initial phase ⁇ avg of the clock signal to be detected converges to 130.004 °, and the phase detection error is 0.004 °.
  • This mode is dedicated to solving the sampling errors that may occur when the 101 sampling circuit samples near the zero-crossing position of the clock signal to be detected.
  • the block diagram of this embodiment is shown in FIG. And use the clock signal of 122.88MHz which is commonly used in the system for sampling.
  • the val ref of the 100 module is 122.88x10 6 and the val sig is 2x10 9.
  • the phase difference between the clock signal to be detected and the sampling clock signal in a single sampling period can be calculated as:
  • the cumulative phase difference between the clock signal to be detected and the sampling clock signal is:
  • the bin output from each sampling period 101 is 2 bits of data, and the phase interval judgment conditions of the 102 module are shown in Table 4. To improve reliability, the range of the determined phase interval is enlarged here.
  • Table 4 Phase interval judgment conditions of specific embodiment 4
  • bin_i bin_q Phase interval 0 0 (- ⁇ / 2, ⁇ ) 0 1 (0,3 ⁇ / 2) 1 0 ( ⁇ , 5 ⁇ / 2) 1 1 ( ⁇ / 2,2 ⁇ )
  • phase of the clock signal to be detected is 130 ° at the initial sampling time, and the sampling period number val sum of the 105 module is 300.
  • the initial phase ⁇ avg of the clock signal to be detected converges to 130.275 °, and the phase detection error is 0.275 °.
  • modules can be implemented by software or hardware. For the latter, they can be implemented by the following methods, but not limited to this: the above-mentioned modules are all located in the same processor; The forms are located in different processors.
  • An embodiment of the present disclosure also provides a storage medium in which a computer program is stored, wherein the computer program is configured to execute any of the steps in the above method embodiments during runtime.
  • the above storage medium may include, but is not limited to: a USB flash drive, a read-only memory (Read-Only Memory, ROM for short), a random access memory (Random Access Memory, RAM for short), Various media that can store computer programs, such as removable hard disks, magnetic disks, or optical disks.
  • An embodiment of the present disclosure also provides an electronic device, including a memory and a processor, where the computer program is stored in the memory, and the processor is configured to run the computer program to perform the steps in any one of the foregoing method embodiments.
  • the electronic device may further include a transmission device and an input-output device, wherein the transmission device is connected to the processor, and the input-output device is connected to the processor.
  • the solution in the embodiments of the present disclosure can reduce the design difficulty of the sampling circuit and the operating frequency of the subsequent digital circuit through the undersampling method, and improve the circuit reliability.
  • the present disclosure can realize phase inversion or standardization processing through simple logic operations without applying the NCO circuit and the arc tangent circuit with a complicated structure, the algorithm is simple, and the design difficulty of digital circuits is reduced.
  • the disclosed algorithm has high compatibility and supports differential, single-ended, or orthogonal sampling methods.
  • the present disclosure can improve the phase detection accuracy by increasing the number of sampling cycles or reducing the correlation between the sampling clock frequency and the clock frequency to be detected.
  • the embodiments of the present disclosure only involve coarse sampling of the clock to be inspected without extracting the amplitude information of the clock to be inspected, so the phase detection scheme of the present disclosure can still achieve high reliability even for signals with high frequencies Sex.
  • the remaining circuits are digital circuits, and the sampling circuit can also be implemented in digital form, that is, TSPC trigger, so the overall circuit scheme is not sensitive to changes in PVT (Process Voltage) Temperature, and can achieve a higher Robustness.
  • modules or steps of the present disclosure can be implemented by a general-purpose computing device, they can be concentrated on a single computing device, or distributed in a network composed of multiple computing devices Above, optionally, they can be implemented with program code executable by the computing device, so that they can be stored in the storage device to be executed by the computing device, and in some cases, can be in a different order than here
  • the steps shown or described are performed, or they are made into individual integrated circuit modules respectively, or multiple modules or steps among them are made into a single integrated circuit module for implementation. In this way, the present disclosure is not limited to any specific combination of hardware and software.
  • the phase detection method, device, storage medium, and electronic device provided by the embodiments of the present invention have the following beneficial effects: making the phase detection algorithm simple, the circuit implementation difficulty low, the phase convergence speed fast, and the phase detection accuracy high.

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Abstract

一种相位检测方法、装置、存储介质及电子装置，其中，该方法包括：对待检测的时钟信号进行采样操作，得到二进制序列(S12)；根据所述二进制序列确定所述待检测的时钟信号在初始采样周期的相位区间，作为第一相位区间(S14)；利用所述第一相位区间中包括的参考相位区间对所述第一相位区间中包括的其他相位区间进行标准化操作，得到第二相位区间，其中，所述参考相位区间为在所述采样操作触发后在第一个采样周期内判定的相位区间，所述其他相位区间为在所述采样操作触发后在所述第一个采样周期之后的采样周期内判定的相位区间(S16)；对所述第二相位区间进行收敛，并根据收敛后的第二相位区间得到所述待检测的时钟信号的相位信息(S18)。

Description

相位检测方法、装置、存储介质及电子装置 技术领域
本公开涉及通信领域，具体而言，涉及一种相位检测方法、装置、存储介质及电子装置。
背景技术
多阵列天线基站中的大规模多输入多输出(Massive MIMO，Massive Multiple In Multiple Out)技术是4.5G以及5G通信中的关键技术。在5G通信中，空分复用(SDMA，Space Division Multiple Access)是Massive MIMO技术应用的一个重要例子。空分多址接入(SDMA，Space Division Multiple Access)使用波束赋型beamforming技术使信号能量集中在特定的方向传播，从而增大频谱利用效率，减小对其它接收机的干扰。beamforming对收发信机多通道之间信号的相位差异有着严苛的要求，例如sub 6G的5G基站收发信机多通道间的相位差异应小于5°。因此，无线基站***会采用一系列相位检测及调整措施来减小通道间的相位误差，进而对齐多通道信号的相位。
在相位同步机制中，对射频时钟信号相位的检测是首要一环，其相位检测精度直接影响多通道同步的效果。而当前并没有一个很好的针对射频时钟信号的高精度相位检测方案，此外，针对其他类型的时钟信号也没有很好的高精度相位检测方案。
针对相关技术中存在的上述问题，目前尚未提出有效的解决方案。
发明内容
本公开实施例提供了一种相位检测方法、装置、存储介质及电子装置，以至少解决相关技术中时钟信号相位检测精度低的问题。
根据本公开的一个实施例，提供了一种相位检测方法，包括：对待检测的时钟信号进行采样操作，得到二进制序列；根据所述二进制序列确定 所述待检测的时钟信号在初始采样周期的相位区间，作为第一相位区间；利用所述第一相位区间中包括的参考相位区间对所述第一相位区间中包括的其他相位区间进行标准化操作，得到第二相位区间，其中，所述参考相位区间为在所述采样操作触发后在第一个采样周期内判定的相位区间，所述其他相位区间为在所述采样操作触发后在所述第一个采样周期之后的采样周期内判定的相位区间；对所述第二相位区间进行收敛，并根据收敛后的第二相位区间得到所述待检测的时钟信号的相位信息。
根据本公开的又一个实施例，还提供了一种相位检测装置，包括：采样模块，设置为对待检测的时钟信号进行采样操作，得到二进制序列；相位区间判定模块，设置为根据所述二进制序列确定所述待检测的时钟信号在初始采样周期的相位区间，作为第一相位区间；标准化模块，设置为利用所述第一相位区间中包括的参考相位区间对所述第一相位区间中包括的其他相位区间进行标准化操作，得到第二相位区间，其中，所述参考相位区间为在所述采样操作触发后在第一个采样周期内判定的相位区间，所述其他相位区间为在所述采样操作触发后在所述第一个采样周期之后的采样周期内判定的相位区间；相位区间收敛模块，设置为对所述第二相位区间进行收敛，并根据收敛后的第二相位区间得到所述待检测的时钟信号的相位信息。
根据本公开的又一个实施例，还提供了一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行上述任一项方法实施例中的步骤。
根据本公开的又一个实施例，还提供了一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行上述任一项方法实施例中的步骤。
在本公开实施例中，通过采样待检测时钟信号信号，得到一系列二进制序列，并基于这些数字采样信息，在各采样周期判定待检测时钟信号的 相位区间，最后通过一系列的相位区间标准化操作，收敛出待检测时钟信号的相位信息。采用本公开实施例中的方案可以使得相位检测算法简单，电路实现难度低，相位收敛速度快，相位检测精度高。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1是根据本公开实施例的相位检测方法的流程图；
图2是根据本公开实施例的相位检测方案的***架构图；
图3是根据本公开实施例的相位差值累加模块的示意图；
图4是根据本公开实施例的采样模块的示意图；
图5是根据本公开实施例的相位区间判定模块的示意图；
图6是根据本公开实施例的相位区间标准化模块的示意图；
图7是根据本公开实施例的相位区间收敛模块的示意图；
图8是根据本公开实施例的采样模块的功能示意图；
图9是根据本公开实施例的普通模式和高精度模式的采样点覆盖图；
图10是根据本公开实施例的普通模式和高精度模式的误差分析图；
图11是根据本公开实施例的相位区间判决模块的功能示意图；
图12是根据本公开实施例的相位区间标准化模块的功能示意图；
图13是根据本公开实施例的相位区间收敛模块的功能示意图；
图14是根据本公开实施例的检测单端时钟相位的实例示意图；
图15是根据本公开实施例的检测正交时钟相位的实例示意图；
图16是根据本公开实施例的高精度检相模式的实例示意图；
图17是根据本公开实施例的高可靠性检相模式的实例示意图；
图18是根据本公开实施例的实施例的相位收敛曲线。
具体实施方式
下文中将参考附图并结合实施例来详细说明本公开。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。
需要说明的是，本公开的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
首先对相关技术如何进行相位检测进行说明：
在相关技术中，鉴频鉴相器(PFD，Phase and Frequency Detector)是常用的鉴别两输入时钟信号频率和相位差值的电路。一般而言，PFD由两D触发器和一个与非门构成，D触发器在接收输入时钟上升沿后，输出高电平，并在两D触发器输出均达到高电平后复位。因此，PFD可以输出表征两输入时钟信号频率或相位差值的脉冲信号。但PFD应用在收发机通道或其它场景的相位检测中会存在以下困难和问题：
首先，PFD鉴相将急剧增大原有***的复杂度。在需要进行相位检测的MIMO***中，收发信机通道数目已达到几十甚至上百，根据PFD鉴别两通路信号的特性，将要使用同等数量的PFD。而且，MIMO***一般采用多芯片组成，芯片与芯片之间的连线及存在的PFD将使PCB板布局变得十分复杂，且会降低电路可靠性。
其次，PFD无法直接或很难间接给出输入时钟信号的相位信息。PFD将两输入时钟信号的频率或相位差值表征为一定宽度的脉冲信号，而非一系列的高低电平或二进制序列，后级数字电路难以将其转化为单纯的相位信息。在需要直接检测出相位值的场景中，PFD无法满足应用需求。
最后，在无线通信场景中，PFD的鉴频鉴相能力受到很大的挑战。随着频谱资源的日益紧张以及传输数据量的剧增，通信技术不断演进，无线 通信频段向高频大带宽方向发展。对5G NR中Sub 6G低频段来说，PFD的鉴频鉴相能力已显得捉襟见肘，更不用说高达24.25～29.5GHz的5G高频段了。并且，这样高频的时钟信号已不是简单的方波或类方波，在接收这些信号后，PFD已不能正常或可靠地表现出其鉴频鉴相能力。
针对相关技术中采用PFD进行相位检测所出现的上述问题，在业界也提出了一些解决方案。例如：
在美国申请的一篇专利中提出了一种适用于无线通信领域的相位检测方法，但是需要说明的是，该专利中均存在以下不足：
在上述专利中使用了数控振荡器NCO及实现反正切功能的数字电路模块，这些数字电路模块能达到的精度有限，若运算迭代次数较小，将极大地限制相位检测精度，若迭代次数较大，虽然可以在一定程度上提高相位检测精度，但是会明显地增加运算资源开销。
由此可知，相关技术中提出的解决方案实际上是无法有效解决时钟信号相位检测精度低的问题，为了有效的解决相关技术中存在的时钟号相位检测精度低的问题，在本公开实施例中提供了一种相位检测方法、装置、存储介质及电子装置，下面结合实施例对本公开进行说明：
在本实施例中提供了一种相位检测方法，图1是根据本公开实施例的相位检测方法的流程图，如图1所示，该流程包括如下步骤：
步骤S12，对待检测的时钟信号进行采样操作，得到二进制序列；
步骤S14，根据所述二进制序列确定所述待检测的时钟信号在初始采样周期的相位区间，作为第一相位区间；
步骤S16，利用所述第一相位区间中包括的参考相位区间对所述第一相位区间中包括的其他相位区间进行标准化操作，得到第二相位区间，其中，所述参考相位区间为在所述采样操作触发后在第一个采样周期内判定的相位区间，所述其他相位区间为在所述采样操作触发后在所述第一个采样周期之后的采样周期内判定的相位区间；
步骤S18，对所述第二相位区间进行收敛，并根据收敛后的第二相位 区间得到所述待检测的时钟信号的相位信息。
其中，执行上述操作的可以是相位检测装置。在上述实施例中，上述得到的二进制序列可以是离散的二进制序列。
在上述实施例中，通过采样待检测时钟信号可以得到一系列二进制序列，基于这些数字采样信息，在各采样周期判定待检测时钟信号的相位区间，最后通过一系列的相位区间标准化操作，收敛出待检测时钟信号的相位信息。
在本公开实施例中，是无需过多地进行运算迭代的，因此，不会增加运算资源开销，此外，需要说明的是，经过实验验证，采用本公开中的方案，在无需过多运算迭代次数的情况下，也能够保证相位检测精度。相对于相关技术中存在的在运算迭代次数较小时，会极大地限制相位检测精度，在运算迭代次数较大时，会增加运算资源开销的问题，本公开实施例中的方案可以实现在降低运算迭代次数的前提下也能够保证相位检测精度。
此外，还需要说明的是，前述提及的相关专利中还包含复杂的矩阵乘法和复共轭运算，由于算法复杂，不利于应用***降低电路规模及功耗。并且，前述提及的专利中对输入的两待检信号有正交要求，因此仅能实现对正交信号的相位检测。而在本公开实施例中，是不会涉及到过于复杂的矩阵乘法和复共轭运算的，因此，可以有效降低应用***的电路规模，以及降低引用***的功耗的。
因此，采用本公开实施例中的方案可以使得相位检测算法简单，电路实现难度低，相位收敛速度快，相位检测精度高。下面结合其他实施例对本发明进行进一步的说明：
在一个可选的实施例中，所述对待检测的时钟信号进行采样操作，得到二进制序列包括：采用采样时钟信号对所述待检测的时钟信号进行采样操作，得到二进制序列，其中，所述采样时钟信号的频率与所述待检测的时钟信号的频率的最小公倍数超过预定阈值。在本实施例中，为了保证采样的多样性，应合理选择采样时钟信号的频率值，使待检测的时钟信号的 频率值与采样时钟信号的频率值具有较大的最小公倍数。
在一个可选的实施例中，根据所述二进制序列确定所述待检测的时钟信号在初始采样周期的相位区间，作为第一相位区间包括：根据所述二进制序列，判定各采样时钟信号上升沿所述待检测的时钟信号的相位区间；根据判定出的相位区间以及所述待检测的时钟信号相对于采样时钟信号的累积的相位差值确定初始采样时刻上所述待检测的时钟信号区间，作为所述第一相位区间，其中，所述采样时钟信号用于对所述待检测的时钟信号进行所述采样操作。
在一个可选的实施例中，根据所述二进制序列，判定各采样时钟信号上升沿所述待检测的时钟信号的相位区间包括：确定与所述二进制序列的类型对应的相位区间判决条件；根据所述二进制序列以及所述相位区间判决条件判定各采样时钟信号上升沿所述待检测的时钟信号的相位区间。
在一个可选的实施例中，所述二进制序列的类型包括以下至少之一：差分类型、单端类型、正交类型。在上述实施例中，根据得到的二进制序列类型(即差分、单端或正交等形式)，相位区间判决条件的配置是不同的，根据快速采样或高可靠性采样的要求，相位区间判决条件的配置不同。
在一个可选的实施例中，利用所述第一相位区间中包括的参考相位区间对所述第一相位区间中包括的其他相位区间进行标准化操作，得到第二相位区间包括：以所述参考相位区间为标准，将所述其他相位区间变换到所述参考相位区间处于的相位周期内，得到所述第二相位区间。
在一个可选的实施例中，以所述参考相位区间为标准，将所述其他相位区间变换到所述参考相位区间处于的相位周期内，得到所述第二相位区间包括：在确定所述其他相位区间与所述参考相位区间之间没有交集时，重复对所述其他相位区间进行翻转，直至所述其他相位区间与所述参考相位区间产生交集为止，将所述参考相位区间和进行了翻转后的所述其他相位区间作为所述第二相位区间。
在一个可选的实施例中，所述翻转包括左移2π或者右移2π。
在一个可选的实施例中，在确定出所述第一相位区间之后，所述方法还包括：在确定所述其他相位区间与所述参考相位区间之间有交集时，在不对所述其他相位区间进行所述标准化操作的前提下，直接对所述第一相位区间进行收敛，并根据收敛后的第一相位区间得到所述待检测的时钟信号的相位信息。
在一个可选的实施例中，在得到所述第二相位区间之后，所述方法还包括：依次求取所述第二相位区间在当前采样周期的交集，直到所述第二相位区间在当前采样周期的交集的上限和下限的差值小于预定值为止，其中，所述第二相位区间在当前采样周期的交集是通过对所述第二相位区间在所述当前采样周期的相位区间与所述第二相位区间在上一采样周期的交集取交集得到的；对所述第二相位区间进行收敛，并根据收敛后的第二相位区间得到所述待检测的时钟信号的相位信息包括：通过对差值小于所述预定值的上限和下限取均值得到所述待检测的时钟信号在初始采样时刻的初始相位；通过对所述初始相位与相位差值求和得到所述当前采样周期内所述待检测时钟信号的相位，其中，所述相位差值为根据所述待检测的时钟信号的频率与进行所述采样操作时所使用的采样时钟信号的频率关系计算出的当前采样周期所述待检测的时钟信号相对于所述采样时钟信号的累积的相位差值。在本实施例中，可以基于加法器或乘法器，根据待检测时钟信号与采样时钟信号的频率关系及经历的采样周期数，统计自触发采样操作起待检测时钟信号相对采样时钟信号的相位差值。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本公开各个实施例所述的方法。
在本实施例中还提供了一种相位检测装置，该装置用于实现上述实施例及优选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
图2是根据本公开实施例的相位检测装置的结构框图，如图2所示，该装置包括：
采样模块101，设置为对待检测的时钟信号进行采样操作，得到二进制序列；相位区间判定模块102，设置为根据所述二进制序列确定所述待检测的时钟信号在初始采样周期的相位区间，作为第一相位区间；标准化模块103(也可以称为相位区间标准化模块)，设置为利用所述第一相位区间中包括的参考相位区间对所述第一相位区间中包括的其他相位区间进行标准化操作，得到第二相位区间，其中，所述参考相位区间为在所述采样操作触发后在第一个采样周期内判定的相位区间，所述其他相位区间为在所述采样操作触发后在所述第一个采样周期之后的采样周期内判定的相位区间；相位区间收敛模块104，设置为对所述第二相位区间进行收敛，并根据收敛后的第二相位区间得到所述待检测的时钟信号的相位信息。
此外，还需要说明的是，图2所示的结构框图除了包括上述各模块外，还可以包括累积相位差计算模块100以及控制模块105，图2中示出了上述的六个模块，各模块之间的连接关系可以参考附图2。其中，图2中各参数在后述的实施例中会进行详细描述。
在上述实施例中，累积相位差计算模块100可以基于加法器或乘法器，根据待检测时钟信号与采样时钟信号的频率关系及经历的采样周期数，统计自触发采样操作起，待检测时钟信号相对采样时钟信号的相位差值。
采样模块101的输入clk sig可以是差分、单端或正交类型的方波、类方波或正弦信号，输出为对应形式的二进制序列。该模块101可以由核心 采样器(也可以简称为采样器)及后级波形整形器构成，目的是将输入的模拟幅度信息，转换为离散的数字信号(即，二进制序列)。核心采样器可由真单向钟控触发器(TSPC，True Single Phase Clock)或电流模逻辑(CML，Current Mode Logic)等形式的触发器来实现。后级波形整形器可由施密特触发器或反相器电路实现，设置为信号摆幅放大及波形整形。根据待检测时钟信号的类型，采样器可选择为差分、单端或正交等形式。根据对检相精度的要求，可选择一定频率的采样时钟，减弱待检测时钟信号与采样时钟信号频率的相关性，即增大待检测时钟信号频率与采样时钟信号频率的最小公倍数。可选地，所述采样模块可以包括采样器，设置为采用采样时钟信号对所述待检测的时钟信号进行采样操作，得到二进制序列，其中，所述采样时钟信号的频率与所述待检测的时钟信号的频率的最小公倍数超过预定阈值。
上述相位区间判定模块102可以根据采样模块101输出的二进制序列，判定各采样时钟信号上升沿待检测时钟信号的相位区间，并根据采样时钟信号与待检测时钟信号的相位关系确定初始采样时刻待检测时钟信号的相位区间。具体地，该相位区间判定模块102可以包括：相位区间判决器，设置为根据所述二进制序列，判定各采样时钟信号上升沿所述待检测的时钟信号的相位区间；加法器，设置为根据判定出的相位区间以及所述待检测的时钟信号相对于采样时钟信号的累积的相位差值确定初始采样时刻上所述待检测的时钟信号区间，作为所述第一相位区间，其中，所述采样时钟信号用于对所述待检测的时钟信号进行所述采样操作。后续会对相位区间判定模块102进行具体描述。
上述相位区间判决器可以确定与所述二进制序列的类型对应的相位区间判决条件；根据所述二进制序列以及所述相位区间判决条件判定各采样时钟信号上升沿所述待检测的时钟信号的相位区间。在本实施例中，根据采样模块101输出的二进制序列类型(即差分、单端或正交等形式)的不同，相位区间判决条件的配置也不同。根据快速采样或高可靠性采样的要求，相位区间判决条件的配置不同。
上述的标准化模块103可以设置为以所述参考相位区间为标准，将所述其他相位区间变换到所述参考相位区间处于的相位周期内，得到所述第二相位区间。可选地，所述标准化模块103包括：相位缩放器，设置为在确定其他相位区间与所述参考相位区间之间没有交集时，重复对所述其他相位区间进行翻转，直至所述其他相位区间与所述参考相位区间产生交集为止，将所述参考相位区间和进行了翻转后的所述其他相位区间作为所述第二相位区间。可选地，上述翻转包括左移2π或者右移2π。
在一个可选的实施例中，上述装置还设置为：在确定出所述第一相位区间之后，在确定所述其他相位区间与所述参考相位区间之间有交集时，在不对所述其他相位区间进行所述标准化操作的前提下，直接对所述第一相位区间进行收敛，并根据收敛后的第一相位区间得到所述待检测的时钟信号的相位信息。
在一个可选的实施例中，上述相位区间收敛模块104包括：区间求交集模块，设置为在得到所述第二相位区间之后，依次求取所述第二相位区间在当前采样周期的交集，直到所述第二相位区间在当前采样周期的交集的上限和下限的差值小于预定值为止，其中，所述第二相位区间在当前采样周期的交集是通过对所述第二相位区间在所述当前采样周期的相位区间与所述第二相位区间在上一采样周期的交集取交集得到的；均值模块，设置为通过对差值小于所述预定值的上限和下限取均值得到所述待检测的时钟信号在初始采样时刻的初始相位；加法器，设置为通过对所述初始相位与相位差值求和得到所述当前采样周期内所述待检测时钟信号的相位，其中，所述相位差值为根据所述待检测的时钟信号的频率与进行所述采样操作时所使用的采样时钟信号的频率关系计算出的当前采样周期所述待检测的时钟信号相对于所述采样时钟信号的累积的相位差值。由此可知，该相位区间收敛模块104是设置为求取相位区间标准化模块103输出相位区间的交集。该模块104可由简单的比较器构成，通过比较当前采样周期输入相位区间与上一采样周期交集相位区间的上限及下限，更新当前采样周期的交集相位区间。通过增加均值模块，相位区间收敛模块可直接 输出初始采样时刻待检测时钟信号的相位值，在此相位值的基础上增加当前待检测时钟信号相对采样时钟信号的相位差值，即可得到当前采样时钟信号的相位值。
在一个可选的实施例中，上述的控制模块105设置为控制本公开实施例中的检相方案中各模块，通过该模块可配置采样周期数，实现触发或终止检相操作，复位检相流程等功能。通过合理配置采样时钟信号频率及采样周期数，本公开检相方案可达到很高的精度。
下面结合附图对上述各个模块及模块所包括的具体器件进行说明：
图3所示为累积相位差计算模块100的结构图，如图3所示，该累积相位差计算模块100可以包括单采样周期相位差值计算器1001和累加器1002，其中单采样周期相位差值计算器1001根据采样时钟信号频率值val ref与待检测时钟信号频率值val sig的关系，计算单采样周期待检测时钟信号与采样时钟信号间的相位差值θ T，其中，θ T＝2π·mod(val sig/val ref)，并通过累加器1002累积k个采样周期后待检测时钟信号相对采样时钟信号的相位差值Δθ k，Δθ k＝K·θ T。
图4所示为采样模块101的结构图，如图4所示，该采样模块101在采样时钟信号下对待检测时钟信号进行采样，将模拟的幅度信息clk sig转换为离散的数字信号bin。该采样模块101可以包括采样器1011和波形整形器1012。
其中采样器1011是由TSPC或CML等形式触发器组成的采样器，1012对1011输出的信号进行摆幅放大和波形整形，并输出理想的数字脉冲信号bin。如图8所示的待检测时钟信号为正交形式的场景，采样器101在每个采样时钟信号clk ref的时钟上升沿采样待检测时钟信号，若采样电平高于或等于共模电平则输出0，若采样电平低于共模电平则输出1。根据对检相精度的要求，可选择一定频率的采样时钟信号，减弱待检测时钟信号与采样时钟信号频率的相关性，即增大待检测时钟信号频率与采样时 钟信号频率的最小公倍数，避免采样进入循环。若待检测时钟信号频率值与采样时钟信号频率值的最小公倍数较小，即存在较小的整数m和n，使得m·val sig＝n·val ref，则采样器101输出的二进制数据在经历n个采样周期后将进入周期性循环，即在n个采样周期达到最大的采样多样性。如图9、图10的普通模式和高精度模式采样点覆盖图及误差分析曲线所示，通过选择频率值与待检测时钟信号频率相关性较弱的采样时钟信号，可使采样点覆盖整个[0,2π)的相位区间，增大采样样本的多样性，并显著地提高整体检相方案的检相精度。
图5所示为相位区间判定模块102的结构图，如图5所示，该模块可以根据输入的二进制序列bin及由reg写入的判决条件，判定当前采样周期待检测时钟信号的相位区间，并根据待检测时钟信号相对采样时钟信号的累积相位差Δθ k确定初始采样时刻待检测时钟信号的相位区间[θ lk,θ hk)，其中下标k为经历的采样周期数。该相位区间判定模块102可以包括相位区间判决器1021和加法器1022，其中相位区间判决器1021，可以根据输入的二进制序列bin及由reg写入的判决条件，判断待检测时钟信号的实时相位区间[φ lk,φ hk)，加法器1022，在[φ lk,φ hk)基础上减去待检测时钟信号相对采样时钟信号的相位差值Δθ k，得到初始采样时刻待检测时钟信号的相位区间[θ lk,θ hk)，θ lk＝φ lk-Δθ k，θ hk＝φ hk-Δθ k。可根据待检测时钟信号的形式(如单端、差分、正交等)和检测可靠性要求，配置相位区间的判决条件。待检测时钟信号为正交形式下，相位区间判定模块102的相位区间判决条件可配置为如图11所示。
图6所示为标准化模块103的结构图，如图6所示，该模块以采样操作触发后第一个采样周期判定的相位区间[θ l0,θ h0)为参考区间，判断后续采样周期的[θ lk,θ hk)是否与[θ l0,θ h0)有区间交叠。若不存在区间交叠，则对[θ lk,θ hk)进行区间翻转，即左移或右移2π操作，直至与[θ l0,θ h0)产生区间交集；若存在区间交叠，则对[θ lk,θ hk)不做区间翻转。103模块输出标准化处理后的相位区间[θ’ lk,θ’ hk)。该模块可以包括相位区间交叠判决器1031和相位缩放器1032，其中，相位区间交叠判决器1031，是以采样操作触发后第一个 采样周期判定的相位区间[θ l0,θ h0)为参考区间，判断后续采样周期的[θ lk,θ hk)是否与[θ l0,θ h0)有区间交叠。若不存在区间交叠，则通过相位缩放器1032对[θ lk,θ hk)进行区间翻转，即左移或右移2π操作，直至与[θ l0,θ h0)产生区间交集；若存在区间交叠，则对[θ lk,θ hk)不做区间翻转。由于相位区间判定模块102存在θ lk＝φ lk-Δθ k、θ hk＝φ hk-Δθ k的相位运算，其中φ lk、φ hk∈[0,2π)，Δθ k∈[0,2π)，则θ lk、θ hk∈[-2π,2π)。因此，在本实施例中做标准化的意义在于将[θ lk,θ hk)变换到参考区间[θ l0,θ h0)处于的相位周期，以便与参考区间进行相位区间上限及下限的比较判断。如图12所示，若[θ lk,θ hk)的上限θ hk小于[θ l0,θ h0)的下限θ l0，则[θ lk,θ hk)右移2π，产生新的区间[θ’ lk,θ’ hk)，并且[θ’ lk,θ’ hk)与[θ l0,θ h0)存在区间交叠[θ l0,θ’ hk)，θ’ lk＝θ lk+2π，θ’ hk＝θ hk+2π；若[θ lk,θ hk)的下限θ lk大于[θ l0,θ h0)的上限θ h0，则[θ lk,θ hk)左移2π，产生新的区间[θ’ lk,θ’ hk)，并且[θ’ lk,θ’ hk)与[θ l0,θ h0)存在区间交叠[θ’ lk,θ h0)，θ’ lk＝θ lk-2π，θ’ hk＝θ hk-2π。
图7所示为相位区间收敛模块104的结构图，如图7所示，该模块对每个采样周期输入的[θ’ lk,θ’ hk)求取交集，不断缩小区间范围。在经历足够的采样周期数k后，通过均值计算方式收敛出初始采样时刻待检测时钟信号的相位信息，根据待检测时钟信号相对采样时钟信号的相位差值Δθ k计算出当前采样周期待检测时钟信号的相位θ sig。该模块可以包括区间求交集模块1041，延时模块1042，均值模块1043和加法器1044，其中，1041通过比较当前采样周期输入相位区间[θ’ lk,θ’ hk)与上一采样周期交集相位区间[θ lik-1,θ hik-1)的上限及下限，更新当前采样周期的交集相位区间[θ lik,θ hik)，[θ lik-1,θ hik-1)通过1042延迟单个采样周期得到。若θ’ lk＜θ lik-1或θ’ hk＜θ hik-1，则θ lik＝θ lik-1、θ hik＝θ’ hk；若θ’ lk≥θ lik-1或θ’ hk≥θ hik-1，则θ lik＝θ’ lk、θ hik＝θ hik-1，即[θ lik,θ hik)＝[θ’ lk,θ’ hk)∩[θ lik-1,θ hik-1)。如图13所示，通过对每个采样周期的[θ’ lk,θ’ hk)不断求交集，待经历足够的采样周期数后，θ lik将无限趋近于θ hik，再经过1043均值模块即可收敛出待检测时钟信号的初始相位θ avg，θ avg＝(θ lik+θ hik)/2。θ avg通过1044加法器与待检测时钟信号相对采样时钟信号的相位差值Δθ k求和，得到待检测时钟信号的实时相位θ sig。
下面结合具体实施例对本公开进行说明：
具体实施例1
该实施例框图如图14所示，待检测时钟信号为单端信号，设定其频率为2GHz，并采用***中常用的频率为122.88MHz的时钟信号进行采样。配置100模块的val ref为122.88x10 6，val sig为2x10 9，可计算出单采样周期待检测时钟信号与采样时钟信号间的相位差值为：
θ T＝99.375°
在经历k个采样周期后，待检测时钟信号与采样时钟信号的累积相位差值为：
Δθ K＝K×99.375°
待检测时钟信号为单端信号时，每采样周期101输出的bin为1bit的数据，102模块的相位区间判决条件如表1所示：
表1具体实施例1相位区间判决条件
bin 相位区间
0 [0,π)
1 [π,2π)
设定采样初始时刻待检测时钟信号相位为130°，105模块的采样周期数val sum为300。如图18相位收敛曲线所示，采样结束后，待检测时钟信号的初始相位θ avg收敛至130.275°，检相误差为0.275°。
具体实施例2
该实施例框图如图15所示，待检测时钟信号为正交信号，设定其频率为2GHz，并采用***中常用的频率为122.88MHz的时钟信号进行采样。配置100模块的val ref为122.88x10 6，val sig为2x10 9，可计算出单采样周期待检测时钟信号与采样时钟信号间的相位差值为：
θ T＝99.375°
在经历k个采样周期后，待检测时钟信号与采样时钟信号的累积相位差值为：
Δθ K＝K×99.375°
待检测时钟信号为正交信号时，每采样周期101输出的bin为2bit的数据，102模块的相位区间判决条件如表2所示：
表2具体实施例2相位区间判决条件
bin_i bin_q 相位区间
0 0 [0,π/2)
0 1 [π/2,π)
1 0 [3π/2,2π)
1 1 [π,3π/2)
设定采样初始时刻待检测时钟信号相位为130°，105模块的采样周期数val sum为300。如图18相位收敛曲线所示，采样结束后，待检测时钟信号的初始相位θ avg收敛至130.275°，检相误差为0.275°。
具体实施例3
该模式致力于提高本公开方案的检相精度，对101采样模块来说，若待检测时钟信号频率值与采样时钟信号频率值的最小公倍数较小，即存在较小的整数m和n，使得m x val sig＝n x val ref，则101输出的二进制数据在经历n个采样周期后将进入周期性循环，即在n个采样周期达到最大的采样多样性。该实施例框图如图16所示，待检测时钟信号为正交信号，设定其频率为2GHz。为提高检相精度，这里采用122.881MHz的时钟信号进行采样。配置100模块的val ref为122.881x10 6，val sig为2x10 9，可计算出单采样周期待检测时钟信号与采样时钟信号间的相位差值为：
θ T＝99.3273°
在经历k个采样周期后，待检测时钟信号与采样时钟信号的累积相位差值为：
Δθ K＝K×99.3273°
待检测时钟信号为正交信号时，每采样周期101输出的bin为2bit的数据，102模块的相位区间判决条件如表3所示：
表3具体实施例3的相位区间判决条件
bin_i bin_q 相位区间
0 0 [0,π/2)
0 1 [π/2,π)
1 0 [3π/2,2π)
1 1 [π,3π/2)
设定采样初始时刻待检测时钟信号相位为130°，105模块的采样周期数val sum为300。如图18相位收敛曲线所示，采样结束后，待检测时钟信号的初始相位θ avg收敛至130.004°，检相误差为0.004°。
具体实施例4
该模式致力于解决101采样电路在待检测时钟信号过零点位置附近采样时可能出现的采样错误，该实施例框图如图17所示，待检测时钟信号为正交信号，设定其频率为2GHz，并采用***中常用的频率为122.88MHz的时钟信号进行采样。配置100模块的val ref为122.88x10 6，val sig为2x10 9，可计算出单采样周期待检测时钟信号与采样时钟信号间的相位差值为：
θ T＝99.375°
在经历k个采样周期后，待检测时钟信号与采样时钟信号的累积相位差值为：
Δθ K＝K×99.375°
待检测时钟信号为正交信号时，每采样周期101输出的bin为2bit的数据，102模块的相位区间判决条件如表4所示。为提高可靠性，这里将判定的相位区间的范围放大。
表4具体实施例4的相位区间判决条件
bin_i bin_q 相位区间
0 0 [-π/2,π)
0 1 [0,3π/2)
1 0 [π,5π/2)
1 1 [π/2,2π)
设定采样初始时刻待检测时钟信号相位为130°，105模块的采样周期 数val sum为300。如图18相位收敛曲线所示，采样结束后，待检测时钟信号的初始相位θ avg收敛至130.275°，检相误差为0.275°。
需要说明的是，上述各个模块是可以通过软件或硬件来实现的，对于后者，可以通过以下方式实现，但不限于此：上述模块均位于同一处理器中；或者，上述各个模块以任意组合的形式分别位于不同的处理器中。
本公开的实施例还提供了一种存储介质，该存储介质中存储有计算机程序，其中，该计算机程序被设置为运行时执行上述任一项方法实施例中的步骤。
可选地，在本实施例中，上述存储介质可以包括但不限于：U盘、只读存储器(Read-Only Memory，简称为ROM)、随机存取存储器(Random Access Memory，简称为RAM)、移动硬盘、磁碟或者光盘等各种可以存储计算机程序的介质。
本公开的实施例还提供了一种电子装置，包括存储器和处理器，该存储器中存储有计算机程序，该处理器被设置为运行计算机程序以执行上述任一项方法实施例中的步骤。
可选地，上述电子装置还可以包括传输设备以及输入输出设备，其中，该传输设备和上述处理器连接，该输入输出设备和上述处理器连接。
可选地，本实施例中的具体示例可以参考上述实施例及可选实施方式中所描述的示例，本实施例在此不再赘述。
与现有技术相比，本公开实施例中的方案可通过欠采样方式，降低采样电路的设计难度及后级数字电路的工作频率，提高了电路可靠性。其次，本公开通过简单的逻辑运算即可实现对相位的翻转或标准化处理，而没有应用结构复杂的NCO电路及反正切电路，算法简单，降低了数字电路的 设计难度。不仅如此，本公开算法兼容性高，支持差分、单端或正交等采样方式。另外，本公开可通过增加采样周期数或降低采样时钟频率与待检时钟频率的相关性，提升检相精度。还有，本公开实施例中只涉及对待检时钟的粗采样，而不提取待检时钟的幅度信息，因此即便对于频率很高的待检信号，本公开检相方案依然能够达到较高的可靠性。最后，本公开除采样电路外，其余电路均为数字电路，并且采样电路也可使用数字形式，即TSPC触发器实现，因此整体电路方案对PVT(Process Voltage Temperature)变化不敏感，可以实现较高的鲁棒性。
显然，本领域的技术人员应该明白，上述的本公开的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本公开不限制于任何特定的硬件和软件结合。
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。
工业实用性
如上所述，本发明实施例提供的一种相位检测方法、装置、存储介质及电子装置具有以下有益效果：使得相位检测算法简单，电路实现难度低，相位收敛速度快，相位检测精度高。

Claims (22)

  1. 一种相位检测方法，包括：
    对待检测的时钟信号进行采样操作，得到二进制序列；
    根据所述二进制序列确定所述待检测的时钟信号在初始采样周期的相位区间，作为第一相位区间；
    利用所述第一相位区间中包括的参考相位区间对所述第一相位区间中包括的其他相位区间进行标准化操作，得到第二相位区间，其中，所述参考相位区间为在所述采样操作触发后在第一个采样周期内判定的相位区间，所述其他相位区间为在所述采样操作触发后在所述第一个采样周期之后的采样周期内判定的相位区间；
    对所述第二相位区间进行收敛，并根据收敛后的第二相位区间得到所述待检测的时钟信号的相位信息。
  2. 根据权利要求1所述的方法，其中，所述对待检测的时钟信号进行采样操作，得到二进制序列包括：
    采用采样时钟信号对所述待检测的时钟信号进行采样操作，得到二进制序列，其中，所述采样时钟信号的频率与所述待检测的时钟信号的频率的最小公倍数超过预定阈值。
  3. 根据权利要求1所述的方法，其中，根据所述二进制序列确定所述待检测的时钟信号在初始采样周期的相位区间，作为第一相位区间包括：
    根据所述二进制序列，判定各采样时钟信号上升沿所述待检测的时钟信号的相位区间；
    根据判定出的相位区间以及所述待检测的时钟信号相对于采样时钟信号的累积的相位差值确定初始采样时刻上所述待检测的时钟信号区间，作为所述第一相位区间，其中，所述采样时钟信号用于对 所述待检测的时钟信号进行所述采样操作。
  4. 根据权利要求3所述的方法，其中，根据所述二进制序列，判定各采样时钟信号上升沿所述待检测的时钟信号的相位区间包括：
    确定与所述二进制序列的类型对应的相位区间判决条件；
    根据所述二进制序列以及所述相位区间判决条件判定各采样时钟信号上升沿所述待检测的时钟信号的相位区间。
  5. 根据权利要求4所述的方法，其中，所述二进制序列的类型包括以下至少之一：
    差分类型、单端类型、正交类型。
  6. 根据权利要求1所述的方法，其中，利用所述第一相位区间中包括的参考相位区间对所述第一相位区间中包括的其他相位区间进行标准化操作，得到第二相位区间包括：
    以所述参考相位区间为标准，将所述其他相位区间变换到所述参考相位区间处于的相位周期内，得到所述第二相位区间。
  7. 根据权利要求6所述的方法，其中，以所述参考相位区间为标准，将所述其他相位区间变换到所述参考相位区间处于的相位周期内，得到所述第二相位区间包括：
    在确定所述其他相位区间与所述参考相位区间之间没有交集时，重复对所述其他相位区间进行翻转，直至所述其他相位区间与所述参考相位区间产生交集为止，将所述参考相位区间和进行了翻转后的所述其他相位区间作为所述第二相位区间。
  8. 根据权利要求7所述的方法，其中，所述翻转包括左移2π或者右移2π。
  9. 根据权利要求1所述的方法，其中，在确定出所述第一相位区间之后，所述方法还包括：
    在确定所述其他相位区间与所述参考相位区间之间有交集时，在不对所述其他相位区间进行所述标准化操作的前提下，直接对所述第一相位区间进行收敛，并根据收敛后的第一相位区间得到所述待检测的时钟信号的相位信息。
  10. 根据权利要求7所述的方法，其中：
    在得到所述第二相位区间之后，所述方法还包括：
    依次求取所述第二相位区间在当前采样周期的交集，直到所述第二相位区间在当前采样周期的交集的上限和下限的差值小于预定值为止，其中，所述第二相位区间在当前采样周期的交集是通过对所述第二相位区间在所述当前采样周期的相位区间与所述第二相位区间在上一采样周期的交集取交集得到的；
    对所述第二相位区间进行收敛，并根据收敛后的第二相位区间得到所述待检测的时钟信号的相位信息包括：
    通过对差值小于所述预定值的上限和下限取均值得到所述待检测的时钟信号在初始采样时刻的初始相位；通过对所述初始相位与相位差值求和得到所述当前采样周期内所述待检测的时钟信号的相位，其中，所述相位差值为根据所述待检测的时钟信号的频率与进行所述采样操作时所使用的采样时钟信号的频率关系计算出的当前采样周期所述待检测的时钟信号相对于所述采样时钟信号的累积的相位差值。
  11. 一种相位检测装置，包括：
    采样模块，设置为对待检测的时钟信号进行采样操作，得到二进制序列；
    相位区间判定模块，设置为根据所述二进制序列确定所述待检测的时钟信号在初始采样周期的相位区间，作为第一相位区间；
    标准化模块，设置为利用所述第一相位区间中包括的参考相位区间对所述第一相位区间中包括的其他相位区间进行标准化操作，得到第二相位区间，其中，所述参考相位区间为在所述采样操作触发后在第一个采样周期内判定的相位区间，所述其他相位区间为在所述采样操作触发后在所述第一个采样周期之后的采样周期内判定的相位区间；
    相位区间收敛模块，设置为对所述第二相位区间进行收敛，并根据收敛后的第二相位区间得到所述待检测的时钟信号的相位信息。
  12. 根据权利要求11所述的装置，其中，所述采样模块包括：
    采样器，设置为采用采样时钟信号对所述待检测的时钟信号进行采样操作，得到二进制序列，其中，所述采样时钟信号的频率与所述待检测的时钟信号的频率的最小公倍数超过预定阈值。
  13. 根据权利要求11所述的装置，其中，所述相位区间判定模块包括：
    相位区间判决器，设置为根据所述二进制序列，判定各采样时钟信号上升沿所述待检测的时钟信号的相位区间；
    加法器，设置为根据判定出的相位区间以及所述待检测的时钟信号相对于采样时钟信号的累积的相位差值确定初始采样时刻上所述待检测的时钟信号区间，作为所述第一相位区间，其中，所述采样时钟信号用于对所述待检测的时钟信号进行所述采样操作。
  14. 根据权利要求13所述的装置，其中，所述相位区间判决器设置为：
    确定与所述二进制序列的类型对应的相位区间判决条件；
    根据所述二进制序列以及所述相位区间判决条件判定各采样时钟信号上升沿所述待检测的时钟信号的相位区间。
  15. 根据权利要求14所述的装置，其中，所述二进制序列的类型包括以下至少之一：
    差分类型、单端类型、正交类型。
  16. 根据权利要求11所述的装置，其中，所述标准化模块设置为：
    以所述参考相位区间为标准，将所述其他相位区间变换到所述参考相位区间处于的相位周期内，得到所述第二相位区间。
  17. 根据权利要求16所述的装置，其中，所述标准化模块包括：
    相位缩放器，设置为在确定其他相位区间与所述参考相位区间之间没有交集时，重复对所述其他相位区间进行翻转，直至所述其他相位区间与所述参考相位区间产生交集为止，将所述参考相位区间和进行了翻转后的所述其他相位区间作为所述第二相位区间。
  18. 根据权利要求17所述的装置，其中，所述翻转包括左移2π或者右移2π。
  19. 根据权利要求11所述的装置，其中，所述装置还设置为：
    在确定出所述第一相位区间之后，在确定所述其他相位区间与所述参考相位区间之间有交集时，在不对所述其他相位区间进行所述标准化操作的前提下，直接对所述第一相位区间进行收敛，并根据收敛后的第一相位区间得到所述待检测的时钟信号的相位信息。
  20. 根据权利要求17所述的装置，其中，所述相位区间收敛模块包括：
    区间求交集模块，设置为在得到所述第二相位区间之后，依次求取所述第二相位区间在当前采样周期的交集，直到所述第二相位区间在当前采样周期的交集的上限和下限的差值小于预定值为止，其中，所述第二相位区间在当前采样周期的交集是通过对所述第二相位区间在所述当前采样周期的相位区间与所述第二相位区间在上一采样周期的交集取交集得到的；
    均值模块，设置为通过对差值小于所述预定值的上限和下限取均值得到所述待检测的时钟信号在初始采样时刻的初始相位；
    加法器，设置为通过对所述初始相位与相位差值求和得到所述当前采样周期内所述待检测的时钟信号的相位，其中，所述相位差值为根据所述待检测的时钟信号的频率与进行所述采样操作时所使用的采样时钟信号的频率关系计算出的当前采样周期所述待检测的时钟信号相对于所述采样时钟信号的累积的相位差值。
  21. 一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行所述权利要求1至10任一项中所述的方法。
  22. 一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行所述权利要求1至10任一项中所述的方法。
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