WO2020042261A1 - 显示面板及其制作方法 - Google Patents

显示面板及其制作方法 Download PDF

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Publication number
WO2020042261A1
WO2020042261A1 PCT/CN2018/107409 CN2018107409W WO2020042261A1 WO 2020042261 A1 WO2020042261 A1 WO 2020042261A1 CN 2018107409 W CN2018107409 W CN 2018107409W WO 2020042261 A1 WO2020042261 A1 WO 2020042261A1
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WIPO (PCT)
Prior art keywords
layer
pixel definition
pixel
display panel
anode
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PCT/CN2018/107409
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English (en)
French (fr)
Inventor
陈哲
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武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/317,572 priority Critical patent/US10930717B2/en
Publication of WO2020042261A1 publication Critical patent/WO2020042261A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/813—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/816—Multilayers, e.g. transparent multilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
    • H10K71/166—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering using selective deposition, e.g. using a mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present application relates to the field of display, and in particular to a display panel and a manufacturing method thereof.
  • OLED Organic Light-Emitting Diode
  • LCD liquid crystal display
  • OLEDs use a very thin coating of organic materials and a glass substrate. When an electric current passes through, these organic materials emit light.
  • the display panel has the advantages of light and thin screen, wide field of vision, and energy saving. Therefore, OLED technology is gradually favored by the market.
  • a planarization layer 12, an anode layer 13, a pixel definition layer 14 and a support layer are respectively disposed above the array substrate 11.
  • the anode layer 12 is enclosed by the pixel defining layer 14 to form an opening region.
  • the size of the opening of the pixel definition layer determines the size of the light outlet of the OLED organic light-emitting layer on the anode layer 12.
  • the size of the opening area of the pixel definition layer 14 cannot completely match the size of the anode layer 13. Excessive openings in the pixel definition layer 14 cause the silver metal in the anode layer 13 to be eroded and damage the anode layer 13.
  • Too small openings in the pixel definition layer 14 will cause the edges of the anode layer 13 to be wrapped by the pixel definition layer 14, resulting in OLED organic
  • the presence of an invalid light-emitting area in the light-emitting layer causes the area of the effective light-emitting area in the OLED organic light-emitting layer to decrease, which reduces the aperture ratio of the display panel. Therefore, a display panel and a manufacturing method thereof are urgently needed to solve the above problems.
  • the pixel definition layer covers the edge portion of the anode layer, which causes a problem that the pixel aperture ratio of the display panel is reduced while protecting the anode layer from being eroded.
  • a method for manufacturing a display panel including the following steps:
  • Step S10 Provide an array substrate on which an active drain metal is disposed;
  • Step S20 A planarization layer and a pixel definition layer are sequentially prepared above the array substrate, the pixel definition layer includes a plurality of pixel definition bodies distributed at intervals, and a space region between the pixel definition bodies forms a pixel area;
  • Step S30 preparing the anode layer in the pixel region, where the anode layer includes a first transparent electrode layer, a silver metal layer, and a second transparent electrode layer, and an edge of the anode layer is bonded to the pixel definition layer;
  • the planarization layer is provided with a via hole, and the anode layer is electrically connected to the source and drain metal through the via hole.
  • the step S30 specifically includes:
  • An anode metal layer is formed in the pixel region, and the anode metal layer is exposed, etched, and developed using a photomask process to form an anode layer.
  • the anode layer includes a raised portion, and the raised portion is located at a bonding position between the anode layer and the pixel definition layer.
  • a side of the pixel defining body near the pixel region is a slope surface.
  • step S20 further includes preparing a support layer above the pixel definition layer, and the preparation materials of the planarization layer, the pixel definition layer, and the support layer are all made of photoresist materials;
  • planarization layer, the pixel definition layer and the support layer are prepared in the same photomask process.
  • a method for manufacturing a display panel including the following steps:
  • Step S10 Provide an array substrate on which an active drain metal is disposed;
  • Step S20 A planarization layer and a pixel definition layer are sequentially prepared above the array substrate, the pixel definition layer includes a plurality of pixel definition bodies distributed at intervals, and a space region between the pixel definition bodies forms a pixel area;
  • Step S30 Prepare the anode layer in the pixel region, and an edge of the anode layer and the pixel definition layer are bonded.
  • the step S30 specifically includes:
  • An anode metal layer is formed in the pixel region, and the anode metal layer is exposed, etched, and developed using a photomask process to form an anode layer.
  • the anode layer includes a raised portion, and the raised portion is located at a bonding position between the anode layer and the pixel definition layer.
  • a side of the pixel defining body near the pixel region is a slope surface.
  • step S20 further includes preparing a support layer above the pixel definition layer, and the preparation materials of the planarization layer, the pixel definition layer, and the support layer are all made of photoresist materials;
  • planarization layer, the pixel definition layer and the support layer are prepared in the same photomask process.
  • a display panel including:
  • An array substrate including source and drain metals
  • a planarization layer disposed on the array substrate
  • a pixel definition layer which is disposed on the planarization layer and includes a plurality of pixel definition bodies distributed at intervals, and an interval region between two adjacent pixel definition bodies forms a pixel area;
  • An anode layer is disposed on the pixel region, and an edge of the anode layer is attached to the pixel definition body.
  • the anode layer includes a raised portion, and the raised portion is located at a bonding position between the anode layer and the pixel definition layer to prevent the inside of the anode layer from being eroded.
  • a slope surface of one side of the pixel definition body is close to the pixel region, and an edge of the anode layer is abutted with a slope surface of the pixel definition body.
  • the anode layer includes a first transparent electrode layer, a silver metal layer, and a second transparent electrode layer.
  • a via hole is provided in the planarization layer, and the anode layer is electrically connected to the source and drain metal through the via hole.
  • the preparation materials of the planarization layer, the pixel definition layer, and the support layer all include a photoresist material.
  • An advantage of the present application is that a display panel and a manufacturing method thereof are provided. After the preparation of the planarization layer and the pixel definition layer is completed, the manufacturing sequence of the anode layer is prepared so that the edge of the anode layer and the pixel definition layer are bonded. In order to prevent the anode layer from being eroded, the pixel aperture ratio of the display panel is improved.
  • FIG. 1 is a schematic structural diagram of a display panel in the prior art
  • Figure 2 is a schematic flowchart of a method for manufacturing a display panel in an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • 4a-4c are schematic structural flow diagrams of a method for manufacturing a display panel according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a photomask process in a method for manufacturing a display panel according to an embodiment of the invention
  • FIG. 6 is a schematic structural diagram of a display panel in another embodiment of the present application.
  • the present application addresses a problem that a pixel definition layer covers an edge portion of an anode layer in an existing process, and protects the anode layer from erosion while reducing the pixel aperture ratio of a display panel.
  • a display panel and a manufacturing method thereof are proposed. Examples can improve this defect.
  • FIG. 2 is a schematic flowchart of a method for manufacturing a display panel according to an embodiment of the present application.
  • FIG. 4a-4c is a schematic flowchart of a method for manufacturing a display panel according to an embodiment of the present application.
  • the present application provides a method for manufacturing a display panel 20, including the following steps:
  • step S10 an array substrate 21 is provided.
  • the array substrate 21 is provided with a source and drain metal 21a electrically connected to the anode layer 23.
  • the array substrate 21 generally includes a substrate and an array of distributed thin film transistors.
  • the source-drain metal 21a mentioned in this application belongs to a part of the thin film transistor.
  • the thin film transistor in the array substrate 21 may be a single-gate thin film transistor or a double-gate transistor. It can be determined by actual needs.
  • a planarization layer 22 and a pixel definition layer 24 are sequentially prepared above the array substrate 21, and the pixel definition layer 24 includes a plurality of pixel definition bodies 24a distributed at intervals.
  • the pixel definition body 24 a is used to define a pixel area 27 where the anode layer 23 is located, and a space area between two adjacent pixel definition bodies 24 a forms a pixel area 27.
  • the pixel region 27 is an enclosed region of the pixel defining body 24a.
  • the manufacturing method of first preparing the anode layer 23 and then the pixel definition layer 22 makes the opening of the pixel definition layer 24 difficult to control.
  • the pixel electrode layer 24 will cover the edges of the anode layer 23 and make the anode layer 23 A part of the invalid light-emitting area is generated above; the opening of the display panel is related to the opening of the pixel definition layer 24, which causes the aperture ratio of the display panel 20 to decrease.
  • the pixel definition layer 24 is first prepared, and then the anode layer 23 is prepared so that the opening size of the pixel definition layer 24 is the same as the area of the anode layer 23, and the aperture ratio of the display panel is not lost because the pixel definition layer 24 covers the anode layer 23. .
  • step S20 further includes: preparing a support layer 25 above the pixel definition layer 24, and the planarization layer 22, the pixel definition layer 24, and the support layer 25 are all made of photoresist material. .
  • the photoresist material is polyimide.
  • planarization layer 22, the pixel definition layer 24, and the support layer 25 are prepared in the same photomask process.
  • FIG. 5 is a schematic structural diagram of a photomask process in the present application.
  • the photomask 30 used in the photomask process is a multi-tone photomask mask.
  • Mask Multi-tone photomask reticle can simultaneously take into account the transmittance of multiple types of light, and use different light transmission intensities in different areas of photomask 3 to determine the degree of reaction of the photoresist layer in the area below photomask 3 to achieve one time. Performance to achieve the purpose of a variety of pattern etching.
  • a support layer 25 In areas where the light transmittance is 0% to 30%, we can prepare a support layer 25. In areas where the light transmittance is equal to 30% to 60%, we can prepare a pixel definition layer 24. In areas where the transmittance is equal to 100%, we can make vias in the planarization layer 22.
  • the photoresist layer is a film layer composed of the support layer 25, the pixel definition layer 24, and the planarization layer 22 in the present application.
  • the material of the planarization layer 22, the pixel definition layer 24, and the support layer 25 is set as a photoresist material.
  • the pixel definition layer 24 and the support layer 25 are prepared first, and then the arrangement of the anode layer 23 is prepared, so that the planarization layer 22, the pixel definition layer 24, and the support layer 25 can be prepared in a photomask process. Furthermore, a photomask process is saved, and the production efficiency of the display panel is greatly improved.
  • planarization layer 22, the pixel definition layer 24, and the support layer 25 are all made of the same photoresist material.
  • a via hole is provided in the planarization layer 22, and the anode layer 22 is electrically connected to the source and drain metal 21 through a via hole.
  • step S30 the anode layer 23 is prepared on the pixel region, and an edge of the anode layer 23 is adhered to the pixel definition layer 24.
  • the pixel area 27 refers to a surrounding area of the adjacent pixel definition body 24a. Therefore, the opening area of the pixel definition layer 24 determines the opening ratio of the display panel to a certain extent.
  • the anode layer 23 includes a first transparent electrode layer, a silver metal layer, and a second transparent electrode layer. Since the silver metal layer is easily eroded in the air, there are generally two methods for protecting the silver metal layer from being eroded.
  • the first type setting the pixel definition layer 24 to cover the edge of the anode layer 23; the second type, setting the anode layer 23 and the pixel definition layer 24 to be attached.
  • This application uses a second protection method to avoid invalid light-emitting areas above the anode layer 23.
  • a side of the pixel defining body near the pixel region is a slope surface.
  • the step S30 specifically includes:
  • An anode metal layer is formed in the pixel region, and the anode metal layer is exposed, etched, and developed using a photomask process to form an anode layer.
  • the contact surface between the pixel definition body and the anode layer 23 is a slope surface
  • the photoresistance at the edge of the anode layer 23 will be affected by the slope of the pixel definition body.
  • the photoresist at the slope cannot be fully exposed and developed, resulting in the residue of the photoresist.
  • the anode layer 23 has a raised portion 23a at the edge. The position of the raised portion 23 is exactly the anode layer 23 and the pixel definition body. The fit.
  • the raised portion can further strengthen the adhesion between the anode layer 23 and the pixel definition body, thereby preventing the anode layer 23 itself from being eroded.
  • the manufacturing order of the pixel definition layer 24 and then the anode layer 23 is prepared. Without additional processes and equipment, the aperture ratio of the display panel 20 is improved, and the anode layer 23 is further protected from erosion. .
  • the manufacturing method of the display panel 20 also includes other existing processes for preparing the display panel except the anode layer. Since other processes do not involve the main inventive point of the present application, they will not be repeated here.
  • a display panel 20 including:
  • the array substrate 21 includes a source / drain metal 21 a electrically connected to the anode layer 23.
  • the planarization layer 22 is disposed on the array substrate 21.
  • the pixel definition layer 24 is disposed on the flattening layer 22 and includes a plurality of pixel definition bodies 24 a spaced apart from each other. A space region between two adjacent pixel definition bodies forms a pixel area.
  • the anode layer 23 is disposed on the pixel region, and an edge of the anode layer 23 is attached to the pixel definition body.
  • the anode layer 23 includes a raised portion 23a, and the raised portion 23a is located at a position where the anode layer 23 and the pixel definition layer 24 are attached to prevent the anode layer 23 from being internally damaged. erosion.
  • the pixel definition body and a side close to the pixel area are sloped surfaces, and an edge of the anode layer 23 is in contact with the slope surface of the pixel definition body.
  • the application of the anode layer 23 and the pixel definition layer 24 in this application can prevent the anode layer from being eroded under the premise of increasing the opening of the pixel definition layer, which effectively improves the quality of the display panel.
  • the advantage of the present application is that by preparing the anode layer after the planarization layer and the pixel definition layer are prepared, the edge of the anode layer is bonded to the pixel definition layer, so as to improve the display panel while avoiding erosion of the anode layer. Pixel aperture ratio.

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Abstract

一种显示面板（20）及其制作方法。该显示面板（20）包括阵列基板（21），阵列基板（21）包括：源漏极金属（21a）；平坦化层（22），设置于阵列基板（21）上；像素定义层（24），设置于平坦化层（22）上，包括间隔分布的多个像素定义体（24a），相邻两个像素定义体（24a）之间的间隔区域形成像素区域（27）；阳极层（23），设置于像素区域（27）上，阳极层（23）的边缘与像素定义体（24a）贴合。显示面板（20）的像素开口率在避免阳极层（23）被侵蚀的同时提高了。

Description

显示面板及其制作方法 技术领域
本申请涉及显示领域，具体涉及一种显示面板及其制作方法。
 背景技术
有机发光二极管(Organic Light-Emitting Diode, 简称OLED)显示技术与传统的LCD显示技术不同，其无需背光灯，且具有自发光的特性。OLED采用非常薄的有机材料涂层和玻璃基板，当电流通过时，这些有机材料就会发光。而且显示面板的显示屏屏轻薄易带、视野广阔和节能省电的优点。因此OLED技术逐渐受到市场的青睐。
请参阅图1，在显示面板中，阵列基板11的上方分别设置有平坦化层12、阳极层13、像素定义层14和支撑层。其中，阳极层12被所述像素定义层14围挡以形成开口区。像素定义层的开口大小就决定了阳极层12上OLED有机发光层出光口的大小。在现有显示面板的制程中，像素定义层14的开口区的大小无法与阳极层13的大小完全匹配。像素定义层14的开口过大会导致阳极层13内的银金属被侵蚀从而损坏阳极层13，像素定义层14的开口过小会导致阳极层13的边缘被像素定义层14包裹，从而导致OLED有机发光层存在无效发光区，造成OLED有机发光层中有效发光区的面积减少，使得显示面板的开口率降低。因此，目前亟需一种显示面板及其制作方法以解决上述问题。
 技术问题
现有工艺中像素定义层覆盖阳极层的边缘部分，在保护阳极层不被侵蚀的同时导致显示面板的像素开口率降低的问题。
 技术解决方案
为实现上述目的，本发明提供的技术方案如下：
根据本申请的一个方面，提出了一种显示面板的制作方法，包括以下步骤：
步骤S10、提供一阵列基板，所述阵列基板上设置有源漏极金属；
步骤S20、在所述阵列基板上方依次制备平坦化层和像素定义层，所述像素定义层包括间隔分布的多个像素定义体，所述像素定义体之间的间隔区域形成像素区域；
步骤S30、在所述像素区域制备所述阳极层，所述阳极层包括第一透明电极层、银金属层和第二透明电极层，所述阳极层的边缘与所述像素定义层贴合；
其中，所述平坦化层中设置有过孔，所述阳极层通过所述过孔与所述源漏极金属电连接。
根据本申请一实施例，所述步骤S30具体包括：
在所述像素区域形成阳极金属层，采用光罩工艺对所述阳极金属层进行曝光、蚀刻、显影以形成阳极层。
根据本申请一实施例，所述阳极层包括翘起部，所述翘起部位于所述阳极层与所述像素定义层的贴合位置。
根据本申请一实施例，所述像素定义体靠近所述像素区域的一侧为斜坡面。
根据本申请一实施例，在步骤S20中还包括在像素定义层上方制备支撑层，所述平坦化层、所述像素定义层和所述支撑层的制备材料均采用光阻材料；
所述平坦化层、所述像素定义层和所述支撑层在同一道光罩工艺中制备。
根据本申请的另一个方面，提出了一种显示面板的制作方法，包括以下步骤：
步骤S10、提供一阵列基板，所述阵列基板上设置有源漏极金属；
步骤S20、在所述阵列基板上方依次制备平坦化层和像素定义层，所述像素定义层包括间隔分布的多个像素定义体，所述像素定义体之间的间隔区域形成像素区域；
步骤S30、在所述像素区域制备所述阳极层，所述阳极层的边缘与所述像素定义层贴合。
根据本申请一实施例，所述步骤S30具体包括：
在所述像素区域形成阳极金属层，采用光罩工艺对所述阳极金属层进行曝光、蚀刻、显影以形成阳极层。
根据本申请一实施例，所述阳极层包括翘起部，所述翘起部位于所述阳极层与所述像素定义层的贴合位置。
根据本申请一实施例，所述像素定义体靠近所述像素区域的一侧为斜坡面。
根据本申请一实施例，在步骤S20中还包括在像素定义层上方制备支撑层，所述平坦化层、所述像素定义层和所述支撑层的制备材料均采用光阻材料；
所述平坦化层、所述像素定义层和所述支撑层在同一道光罩工艺中制备。
根据本申请的又一个发明，提供了一种显示面板，包括：
阵列基板，包括源漏极金属；
平坦化层，设置于所述阵列基板的上；
像素定义层，设置于所述平坦化层的上，包括间隔分布的多个像素定义体，相邻两个所述像素定义体之间的间隔区域形成像素区域；
阳极层，设置于所述像素区域上，所述阳极层的边缘与所述像素定义体贴合。
根据本申请一实施例，所述阳极层包括翘起部，所述翘起部位于所述阳极层与所述像素定义层的贴合位置以防止所述阳极层内部被侵蚀。
根据本申请一实施例，所述像素定义体靠近所述像素区域的一侧斜坡面，所述阳极层的边缘与所述像素定义体的斜坡面贴合。
根据本申请一实施例，所述阳极层包括第一透明电极层、银金属层和第二透明电极层。
根据本申请一实施例，所述平坦化层中设置有过孔，所述阳极层通过所述过孔与所述源漏极金属电连接。
根据本申请一实施例，所述平坦化层、所述像素定义层和所述支撑层的制备材料均包括光阻材料。
 有益效果
本申请的优点是，提供了一种显示面板及其制作方法，通过在平坦化层和像素定义层制备完成之后，再制备阳极层的制作顺序，使得阳极层的边缘与像素定义层贴合，以在避免阳极层被侵蚀的同时提高显示面板的像素开口率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中显示面板的结构示意图；
图2为本申请实施例中显示面板的制作方法的流程示意图;
图3为本申请实施例中显示面板的结构示意图；
图4a-4c为本申请实施例中显示面板的制作方法的结构流程示意图；
图5为发明实施例中显示面板的制作方法中光罩工艺的结构示意图；
图6为本申请另一实施例中显示面板的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本申请针对现有工艺中像素定义层覆盖阳极层的边缘部分，在保护阳极层不会侵蚀的同时导致显示面板的像素开口率降低的问题，提出了一种显示面板及其制作方法，本实施例能够改善该缺陷。
下面结合附图和具体实施例对本申请做进一步的说明：
请参阅图2和图4a-4c，图2为本申请实施例中显示面板的制作方法的流程示意图; 图4a-4c为本申请实施例中显示面板的制作方法的结构流程示意图。
本申请提供了一种显示面板20的制作方法，包括以下步骤：
请参阅图4a，步骤S10、提供一阵列基板21，所述阵列基板21设置有与阳极层23电连接的源漏极金属21a。
在一种实施例中，阵列基板21通常包括衬底和阵列分布的薄膜晶体管。本申请中提到的源漏极金属21a属于薄膜晶体管中的一部分。
在一种实施例中，阵列基板21中的薄膜晶体管既可以是单栅薄膜晶体管，也有可能是双栅晶体管。具体可依靠实际的需求进行确定。
请参阅图4b，步骤S20、在所述阵列基板21上方依次制备平坦化层22和像素定义层24，所述像素定义层24包括间隔分布的多个像素定义体24a。
所述像素定义体24a用于定义所述阳极层23所在像素区域27，相邻两个所述像素定义体24a之间的间隔区域形成像素区域27。其中，所述像素区域27即所述像素定义体24a的围挡区域。
现有的工艺是采用先制备阳极层23，再制备像素定义层22的制作方式，使得像素定义层24的开口不好控制，像素电极层24同行会覆盖阳极层23的边缘，使得阳极层23的上方产生一部分无效发光区；显示面板的开口与像素定义层24的开口有关，导致显示面板20的开口率减小。
本申请通过先制备像素定义层24，再制备阳极层23的方式使得像素定义层24的开口大小与阳极层23的面积相同，不用因为像素定义层24覆盖阳极层23而损失显示面板的开口率。
在一种实施例中，步骤S20还包括：在像素定义层24上方制备支撑层25，所述平坦化层22、所述像素定义层24和所述支撑层25的制备材料均采用光阻材料。
在一种实施例中，所述光阻材料为聚酰亚胺。
所述平坦化层22、所述像素定义层24和所述支撑层25在同一道光罩工艺中制备。
请参阅图5，图5为本申请中光罩工艺的结构示意图。
在一种实施例中，所述光罩工艺采用的光罩30为多种色调光罩掩模版（Multi-tone Mask）。多种色调光罩掩模版可以同时兼顾多种光的透过率，利用光罩3不同区域的光的透过强度不同，进而决定光罩3下方区域的光阻层的反应程度，以达到一次性实现多种图案蚀刻的目的。
在光的透过率为0%至30%的区域，我们可以制备出支撑层25，在光的透过率分别等于30%至60%的区域，我们可以制备出像素定义层24，在光的透过率等于100%的区域，我们可以制作平坦化层22中的过孔。
在一种实施例中，所述光阻层为本申请中的支撑层25、像素定义层24和平坦化层22共同组成的膜层。
本申请通过将平坦化层22、像素定义层24和支撑层25的材料设置为光阻材料。先制备像素定义层24、支撑层25，再制备阳极层23的设置，使得平坦化层22、像素定义层24和支撑层25可以在一道光罩工艺中制备。进而节省了一道光罩工艺制程，大幅度的提高了显示面板的生产效率。
在一种实施例中，所述平坦化层22、像素定义层24和支撑层25均采用同一种光阻材料制备。
在一种实施例中，所述平坦化层22中设置有过孔，所述阳极层22通过通孔与所述源漏极金属21电连接。
请参阅图4c，步骤S30、在所述像素区域上制备所述阳极层23，所述阳极层23的边缘与所述像素定义层24贴合。
在一种实施例中，像素区域27指的是相邻像素定义体24a的围挡区域。因此，像素定义层24的开口面积在一定程度上决定了显示面板的开口率。
在一种实施例中，所述阳极层23包括第一透明电极层、银金属层和第二透明电极层。由于银金属层在空气中容易受到侵蚀，一般有两种方法用以保护银金属层不被侵蚀。
第一种：设置像素定义层24覆盖所述阳极层23的边缘；第二种，设置阳极层23与像素定义层24贴合。本申请采用第二种保护方式以避免阳极层23的上方出现无效发光区。
在一种实施例中，所述像素定义体靠近所述像素区域的一侧为斜坡面。
在一种实施例中，所述步骤S30具体包括：
在所述像素区域形成阳极金属层，采用光罩工艺对所述阳极金属层进行曝光、蚀刻、显影以形成阳极层。
需要解释的是，当像素定义体与所述阳极层23的接触面为斜坡面时，在对阳极层23进行图案化时，阳极层23边缘处的光阻由于像素定义体斜坡的影响，会使得斜坡处的光阻不能被完全曝光显影，造成光阻的残留，最终导致阳极层23在边缘的地方有翘起部23a，翘起部23所在的位置正好为阳极层23与像素定义体的贴合处。
所述翘起部可以进一步的巩固所述阳极层23与像素定义体的贴合作用，从而避免阳极层23本身被侵蚀。本申请通过先制备像素定义层24，再制备阳极层23的制作顺序，在不需额外工艺和设备的情况下，即提升了显示面板20的开口率，也进一步保护了阳极层23不被侵蚀。
可以理解的是，在显示面板20的制作方法中，还包括制备显示面板除阳极层以外其他现有工艺，由于其他工艺不涉及本申请的主要发明点，因此这里就不加以赘述。
如图6所示，根据本申请的另一个方面，提供了一种显示面板20，包括：
阵列基板21，包括与阳极层23电连接的源漏极金属21a。
平坦化层22，设置于所述阵列基板21的上。
像素定义层24，设置于所述平坦化层22的上，包括间隔分布的多个像素定义体24a，相邻两个所述像素定义体之间的间隔区域形成像素区域。
阳极层23，设置于所述像素区域上，所述阳极层23的边缘与所述像素定义体贴合。
在一种实施例中，所述阳极层23包括翘起部23a，所述翘起部23a位于所述阳极层23与所述像素定义层24的贴合位置以防止所述阳极层23内部被侵蚀。
在一种实施例中，所述像素定义体与靠近所述像素区域的一侧为斜坡面，所述阳极层23的边缘与所述像素定义体的斜坡面贴合。
本申请设置阳极层23与像素定义层24贴合，能够在增大像素定义层的开口的前提下避免阳极层被侵蚀，有效的提高了显示面板的品质。
本申请的优点是，通过在平坦化层和像素定义层制备完成之后，再制备阳极层的方式，使得阳极层的边缘与像素定义层贴合，以在避免阳极层被侵蚀的同时提高显示面板的像素开口率。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种显示面板的制作方法，其包括以下步骤：
    步骤S10、提供一阵列基板，所述阵列基板上设置有源漏极金属；
    步骤S20、在所述阵列基板上方依次制备平坦化层和像素定义层，所述像素定义层包括间隔分布的多个像素定义体，相邻两个所述像素定义体之间的间隔区域形成像素区域；
    步骤S30、在所述像素区域制备所述阳极层，所述阳极层包括第一透明电极层、银金属层和第二透明电极层，所述阳极层的边缘与所述像素定义层贴合；
    其中，所述平坦化层中设置有过孔，所述阳极层通过所述过孔与所述源漏极金属电连接。
  2. 根据权利要求1所述的显示面板的制作方法，其中，所述步骤S30具体包括：
    在所述像素区域形成阳极金属层，采用光罩工艺对所述阳极金属层进行曝光、蚀刻、显影以形成阳极层。
  3. 根据权利要求2所述的显示面板的制作方法，其中，所述阳极层包括翘起部，所述翘起部位于所述阳极层与所述像素定义层的贴合位置。
  4. 根据权利要求3所述的显示面板的制作方法，其中，所述像素定义体靠近所述像素区域的一侧为斜坡面。
  5. 根据权利要求1所述的显示面板的制作方法，其中，在步骤S20中还包括在像素定义层上方制备支撑层，所述平坦化层、所述像素定义层和所述支撑层的制备材料均采用光阻材料，且所述平坦化层、所述像素定义层和所述支撑层在同一道光罩工艺中制备。
  6. 一种显示面板的制作方法，其包括以下步骤：
    步骤S10、提供一阵列基板，所述阵列基板上设置有源漏极金属；
    步骤S20、在所述阵列基板上方依次制备平坦化层和像素定义层，所述像素定义层包括间隔分布的多个像素定义体，相邻两个所述像素定义体之间的间隔区域形成像素区域；
    步骤S30、在所述像素区域制备所述阳极层，所述阳极层的边缘与所述像素定义层贴合。
  7. 根据权利要求6所述的显示面板的制作方法，其中，所述步骤S30具体包括：
    在所述像素区域形成阳极金属层，采用光罩工艺对所述阳极金属层进行曝光、蚀刻、显影以形成阳极层。
  8. 根据权利要求7所述的显示面板的制作方法，其中，所述阳极层包括翘起部，所述翘起部位于所述阳极层与所述像素定义层的贴合位置。
  9. 根据权利要求8所述的显示面板的制作方法，其中，所述像素定义体靠近所述像素区域的一侧为斜坡面。
  10. 根据权利要求6所述的显示面板的制作方法，其中，在步骤S20中还包括在像素定义层上方制备支撑层，所述平坦化层、所述像素定义层和所述支撑层的制备材料均采用光阻材料；
    所述平坦化层、所述像素定义层和所述支撑层在同一道光罩工艺中制备。
  11. 一种显示面板，其包括：
    阵列基板，包括源漏极金属；
    平坦化层，设置于所述阵列基板上；
    像素定义层，设置于所述平坦化层上，包括间隔分布的多个像素定义体，相邻两个所述像素定义体之间的间隔区域形成像素区域；
    阳极层，设置于所述像素区域上，所述阳极层的边缘与所述像素定义体贴合。
  12. 根据权利要求11所述的显示面板，其中，所述阳极层包括翘起部，所述翘起部位于所述阳极层与所述像素定义层的贴合位置以防止所述阳极层内部被侵蚀。
  13. 根据权利要求12所述的显示面板，其中，所述像素定义体靠近所述像素区域的一侧为斜坡面，所述阳极层的边缘与所述像素定义体的斜坡面贴合。
  14. 根据权利要求11所述的显示面板，其中，所述阳极层包括第一透明电极层、银金属层和第二透明电极层。
  15. 根据权利要求11所述的显示面板，其中，所述平坦化层中设置有过孔，所述阳极层通过所述过孔与所述源漏极金属电连接。
  16. 根据权利要求11所述的显示面板，其中，所述平坦化层、所述像素定义层和所述支撑层的制备材料均包括光阻材料。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102608772B1 (ko) * 2018-07-19 2023-12-04 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법
CN111048685A (zh) * 2019-11-08 2020-04-21 深圳市华星光电半导体显示技术有限公司 显示面板及其制备方法
CN111312766B (zh) * 2020-02-21 2022-12-06 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法
CN112750889A (zh) * 2021-03-04 2021-05-04 安徽熙泰智能科技有限公司 一种自对准像素定义层结构及其加工方法
CN113097259B (zh) * 2021-03-22 2022-06-10 深圳市华星光电半导体显示技术有限公司 一种显示面板、显示面板制程方法及显示装置
CN114497430A (zh) * 2022-01-20 2022-05-13 昆山梦显电子科技有限公司 一种硅基oled制备阳极结构的方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060125381A1 (en) * 2004-12-14 2006-06-15 Sang-Hun Oh Organic light emitting display device and method of fabricating the same
CN104037357A (zh) * 2014-06-05 2014-09-10 京东方科技集团股份有限公司 一种有机发光显示装置及其制造方法
CN104078489A (zh) * 2014-06-11 2014-10-01 京东方科技集团股份有限公司 一种有机发光二极管显示面板和显示装置
CN106449657A (zh) * 2016-10-27 2017-02-22 上海天马微电子有限公司 Oled显示面板、显示装置、阵列基板及其制作方法
CN106486512A (zh) * 2015-08-31 2017-03-08 上海和辉光电有限公司 一种有机发光二极管器件及有机发光显示器

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102620576B1 (ko) 2016-06-30 2024-01-02 엘지디스플레이 주식회사 유기발광 표시장치 및 그의 제조방법
CN106653768B (zh) 2016-12-13 2020-01-31 武汉华星光电技术有限公司 Tft背板及其制作方法
CN106601778B (zh) * 2016-12-29 2019-12-24 深圳市华星光电技术有限公司 Oled背板及其制作方法
KR20180077439A (ko) * 2016-12-29 2018-07-09 엘지디스플레이 주식회사 전계 발광 표시 장치 및 그 제조 방법
KR20180079097A (ko) 2016-12-30 2018-07-10 엘지디스플레이 주식회사 유기 발광 표시 장치
CN107424957B (zh) * 2017-06-16 2020-01-31 武汉华星光电半导体显示技术有限公司 柔性tft基板的制作方法
US10249652B2 (en) 2017-06-16 2019-04-02 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Manufacturing method of flexible TFT substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060125381A1 (en) * 2004-12-14 2006-06-15 Sang-Hun Oh Organic light emitting display device and method of fabricating the same
CN104037357A (zh) * 2014-06-05 2014-09-10 京东方科技集团股份有限公司 一种有机发光显示装置及其制造方法
CN104078489A (zh) * 2014-06-11 2014-10-01 京东方科技集团股份有限公司 一种有机发光二极管显示面板和显示装置
CN106486512A (zh) * 2015-08-31 2017-03-08 上海和辉光电有限公司 一种有机发光二极管器件及有机发光显示器
CN106449657A (zh) * 2016-10-27 2017-02-22 上海天马微电子有限公司 Oled显示面板、显示装置、阵列基板及其制作方法

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