WO2020012986A1 - 基板処理システム及び基板処理方法 - Google Patents

基板処理システム及び基板処理方法 Download PDF

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Publication number
WO2020012986A1
WO2020012986A1 PCT/JP2019/025817 JP2019025817W WO2020012986A1 WO 2020012986 A1 WO2020012986 A1 WO 2020012986A1 JP 2019025817 W JP2019025817 W JP 2019025817W WO 2020012986 A1 WO2020012986 A1 WO 2020012986A1
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Prior art keywords
peripheral portion
surface film
outer peripheral
wafer
substrate processing
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PCT/JP2019/025817
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English (en)
French (fr)
Japanese (ja)
Inventor
隼斗 田之上
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東京エレクトロン株式会社
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Priority to JP2020530108A priority Critical patent/JP7058737B2/ja
Publication of WO2020012986A1 publication Critical patent/WO2020012986A1/ja

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

Definitions

  • the present disclosure relates to a substrate processing system and a substrate processing method.
  • Patent Document 1 discloses a device for bonding two wafers.
  • the bonding apparatus first, the center portion of the upper wafer of the two wafers that are vertically opposed to each other is pressed by a push pin to bring the center portion into contact with the lower wafer. Thereafter, the spacer supporting the upper wafer is retracted, the entire surface of the upper wafer is brought into contact with the entire surface of the lower wafer, and the wafers are joined.
  • Patent Document 2 discloses an end surface grinding device for grinding a peripheral end portion of a semiconductor wafer.
  • a disk-shaped grinding tool provided with abrasive grains on the outer peripheral portion is rotated, and at least the outer peripheral surface of the grinding tool is brought into linear contact with the semiconductor wafer so that the peripheral edge of the semiconductor wafer is substantially L-shaped.
  • the semiconductor wafer is manufactured by bonding two silicon wafers together.
  • the technology according to the present disclosure suppresses voids generated at the peripheral edge of the substrate when the substrates are joined to each other.
  • One embodiment of the present disclosure is a substrate processing system for processing a substrate, wherein the substrate processing system is formed on a surface of a first substrate before being bonded to a second surface film formed on a surface of the second substrate. There is a surface modification device for modifying the outer peripheral portion of the first surface film.
  • FIG. 2 is a plan view schematically showing the outline of the configuration of the wafer processing system according to the first embodiment. It is a side view which shows the outline of a structure of a surface modification apparatus.
  • FIG. 4 is a flowchart showing main steps of wafer processing according to the first embodiment.
  • FIG. 3 is an explanatory diagram of main steps of wafer processing according to the first embodiment. It is explanatory drawing which shows a mode that the modified layer was formed in the to-be-processed wafer. It is explanatory drawing which shows a mode that a peripheral edge modification layer is formed in a to-be-processed wafer. It is explanatory drawing which shows a mode that a division
  • FIG. 11 is a flowchart showing main steps of wafer processing according to the second embodiment. It is an explanatory view of a main process of wafer processing according to a second embodiment. It is a side view which shows the outline of a structure of the surface modification apparatus concerning another embodiment.
  • FIG. 19 is an explanatory diagram showing how the outer peripheral portion of the oxide film is removed and the wafers are joined together in the surface reforming device shown in FIG. 18.
  • FIG. 24 is an explanatory diagram showing how the outer peripheral portion of the oxide film is removed in the surface reforming apparatus shown in FIG. 23 and the wafers are joined together.
  • FIG. 24 is a plan view schematically showing how an oxide film is removed in the surface modification device shown in FIG. 23.
  • FIG. 24 is a side view schematically showing how an oxide film is removed in the surface modification device shown in FIG. 23.
  • FIG. 24 is an explanatory diagram schematically showing how an outer peripheral portion of an oxide film is removed by another method in the surface modifying apparatus shown in FIG. 23. It is a side view which shows the outline of a structure of the surface reforming apparatus with which the wafer processing system concerning 3rd Embodiment is provided.
  • FIG. 14 is a flowchart showing main steps of wafer processing according to a third embodiment. It is an explanatory view of a main process of wafer processing according to a third embodiment. It is explanatory drawing which shows typically the mode of thinning of the to-be-processed wafer by another method. It is explanatory drawing which shows typically the mode of the edge trim of the to-be-processed wafer by another method.
  • wafers two semiconductor wafers (hereinafter, referred to as wafers) are joined. Specifically, for example, the wafers are joined together by van der Waals force and hydrogen bonding (intermolecular force).
  • the bonding of the wafers is performed by, for example, a bonding apparatus disclosed in Patent Document 1.
  • a back surface of a wafer having devices such as a plurality of electronic circuits formed on a front surface of a bonded superposed wafer is ground to thin the wafer. .
  • the peripheral portion of the wafer is chamfered.
  • the peripheral portion of the wafer becomes sharp and sharp (a so-called knife edge shape).
  • chipping occurs at the peripheral portion of the wafer, and the wafer may be damaged. Therefore, so-called edge trimming, in which the peripheral portion of the wafer is cut in advance before the grinding process, is performed. This edge trimming is performed by, for example, an end face grinding device disclosed in Patent Document 2.
  • edge voids voids generated at the peripheral edge of the bonded superposed wafer, and it is required to suppress the edge voids.
  • edge voids are generated in the overlapped wafer as described above.
  • the processing target wafer W and the support wafer S are joined.
  • a device layer D and an oxide film Fw are formed on the surface Wa of the processing target wafer W, and an oxide film Fs is formed on the surface Sa of the support wafer S.
  • the surface Wa of the peripheral portion We of the processing target wafer W is removed (edge trim).
  • the wafer W to be processed and the support wafer S that have been edge-trimmed are joined.
  • the edge void V described above is formed between the oxide films Fw and Fs in the bonded overlapped wafer T.
  • the back surface Wb of the processing target wafer W is ground on the overlapped wafer T.
  • an edge void V occurs in the overlapped wafer T
  • the processing of the processing target wafer W may be separated (peeled) by the edge void V.
  • cracks and chipping may occur in the wafer W to be processed based on the peeling.
  • metal vias and pads are formed on each of the wafers W and S, and these vias and pads may be connected by diffusion bonding. In such a case, if an edge void occurs at a location of a via or a pad, diffusion bonding does not occur and a connection failure may occur.
  • the effective area (usable area) of the processing target wafer W also becomes smaller.
  • the distance L1 from the end of the processing target wafer W to the inner end of the edge void V before processing was about 7 mm. Therefore, when the diameter of the processing target wafer W before the processing is 300 mm, the effective area is an area of ⁇ 286 mm.
  • the technology according to the present disclosure suppresses edge voids when bonding wafers.
  • the present inventors have elucidated the generation mechanism of edge voids, and based on the knowledge, have arrived at a system and method for suppressing edge voids.
  • the processing target wafer W as the first substrate and the supporting wafer S as the second substrate are joined.
  • the surface to be joined is referred to as a front surface Wa
  • the surface opposite to the front surface Wa is referred to as a back surface Wb.
  • the surface to be joined is referred to as a front surface Sa
  • the surface opposite to the front surface Sa is referred to as a back surface Sb.
  • the processing target wafer W is a semiconductor wafer such as a silicon wafer, for example, and a device layer D including a plurality of devices is formed on a front surface Wa. Further, an oxide film Fw as a first surface film, for example, an SiO 2 film (TEOS film) is further formed on the device layer D.
  • TEOS film SiO 2 film
  • the support wafer S is a wafer that supports the processing target wafer W.
  • an oxide film Fs as a second surface film for example, an SiO 2 film (TEOS film) is formed.
  • the support wafer S functions as a protective material for protecting devices on the surface Wa of the processing target wafer W.
  • a device layer (not shown) is formed on the surface Sa, similarly to the wafer W to be processed.
  • the device layer D and the oxide films Fw and Fs may be omitted in order to avoid complexity.
  • the mechanism of generation of edge voids will be described.
  • the respective surfaces of the oxide films Fw and Fs are activated by plasma processing in a reduced-pressure atmosphere. Thereafter, the activated surface is hydrophilized, and an OH group (hydroxy group) is provided to the dangling bond formed on the surface. Then, at the time of bonding, the oxide films Fw and Fs are in contact with each other and the OH groups are hydrogen-bonded, so that the oxide films Fw and Fs are bonded to each other.
  • the bonded oxide films Fw and Fs are further subjected to an annealing treatment to remove water, thereby securing the bonding strength.
  • the processing target wafer W is suction-held by the upper chuck 300
  • the support wafer S is suction-held by the lower chuck 301.
  • the upper chuck 300 can suck the wafer W to be processed independently from the suction ports 300a and 300b
  • the lower chuck 301 can suck the support wafer S independently from the suction ports 301a and 301b.
  • FIG. 3B the suction from the suction port 300a at the center is stopped, and the pressing member 302 provided on the upper chuck 300 is lowered to press the center of the wafer W to be processed. You.
  • the central portion of the processing target wafer W and the central portion of the supporting wafer S abut, and bonding by hydrogen bonding starts, so that a so-called bonding wave B is generated.
  • the bonding wave B is diffused from the center to the periphery.
  • the suction from the suction port 300b in the peripheral portion is stopped as shown in FIG. 3D, and the peripheral portion of the wafer W to be processed falls on the support wafer S.
  • the processing target wafer W and the support wafer S are joined as shown in FIG.
  • the space between the wafers W and S is compressed to a high pressure due to the air.
  • the atmosphere compressed at the end Be of the bonding wave B to a high pressure (for example, three times the atmospheric pressure) is opened to the atmosphere, and rapidly.
  • the pressure will be reduced to atmospheric pressure.
  • the Joule-Thomson effect occurs due to the rapid pressure reduction, the temperature decreases (for example, decreases by 1.5 ° C.), and dew condensation occurs.
  • edge voids are generated by a sudden change in pressure between the wafers W and S.
  • the present inventors have come to think of suppressing the abrupt pressure change to suppress the edge void.
  • a wafer processing system as a substrate processing system and a wafer processing method as a substrate processing method according to the present embodiment will be described with reference to the drawings.
  • elements having substantially the same function and configuration are denoted by the same reference numerals, and redundant description is omitted.
  • FIG. 6 is a plan view schematically showing the outline of the configuration of the wafer processing system 1.
  • edge trimming is performed after bonding.
  • the wafer processing system 1 has a configuration in which the loading / unloading station 2 and the processing station 3 are integrally connected.
  • cassettes Cw, Cs, and Ct capable of accommodating a plurality of wafers W to be processed, a plurality of support wafers S, and a plurality of overlapped wafers T with the outside, respectively, are carried into and out of the carry-in / out station 2.
  • the processing station 3 includes various processing apparatuses that perform predetermined processing on the processing target wafer W, the support wafer S, and the overlapped wafer T.
  • the cassette loading table 10 is provided at the loading / unloading station 2.
  • a plurality of, for example, four cassettes Cw, Cs, Ct can be mounted on the cassette mounting table 10 in a line in the X-axis direction.
  • the number of cassettes Cw, Cs, Ct to be mounted on the cassette mounting table 10 is not limited to the present embodiment, and can be arbitrarily determined.
  • the wafer transfer area 20 is provided in the loading / unloading station 2 adjacent to the cassette mounting table 10.
  • the wafer transfer area 20 is provided with a wafer transfer device 22 movable on a transfer path 21 extending in the X-axis direction.
  • the wafer transfer device 22 has, for example, two transfer arms 23, 23 for holding and transferring the processing target wafer W, the support wafer S, and the overlapped wafer T.
  • Each transfer arm 23 is configured to be movable in a horizontal direction, a vertical direction, around a horizontal axis, and around a vertical axis. Note that the configuration of the transfer arm 23 is not limited to the present embodiment, and may have any configuration.
  • the processing station 3 is provided with a wafer transfer area 30.
  • the wafer transfer area 30 is provided with a wafer transfer device 32 movable on a transfer path 31 extending in the X-axis direction.
  • the wafer transfer device 32 sends a processing target wafer W, a support wafer S, and a polymerization device to a transition device 34, a bonding device 40, an internal reforming device 41, a surface reforming device 42, a hydrophobizing device 43, and a processing device 50 described later.
  • the wafer T is configured to be transportable.
  • the wafer transfer device 32 has, for example, two transfer arms 33, 33 for holding and transferring the processing target wafer W, the support wafer S, and the superposed wafer T.
  • Each transfer arm 33 is configured to be movable in a horizontal direction, a vertical direction, around a horizontal axis, and around a vertical axis. Note that the configuration of the transfer arm 33 is not limited to the present embodiment, and may have any configuration.
  • a transition device 34 for transferring the processing target wafer W, the support wafer S, and the overlapped wafer T is provided between the wafer transfer area 20 and the wafer transfer area 30.
  • a bonding device 40 and an internal reforming device 41 are arranged in this order in the X-axis direction from the loading / unloading station 2 side.
  • a surface reforming device 42 and a hydrophobizing device 43 are arranged in this order in the X-axis direction from the loading / unloading station 2 side.
  • the bonding device 40 bonds the oxide film Fw of the processing target wafer W and the oxide film Fs of the support wafer S.
  • the oxide film Fw and the oxide film Fs Prior to the bonding, the oxide film Fw and the oxide film Fs are respectively activated and hydrophilized. Specifically, when activating the oxide film Fw and the oxide film Fs, for example, under a reduced pressure atmosphere, an oxygen gas or a nitrogen gas as a processing gas is excited to be turned into plasma and ionized.
  • the oxide film Fw and the oxide film Fs are irradiated with the oxygen ions or the nitrogen ions, and the oxide film Fw and the oxide film Fs are plasma-treated and activated.
  • oxide film Fw and the oxide film Fs activated in this way, and an OH group is given to a dangling bond between the oxide film Fw and the oxide film Fs to make them hydrophilic. Then, as shown in FIG. 3, oxide film Fw and oxide film Fs are joined by hydrogen bonding. Further, an annealing process is performed on the bonded overlapped wafer T to remove water from the oxide film Fw and the oxide film Fs, thereby securing the bonding strength.
  • the internal reforming device 41 forms a peripheral reforming layer and a split reforming layer inside the wafer W to be processed.
  • a laser beam is emitted from a laser head (not shown) to the inside of the wafer to be processed W while the overlapped wafer T is rotated and held by a chuck (not shown).
  • the laser head receives high-frequency pulsed laser light oscillated from a laser light oscillator (not shown), and has a wavelength that is transparent to the wafer W to be processed, for example, infrared light.
  • the light is focused and irradiated on a predetermined position inside the processing wafer W. Thereby, the portion where the laser light is focused inside the wafer W to be processed is modified.
  • the peripheral edge modified layer is formed along the boundary between the peripheral edge portion We to be removed and the central portion of the processing target wafer W.
  • the split modified layer is formed to extend in the radial direction on the radially outside of the peripheral edge modified layer.
  • the laser head further includes a spatial light modulator (not shown).
  • the spatial light modulator modulates and outputs the laser light.
  • the spatial light modulator can control the focal position and phase of the laser light, and can adjust the shape and number (the number of branches) of the laser light applied to the processing target wafer W.
  • the surface reforming device 42 reforms the outer peripheral portion of the oxide film Fw of the processing target wafer W, and removes the outer peripheral portion in the present embodiment.
  • wet etching is performed on the outer peripheral portion of the oxide film Fw with an etching solution such as hydrofluoric acid.
  • the hydrophobizing device 43 immerses the polymerized wafer T in an organic solvent to bond, for example, CH 3 groups (methyl groups) to the surfaces of the unbonded oxide films Fw and Fs.
  • the interface between the oxide films Fw and Fs joined by the joining device 40 corresponds to the joining region where the oxide films Fw and Fs are joined and the oxide film Fw removed by the surface reforming device 42 as described later.
  • An unjoined region is formed.
  • the dangling bonds formed on the surfaces of the oxide films Fw and Fs in the unbonded regions are hydrophobized by, for example, bonding CH 3 groups.
  • the hydrophobicity of the surfaces of the oxide films Fw and Fs is not limited to the bonding of the CH 3 group, and for example, a group containing another carbon may be bonded to the surfaces of the oxide films Fw and Fs.
  • the superposed wafer T is immersed in the organic solvent, but the method of providing the CH 3 group is not limited to this, and the organic solvent may be supplied to the surfaces of the oxide films Fw and Fs.
  • the surfaces of the oxide films Fw and Fs may be exposed to an organic solvent atmosphere.
  • a processing apparatus 50 is disposed on the X-axis positive direction side of the wafer transfer area 30. In the processing apparatus 50, processing such as grinding and cleaning is performed on the wafer W to be processed.
  • the processing device 50 includes a rotary table 60, a transport unit 70, an alignment unit 80, a first cleaning unit 90, a second cleaning unit 100, a rough grinding unit 110, a medium grinding unit 120, and a finish grinding unit 130. I have.
  • the rotary table 60 is configured to be rotatable by a rotating mechanism (not shown).
  • a rotating mechanism not shown
  • four chucks 61 for holding the overlapped wafer T by suction are provided on the turntable 60.
  • the chucks 61 are evenly arranged on the same circumference as the rotary table 60, that is, are arranged at intervals of 90 degrees.
  • the four chucks 61 can be moved to the delivery position A0 and the processing positions A1 to A3 by rotating the rotary table 60.
  • the chuck 61 is held by a chuck base (not shown), and is configured to be rotatable by a rotation mechanism (not shown).
  • the delivery position A0 is a position on the X-axis negative direction side and the Y-axis negative direction side of the turntable 60, and the second cleaning unit 100 and the alignment unit are located on the X-axis negative direction side of the delivery position A0.
  • the 80 and the first cleaning unit 90 are arranged side by side.
  • the alignment unit 80 and the first cleaning unit 90 are stacked and arranged in this order from above.
  • the first processing position A1 is a position on the X-axis positive direction side and the Y-axis negative direction side of the turntable 60, and the coarse grinding unit 110 is disposed.
  • the second processing position A2 is a position on the X-axis positive direction side and the Y-axis positive direction side of the turntable 60, and the medium grinding unit 120 is disposed.
  • the third processing position A3 is a position on the X-axis negative direction side and the Y-axis positive direction side of the rotary table 60, and the finish grinding unit 130 is disposed.
  • the transfer unit 70 is an articulated robot having a plurality of, for example, three arms 71. Each of the three arms 71 is configured to be pivotable. A transfer pad 72 for sucking and holding the overlapped wafer T is attached to the tip arm 71. The base arm 71 is attached to a moving mechanism 73 that moves the arm 71 in the vertical direction. Then, the transfer unit 70 having such a configuration can transfer the overlapped wafer T to the delivery position A0, the alignment unit 80, the first cleaning unit 90, and the second cleaning unit 100.
  • the horizontal direction of the overlapped wafer T before the grinding process is adjusted.
  • the position of the notch portion is adjusted by detecting the position of the notch portion of the processing target wafer W by the detection unit (not shown) while rotating the overlapped wafer T held by the chuck (not shown). To adjust the horizontal direction of the overlapped wafer T.
  • the first cleaning unit 90 cleans the back surface Wb of the processed wafer W after the grinding process, and more specifically performs spin cleaning.
  • the second cleaning unit 100 cleans the back surface Sb of the support wafer S in a state where the wafer W after the grinding process is held on the transfer pad 72, and also cleans the transfer pad 72.
  • the rough grinding unit 110 roughly grinds the back surface of the wafer W to be processed.
  • the coarse grinding unit 110 has a coarse grinding unit 111 provided with a rotatable coarse grinding wheel (not shown) having an annular shape.
  • the rough grinding unit 111 is configured to be movable in the vertical and horizontal directions along the column 112. Then, with the back surface of the wafer W to be processed held by the chuck 61 being in contact with the rough grinding wheel, the chuck 61 and the rough grinding wheel are respectively rotated, and the rough grinding wheel is further lowered, whereby the wafer to be processed is lowered.
  • the back surface of W is roughly ground.
  • the medium grinding unit 120 performs medium grinding on the back surface of the wafer W to be processed.
  • the medium grinding unit 120 has a medium grinding unit 121 provided with an annular and rotatable medium grinding wheel (not shown).
  • the middle grinding portion 121 is configured to be movable in the vertical and horizontal directions along the column 122.
  • the grain size of the abrasive grains of the medium grinding wheel is smaller than the grain size of the abrasive grains of the coarse grinding wheel. Then, with the back surface of the wafer W to be processed held by the chuck 61 being in contact with the medium grinding wheel, the chuck 61 and the medium grinding wheel are respectively rotated, and the medium grinding wheel is further lowered, so that the back surface is centered. Grind.
  • the finish grinding unit 130 finish-grinds the back surface of the wafer W to be processed.
  • the finish grinding unit 130 has a finish grinding unit 131 having a ring-shaped rotatable finish grinding wheel (not shown). Further, the finish grinding section 131 is configured to be movable in the vertical and horizontal directions along the column 132.
  • the grain size of the abrasive grains of the finish grinding wheel is smaller than the grain size of the abrasive grains of the medium grinding wheel. Then, while the back surface of the wafer W to be processed held by the chuck 61 is in contact with the finishing grinding wheel, the chuck 61 and the finishing grinding wheel are respectively rotated, and the finishing grinding wheel is further lowered to finish the back surface. Grind.
  • the peripheral edge portion We of the processing target wafer W is removed, and the processing device 50 constitutes a peripheral edge removing device. are doing.
  • the control device 140 is a computer, for example, and has a program storage unit (not shown).
  • the program storage section stores a program for controlling wafer processing in the wafer processing system 1.
  • the program storage unit also stores programs for controlling operations of driving systems such as the above-described various types of processing apparatuses and transfer apparatuses, and for realizing wafer processing to be described later in the wafer processing system 1.
  • the program may be recorded on a computer-readable storage medium H, and may be installed from the storage medium H to the control device 140.
  • the surface reforming apparatus 42 has a chuck 150 for holding the wafer W to be processed with the oxide film Fw facing upward.
  • the chuck 150 is configured to be rotatable around a vertical axis by a rotation mechanism 151.
  • a nozzle 152 for applying the etching solution E to the outer peripheral portion of the oxide film Fw is provided above the chuck 150.
  • the nozzle 152 is in communication with an etchant supply source (not shown) that stores and supplies the etchant E.
  • the nozzle 152 is configured to be movable in the X-axis direction, the Y-axis direction, and the Z-axis direction by a moving mechanism (not shown).
  • the surface layer of the outer peripheral portion Fwe of the oxide film Fw is removed by the etching solution E as shown in FIG. Then, as shown in FIG. 8B, in the outer peripheral portion Fwe, the oxide films Fw and Fs are not joined during the joining process. That is, when the oxide films Fw and Fs are joined, an unjoined region Ae corresponding to the outer peripheral portion Fwe and a joined region Ac where the oxide films Fw and Fs are joined are formed at the interface between the oxide films Fw and Fs. You.
  • the thickness H of the outer peripheral portion Fwe to be removed shown in FIG. 8 is desirably within 400 nm from the surface. As the thickness H of the outer peripheral portion Fwe becomes larger than 400 nm, the space where the atmosphere at the end of the bonding wave is opened increases, and the degree of pressure reduction increases. Therefore, the smaller the thickness H of the outer peripheral portion Fwe, the better.
  • the present inventors conducted an experiment and confirmed that edge voids can be reliably suppressed if the thickness H of the outer peripheral portion Fwe is within 400 nm.
  • the width La of the unjoined area Ae shown in FIG. 8 is, for example, within 4 mm.
  • the width La does not contribute to the generation of edge voids. Even if the width La is as large as 4 mm, for example, the edge voids can be suppressed. However, in order to increase the effective area of the processing target wafer W as described later, it is preferable that the width La is as small as possible.
  • the cassette Cw storing a plurality of wafers W to be processed and the cassette Cs storing a plurality of supporting wafers S are mounted on the cassette mounting table 10 of the loading / unloading station 2.
  • the wafer W to be processed in the cassette Cw is taken out by the wafer transfer device 22 and transferred to the transition device 34.
  • the processing target wafer W of the transition device 34 is taken out by the wafer transfer device 32 and transferred to the surface reforming device 42.
  • the etchant E is supplied to the outer peripheral portion Fwe of the oxide film Fw of the processing target wafer W, and the surface layer of the outer peripheral portion Fwe is removed as shown in FIG. 10A (step in FIG. 9). P1).
  • the outer peripheral portion Fwe is removed such that the distance L2 from the end of the processing target wafer W becomes about 0.5 mm.
  • Step P1 the support wafer S in the cassette Cs is taken out by the wafer transfer device 22 and transferred to the bonding device 40 by the wafer transfer device 32 via the transition device 34.
  • the processing target wafer W is transferred to the bonding device 40 by the wafer transfer device 32.
  • the front and back surfaces of the processing target wafer W are reversed by the wafer transfer device 22 or the reversing device (not shown).
  • the oxide film Fw of the processing target wafer W and the oxide film Fs of the support wafer S are bonded to form the overlapped wafer T (Step P2 in FIG. 9).
  • the oxide films Fw and Fs are not bonded at the outer peripheral portion Fwe, and a bonded region Ac and an unbonded region Ae are formed at the interface between the oxide films Fw and Fs.
  • the unbonded region Ae reduces the space at the end of the bonding wave where the high-pressure atmosphere is released, and does not reduce the pressure to the atmospheric pressure. By suppressing such rapid pressure reduction, edge voids can be suppressed.
  • the overlapped wafer T is transferred to the hydrophobizing device 43 by the wafer transfer device 32.
  • the polymerized wafer T is immersed in an organic solvent to bond CH 3 groups to the surfaces of the oxide films Fw and Fs in the unbonded region Ae as shown in FIG. 10C (step in FIG. 9). P3).
  • the peripheral portion We of the processing target wafer W may not be appropriately removed in step P5 described below.
  • a problem may be caused by making the surfaces of the oxide films Fw and Fs hydrophobic.
  • the peripheral portion We can be appropriately removed. Note that the oxide films Fw and Fs may not adhere to each other after the bonding process depending on the humidity of the surrounding environment such as a dry environment. In such a case, Step P3 becomes unnecessary and can be omitted.
  • the overlapped wafer T is transferred to the internal reforming device 41 by the wafer transfer device 32.
  • the internal reforming device 41 irradiates the inside of the processing target wafer W with laser light from the laser head while rotating the processing target wafer W.
  • an annular peripheral modification layer M1 is formed inside the processing target wafer W.
  • the peripheral edge modified layer M1 is formed so as to coincide with the boundary between the joined region Ac and the unjoined region Ae, or radially inward of the boundary.
  • the peripheral edge modified layer M1 is formed at seven places in the thickness direction of the processing target wafer W, but the number of the peripheral edge modified layer M1 is arbitrary.
  • the peripheral edge modified layer M1 laser light emitted from a laser head is switched by the spatial light modulator, and the shape and number thereof are adjusted. Specifically, first, as shown in FIG. 12A, the surface Wa side in the thickness direction of the processing target wafer W is irradiated with the laser beam Lr1 to form the peripheral edge modified layers M1 (1) to M3 (3). To form The number of focal points of the laser beam Lr1 is one (single focus processing). Next, as shown in FIG. 12B, on the upper side of the peripheral edge modified layer M1 (3), that is, on the rear surface Wb side in the thickness direction of the processing target wafer W, the peripheral edge modified layer M1 (4) to ( 7) is formed. The number of focal points of the laser beam Lr2 is, for example, two, that is, the peripheral modified layers M1 (4) and (5) or the peripheral modified layers M1 (6) and (7) are formed at the same time. (Multi focus processing).
  • the number of the peripheral edge modified layers M1 formed by the laser beams Lr1 and Lr2 and the number of converging points of the laser beams Lr1 and Lr2 are arbitrary. However, in the peripheral modified layers M1 (1) to M (3) formed on the device layer D side of the processing target wafer W, cracks that propagate in the direction of the device layer D are controlled, that is, damage to the device layer D is prevented. In order to suppress giving, it is preferable that the peripheral modified layer M1 is formed with high precision by the single focus processing. On the other hand, the possibility of damaging the device layer D of the peripheral modified layers M1 (4) to (7) is lower than that of the peripheral modified layers M1 (1) to (3). Thereby, the throughput in the internal reforming device 41 can be improved.
  • a divided modified layer M2 extending in the radial direction of the wafer W to be processed is formed outside the peripheral modified layer M1 in the radial direction (Step P4 in FIG. 9).
  • the divided modified layers M2 are formed at eight locations in the circumferential direction and seven locations in the thickness direction of the wafer W to be processed, but the number of the divided modified layers M2 is arbitrary.
  • the spatial light modulator switches the laser light emitted from the laser head, and adjusts the shape and number of the laser light. Specifically, as shown in FIG. 13, the inside of the processing target wafer W is irradiated with the laser beam Lr3 to form the divided modified layer M2.
  • the number of focal points of the laser beam Lr3 is, for example, two (multi-focus processing).
  • the number of divided modified layers M2 formed by the laser light Lr3 and the number of converging points of the laser light Lr3 are arbitrary.
  • the split modified layer M2 is formed at a position where it is removed by the subsequent edge trim, and has a low possibility of giving a damaged layer to the device layer D as described above. Throughput in the reformer 41 can be improved.
  • the overlapped wafer T is transferred to the processing device 50 by the wafer transfer device 32.
  • the overlapped wafer T transferred to the processing device is transferred to the alignment unit 80.
  • the alignment unit 80 the horizontal direction of the processing target wafer W is adjusted.
  • the overlapped wafer T is transferred from the alignment unit 80 to the transfer position A0 by the transfer unit 70, and transferred to the chuck 61 at the transfer position A0. Thereafter, the chuck 61 is moved to the first processing position A1. Then, the back surface Wb of the processing target wafer W is roughly ground by the rough grinding unit 110 (Step P5 in FIG. 9).
  • cracks C1 and C2 are substantially linearly formed in the thickness direction from the peripheral modified layer M1 and the divided modified layer M2 inside the wafer W to be processed. And reaches the back surface Wb and the front surface Wa. Further, as the grinding of the back surface Wb proceeds, as shown in FIG. 10E, the peripheral edge portion We of the processing target wafer W is peeled off and removed from the peripheral edge modified layer M1 and the crack C1 as a base point. Further, at this time, the peripheral edge portion We is fragmented based on the divided modified layer M2 and the crack C2, and the peripheral edge portion We can be more easily removed. In the grinding of the back surface Wb, since the unbonded region Ae is formed at the interface between the oxide films Fw and Fs, the peripheral portion We can be appropriately removed.
  • the distance L2 between the end of the processed wafer W before the processing in step P1 and the end of the processed wafer W after the processing in step P5 can be set to about 0.5 mm. That is, the effective area is an area of ⁇ 299 mm. Therefore, the effective area can be increased as compared with the conventional example shown in FIG. In the present embodiment, since the edge void can be suppressed, the effective area can be increased. Further, in Step P5, since the peripheral portion We can be removed starting from the peripheral modified layer M1, the width (trim width) of the peripheral portion We can be reduced, and the effective area can be further increased. For example, when edge trimming is performed using a grinding tool (blade) as in the related art, a trim width of about 2 mm is required. However, in this embodiment, no trimming tool is used, and the trim width can be reduced.
  • blade grinding tool
  • the chuck 61 is moved to the second processing position A2. Then, the back surface Wb of the wafer W to be processed is subjected to middle grinding by the middle grinding unit 120. In the case where the peripheral portion We cannot be completely removed in the above-described rough grinding unit 110, the peripheral portion We is completely removed by the middle grinding unit 120.
  • the chuck 61 is moved to the third processing position A3. Then, the back surface Wb of the processing target wafer W is finish-ground by the finish grinding unit 130.
  • the chuck 61 is moved to the delivery position A0.
  • the back surface Wb of the processing target wafer W is roughly cleaned with a cleaning liquid using a cleaning liquid nozzle (not shown). At this time, cleaning for removing stains on the back surface Wb to some extent is performed.
  • the overlapped wafer T is transferred from the delivery position A0 to the second cleaning unit 100 by the transfer unit 70. Then, in the second cleaning unit 100, the back surface Sb of the support wafer S is cleaned and dried while the processing target wafer W is held by the transfer pad 72.
  • the superposed wafer T is transferred from the second cleaning unit 100 to the first cleaning unit 90 by the transfer unit 70.
  • the back surface Wb of the processing target wafer W is finish-cleaned by the cleaning liquid using a cleaning liquid nozzle (not shown).
  • the back surface Wb is washed to a desired degree of cleanliness and dried.
  • the overlapped wafer T that has been subjected to all the processes is transferred to the transition device 34 by the wafer transfer device 32, and further transferred to the cassette Ct of the cassette mounting table 10 by the wafer transfer device 22.
  • a series of wafer processing in the wafer processing system 1 ends.
  • the surface layer of the outer peripheral portion Fwe of the oxide film Fw is removed in step P1, and when the oxide films Fw and Fs are joined in step P2, the oxide films Fw and Fs are removed.
  • An unbonded region Ae is formed at the interface.
  • the unbonded region Ae can suppress a rapid pressure reduction of the atmosphere at the end of the bonding wave, and as a result, can suppress edge voids.
  • the CH 3 groups are bonded to the surfaces of the oxide films Fw and Fs in the unbonded region Ae to make them hydrophobic in step P3, the adhesion (bonding) of the oxide films Fw and Fs can be suppressed. . Since the unjoined area Ae can be secured in this way, edge voids can be further suppressed. In addition, by making the surfaces of the oxide films Fw and Fs in the unbonded region Ae hydrophobic, the peripheral portion We of the processing target wafer W can be appropriately removed in Step P5.
  • the effective area of the processing target wafer W can be increased.
  • the peripheral portion We can be removed starting from the modified layer M in Step P5
  • the width (trim width) of the peripheral portion We can be reduced, and the effective area can be further increased.
  • the distance L1 from the end of the processing target wafer W to the edge void V before processing is about 7 mm
  • the effective area is an area of ⁇ 286 mm.
  • the distance L2 between the end of the processing target wafer W before the processing in step P1 and the end of the processing target wafer W after the processing in step P5 is about 0. 5 mm
  • the effective area is an area of ⁇ 299 mm.
  • the effective area of the processing target wafer W can be increased as compared with the related art, and a large number of chips as products can be manufactured.
  • the activation process, the hydrophilization process, the bonding process, and the annealing process of the oxide films Fw and Fs are sequentially performed in Step P2, and then, in Step P3, the surfaces of the oxide films Fw and Fs in the non-bonded region Ae. Was hydrophobized.
  • step P3 may be performed between the hydrophilic treatment and the bonding process in step P2, or may be performed between the bonding process and the annealing process.
  • the wafer processing system 1 of the present embodiment includes the bonding device 40, the internal reforming device 41, the surface reforming device 42, the hydrophobizing device 43, and the processing device 50, but the device configuration is arbitrary.
  • the joining device 40 and the surface reforming device 42 may be provided in one system, and the internal reforming device 41, the hydrophobizing device 43, and the processing device 50 may be provided in another system.
  • an internal reforming device 41 and a processing device 50 are provided in the wafer processing system 1, and a bonding device 40, a surface reforming device 42, and a hydrophobic device 43 are provided in another system (not shown). May be provided.
  • a cassette Ct capable of accommodating a plurality of overlapped wafers T is loaded and unloaded into the loading and unloading station 2 of the wafer processing system 1.
  • the cassettes Ct can be mounted on the cassette mounting table 10 in a line in the X-axis direction.
  • a processing device 50 is provided adjacent to the wafer transfer area 20.
  • the internal reforming device 41 is provided inside the processing device 50 and on the Y axis positive direction side of the transport unit 70 and the X axis negative direction side of the finish grinding unit 130.
  • the overlapped wafer T on which the above-described steps P1 to P3 have been performed in the external system is carried into the carry-in / out station 2 of the wafer processing system 1. That is, the surface layer of the outer peripheral portion Fwe is removed by the surface reforming device 42 from the loaded superposed wafer T (Step P1), and the oxide films Fw and Fs are joined by the joining device 40 (Step P2). At 43, the oxide films Fw and Fs are hydrophobized (step P3). Then, in the wafer processing system 1, steps P4 to P5 are performed on the overlapped wafer T.
  • Step P4 After the reformed layer M is formed inside the processing target wafer W by the internal reforming device 41 (step P4), the back surface Wb of the processing target wafer W is ground by the processing device 50, and the peripheral edge We is removed. (Step P5).
  • a substrate processing system for processing a substrate comprising: a first substrate having a thickness of 400 nm or less removed from a surface in a thickness direction of the surface film at an outer peripheral portion of the surface film; On the other hand, an internal reforming device that forms a modified layer inside the first substrate along a boundary between a peripheral portion and a central portion to be removed, and a peripheral edge that removes the peripheral portion based on the modified layer.
  • a substrate processing system comprising: a removing device.
  • a substrate processing method for processing a substrate comprising: removing a first substrate having a thickness of 400 nm or less removed from a surface in a thickness direction of the surface film at an outer peripheral portion of the surface film; On the other hand, an internal reforming step of forming a modified layer inside the first substrate along a boundary between a peripheral portion to be removed and a central portion, and a peripheral edge for removing the peripheral portion from the modified layer as a base point And a removing step.
  • the bonding device 40 may be provided in the wafer processing system 1, and the internal reforming device 41, the surface reforming device 42, and the hydrophobizing device 43 may be provided in another system.
  • the surface modification processing of the processing target wafer W in another system that is, the processing target wafer W from which the surface layer of the outer peripheral portion Fwe has been removed is carried into the wafer processing system 1, and thereafter, The overlapped wafer T is formed in the joining device 40.
  • a substrate processing method for processing a substrate comprising: preparing a first substrate having an outer peripheral portion of a first surface film modified by a surface modification step; A bonding step of bonding the first surface film of the first substrate prepared in the step of preparing the first substrate and a second surface film formed on a surface of the second substrate;
  • a substrate processing method comprising:
  • FIG. 15 is a plan view schematically showing the outline of the configuration of the wafer processing system 200.
  • edge trimming is performed before bonding.
  • the wafer processing system 200 has a configuration in which, in the configuration of the wafer processing system 1 according to the first embodiment, a peripheral edge removing device 210 is provided instead of the internal reforming device 41, and a hydrophilic device 220 is provided instead of the hydrophobic device 43. have.
  • the peripheral edge removing device 210 removes the peripheral edge portion We of the processing target wafer W using a grinding tool (not shown) such as a blade (edge trim). At this time, the peripheral edge portion We may be completely removed from the front surface Wa to the back surface Wb. However, in the present embodiment, only the surface layer is removed from the front surface Wa because the back surface Wb is ground later.
  • the hydrophilizing device 220 immerses the superposed wafer T in pure water to bond, for example, OH groups to the surfaces of the oxide films Fw and Fs in the unbonded region Ae. Specifically, the dangling bonds formed on the surfaces of the oxide films Fw and Fs in the unbonded region Ae are made hydrophilic by bonding OH groups.
  • the superposed wafer T is immersed in pure water, but the method of providing OH groups is not limited to this, and it is sufficient to supply water vapor to the surfaces of the oxide films Fw and Fs. For example, the surfaces of the oxide films Fw and Fs may be exposed to a high humidity atmosphere.
  • the wafer W to be processed in the cassette Cw is taken out by the wafer transfer device 22 and transferred to the transition device 34.
  • the wafer W to be processed in the transition device 34 is taken out by the wafer transfer device 32 and transferred to the peripheral edge removing device 210.
  • the peripheral edge removing device 210 as shown in FIG. 17A, the surface layer of the peripheral edge portion We of the processing target wafer W is removed (Step Q1 in FIG. 16).
  • the width L3 (trim width) of the peripheral edge portion We is about 2 mm.
  • the surface layer of the peripheral portion We is removed, and the device layer D and the oxide film Fw in the peripheral portion We are also removed.
  • the wafer W to be processed is transferred to the surface reforming device 42 by the wafer transfer device 32.
  • the etchant E is supplied to the outer peripheral portion Fwe of the oxide film Fw of the processing target wafer W, and the surface layer of the outer peripheral portion Fwe is removed as shown in FIG. 17B (step in FIG. 16). Q2).
  • the outer peripheral portion Fwe is removed inward from the inner end of the peripheral edge portion We, and the width of the outer peripheral portion Fwe is about 0.5 mm.
  • the support wafer S in the cassette Cs is taken out by the wafer transfer device 22 and transferred to the bonding device 40 by the wafer transfer device 32 via the transition device 34.
  • the processing target wafer W is transferred to the bonding device 40 by the wafer transfer device 32.
  • the bonding apparatus 40 as shown in FIG. 17C, the oxide film Fw of the processing target wafer W and the oxide film Fs of the support wafer S are bonded to form the overlapped wafer T (Step Q3 in FIG. 16).
  • the oxide films Fw and Fs are not bonded at the outer peripheral portion Fwe, and a bonded region Ac and an unbonded region Ae are formed at the interface between the oxide films Fw and Fs.
  • the unbonded region Ae reduces the space at the end of the bonding wave where the high-pressure atmosphere is released, and does not reduce the pressure to the atmospheric pressure. By suppressing such rapid pressure reduction, edge voids can be suppressed.
  • the wafer W to be processed is transferred by the wafer transfer device 32 to the hydrophilizing device 220.
  • the hydrophilizing device 220 the superposed wafer T is immersed in pure water to bond OH groups to the surfaces of the oxide films Fw and Fs in the unbonded region Ae as shown in FIG. 17D (step Q4 in FIG. 16). ).
  • the surfaces of the oxide films Fw and Fs in the unbonded region Ae are made hydrophilic, so that the oxide films Fw and Fs are bonded by hydrogen bonding.
  • the oxide films Fw and Fs are joined on the entire surface.
  • an annealing process may be further performed.
  • step Q4 is unnecessary and is omitted. be able to.
  • the overlapped wafer T is transferred to the processing device 50 by the wafer transfer device 32.
  • the same processing as in the first embodiment is performed.
  • the back surface Wb of the processing target wafer W is ground (Step Q5 in FIG. 16).
  • the overlapped wafer T that has been subjected to all the processes is transferred to the transition device 34 by the wafer transfer device 32, and further transferred to the cassette Ct of the cassette mounting table 10 by the wafer transfer device 22.
  • a series of wafer processing in the wafer processing system 1 ends.
  • the same effects as in the first embodiment can be obtained. That is, the surface layer of the outer peripheral portion Fwe of the oxide film Fw is removed in step Q2, and when the oxide films Fw and Fs are joined in step Q3, an unjoined region Ae is formed at the interface between the oxide films Fw and Fs. You.
  • the unbonded region Ae can suppress a rapid pressure reduction of the atmosphere at the end of the bonding wave, and as a result, can suppress edge voids.
  • the oxide films Fw and Fs can be adhered (joined). Since the oxide films Fw and Fs can be bonded on the entire surface, the effective area of the wafer W to be processed can be increased.
  • the effective area of the wafer W to be processed can be increased by suppressing edge voids and making the oxide films Fw and Fs of the unbonded area Ae adhere to each other.
  • the distance L1 from the end of the processing target wafer W to the edge void V before processing is about 7 mm, and the effective area is an area of ⁇ 286 mm.
  • the distance L3 between the end of the processing target wafer W before the processing in step Q1 and the end of the processing target wafer W after the processing in step Q5 is about 2 mm.
  • the effective area is an area of ⁇ 296 mm.
  • the effective area of the processing target wafer W can be increased as compared with the related art, and a large number of chips as products can be manufactured.
  • step Q4 the activation process, the hydrophilization process, the bonding process, and the annealing process of the oxide films Fw and Fs are sequentially performed in step Q3, and then, in step Q4, the surfaces of the oxide films Fw and Fs in the unbonded region Ae are processed.
  • step Q4 may be performed between the hydrophilic treatment and the bonding processing in step Q3, or may be performed between the bonding processing and the annealing processing. In such a case, the annealing process in step Q4 can be omitted.
  • the wafer processing system 1 of the present embodiment includes the bonding device 40, the surface reforming device 42, the processing device 50, the peripheral edge removing device 210, and the hydrophilizing device 220
  • the device configuration is arbitrary.
  • the joining device 40, the surface modification device 42, the peripheral edge removing device 210, and the hydrophilizing device 220 may be provided in one system, and the processing device 50 may be provided in another system.
  • the surface modification device 42 removes the outer peripheral portion Fwe of the oxide film Fw by performing wet etching, but the method of removing the outer peripheral portion Fwe is not limited to this. Not limited.
  • the surface reforming apparatus 230 includes a chuck 231 that holds the wafer W to be processed with the oxide film Fw facing upward.
  • the chuck 231 is configured to be rotatable around a vertical axis by a rotation mechanism 232.
  • a polishing member 233 pressed by the outer peripheral portion Fwe to remove the oxide film Fw is provided above the chuck 231, a polishing member 233 pressed by the outer peripheral portion Fwe to remove the oxide film Fw is provided.
  • the polishing member 233 is configured to be movable in the Z-axis direction by a moving mechanism (not shown).
  • the surface grain size of the polishing member 233 that is, the abrasive grain size of the polishing member 233 can be arbitrarily selected
  • the film removal rate of the oxide film Fw and the surface roughness of the oxide film Fw after the film removal are arbitrary. Can be adjusted. Thereby, generation of the edge void V and re-adhesion of the unjoined area Ae can be more appropriately suppressed.
  • the outer peripheral portion Fwe may be removed so that an inclination is formed, that is, such that the thickness of the oxide film Fw decreases toward the radially outward side in a side view.
  • the inclination is formed by the difference between the abrasive grain size of the polishing member 233 and the thickness of the oxide film Fw.
  • a polishing member having a shape capable of forming the inclination in advance may be pressed.
  • the inclination may be formed by devising the pressing direction of the polishing member 233, for example.
  • the formation of the slope on the outer peripheral portion Fwe may also be performed in the surface reforming device 42, that is, when the outer peripheral portion Fwe of the oxide film Fw is removed by wet etching. In such a case, for example, by controlling the supply angle of the etchant or the supply amount of the etchant, the inclination is formed toward the outer peripheral direction.
  • debris for removing the oxide film Fw (hereinafter, referred to as “debris”) is generated. Since the debris may cause defective bonding between wafers or defective product devices, it is necessary to prevent the debris from adhering to the surface of the wafer W to be processed, particularly to the surface of the device layer D.
  • a fluid nozzle 244 for diffusing is provided.
  • the fluid nozzle 244 is provided, for example, above the peripheral edge portion We of the processing target wafer W. Further, for example, pure water, air, or the like is supplied from the fluid nozzle 244, and debris generated from the polished surface can be diffused outward in the outer peripheral direction. Thereby, it is possible to suppress the debris generated by the polishing from scattering to the inside in the radial direction of the processing target wafer W and adhering to the surface of the processing target wafer W.
  • the fluid nozzle 244 may be further provided, for example, above a central portion of the processing target wafer W or on a back surface side of the processing target wafer W in order to more reliably scatter generated debris outward in the outer peripheral direction. .
  • the configuration of the surface reforming device 230 may be any configuration as long as the generated debris can be scattered in the outer peripheral direction, and is not limited to the configuration described above.
  • the inside of the wafer W to be processed in the radial direction is positive pressure (“+” in FIG. 20B), and the outside is negative pressure (“ ⁇ ” in FIG. 20B).
  • the pressure inside the surface reforming device 230 may be controlled so as to be as follows.
  • an airflow is formed from the radially inner side to the outer side of the processing target wafer W, and the generated debris can be appropriately scattered in the outer peripheral direction.
  • the suction mechanism 245 such as a vacuum pump on the outer peripheral side of the outer peripheral portion Fwe to be polished, it is possible to more appropriately form an airflow from the radially inner side to the outer side. .
  • the polishing member 233 having a large abrasive particle diameter causes the boundary between the peripheral portion We and the central portion Wc, that is, the inner peripheral end of the peripheral portion We to be removed. (Hereinafter sometimes simply referred to as “edge”) becomes coarse, and the trimming processing position cannot be appropriately set in the radial direction.
  • the present inventor processes the edge of the peripheral portion We as shown in FIG. It has been found that the accuracy is improved and the trimming processing position can be appropriately set in the radial direction.
  • polishing is performed using a polishing member 234 having a small abrasive particle diameter at the edge of the peripheral edge We.
  • One polishing region 234a is formed.
  • the polishing is performed by the polishing member 234 having a small abrasive particle diameter, so that the processing accuracy of the inner peripheral end of the first polishing region 234a, that is, the peripheral edge portion We is improved. I do.
  • polishing member 234 is left on the edge of the peripheral edge We, that is, a position separated from the inner peripheral end of the first polishing area 234a by a distance L to both radial outer sides. Then, polishing is performed by the polishing member 233 having a large abrasive particle diameter toward the edge of the processing target wafer W to form a second polishing region 233a.
  • the surface of the oxide film Fw in order to appropriately form the unbonded region Ae and to suppress re-adhesion in the unbonded region Ae, the surface of the oxide film Fw must be formed. It is preferable that the area of the roughened second polishing region 233a is large. That is, the first polishing region 234a is sufficient if the processing accuracy of the edge of the peripheral portion We required in the alignment processing can be ensured, and the distance L is desirably small. Specifically, by setting the distance L to be larger than at least the abrasive grain size of the polishing member 233 forming the second polishing region 233a, the alignment processing can be appropriately performed.
  • the processing accuracy of the edge of the peripheral portion We is increased, so that the alignment in the formation of the modified layer M (Step P4 in FIG. 9) can be appropriately performed, and the edge of the wafer W to be processed can be formed.
  • a damage layer is formed on the surface of the oxide film Fw, so that the generation of the edge voids V can be suppressed and, at the same time, the re-adhesion of the unjoined region Ae can be appropriately suppressed.
  • the abrasive particle size of the polishing member 233 can be arbitrarily selected, the film removal rate of the oxide film Fw and the surface roughness of the oxide film Fw after the film removal can be arbitrarily adjusted. Thereby, generation of the edge void V and re-adhesion of the unjoined area Ae can be more appropriately suppressed.
  • the second polishing region 233a is formed after forming the first polishing region 234a, but the processing order by the polishing members 233 and 234 is not limited to this.
  • the first polishing region 234a may be formed after forming the second polishing region 233a.
  • the grinding of the edges of the peripheral portion We by the polishing member 234 having a small abrasive particle diameter may be performed, for example, in a case where a slope is formed radially outward of the processing target wafer W as illustrated in FIG. Good.
  • the surface modification device 42 removes the outer peripheral portion Fwe of the oxide film Fw by performing wet etching. It is not limited to.
  • the outer peripheral portion Fwe may be removed by irradiating the outer peripheral portion Fwe with laser light having a wavelength that does not pass through the oxide film Fw, for example, ultraviolet light.
  • the surface modification device 42 removes the outer peripheral portion Fwe as the modification process of the outer peripheral portion Fwe of the oxide film Fw, the outer peripheral portion Fwe may be made to project.
  • the surface reforming device 240 has a chuck 241 that holds the processing target wafer W with the oxide film Fw facing upward.
  • the chuck 241 is configured to be rotatable around a vertical axis by a rotation mechanism 242.
  • a laser head 243 for irradiating the laser beam R to the outer peripheral portion Fwe is provided.
  • the laser light R for example, ultraviolet light is used.
  • the laser head 243 is configured to be movable in the X-axis direction, the Y-axis direction, and the Z-axis direction by a moving mechanism (not shown).
  • the outer peripheral portion Fwe is projected by the laser beam R as shown in FIG. Then, as shown in FIG. 24B, the oxide films Fw and Fs are not joined at the outer peripheral portion Fwe. That is, when the oxide films Fw and Fs are joined, an unjoined region Ae corresponding to the outer peripheral portion Fwe and a joined region Ac where the oxide films Fw and Fs are joined are formed at the interface between the oxide films Fw and Fs. You.
  • the unjoined region Ae is formed in the present embodiment, so that the space where the high-pressure atmosphere at the end of the bonding wave is released becomes smaller. It is not reduced to atmospheric pressure. By suppressing such rapid pressure reduction, edge voids can be suppressed. Moreover, by forming the protrusion of the outer peripheral portion Fwe discontinuously in the circumferential direction, the high-pressure atmosphere at the end of the bonding wave can be released to the outside of the overlapped wafer T. Then, even if dew condensation occurs at the outer peripheral portion Fwe, the water vapor can escape to the outside of the superposed wafer T.
  • the laser beam R is used when projecting the outer peripheral portion Fwe.
  • the laser light R roughens the top of the outer peripheral portion Fwe and roughens the outer peripheral portion Fwe.
  • the bonding of the oxide films Fw and Fs at the outer peripheral portion Fwe can be further suppressed, that is, the unbonded region Ae can be formed more reliably.
  • sharp voids can be suppressed, and edge voids can be suppressed.
  • the roughening of the outer peripheral portion Fwe may be performed even when the surface layer of the outer peripheral portion Fwe is removed by using the surface reforming device 42.
  • the removal of the oxide film Fw by the laser beam R is performed by dividing the outer peripheral portion Fwe into a plurality of regions in the radial direction of the processing target wafer W and inward from the radially outer side of the plurality of regions. May be performed in order.
  • FIG. 25 shows a region distribution when the outer peripheral portion Fwe of the oxide film Fw is divided into, for example, two annular regions in the radial direction. As shown in FIG. 25, the outer peripheral portion Fwe is divided into annular regions Fwe1 and Fwe2 in order from the outside in the radial direction.
  • the irradiation point Pt (1) of the laser light on the annular region Fwe1 is irradiated with the laser light R, and the oxide film Fw at the irradiation point Pt (1) is removed.
  • the annular region Fwe1 where the irradiation point Pt (1) is located faces an open space on the outer side in the outer peripheral direction of the processing target wafer W as shown in FIG. Spread into open space.
  • the oxide film Fw is removed at the irradiation point Pt (1), the wafer W to be processed subsequently rotates, and the irradiation point Pt (2) is irradiated with the laser beam R.
  • the irradiation point Pt (2) is set adjacent to the irradiation point Pt (1).
  • the irradiation point Pt (2) is located in the annular region Fwe1 and also faces the irradiation point Pt (1) from which the oxide film Fw has already been removed. Diffusion to the inside is more reliably suppressed.
  • the oxide film Fw is removed over the entire circumference of the annular region Fwe1 by repeating such a series of the irradiation operation of the laser beam R and the rotation operation of the processing target wafer W.
  • the laser head 243 subsequently moves above the annular region Fwe2, and the removal of the oxide film Fw from the annular region Fwe2 is started.
  • the annular region Fwe2 faces the open space on the outer side in the outer peripheral direction of the processing target wafer W, as shown in FIG. The generated debris is diffused into the open space.
  • the above series of irradiation operation of the laser beam R and the rotation operation of the processing target wafer W are repeatedly performed, and the oxide film Fw is removed over the entire circumference of the annular region Fwe2.
  • the irradiation point of the laser beam R since the irradiation point of the laser beam R always faces the open space on the outer side in the outer peripheral direction of the processing target wafer W, it is possible to suppress the diffusion of debris to the radially inner side of the processing target wafer W. Thus, adhesion to the processing target wafer W can be appropriately suppressed. Further, according to the above operation, the scattering direction of the debris can be directed to the outer peripheral direction of the processing target wafer W and to the irradiation point direction of the immediately preceding laser beam R, so that the adhesion to the processing target wafer W is further improved. In addition to being able to appropriately suppress, it is possible to simplify the configuration of the exhaust equipment in the surface reforming device 240.
  • the surface reforming device 240 is provided with, for example, a fluid nozzle or the like in the same manner as the surface reforming device 230 in order to more appropriately prevent the debris generated by the laser light irradiation from adhering to the processing target wafer W. You may. Naturally, the internal pressure of the surface reforming device 240 may be controlled to generate an airflow from the radially inner side to the outer side of the processing target wafer W, or a suction mechanism may be provided. Is also good.
  • the irradiation point depth of the laser beam in the annular region Fwe2 may be controlled to be smaller than the irradiation point depth of the laser beam in the annular region Fwe1. That is, as shown in FIG. 27, the irradiation point depth of the laser beam R may be changed so that the removal thickness of the oxide film Fw gradually increases toward the outside in the radial direction of the processing target wafer W.
  • the surface of the outer peripheral portion Fwe is removed so as to have a substantially inclined surface, the same effects as those of the outer peripheral portion Fwe having the above-described inclined surface can be enjoyed, and the generation of the edge void V and the reconnection of the unjoined region Ae can be achieved. Adhesion can be appropriately suppressed. In this case, it is desirable that the difference H2 in the removal thickness in each annular region is within 400 nm.
  • the case where the outer peripheral portion Fwe is divided into two in the radial direction has been described as an example, but the number of divisions of the outer peripheral portion Fwe is not limited to this, and the surface of the oxide film Fw may be arbitrarily divided. Can be removed. In such a case, by increasing the number of divisions, the resolution of the above-mentioned substantially tilt can be increased, and the effect of suppressing the generation of the edge void V and the re-adhesion of the unjoined region Ae can be more appropriately enjoyed.
  • the surface film is not limited to this.
  • a SiC film, a SiCN film, or the like may be formed.
  • the second embodiment can also be applied to a case where the peripheral edge portion We of the processing target wafer W is left without being removed, that is, a case where Step Q1 is not performed.
  • the unbonded region Ae is formed by removing the oxide film Fw in the outer peripheral portion Fwe, but the method of forming the unbonded region Ae is not limited to this.
  • the oxide film Fw of the processing target wafer W and the oxide film Fs of the support wafer S are made hydrophilic by imparting OH groups to the dangling bonds formed on the surfaces of the oxide films Fw and Fs. And oxide film Fs are joined by hydrogen bonding.
  • the unbonded area Ae is supplied by supplying the hydrophobic material to the oxide film Fw of the processing target wafer W before the bonding.
  • the outer peripheral portion Fwe is made hydrophobic and water repellent by supplying the silylating material G to the outer peripheral portion Fwe of the oxide film Fw.
  • FIG. 28 is a side view schematically showing the outline of the configuration of the surface reforming device 330.
  • FIG. 29 is a flowchart showing main steps of wafer processing in the wafer processing system according to the third embodiment.
  • FIG. 30 is an explanatory diagram showing a state of wafer processing in the third embodiment.
  • elements having substantially the same functional configuration as those of the above-described first and second embodiments are denoted by the same reference numerals, and redundant description is omitted.
  • the surface reforming apparatus 330 has a chuck 350 for holding the wafer W to be processed with the oxide film Fw facing upward.
  • the chuck 350 is configured to be rotatable around a vertical axis by a rotation mechanism 351.
  • a nozzle 352 for applying the silylating material G to the outer peripheral portion of the oxide film Fw is provided above the chuck 350.
  • the nozzle 352 communicates with a silylating material supply source (not shown) that stores and supplies the silylating material G.
  • the nozzle 352 is configured to be movable in the X-axis direction, the Y-axis direction, and the Z-axis direction by a moving mechanism (not shown).
  • the wafer to be processed W in the cassette Cw is taken out by the wafer transfer device 22 and transferred to the transition device 34.
  • the processing target wafer W of the transition device 34 is taken out by the wafer transfer device 32 and transferred to the surface reforming device 330.
  • the surface reforming device 330 before the bonding is performed (before step U2 in FIG. 29), the dangling bond formed on the outer peripheral portion Fwe of the oxide film Fw by the silylation material G is added to a silyl group (Si—R). (Step U1 in FIG. 29).
  • a silylation region Fws is formed in the outer peripheral portion Fwe.
  • the processed wafer W having the silylated region Fws formed in the outer peripheral portion Fwe is subsequently transferred to the bonding device 40 by the wafer transfer device 32.
  • the oxide film Fw is activated and hydrophilized prior to bonding.
  • a silyl group is provided to the outer peripheral portion Fwe in step U1.
  • the hydrophilic treatment is performed by giving an OH group to the dangling bond formed on the oxide film Fw as described above.
  • the silyl group since the silyl group has already been imparted to the outer peripheral portion Fwe, it has been rendered hydrophobic and water repellent, so that the OH group is not imparted to the outer peripheral portion Fwe.
  • the oxide film Fw of the processing target wafer W and the oxidation of the support wafer S which has been activated and hydrophilized in advance are oxidized.
  • the film Fs is bonded to form the overlapped wafer T (Step U2 in FIG. 29).
  • the oxide films Fw and Fs are not bonded at the outer peripheral portion Fwe, and a bonded region Ac and an unbonded region Ae are formed at the interface between the oxide films Fw and Fs.
  • the overlapped wafer T is transferred to the internal reforming device 41 by the wafer transfer device 32.
  • the internal reforming device 41 irradiates the inside of the processing target wafer W with laser light from the laser head while rotating the processing target wafer W.
  • an annular peripheral modification layer M1 is formed inside the processing target wafer W (FIG. 29).
  • Step U3 by moving the laser head, a divided modified layer M2 extending in the radial direction of the processing target wafer W is formed radially outside the peripheral modified layer M1.
  • the overlapped wafer T is transferred by the transfer unit 70 to the processing device 50 via the alignment unit 80.
  • the back surface Wb of the processing target wafer W is ground by the processing apparatus 50, and the peripheral edge We is removed as shown in FIG. 30D (step U4 in FIG. 29).
  • the overlapped wafer T that has been subjected to all the processes is transferred to the transition device 34 by the wafer transfer device 32, and further transferred to the cassette Ct of the cassette mounting table 10 by the wafer transfer device 22.
  • a series of wafer processing in the wafer processing system 1 ends.
  • the removal of the oxide film Fw and the roughening of the surface are not performed in the unbonded region Ae. That is, the high-pressure atmosphere at the end of the bonding wave B according to the present embodiment is released at the end of the wafer W to be processed, and an edge void V is generated as shown in FIG.
  • the position where the edge void V is generated is on the end side of the processing target wafer W, that is, the outer periphery of the peripheral edge We to be removed. It is formed at the portion Fwe.
  • the outer peripheral portion Fwe is not a device forming portion, and thus does not substantially affect the semiconductor device manufacturing process.
  • the silylation of the outer peripheral portion Fwe of the oxide film Fw can be performed at an arbitrary timing before the bonding of the processing target wafer W. That is, in the above embodiment, the silylation process is performed before the bonding and before the activation of the oxide film Fw, but may be performed between the activation process and the hydrophilization process, for example. It may be performed after performing the hydrophilic treatment. In any case, by performing silylation of the outer peripheral portion Fwe before hydrogen bonding between the oxide film Fw and the oxide film Fs in the bonding process, the unbonded region Ae can be appropriately formed.
  • the unbonded region Ae is formed by performing silylation on the outer peripheral portion Fwe of the oxide film Fw.
  • the outer peripheral portion Fwe can be made hydrophobic and water repellent, it can be formed.
  • the method of making the outer peripheral portion Fwe hydrophobic is not limited to this. For example, by imparting a methyl group to the dangling bond as described above, the outer peripheral portion Fwe may be made hydrophobic. Further, for example, a release agent may be supplied to the outer peripheral portion Fwe of the oxide film Fw.
  • the thinning of the processing target wafer W is performed by grinding the back surface Wb in the processing apparatus, but the method of thinning the processing target wafer W is not limited to this. I can't.
  • the peripheral surface modified layer M1 and the internal surface modified layer M3 are formed along the surface direction of the processed wafer W inside the processed wafer W.
  • the order of forming the peripheral edge modified layer M1 and the internal surface modified layer M3 can be arbitrarily determined.
  • the unjoined region Ae is formed in the outer peripheral portion Fwe, the re-adhesion of the outer peripheral portion Fwe is suppressed, and the peeling of the peripheral edge portion We is appropriately performed. It can be carried out.
  • the thinning of the processing target wafer W by the separation based on the internal surface modified layer M3 as described above, it is necessary to grind the back surface Wb and the end surface for thinning and edge trim as in the related art. There is no. That is, when thinning and edge trimming of the wafer W to be processed, grinding chips are not generated, and there is no need to provide a grinding tool which is a consumable product, so that the apparatus configuration can be simplified.
  • the processing target wafer W may be thinned and the edge trim may be performed simultaneously.
  • the upper end of the peripheral edge modified layer M1 formed as shown in FIG. 32A is made substantially coincident with the height at which the internal surface modified layer M3 is formed. Then, in this state, by separating the back surface Wb side of the processing target wafer W from the peripheral modified layer M1 and the internal surface modified layer M3 as a base point, the peripheral portion We is formed on the rear surface as shown in FIG. It is removed integrally with the wafer on the Wb side.
  • the wafer processing according to the present embodiment since the unjoined region Ae is formed in the outer peripheral portion Fwe, re-adhesion of the outer peripheral portion Fwe is suppressed, and The peripheral portion We can be peeled off. Further, conventionally, grinding for thinning of the processing target wafer W and grinding for edge trimming are performed, respectively. However, thinning and edge trimming of the processing target wafer W can be performed simultaneously.
  • the wafer W to be processed is thinned by separation with the internal surface reforming layer M3 as a base point, so that the back surface Wb and the end surface are ground for thinning and edge trim as in the related art. No need. That is, when thinning and edge trimming of the wafer W to be processed, grinding chips are not generated, and there is no need to provide a grinding tool which is a consumable product, so that the apparatus configuration can be simplified.

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113097130A (zh) * 2020-03-27 2021-07-09 台湾积体电路制造股份有限公司 半导体器件及其形成方法
WO2021199585A1 (ja) * 2020-04-02 2021-10-07 東京エレクトロン株式会社 基板処理方法及び基板処理装置
JP7515292B2 (ja) 2020-04-28 2024-07-12 株式会社ディスコ チップの製造方法及びエッジトリミング装置

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11437344B2 (en) 2020-03-27 2022-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer bonding method
TWI799989B (zh) * 2021-09-13 2023-04-21 日商雅馬哈智能機器控股股份有限公司 表面處理裝置及半導體裝置的製造裝置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014056910A (ja) * 2012-09-12 2014-03-27 Tokyo Electron Ltd 塗布処理装置、接合システム、塗布処理方法、プログラム及びコンピュータ記憶媒体
JP2015207691A (ja) * 2014-04-22 2015-11-19 東京エレクトロン株式会社 基板処理システム、基板処理方法、プログラム及びコンピュータ記憶媒体
JP2017034107A (ja) * 2015-08-03 2017-02-09 東京エレクトロン株式会社 接合装置、接合システム、接合方法、プログラム及びコンピュータ記憶媒体
JP2018043340A (ja) * 2016-09-15 2018-03-22 株式会社荏原製作所 基板加工方法および基板加工装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04263425A (ja) * 1991-02-18 1992-09-18 Toshiba Corp 半導体基板の研削装置及び研削方法
JPH0981904A (ja) * 1995-09-13 1997-03-28 Sony Corp 磁気ヘッドの製造方法
JP4306540B2 (ja) 2004-06-09 2009-08-05 セイコーエプソン株式会社 半導体基板の薄型加工方法
JP2006108532A (ja) * 2004-10-08 2006-04-20 Disco Abrasive Syst Ltd ウエーハの研削方法
US20060284167A1 (en) * 2005-06-17 2006-12-21 Godfrey Augustine Multilayered substrate obtained via wafer bonding for power applications

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014056910A (ja) * 2012-09-12 2014-03-27 Tokyo Electron Ltd 塗布処理装置、接合システム、塗布処理方法、プログラム及びコンピュータ記憶媒体
JP2015207691A (ja) * 2014-04-22 2015-11-19 東京エレクトロン株式会社 基板処理システム、基板処理方法、プログラム及びコンピュータ記憶媒体
JP2017034107A (ja) * 2015-08-03 2017-02-09 東京エレクトロン株式会社 接合装置、接合システム、接合方法、プログラム及びコンピュータ記憶媒体
JP2018043340A (ja) * 2016-09-15 2018-03-22 株式会社荏原製作所 基板加工方法および基板加工装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113097130A (zh) * 2020-03-27 2021-07-09 台湾积体电路制造股份有限公司 半导体器件及其形成方法
US12015008B2 (en) 2020-03-27 2024-06-18 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer bonding method
WO2021199585A1 (ja) * 2020-04-02 2021-10-07 東京エレクトロン株式会社 基板処理方法及び基板処理装置
JPWO2021199585A1 (zh) * 2020-04-02 2021-10-07
JP7354420B2 (ja) 2020-04-02 2023-10-02 東京エレクトロン株式会社 基板処理方法及び基板処理装置
JP7515292B2 (ja) 2020-04-28 2024-07-12 株式会社ディスコ チップの製造方法及びエッジトリミング装置

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