WO2019222866A1 - True random number generation method and device having detection and correction functions - Google Patents

True random number generation method and device having detection and correction functions Download PDF

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WO2019222866A1
WO2019222866A1 PCT/CN2018/000399 CN2018000399W WO2019222866A1 WO 2019222866 A1 WO2019222866 A1 WO 2019222866A1 CN 2018000399 W CN2018000399 W CN 2018000399W WO 2019222866 A1 WO2019222866 A1 WO 2019222866A1
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input
gate
flip
module
stage
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PCT/CN2018/000399
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French (fr)
Chinese (zh)
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张建国
侯二林
李璞
王安帮
王云才
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太原理工大学
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/588—Random number generators, i.e. based on natural stochastic processes

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  • the invention relates to the field of integrated circuits and the field of cryptographic chips, and is a method and device for generating true random numbers with detection and correction functions.
  • True random number generators have very important applications in the field of modern cryptography. It is an important part of the crypto chip system.
  • the current pseudo-random number generator has the disadvantages of periodicity and easy cracking of the generated sequence, and is not suitable for use in the security field.
  • the random sequence generated by the true random number generator is unpredictable and unreproducible, so it can better protect the transmission of information.
  • people use physical phenomena in nature as a random source to generate random sequences.
  • the existing random number generation methods and devices have the disadvantages of complex structure, large power consumption, low speed, offline detection, etc. Therefore, there is a great need for a high-speed, low power consumption, online detection physical random number generation method and solution.
  • the purpose of the present invention is to solve the shortcomings of the existing random number generation methods and devices, such as complex structure, large power consumption, low speed, offline detection, and the like, and provide a high-speed, low power, online detection physical random number generation method and solution. .
  • the invention provides a method for generating a true random number with a detection and correction function, which is implemented with the following structure: the structure includes an entropy source module, a sampling module, an XOR logic gate, a cell state machine, a test module, a CPU, and a selection controller ;
  • the entropy source module is composed of two identical oscillator structures.
  • the oscillator is a chaotic oscillator structure based on an autonomous Boolean network.
  • the autonomous Boolean network consists of three two-input XOR gates, A three-input XOR gate, a NOT gate, and a four-input XOR gate; three two-input XOR gates and a three-input XOR gate are connected end-to-end to form a circular Boolean network structure, and an input and output of an NOT gate are self-connected Form a ring oscillator, and connect the output of the NOT gate to the input of the three-input XOR gate; the output of each node of the ring Boolean network structure is connected to the input of the four-input XOR gate; Frequency periodic signals, repeated repeated oscillations of the ring Boolean network structure, constantly destroying the fixed points existing in the structure, so that the entropy source module can continuously generate high-quality
  • the sampling module includes a double sampling structure composed of a D flip-flop and an inverter, where the D flip-flop is divided into two stages, two in each stage; the inverter is also two; the two outputs of the entropy source module are respectively.
  • the two D flip-flops in the first stage are quantified.
  • the clock is an external clock.
  • the random number rate can be adjusted by adjusting the external clock.
  • the two random sequences quantized by the two first-stage D flip-flops are connected to the second D respectively.
  • the two random sequences quantized by the first-stage D flip-flop are inverted by an inverter and connected to the clock terminal of the other D-flip-flop of the second stage as the clock signal input;
  • the random sequence sampled by the stage D trigger is XORed, and the quantized sampling sequence is output to the cellular state machine;
  • the cell state machine is a post-processing module composed of four different logic circuits.
  • the multi-path selection controller 700 selects different post-processing to improve the quality of the random sequence and increase the randomness of the random sequence;
  • the test module performs a frequency check, a run length test, a longest run length test within the block, a discrete Fourier transform test on the random sequence sent by the cell state machine, and sends the test result to the CPU;
  • the CPU judges the inspection result, and if it passes the test, it outputs a random sequence directly; if it fails, it returns the data to the XOR logic gate again;
  • the selection controller is a four-way selection controller.
  • the CPU sends control signals to switch control the four logic circuits of the cellular state machine.
  • the invention comprises three parts: an entropy source module, a sampling module and an online detection.
  • the entropy source module and the sampling module are all composed of digital logic devices, which have a simple structure and are easy to integrate and manufacture.
  • traditional circular two-input Boolean networks have structural defects, and can only appear when the number of nodes in the circular two-input network is 3N (N is not less than 1)
  • N is not less than 1
  • a two-input Boolean network with no 3N nodes will have a Boolean fixed point due to the logical defects of its structure, so that the network is in a stable state.
  • an oscillating circuit composed of an NOT gate (103) is appropriately added to the two-input Boolean network structure, and the oscillating signal generated by the oscillating circuit is coupled to the Boolean network.
  • the network oscillates, thereby breaking the Boolean fixed point existing in the non-3N node two-input Boolean network, and can generate a high-entropy chaotic signal with a small number of nodes.
  • the invention breaks the limitation of the fixed point of the two-input Boolean network, greatly reduces the number of network nodes, and reduces the power consumption by simplifying the structure.
  • the use of two-input logic gate devices can greatly reduce the power consumption level, because a three-input XOR or a three-input XOR requires two two-input XOR gates in principle. Or two two-input XOR gates are cascaded, which means that when the number of nodes in the autonomous Boolean network is the same, the actual number of logic gate devices used in the present invention is about half of that of three-input logic gates; Power consumption can also be reduced by about half.
  • the two-input logic gate is about 1/2 of the three-input logic gate; therefore, the random number generation rate can be increased by about 2 times.
  • the single-channel random number generation speed of the present invention is Up to 1GbDs.
  • the invention uses a double sampling structure composed of a D flip-flop and an inverter to sample the chaotic signal generated by the entropy source.
  • the chaotic signals generated by two identical Boolean network structures are quantized and sampled and XORed. Since one chaotic sequence is used as the clock signal of another chaotic sequence, the randomness of the entropy source signal can be improved, and the sequence can be improved. frequency.
  • the present invention uses a cellular state machine as a post-processing to improve the quality of the sequence.
  • Cell state machine is a parallel mathematical model with discrete time and space and discrete states. It is composed of a large number of simple cells with local interaction. The cell state machine evolves at each discrete time point, and the value of each grid point is updated synchronously according to the value of the previous cell of the neighboring cell according to a predefined local rule.
  • four different local definitions f1, f2, f3, and f4 are used to perform different post-processing on different data, respectively. Different locally defined choices are selected by the multiplexer. This method can improve the chaos of random sequences and improve the pass rate of data tests.
  • test module of the present invention includes the following tests:
  • the test mainly looks at the proportion of 0 and 1 in the entire sequence.
  • the purpose of the test is to determine if the 1 and 0 numbers in the sequence are approximately the same as the 1 and 0 numbers in a truly random sequence.
  • the test evaluates 1 code to 1/2, that is, the number of 0s and 1s is the same throughout the sequence.
  • the other testing methods are based on the establishment of the test, and there is no evidence that the tested sequence is not random.
  • a run refers to a sequence of the same number without interruption, that is, the run is either "1111 " or "0000 ".
  • a run of length k contains k identical bits.
  • the purpose of run detection is to determine whether the number of "1" runs of different lengths and the number of "0" runs are consistent with the expected value of an ideal random sequence. Specifically, it is the inspection means that determines whether the oscillation between such "0" and "1" sub-blocks is too fast or too slow.
  • the test mainly looks at the longest "1" run in a sub-block of length M-bits.
  • the purpose of this test is to determine whether the length of the longest "1" run of the sequence to be tested is the same as that of the random sequence. Note: An irregular change in the length of the longest "1” run means that there is also an irregular change in the length of the corresponding "0" run, so it is sufficient to test only the "1" run.
  • the purpose of this test is to look at the peak height of the sequence after stepwise Fourier transform.
  • the purpose is to detect the periodicity of the signal to be tested, so as to reveal the degree of deviation from the corresponding random signal. This is done by observing whether the number of peaks above the 95% threshold is significantly different from the number of peaks below the 5%.
  • the test module transmits the test result to the CPU for judgment.
  • the CPU judges that the data test result passes, it outputs the random sequence directly, that is, the random sequence can be regarded as a high-quality true random sequence after the test.
  • the CPU judges that the test result fails, it will
  • the original data is transmitted to the input terminal of the XOR logic gate after the sampling module, XORed with the new data, and the XOR result is re-entered into the cell state machine for post-processing. After post-processing, the data is input into the detection module again until the test is passed.
  • a true random number generating device with a detection and correction function includes an entropy source module, a sampling module, an exclusive-OR logic gate, a cell state machine, a test module, a CPU, and a selection controller;
  • the entropy source module is composed of two identical oscillator structures.
  • the oscillator is a chaotic oscillator structure based on an autonomous Boolean network.
  • the autonomous Boolean network consists of three two-input XOR gates, A three-input XOR gate, a NOT gate, and a four-input XOR gate; three two-input XOR gates and a three-input XOR gate are connected end-to-end to form a circular Boolean network structure, and an input and output of an NOT gate are self-connected Form a ring oscillator and connect the output of the NOT gate to the input of the three-input XOR gate; the output of each node of the ring Boolean network structure is connected to the input of the four-input XOR gate; the output of the four-input XOR gate is sampled
  • the modules are connected to perform the sampling and quantization process;
  • the sampling module includes a double sampling structure composed of a D flip-flop and an inverter, where the D flip-flop is divided into two stages, two in each stage; the inverter is also two; the two outputs of the entropy source module are respectively Two D flip-flops in one stage are used for quantification.
  • the clock ends of the two first-stage D flip-flops are respectively connected to a clock module; the signal output ends of the two first-stage D flip-flops are respectively connected to the second-stage D flip-flops.
  • the signal output ends of the two first-stage D flip-flops are connected to the clock stage of the other D-flip-flop of the second stage after passing through an inverter, respectively, as the clock signal input of the second-stage D-flip-flop;
  • the two-stage D flip-flop output terminal is commonly connected with a two-input XOR gate, and the output of the two-input XOR gate is connected to the XOR logic gate input terminal; the XOR logic gate output is connected to the cell state machine input terminal;
  • Cell state machine is a post-processing module composed of four different logic circuits, and different post-processing is selected by the multi-channel selection controller;
  • the signal output of the cell state machine is connected to the signal input of the test module; the signal output of the test module is connected to the signal input of the CPU;
  • the CPU signal output is connected to the XOR logic gate signal input;
  • the selection controller is a four-way selection controller.
  • the signal input terminal of the selection controller is connected to the signal output terminal of the CPU, and the signal output terminal of the selection controller is connected to the signal input terminal of the cellular state machine to receive the signals sent by the CPU. Control signals, and switch the four logic circuits of the cellular state machine.
  • the random number generating method and device, the entropy source module and the sampling module are all composed of digital logic gates, the circuit structure is simple and easy to integrate, and the power consumption is very low, which is compatible with various programmable logic circuits.
  • the random number generating method and device can realize online detection, can output a high-quality random sequence that passes the test, and can be widely used in information security fields such as confidential communication.
  • the entropy sampling module is implemented by a double sampling structure composed of a D flip-flop and an inverter.
  • the D flip-flop has a clock signal input terminal connected to an external clock signal, and the double sampling structure can increase sequence frequency and increase sequence chaos.
  • the invention provides a method and a device for generating a true random number with a detection and correction function, which have the following advantages:
  • the generated random number sequence does not have periodicity.
  • random numbers of 0 to 1 Gbit / s that can pass international random number industry test standards (NIST and Diehard statistical tests) and have good random characteristics can be generated.
  • the system uses logical gates such as XOR gates and XOR gates to form a ring topology.
  • logical gates such as XOR gates and XOR gates
  • the three-input XOR gate and XOR gates are used to overcome the three-input entropy source.
  • the structural defects of the entropy source formed by the XOR gate and XOR gate have no Boolean fixed point. It can generate chaotic signals with fewer nodes, and has higher frequency and lower power consumption.
  • the entropy sampling module (200) of the system is implemented by a dual sampling structure composed of a D flip-flop and an inverter.
  • the D flip-flop has a clock signal input terminal connected to an external clock signal.
  • the dual sampling structure can increase the sequence frequency and increase at the same time. Sequence chaos. Because the entropy source module (100) is not driven by a clock signal, there are events that do not meet the setup and hold times of the D-flip-flop sampling quantization, resulting in the occurrence of a metastable state, which further increases the randomness of the system.
  • the system adopts digital logic gates, the circuit structure is simple, it can be compatible with various programmable logic circuits, and it has universal applicability and flexibility.
  • the random number generating method and device can realize integration and miniaturization, and can be widely used in information security fields such as confidential communication.
  • FIG. 1 is a block diagram of a circuit structure of the patent of the present invention.
  • 100 entropy source module
  • 200 sampling module
  • 300 XOR logic gate
  • 400 cell state machine
  • 500 test module
  • 600 CPU
  • 700 select controller.
  • FIG. 2 is a circuit structure diagram of an entropy source module.
  • FIG. 3 is a circuit diagram of a sampling module according to the present invention.
  • FIG. 4 is a circuit structure diagram of an entropy source module and a sampling module according to the present invention.
  • FIG. 5 is a diagram of different post-processing structures in a cell state machine according to the present invention.
  • Fig. 6 is a structural block diagram of a multi-channel selection controller.
  • the invention provides a method for generating a true random number with a detection and correction function.
  • the structure block diagram is shown in FIG. 1. It is mainly composed of an entropy source module 100, a sampling module 200, an exclusive OR logic gate 300, a cell state machine 400, a test module 500, a CPU 600, and a selection controller 700.
  • the entropy source module 100 is composed of two identical oscillator structures.
  • the oscillator is a chaotic oscillator structure based on an autonomous Boolean network.
  • the Boolean network consists of three two-input XOR gates 101 (1011, 1012, 1013, 1014), a three-input XOR gate 102, an NOT gate 103, and a four-input XOR gate 104.
  • Three two-input XOR gates 101 and one three-input XOR gate 102 are connected end-to-end with adjacent logic gates to form a ring Boolean network structure.
  • the input and output of one NOT gate 103 are connected to form a ring oscillator, and the inverter 103 is output.
  • the output of each node of the ring network structure is connected to the input of the four-input XOR gate 104.
  • the high-frequency periodic signal is generated by the oscillating ring structure formed by the inverter 103, and the Boolean network structure is repeatedly repeatedly vibrated, constantly destroying the fixed points existing in the structure, so that the entropy source module can continuously generate high-quality chaotic signals.
  • the output of the four-input XOR gate 104 is connected to the sampling module 200 to perform a sampling and quantization process.
  • the sampling module 200 is a dual sampling structure composed of a D flip-flop and an inverter.
  • the two outputs of the entropy source module are quantized by the first-stage D flip-flops (2011 and 2013) respectively.
  • the random number rate can be adjusted by adjusting the external clock, and the external clock frequency does not exceed 1GHz / s.
  • the quantized sequences of the two D flip-flops are respectively connected to the next D flip-flops (2012 and 2014), and the sequence is inverted and connected to the other D flip-flop clock end as the clock signal input, which is the D flip-flop 2011.
  • the output is connected to D flip-flop 2012, the output of D flip-flop 2013 is connected to D flip-flop 2014; at the same time, the output of D flip-flop 2011 is connected to D flip-flop 2014 through inverter 2022, and the output of D flip-flop 2013 is connected to inverter 2021 is connected to the D flip-flop 2012.
  • the random sequence sampled by the two-stage D flip-flop is input to the two-input XOR gate 203 for XOR processing, and a quantized sampling sequence is output, and then input to the XOR logic gate 300.
  • Cell state machine 400 is a post-processing module composed of four different logic circuits, as shown in FIG. 5.
  • f1, f2, f3, f4 are four different local definitions. In this example, you can choose AND, OR, OR, NAND, or NOR.
  • the multi-path selection controller selects different post-processing to improve the quality of the random sequence and increase the randomness of the random sequence.
  • the test module 500 performs a frequency test, a run test, a longest run test within a block, and a discrete Fourier transform test on the random sequence, and sends the test result to the CPU.
  • the CPU 600 judges the inspection result, and directly outputs a random sequence if it passes the test; if it fails, it returns the data again.
  • the selection controller 700 is a four-way selection controller, and a control signal is sent by the CPU 600 to switch control the four logic circuits of the cellular state machine 400 respectively.

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Abstract

A true random number generation method and device, the device comprising an entropy source module (100), a sampling module (200), an XOR logic gate (300), a cellular finite state machine (400), a test module (500), a CPU (600) and a selection controller (700). The entropy source module (100) is composed of two identical oscillator structures, an oscillator being a chaotic oscillator structure based on an autonomous Boolean network. The entropy source module (100) may generate wide spectrum and high bandwidth chaotic signals. After a random sequence is tested by the test module, whether the sequence passes testing or not is determined by the CPU (600), the sequence being directly outputted if the sequence passes testing. Data are returned and enter a postprocessing module by means of the XOR logic gate (300) if the sequence does not pass testing. At the same time, the selection controller (700) selects different postprocessing modes to process the data, wherein the processed data enter the test module to be tested again, until the data pass the testing. Thus, a random code sequence generated by the present method and device may pass a random number industry standard test.

Description

一种具有检测校正功能的真随机数产生方法与装置Method and device for generating true random number with detection and correction function 技术领域Technical field
本发明涉及集成电路领域、密码芯片领域，是一种具有检测校正功能的真随机数产生方法与装置。The invention relates to the field of integrated circuits and the field of cryptographic chips, and is a method and device for generating true random numbers with detection and correction functions.
背景技术Background technique
随着信息化社会的不断发展，信息在社会中的地位越来越重要，信息的产生、存储、处理与每个人都密切相关。相应的信息的安全与保密问题成为了人人都关心的事情。特别是在通信和金融领域，对信息的安全性有更加严格的要求。With the continuous development of the information society, the status of information in society is more and more important. The generation, storage, and processing of information are closely related to everyone. The security and confidentiality of the corresponding information has become a concern for everyone. Especially in the field of communication and finance, there are stricter requirements on the security of information.
真随机数发生器在现代密码学领域有非常重要的应用。它是密码芯片***中的重要组成部分。然而，现阶段的伪随机数发生器具有其产生序列的周期性、易破解等缺点，不适合用于安全领域。真随机数发生器所产生的随机序列无法预知、不可再现，因此能够更好的保护信息的传递。一般人们利用自然界中的物理现象来作为随机源产生随机序列，在电路中主要有三种方法来实现真随机数发生器：(1)利用电阻热噪声源直接放大；(2)利用带有抖动噪声的振荡器的采样；(3)利用离散时间的混沌***映射。这三种方法均可用于产生随机序列，为密码算法提供密钥。但是现有随机数产生方法和装置存在结构复杂、功耗大、速率低、离线检测等缺点，因此非常需要一种高速、低功耗、在线检测的物理随机数产生方法和解决方案。True random number generators have very important applications in the field of modern cryptography. It is an important part of the crypto chip system. However, the current pseudo-random number generator has the disadvantages of periodicity and easy cracking of the generated sequence, and is not suitable for use in the security field. The random sequence generated by the true random number generator is unpredictable and unreproducible, so it can better protect the transmission of information. Generally, people use physical phenomena in nature as a random source to generate random sequences. There are three main ways to implement a true random number generator in a circuit: (1) using a resistance thermal noise source to directly amplify it; (2) using jitter noise Sampling of the oscillator; (3) using discrete-time chaotic system mapping. All three methods can be used to generate random sequences and provide keys for cryptographic algorithms. However, the existing random number generation methods and devices have the disadvantages of complex structure, large power consumption, low speed, offline detection, etc. Therefore, there is a great need for a high-speed, low power consumption, online detection physical random number generation method and solution.
发明内容Summary of the Invention
本发明的目的是为了解决现有随机数产生方法和装置结构复杂、功耗大、速率低、离线检测等缺点，提供一种高速、低功耗、在线检测的物理随机数产生方法和解决方案。The purpose of the present invention is to solve the shortcomings of the existing random number generation methods and devices, such as complex structure, large power consumption, low speed, offline detection, and the like, and provide a high-speed, low power, online detection physical random number generation method and solution. .
本发明提供一种具有检测校正功能的真随机数产生方法，采用如下结构实现：所述结构包括熵源模块、采样模块、异或逻辑门、元胞状态机、测试模块、CPU和选择控制器；The invention provides a method for generating a true random number with a detection and correction function, which is implemented with the following structure: the structure includes an entropy source module, a sampling module, an XOR logic gate, a cell state machine, a test module, a CPU, and a selection controller ;
(1)所述熵源模块是由两块完全相同的振荡器结构组成，该振荡器是 一种基于自治布尔网络的混沌振荡器结构；所述自治布尔网络由三个二输入异或门、一个三输入异或非门、一个非门和一个四输入异或门组成；三个二输入异或门和一个三输入异或非门首尾相连构成环形布尔网络结构，一个非门输入输出自相连构成环形振荡器，并将非门输出与三输入异或非门输入端相连；环形布尔网络结构每个节点输出均与四输入异或门输入端连接；利用非门构成的振荡环结构产生高频周期信号，对环形布尔网络结构进行多次重复起振，不断破坏结构中存在的固定点，使熵源模块能够不断产生高质量混沌信号；四输入异或门的输出端与采样模块相连接，进行采样量化过程；(1) The entropy source module is composed of two identical oscillator structures. The oscillator is a chaotic oscillator structure based on an autonomous Boolean network. The autonomous Boolean network consists of three two-input XOR gates, A three-input XOR gate, a NOT gate, and a four-input XOR gate; three two-input XOR gates and a three-input XOR gate are connected end-to-end to form a circular Boolean network structure, and an input and output of an NOT gate are self-connected Form a ring oscillator, and connect the output of the NOT gate to the input of the three-input XOR gate; the output of each node of the ring Boolean network structure is connected to the input of the four-input XOR gate; Frequency periodic signals, repeated repeated oscillations of the ring Boolean network structure, constantly destroying the fixed points existing in the structure, so that the entropy source module can continuously generate high-quality chaotic signals; the output of the four-input XOR gate is connected to the sampling module To perform the sampling and quantization process;
(2)采样模块包括D触发器和反相器构成的双采样结构，其中D触发器分为两级，每级两个；反相器也为两个；熵源模块两路输出分别经第一级的两个D触发器进行量化，时钟采用外部时钟，可通过调节外部时钟来调节随机数速率；经两个第一级D触发器量化后的两路随机序列分别接入第二级D触发器其中一个，同时将第一级D触发器量化后的两路随机序列各通过一个反相器取反后接入第二级另一D触发器时钟端，作为时钟信号输入；将第二级D触发器采样后的随机序列进行异或处理，向元胞状态机输出量化采样序列；(2) The sampling module includes a double sampling structure composed of a D flip-flop and an inverter, where the D flip-flop is divided into two stages, two in each stage; the inverter is also two; the two outputs of the entropy source module are respectively The two D flip-flops in the first stage are quantified. The clock is an external clock. The random number rate can be adjusted by adjusting the external clock. The two random sequences quantized by the two first-stage D flip-flops are connected to the second D respectively. One of the flip-flops, at the same time, the two random sequences quantized by the first-stage D flip-flop are inverted by an inverter and connected to the clock terminal of the other D-flip-flop of the second stage as the clock signal input; The random sequence sampled by the stage D trigger is XORed, and the quantized sampling sequence is output to the cellular state machine;
(3)元胞状态机是由四个不同逻辑电路组成的后处理模块，由多路选择控制器700选择不同后处理，提高随机序列质量，增大随机序列的随机性；(3) The cell state machine is a post-processing module composed of four different logic circuits. The multi-path selection controller 700 selects different post-processing to improve the quality of the random sequence and increase the randomness of the random sequence;
(4)测试模块在相应软件的支持下对元胞状态机发送的随机序列进行频数检验、游程检验、块内最长游程检验、离散傅里叶变换检验，并将检验结果发送到CPU；(4) The test module, with the support of the corresponding software, performs a frequency check, a run length test, a longest run length test within the block, a discrete Fourier transform test on the random sequence sent by the cell state machine, and sends the test result to the CPU;
(5)CPU对检验结果进行判断，若通过测试则直接输出随机序列；若未通过测试，则将数据重新返回异或逻辑门；(5) The CPU judges the inspection result, and if it passes the test, it outputs a random sequence directly; if it fails, it returns the data to the XOR logic gate again;
(6)选择控制器为四路选择控制器，由CPU发送控制信号，分别对元胞状态机四路逻辑电路进行开关控制。(6) The selection controller is a four-way selection controller. The CPU sends control signals to switch control the four logic circuits of the cellular state machine.
本发明包含熵源模块、采样模块、在线检测三部分。熵源模块和采样模块全部由数字逻辑器件组成，结构简单且易于集成制造。与常见二输入 逻辑器件组成的环状布尔网络比较：传统环状二输入布尔网络具有结构缺陷，有且只有当环状二输入网络节点个数为3N(N不小于1)时，才可出现混沌状态，非3N节点的二输入布尔网络由于其结构的逻辑缺陷，将存在布尔固定点，从而使该网络处于稳定状态。而本发明结构在二输入布尔网络结构中适当的添加了一个由非门(103)构成的振荡电路，将其产生的振荡信号耦合到布尔网络中，以多次、重复的信号不停对布尔网络进行起振，从而打破了非3N节点二输入布尔网络中存在的布尔固定点，可以在少量节点时产生高熵的混沌信号。The invention comprises three parts: an entropy source module, a sampling module and an online detection. The entropy source module and the sampling module are all composed of digital logic devices, which have a simple structure and are easy to integrate and manufacture. Compared with the common two-input Boolean network composed of circular Boolean networks: traditional circular two-input Boolean networks have structural defects, and can only appear when the number of nodes in the circular two-input network is 3N (N is not less than 1) In a chaotic state, a two-input Boolean network with no 3N nodes will have a Boolean fixed point due to the logical defects of its structure, so that the network is in a stable state. In the structure of the present invention, an oscillating circuit composed of an NOT gate (103) is appropriately added to the two-input Boolean network structure, and the oscillating signal generated by the oscillating circuit is coupled to the Boolean network. The network oscillates, thereby breaking the Boolean fixed point existing in the non-3N node two-input Boolean network, and can generate a high-entropy chaotic signal with a small number of nodes.
本发明打破二输入布尔网络固定点的限制，大量减少网络节点个数，结构简化使其功耗降低。使用二输入逻辑门器件可以极大减小功耗水平，原因在于一个三输入异或非门(XNOR)或一个三输入异或门(XOR)原理上分别需要由两个二输入异或非门或两个二输入异或门来级联构成，这就意味着在自治布尔网络中节点数量一致的情况下，本发明实际的逻辑门器件使用数量约为三输入逻辑门的一半左右；因此装置功耗也可以降低约一半。最后，在器件传输延迟时间上，二输入逻辑门约是三输入逻辑门的1/2；因此，随机数产生速率可提高约2倍，在实际测试中，本发明的单路随机数产生速度最高可至1GbDs。The invention breaks the limitation of the fixed point of the two-input Boolean network, greatly reduces the number of network nodes, and reduces the power consumption by simplifying the structure. The use of two-input logic gate devices can greatly reduce the power consumption level, because a three-input XOR or a three-input XOR requires two two-input XOR gates in principle. Or two two-input XOR gates are cascaded, which means that when the number of nodes in the autonomous Boolean network is the same, the actual number of logic gate devices used in the present invention is about half of that of three-input logic gates; Power consumption can also be reduced by about half. Finally, in the device transmission delay time, the two-input logic gate is about 1/2 of the three-input logic gate; therefore, the random number generation rate can be increased by about 2 times. In actual tests, the single-channel random number generation speed of the present invention is Up to 1GbDs.
本发明采用D触发器和反相器构成的双采样结构对熵源产生的混沌信号进行采样。将两个完全相同布尔网络结构产生的混沌信号进行量化采样，并进行异或处理，由于是使用一混沌序列作为另一混沌序列的时钟信号，可以提高熵源信号的随机性，并提高序列的频率。The invention uses a double sampling structure composed of a D flip-flop and an inverter to sample the chaotic signal generated by the entropy source. The chaotic signals generated by two identical Boolean network structures are quantized and sampled and XORed. Since one chaotic sequence is used as the clock signal of another chaotic sequence, the randomness of the entropy source signal can be improved, and the sequence can be improved. frequency.
本发明采用元胞状态机作为后处理，来提高序列的质量。元胞状态机是一个时空离散、状态离散的并行数学模型，它是由大量简单的、具有局部相互作用的元胞所构成。元胞状态机在每一个离散时间点进行演化，每一格点的值根据一个预定义的局部规则，按照相邻元胞前一刻的值同步更新。在本发明中，采用四个不同局部定义f1、f2、f3、f4，分别对不同数据进行不同后处理。不同局部定义的选择是由多路选择器选择。该方法可提高随机序列的混乱性，提高数据测试的通过率。The present invention uses a cellular state machine as a post-processing to improve the quality of the sequence. Cell state machine is a parallel mathematical model with discrete time and space and discrete states. It is composed of a large number of simple cells with local interaction. The cell state machine evolves at each discrete time point, and the value of each grid point is updated synchronously according to the value of the previous cell of the neighboring cell according to a predefined local rule. In the present invention, four different local definitions f1, f2, f3, and f4 are used to perform different post-processing on different data, respectively. Different locally defined choices are selected by the multiplexer. This method can improve the chaos of random sequences and improve the pass rate of data tests.
本发明测试模块包含以下测试：The test module of the present invention includes the following tests:
1.频数检验Frequency test
该检验主要是看0和1在整个序列中所占的比例。检验的目的是确定序列中的1和0数是否与真正的随机序列中的1和0数近似相同。检验评定1码占1/2，也就是说，在整个序列中0和1的数目是一样的。其余别的检验手段都是在该检验成立的基础上进行的，并且没有任何证据表明被测序列是不随机的。The test mainly looks at the proportion of 0 and 1 in the entire sequence. The purpose of the test is to determine if the 1 and 0 numbers in the sequence are approximately the same as the 1 and 0 numbers in a truly random sequence. The test evaluates 1 code to 1/2, that is, the number of 0s and 1s is the same throughout the sequence. The other testing methods are based on the establishment of the test, and there is no evidence that the tested sequence is not random.
2.游程检验Run-length inspection
此检验主要是看游程的总数，游程指的是一个没有间断的相同数序列，即游程或者是“1111…”或者是“0000…”。一个长度为k的游程包含k个相同的位。游程检测的目的是判定不同长度的“1”游程的数目以及“0”游程的数目是否跟理想的随机序列的期望值相一致。具体的讲，就是该检验手段判定在这样的“0”“1”子块之间的振荡是否太快或太慢。This test mainly looks at the total number of runs. A run refers to a sequence of the same number without interruption, that is, the run is either "1111 ..." or "0000 ...". A run of length k contains k identical bits. The purpose of run detection is to determine whether the number of "1" runs of different lengths and the number of "0" runs are consistent with the expected value of an ideal random sequence. Specifically, it is the inspection means that determines whether the oscillation between such "0" and "1" sub-blocks is too fast or too slow.
3.块内最长游程检验3. Longest run test in block
该检验主要是看长度为M-bits的子块中的最长“1”游程。这项检验的目的是判定待检验序列的最长“1”游程的长度是否同随机序列的相同。注意：最长“1”游程长度上的一个不规则变化意味着相应的“0”游程长度上也有一个不规则变化，因此，仅仅对“1”游程进行检验是足够的。The test mainly looks at the longest "1" run in a sub-block of length M-bits. The purpose of this test is to determine whether the length of the longest "1" run of the sequence to be tested is the same as that of the random sequence. Note: An irregular change in the length of the longest "1" run means that there is also an irregular change in the length of the corresponding "0" run, so it is sufficient to test only the "1" run.
4.离散傅里叶变换检验4. Discrete Fourier transform test
本检验主要是看对序列进行分步傅里叶变换后的峰值高度。目的是探测待检验信号的周期性，以此揭示其与相应的随机信号之间的偏差程度。做法是观察超过95％阈值的峰值数目与低于5％峰值的数目是否有显著不同。The purpose of this test is to look at the peak height of the sequence after stepwise Fourier transform. The purpose is to detect the periodicity of the signal to be tested, so as to reveal the degree of deviation from the corresponding random signal. This is done by observing whether the number of peaks above the 95% threshold is significantly different from the number of peaks below the 5%.
测试模块将测试结果传输给CPU进行判断，当CPU判断数据测试结果通过时，直接将随机序列输出，即通过测试可认为随机序列为高质量真随机序列；当CPU判断测试结果未通过时，将原数据传输到采样模块后异或逻辑门输入端，与新数据进行异或处理并将异或结果重新输入元胞状态机进行后处理。经后处理后将数据再次输入检测模块，直至通过测试。The test module transmits the test result to the CPU for judgment. When the CPU judges that the data test result passes, it outputs the random sequence directly, that is, the random sequence can be regarded as a high-quality true random sequence after the test. When the CPU judges that the test result fails, it will The original data is transmitted to the input terminal of the XOR logic gate after the sampling module, XORed with the new data, and the XOR result is re-entered into the cell state machine for post-processing. After post-processing, the data is input into the detection module again until the test is passed.
一种具有检测校正功能的真随机数产生装置，所述装置包括熵源模块、采样模块、异或逻辑门、元胞状态机、测试模块、CPU和选择控制器；A true random number generating device with a detection and correction function, the device includes an entropy source module, a sampling module, an exclusive-OR logic gate, a cell state machine, a test module, a CPU, and a selection controller;
(1)所述熵源模块是由两块完全相同的振荡器结构组成，该振荡器是一种基于自治布尔网络的混沌振荡器结构；所述自治布尔网络由三个二输入异或门、一个三输入异或非门、一个非门和一个四输入异或门组成；三个二输入异或门和一个三输入异或非门首尾相连构成环形布尔网络结构，一个非门输入输出自相连构成环形振荡器，并将非门输出与三输入异或非门输入端相连；环形布尔网络结构每个节点输出均与四输入异或门输入端连接；四输入异或门的输出端与采样模块相连接，进行采样量化过程；(1) The entropy source module is composed of two identical oscillator structures. The oscillator is a chaotic oscillator structure based on an autonomous Boolean network. The autonomous Boolean network consists of three two-input XOR gates, A three-input XOR gate, a NOT gate, and a four-input XOR gate; three two-input XOR gates and a three-input XOR gate are connected end-to-end to form a circular Boolean network structure, and an input and output of an NOT gate are self-connected Form a ring oscillator and connect the output of the NOT gate to the input of the three-input XOR gate; the output of each node of the ring Boolean network structure is connected to the input of the four-input XOR gate; the output of the four-input XOR gate is sampled The modules are connected to perform the sampling and quantization process;
(2)采样模块包括D触发器和反相器构成的双采样结构，其中D触发器分为两级，每级两个；反相器也为两个；熵源模块两路输出分别经第一级的两个D触发器进行量化，两个第一级D触发器的时钟端分别连接有一个时钟模块；两个第一级D触发器的信号输出端分别接入第二级D触发器中的其中一个，同时两个第一级D触发器的信号输出端各通过一个反相器后接入第二级另一个D触发器时钟端，作为第二级D触发器的时钟信号输入；第二级D触发器输出端共同连接有二输入异或门，二输入异或门的输出与异或逻辑门输入端相连接；异或逻辑门输出与元胞状态机的输入端相连接；(2) The sampling module includes a double sampling structure composed of a D flip-flop and an inverter, where the D flip-flop is divided into two stages, two in each stage; the inverter is also two; the two outputs of the entropy source module are respectively Two D flip-flops in one stage are used for quantification. The clock ends of the two first-stage D flip-flops are respectively connected to a clock module; the signal output ends of the two first-stage D flip-flops are respectively connected to the second-stage D flip-flops. One of them, at the same time, the signal output ends of the two first-stage D flip-flops are connected to the clock stage of the other D-flip-flop of the second stage after passing through an inverter, respectively, as the clock signal input of the second-stage D-flip-flop; The two-stage D flip-flop output terminal is commonly connected with a two-input XOR gate, and the output of the two-input XOR gate is connected to the XOR logic gate input terminal; the XOR logic gate output is connected to the cell state machine input terminal;
(3)元胞状态机是由四个不同逻辑电路组成的后处理模块，由多路选择控制器选择不同后处理；(3) Cell state machine is a post-processing module composed of four different logic circuits, and different post-processing is selected by the multi-channel selection controller;
(4)元胞状态机的信号输出端与测试模块的信号输入端相连接；测试模块的信号输出端与CPU的信号输入端相连接；(4) The signal output of the cell state machine is connected to the signal input of the test module; the signal output of the test module is connected to the signal input of the CPU;
(5)CPU信号输出端与异或逻辑门信号输入端相连接；(5) The CPU signal output is connected to the XOR logic gate signal input;
(6)选择控制器为四路选择控制器，选择控制器信号输入端与CPU信号输出端相连接，选择控制器信号输出端与元胞状态机的信号输入端相连接，以接收CPU发送的控制信号，并分别对元胞状态机四路逻辑电路进行开关控制。(6) The selection controller is a four-way selection controller. The signal input terminal of the selection controller is connected to the signal output terminal of the CPU, and the signal output terminal of the selection controller is connected to the signal input terminal of the cellular state machine to receive the signals sent by the CPU. Control signals, and switch the four logic circuits of the cellular state machine.
所述随机数产生方法及装置熵源模块和采样模块全部由数字逻辑门组成，电路结构简单易集成，并且功耗很低，可兼容各种不同的可编程逻辑电路。The random number generating method and device, the entropy source module and the sampling module are all composed of digital logic gates, the circuit structure is simple and easy to integrate, and the power consumption is very low, which is compatible with various programmable logic circuits.
所述随机数产生方法及装置可实现在线检测，能输出通过测试的高质 量随机序列，可广泛应用在保密通信等信息安全领域。The random number generating method and device can realize online detection, can output a high-quality random sequence that passes the test, and can be widely used in information security fields such as confidential communication.
所述熵采样模块由D触发器和反相器构成双采样结构实现，D触发器存在时钟信号输入端连接外部时钟信号，双采样结构能提高序列频率的同时增大序列混乱性。The entropy sampling module is implemented by a double sampling structure composed of a D flip-flop and an inverter. The D flip-flop has a clock signal input terminal connected to an external clock signal, and the double sampling structure can increase sequence frequency and increase sequence chaos.
本发明所提供的一种具有检测校正功能的真随机数产生方法及装置，其优点在于：The invention provides a method and a device for generating a true random number with a detection and correction function, which have the following advantages:
第一，所产生的随机数序列不存在周期性，通过调节时钟频率即可产生0～1Gbit/s可以通过国际随机数行业测试标准(NIST和Diehard统计测试)的具有良好随机特性的随机数。First, the generated random number sequence does not have periodicity. By adjusting the clock frequency, random numbers of 0 to 1 Gbit / s that can pass international random number industry test standards (NIST and Diehard statistical tests) and have good random characteristics can be generated.
第二，***全部采用异或非门和异或门等逻辑门构成环状拓扑结构，作为熵源，相对于全部采用三输入异或非门和异或门构成的熵源，克服了三输入异或非门和异或门构成的熵源的结构缺陷，无布尔固定点。能够以较少节点数产生混沌信号，且具有更高的频率和更低功耗。Second, the system uses logical gates such as XOR gates and XOR gates to form a ring topology. As an entropy source, the three-input XOR gate and XOR gates are used to overcome the three-input entropy source. The structural defects of the entropy source formed by the XOR gate and XOR gate have no Boolean fixed point. It can generate chaotic signals with fewer nodes, and has higher frequency and lower power consumption.
第三，***所述熵采样模块(200)由D触发器和反相器构成双采样结构实现，D触发器存在时钟信号输入端连接外部时钟信号，双采样结构能提高序列频率的同时增大序列混乱性。，由于熵源模块(100)没有时钟信号驱动，所以存在不满足D触发器采样量化的建立和保持时间的事件，导致出现亚稳态，进一步增加了***的随机性。Third, the entropy sampling module (200) of the system is implemented by a dual sampling structure composed of a D flip-flop and an inverter. The D flip-flop has a clock signal input terminal connected to an external clock signal. The dual sampling structure can increase the sequence frequency and increase at the same time. Sequence chaos. Because the entropy source module (100) is not driven by a clock signal, there are events that do not meet the setup and hold times of the D-flip-flop sampling quantization, resulting in the occurrence of a metastable state, which further increases the randomness of the system.
第四，***全部采用数字逻辑门，电路结构简单，可兼容各种不同的可编程逻辑电路，具有普遍的适用性和灵活性。Fourth, the system adopts digital logic gates, the circuit structure is simple, it can be compatible with various programmable logic circuits, and it has universal applicability and flexibility.
第五，该随机数产生方法及装置可实现集成化小型化，可广泛应用在保密通信等信息安全领域。Fifth, the random number generating method and device can realize integration and miniaturization, and can be widely used in information security fields such as confidential communication.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1是本发明专利的电路结构框图。FIG. 1 is a block diagram of a circuit structure of the patent of the present invention.
100：熵源模块；200：采样模块；300：异或逻辑门；400：元胞状态机；500：测试模块；600：CPU；700：选择控制器。100: entropy source module; 200: sampling module; 300: XOR logic gate; 400: cell state machine; 500: test module; 600: CPU; 700: select controller.
图2为熵源模块电路结构图。FIG. 2 is a circuit structure diagram of an entropy source module.
201：D触发器；202：反相器；203：二输入异或门；204：时钟模块。图3为本发明采样模块电路图。201: D flip-flop; 202: inverter; 203: two-input XOR gate; 204: clock module. FIG. 3 is a circuit diagram of a sampling module according to the present invention.
图4为本发明熵源模块与采样模块电路结构图。FIG. 4 is a circuit structure diagram of an entropy source module and a sampling module according to the present invention.
图5为本发明元胞状态机内不同后处理结构图。FIG. 5 is a diagram of different post-processing structures in a cell state machine according to the present invention.
图6为多路选择控制器结构框图。Fig. 6 is a structural block diagram of a multi-channel selection controller.
具体实施方式Detailed ways
本发明提供一种具有检测校正功能的真随机数产生方法，其结构框图如图1所示。主要由熵源模块100、采样模块200、异或逻辑门300、元胞状态机400、测试模块500、CPU600和选择控制器700组成。The invention provides a method for generating a true random number with a detection and correction function. The structure block diagram is shown in FIG. 1. It is mainly composed of an entropy source module 100, a sampling module 200, an exclusive OR logic gate 300, a cell state machine 400, a test module 500, a CPU 600, and a selection controller 700.
所述熵源模块100如图2所示，是由两块完全相同的振荡器结构组成，该振荡器是一种基于自治布尔网络的混沌振荡器结构。该布尔网络由三个二输入异或门101(1011、1012、1013、1014)、一个三输入异或非门102、一个非门103和一个四输入异或门104组成。三个二输入异或门101和一个三输入异或非门102与相邻逻辑门首尾相连构成环形布尔网络结构，一个非门103输入输出自相连构成环形振荡器，并将反相器103输出与三输入异或非门102输入端相连。环形网络结构每个节点输出均与四输入异或门104输入端连接。利用反相器103构成的振荡环结构产生高频周期信号，对布尔网络结构进行多次重复起振，不断破坏结构中存在的固定点，使熵源模块能够不断产生高质量混沌信号。四输入异或门104的输出端与采样模块200相连接，进行采样量化过程。As shown in FIG. 2, the entropy source module 100 is composed of two identical oscillator structures. The oscillator is a chaotic oscillator structure based on an autonomous Boolean network. The Boolean network consists of three two-input XOR gates 101 (1011, 1012, 1013, 1014), a three-input XOR gate 102, an NOT gate 103, and a four-input XOR gate 104. Three two-input XOR gates 101 and one three-input XOR gate 102 are connected end-to-end with adjacent logic gates to form a ring Boolean network structure. The input and output of one NOT gate 103 are connected to form a ring oscillator, and the inverter 103 is output. Connected to the input terminal of the three-input XOR gate 102. The output of each node of the ring network structure is connected to the input of the four-input XOR gate 104. The high-frequency periodic signal is generated by the oscillating ring structure formed by the inverter 103, and the Boolean network structure is repeatedly repeatedly vibrated, constantly destroying the fixed points existing in the structure, so that the entropy source module can continuously generate high-quality chaotic signals. The output of the four-input XOR gate 104 is connected to the sampling module 200 to perform a sampling and quantization process.
采样模块200如图3所示，为D触发器和反相器构成的双采样结构，熵源模块两路输出分别经第一级D触发器(2011和2013)进行量化，时钟采用外部时钟，可通过调节外部时钟来调节随机数速率，外部时钟频率不超过1GHz/s。两路D触发器量化后序列分别接入下一级D触发器(2012和2014)，并将序列取反后接入另一D触发器时钟端，作为时钟信号输入，也就是D触发器2011输出与D触发器2012相连接，D触发器2013输出与D触发器2014相连接；同时D触发器2011输出通过反相器2022与D触发器2014相连接，D触发器2013输出通过反相器2021与D触发器2012相连接。将两级D触发器采样后的随机序列输入至二输入异或门203进行异或处理，输出量化采样序列，之后再输入至异或逻辑门300。The sampling module 200 is a dual sampling structure composed of a D flip-flop and an inverter. The two outputs of the entropy source module are quantized by the first-stage D flip-flops (2011 and 2013) respectively. The random number rate can be adjusted by adjusting the external clock, and the external clock frequency does not exceed 1GHz / s. The quantized sequences of the two D flip-flops are respectively connected to the next D flip-flops (2012 and 2014), and the sequence is inverted and connected to the other D flip-flop clock end as the clock signal input, which is the D flip-flop 2011. The output is connected to D flip-flop 2012, the output of D flip-flop 2013 is connected to D flip-flop 2014; at the same time, the output of D flip-flop 2011 is connected to D flip-flop 2014 through inverter 2022, and the output of D flip-flop 2013 is connected to inverter 2021 is connected to the D flip-flop 2012. The random sequence sampled by the two-stage D flip-flop is input to the two-input XOR gate 203 for XOR processing, and a quantized sampling sequence is output, and then input to the XOR logic gate 300.
元胞状态机400是由四个不同逻辑电路组成的后处理模块，如图5所 示。f1、f2、f3、f4分别为四种不同局部定义，本例中可选择与(AND)、或(OR)、与非(NAND)、或非(NOR)。由多路选择控制器选择不同后处理，提高随机序列质量，增大随机序列的随机性。 Cell state machine 400 is a post-processing module composed of four different logic circuits, as shown in FIG. 5. f1, f2, f3, f4 are four different local definitions. In this example, you can choose AND, OR, OR, NAND, or NOR. The multi-path selection controller selects different post-processing to improve the quality of the random sequence and increase the randomness of the random sequence.
测试模块500对随机序列进行频数检验、游程检验、块内最长游程检验、离散傅里叶变换检验，并将检验结果发送到CPU。The test module 500 performs a frequency test, a run test, a longest run test within a block, and a discrete Fourier transform test on the random sequence, and sends the test result to the CPU.
CPU600对检验结果进行判断，若通过测试则直接输出随机序列；若未通过测试，则将数据重新返回。The CPU 600 judges the inspection result, and directly outputs a random sequence if it passes the test; if it fails, it returns the data again.
选择控制器700为四路选择控制器，由CPU600发送控制信号，分别对元胞状态机400四路逻辑电路进行开关控制。The selection controller 700 is a four-way selection controller, and a control signal is sent by the CPU 600 to switch control the four logic circuits of the cellular state machine 400 respectively.
以上实施实例仅用具体实施说明本发明的基本原理和实现结构，在此基础上还可以做出若干改进和润饰，这种基于本发明的改进和润饰均包含在本发明的保护范围之内。The above implementation examples only use specific implementations to explain the basic principle and implementation structure of the present invention. On this basis, several improvements and retouches can be made. Such improvements and retouches based on the present invention are all included in the protection scope of the present invention.

Claims (5)

  1. 一种具有检测校正功能的真随机数产生方法，其特征在于，采用如下结构实现：所述结构包括熵源模块(100)、采样模块(200)、异或逻辑门(300)、元胞状态机(400)、测试模块(500)、CPU(600)和选择控制器(700)；A method for generating a true random number with a detection and correction function is characterized in that it is implemented with the following structure: the structure includes an entropy source module (100), a sampling module (200), an exclusive OR logic gate (300), and a cell state Machine (400), test module (500), CPU (600), and selection controller (700);
    (1)所述熵源模块(100)是由两块完全相同的振荡器结构组成，该振荡器是一种基于自治布尔网络的混沌振荡器结构；所述自治布尔网络由三个二输入异或门(101)、一个三输入异或非门(102)、一个非门(103)和一个四输入异或门(104)组成；三个二输入异或门(101)和一个三输入异或非门(102)首尾相连构成环形布尔网络结构，一个非门(103)输入输出自相连构成环形振荡器，并将非门(103)输出与三输入异或非门(102)输入端相连；环形自治布尔网络结构每个节点输出均与四输入异或门(104)输入端连接；利用非门(103)构成的振荡环结构产生高频周期信号，对环形自治布尔网络结构进行多次重复起振，不断破坏结构中存在的固定点，使熵源模块(100)能够不断产生高质量混沌信号；四输入异或门(104)的输出端与采样模块(200)相连接，进行采样量化过程；(1) The entropy source module (100) is composed of two identical oscillator structures, which is a chaotic oscillator structure based on an autonomous Boolean network; the autonomous Boolean network consists of three two-input different The OR gate (101), a three-input XOR gate (102), a NOT gate (103), and a four-input XOR gate (104); three two-input XOR gates (101), and a three-input XOR gate. The NOR gate (102) is connected end to end to form a ring Boolean network structure. The input and output of a NOR gate (103) are self-connected to form a ring oscillator, and the output of the NOR gate (103) is connected to the input of the three-input XOR gate (102). ; Each node output of the ring autonomous Boolean network structure is connected to the input end of the four-input XOR gate (104); the oscillation ring structure formed by the NOT gate (103) is used to generate high-frequency periodic signals, and the ring autonomous Boolean network structure is performed multiple times Repeated vibrations continuously destroy fixed points existing in the structure, so that the entropy source module (100) can continuously generate high-quality chaotic signals; the output of the four-input XOR gate (104) is connected to the sampling module (200) for sampling Quantification process
    (2)采样模块(200)包括D触发器和反相器构成的双采样结构，其中D触发器分为两级，每级两个；反相器也为两个；熵源模块(100)两路输出分别经第一级的两个D触发器进行量化，时钟采用外部时钟，可通过调节外部时钟来调节随机数速率；经两个第一级D触发器量化后的两路随机序列分别接入第二级D触发器其中一个，同时将第一级D触发器量化后的两路随机序列各通过一个反相器取反后接入第二级另一D触发器时钟端，作为时钟信号输入；将第二级D触发器采样后的随机序列进行异或处理，后输入异或逻辑门(300)，与返回数据进行异或，并向元胞状态机(400)输出量化采样序列；(2) The sampling module (200) includes a dual sampling structure composed of a D flip-flop and an inverter, where the D flip-flop is divided into two stages, two in each stage; the inverter is also two; the entropy source module (100) The two outputs are quantized by two first-stage D flip-flops respectively. The clock is an external clock, and the random number rate can be adjusted by adjusting the external clock; the two random sequences quantized by two first-stage D flip-flops are respectively One of the second-stage D flip-flops is connected, and the two random sequences quantized by the first-stage D flip-flop are each inverted by an inverter and then connected to the other D-flip-flop clock of the second stage as a clock. Signal input; XOR the random sequence sampled by the second-stage D flip-flop, and then input the XOR logic gate (300) to XOR with the returned data, and output the quantized sampling sequence to the cell state machine (400) ;
    (3)元胞状态机(400)是由四个不同逻辑电路组成的后处理模块，由多路选择控制器(700)选择不同后处理，提高随机序列质量，增大随机序列的随机性；(3) The cell state machine (400) is a post-processing module composed of four different logic circuits. The multi-path selection controller (700) selects different post-processing to improve the quality of the random sequence and increase the randomness of the random sequence;
    (4)测试模块(500)在相应软件的支持下对元胞状态机(400)发送的随机序列进行频数检验、游程检验、块内最长游程检验、离散傅里叶变换检验，并将检验结果发送到CPU(600)；(4) The test module (500), with the support of the corresponding software, performs a frequency check, a run length test, a longest run length test within the block, a discrete Fourier transform test on the random sequence sent by the cell state machine (400), and performs the test. The result is sent to the CPU (600);
    (5)CPU(600)对检验结果进行判断，若通过测试则直接输出随机序列；若未通过测试，则将数据重新返回异或逻辑门(300)；(5) The CPU (600) judges the inspection result, and outputs a random sequence directly if it passes the test; if it fails, it returns the data to the exclusive-OR logic gate (300);
    (6)选择控制器(700)为四路选择控制器，由CPU(600)发送控制信号，分别对元胞状态机(400)四路逻辑电路进行开关控制。(6) The selection controller (700) is a four-way selection controller. The CPU (600) sends control signals to switch control the four logic circuits of the cell state machine (400), respectively.
  2. 如权利要求1所述的一种具有检测校正功能的真随机数产生方法，其特征在于打破二输入布尔网络固定点的限制，减少节点个数，产生高质量随机序列；所述第一级D触发器的时钟由外部时钟提供，时钟信号≤1GHz。The method for generating a true random number with a detection and correction function according to claim 1, characterized in that the limitation of fixed points of a two-input Boolean network is broken, the number of nodes is reduced, and a high-quality random sequence is generated; The clock of the trigger is provided by an external clock, and the clock signal is ≤1GHz.
  3. 如权利要求1或2所述的一种具有检测校正功能的真随机数产生方法，其特征在于，能够在线检测随机数序列的质量，并能够对未通过测试的随机数进行后处理，提高随机性，使其通过测试。The method for generating a true random number with a detection and correction function according to claim 1 or 2, characterized in that the quality of the random number sequence can be detected online, and random numbers that fail the test can be post-processed to improve randomness. Sex to make it pass the test.
  4. 一种具有检测校正功能的真随机数产生装置，用于实现如权利要求1所述的方法，其特征在于，所述装置包括熵源模块(100)、采样模块(200)、异或逻辑门(300)、元胞状态机(400)、测试模块(500)、CPU(600)和选择控制器(700)；A true random number generating device with a detection and correction function, used to implement the method according to claim 1, wherein the device comprises an entropy source module (100), a sampling module (200), and an exclusive-OR logic gate. (300), a cell state machine (400), a test module (500), a CPU (600), and a selection controller (700);
    所述熵源模块(100)是由两块完全相同的振荡器结构组成，该振荡器是一种基于自治布尔网络的混沌振荡器结构；所述自治布尔网络由三个二输入异或门(101)、一个三输入异或非门(102)、一个非门(103)和一个四输入异或门(104)组成；三个二输入异或门(101)和一个三输入异或非门(102)首尾相连构成环形布尔网络结构，一个非门(103)输入输出自相连构成环形振荡器，并将非门(103)输出与三输入异或非门(102)输入端相连；环形布尔网络结构每个节点输出均与四输入异或门(104)输入端连接；四输入异或门(104)的输出端与采样模块(200)相连接，进行采样量化过程；The entropy source module (100) is composed of two identical oscillator structures. The oscillator is a chaotic oscillator structure based on an autonomous Boolean network. The autonomous Boolean network consists of three two-input XOR gates ( 101), a three-input XOR gate (102), a NOT gate (103), and a four-input XOR gate (104); three two-input XOR gates (101), and a three-input XOR gate (102) End-to-end is connected to form a ring Boolean network structure. The input and output of an NOT gate (103) are self-connected to form a ring oscillator, and the output of the NOT gate (103) is connected to the input of the three-input XOR gate (102). The output of each node of the network structure is connected to the input of the four-input XOR gate (104); the output of the four-input XOR gate (104) is connected to the sampling module (200) to perform the sampling and quantization process;
    采样模块(200)包括D触发器和反相器构成的双采样结构，其中D触发器分为两级，每级两个；反相器也为两个；熵源模块(100)两路输出分别经第一级的两个D触发器进行量化，两个第一级D触发器的时钟端分别 连接有一个时钟模块(204)；两个第一级D触发器的信号输出端分别接入第二级D触发器中的其中一个，同时两个第一级D触发器的信号输出端各通过一个反相器后接入第二级另一个D触发器时钟端，作为第二级D触发器的时钟信号输入；第二级D触发器输出端共同连接有二输入异或门(203)，二输入异或门(203)的输出与异或逻辑门(300)输入端相连接；异或逻辑门(300)输出与元胞状态机(400)的输入端相连接；The sampling module (200) includes a dual sampling structure composed of a D flip-flop and an inverter, where the D flip-flop is divided into two stages, two each; the inverter is also two; the entropy source module (100) has two outputs The two first-stage D flip-flops are used for quantification. The clock ends of the two first-stage D flip-flops are respectively connected with a clock module (204); the signal outputs of the two first-stage D flip-flops are connected respectively. One of the second-stage D flip-flops, while the signal output terminals of the two first-stage D flip-flops each pass through an inverter and connected to the second-stage D-d flip-flop clock terminal as the second-stage D-trigger Clock signal input of the transmitter; the two-stage D flip-flop output terminal is commonly connected with a two-input XOR gate (203), and the output of the two-input XOR gate (203) is connected with the XOR logic gate (300) input terminal; The output of the OR gate (300) is connected to the input of the cellular state machine (400);
    元胞状态机(400)是由四个不同逻辑电路组成的后处理模块，由多路选择控制器(700)选择不同后处理；The cell state machine (400) is a post-processing module composed of four different logic circuits, and different post-processing is selected by a multiplex selection controller (700);
    元胞状态机(400)的信号输出端与测试模块(500)的信号输入端相连接；测试模块(500)的信号输出端与CPU(600)的信号输入端相连接；The signal output terminal of the cellular state machine (400) is connected to the signal input terminal of the test module (500); the signal output terminal of the test module (500) is connected to the signal input terminal of the CPU (600);
    CPU(600)信号输出端与异或逻辑门(300)信号输入端相连接；The CPU (600) signal output terminal is connected to the XOR logic gate (300) signal input terminal;
    选择控制器(700)为四路选择控制器，选择控制器(700)信号输入端与CPU(600)信号输出端相连接，选择控制器(700)信号输出端与元胞状态机(400)的信号输入端相连接，以接收CPU(600)发送的控制信号，并分别对元胞状态机(400)四路逻辑电路进行开关控制。The selection controller (700) is a four-way selection controller. The signal input terminal of the selection controller (700) is connected to the signal output terminal of the CPU (600). The signal output terminal of the selection controller (700) is connected to the cell state machine (400). The signal input terminals are connected to receive control signals sent by the CPU (600), and switch control the four logic circuits of the cellular state machine (400) respectively.
  5. 如权利要求4所述的一种具有检测校正功能的真随机数产生装置，其特征在于，时钟模块(204)由外部时钟提供，时钟信号≤1GHz。The device for generating true random numbers with a detection and correction function according to claim 4, wherein the clock module (204) is provided by an external clock, and the clock signal is ≤1 GHz.
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