CN116880801B - Dual-entropy source physical random number generator - Google Patents
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Abstract
The invention relates to the technical field of information security, in particular to a dual-entropy source physical random number generation methodA device for solving the technical problems in the background technology, which comprises two exclusive-or units XOR 1 Sum XOR (exclusive OR) 2 An exclusive nor unit XNOR 0 The clock generation module, the double-edge D trigger and the post-processing unit; exclusive or unit XOR 1 The device consists of a first exclusive-OR gate, four delay units and two multiplexers; exclusive or unit XOR 2 The device consists of a second exclusive-OR gate, four delay units and two multiplexers; exclusive nor unit XNOR 0 The invention can realize two completely different entropy source modes by adjusting control signals, realizes mutually independent dual-entropy source random number generators, has simple structure and easy integration, and has great practical significance.
Description
Technical Field
The invention relates to the technical field of information security, in particular to a dual-entropy source physical random number generator.
Background
Random numbers are important applications in the fields of authentication, analog computation, and information security. In particular, in the field of information security, a random number is used as a key to encrypt information, so that unpredictable random numbers are key to ensuring information security.
Currently, random numbers are largely classified into pseudo random numbers and physical random numbers according to the generation method. The security of pseudo-random numbers depends on the complexity of the algorithm and will be predictable once the algorithm is breached. The physical random number extracts a random process in the nature to generate an unpredictable random number, namely a true random number. Most of the existing true random number generation methods sample and quantify a single entropy source, cannot meet the requirements of mutually independent multi-entropy sources in a password chip, and are not safe enough, complex in structure and difficult to integrate.
Therefore, the true random number generation method and technology which have simple structure, easy integration, strong portability and capability of generating the dual entropy sources are provided by the application and have great practical significance
Disclosure of Invention
In order to overcome the technical defects that the prior true random number generation method mostly carries out sampling quantization on a single entropy source and cannot meet the requirements of mutually independent multi-entropy sources in a password chip and has low safety, the invention provides a dual-entropy-source physical random number generator.
The invention discloses a dual-entropy source physical random number generator, which comprises two exclusive-or units XOR 1 Sum XOR (exclusive OR) 2 An exclusive nor unit XNOR 0 Clock generation module, double-edge D trigger and post-processing unit；
Exclusive or unit XOR 1 The device consists of a first exclusive-OR gate, four delay units and two multiplexers, wherein the first delay unit and the second delay unit are respectively connected to the input ends of the first multiplexers, and the input ends of the first delay unit and the second delay unit are connected in parallel and then serve as exclusive-OR units XOR 1 The output end of the first multiplexer is connected to one input end of the first exclusive-OR gate, the third delay unit and the fourth delay unit are respectively connected to the input end of the second multiplexer, the output end of the second multiplexer is connected to the other input end of the first exclusive-OR gate, and the input ends of the third delay unit and the fourth delay unit are connected in parallel and then serve as an exclusive-OR unit XOR 1 The output end of the first exclusive OR gate is an exclusive OR unit XOR 1 An output terminal of (a);
exclusive or unit XOR 2 The device consists of a second exclusive-OR gate, four delay units and two multiplexers, wherein a fifth delay unit and a sixth delay unit are respectively connected to the input end of the third multiplexer, and the input ends of the fifth delay unit and the sixth delay unit are connected in parallel and then serve as an exclusive-OR unit XOR 2 The output end of the third multiplexer is connected to one input end of the second exclusive-OR gate, the seventh delay unit and the eighth delay unit are respectively connected to the input end of the fourth multiplexer, the output end of the fourth multiplexer is connected to the other input end of the second exclusive-OR gate, and the input ends of the seventh delay unit and the eighth delay unit are connected in parallel and then serve as an exclusive-OR unit XOR 2 The output end of the second exclusive OR gate is an exclusive OR unit XOR 2 An output terminal of (a);
exclusive nor unit XNOR 0 The output ends of the ninth delay unit and the tenth delay unit are respectively connected to the input ends of the fifth multiplexer, and the input ends of the ninth delay unit and the tenth delay unit are connected in parallel and then used as an exclusive-or NOT unit XNOR 0 The output end of the fifth multiplexer is connected to one input end of the exclusive OR gate, and the outputs of the eleventh delay unit and the twelfth delay unitThe input ends of the eleventh delay unit and the twelfth delay unit are connected in parallel and then used as exclusive-or non-unit XNOR 0 The output end of the sixth multiplexer is connected to the other input end of the exclusive-or gate, the output end of the exclusive-or gate is the exclusive-or unit XNOR 0 An output terminal of (a);
the delay of the first delay unit, the third delay unit, the fifth delay unit and the seventh delay unit are equal, the delay of the ninth delay unit and the eleventh delay unit are equal, and the first delay unit, the third delay unit, the fifth delay unit, the seventh delay unit, the ninth delay unit and the eleventh delay unit form a symmetrical circuit; the second delay unit, the fourth delay unit, the sixth delay unit, the eighth delay unit, the tenth delay unit and the twelfth delay unit form an asymmetric circuit in different delays;
exclusive or unit XOR 1 Exclusive or unit XOR 2 Sum exclusive-or not unit XNOR 0 Two inputs of any one unit are respectively from the outputs of the other two units, exclusive or unit XOR 1 Or exclusive or unit XOR 2 Is connected as an output of the entropy source to the data input of the double-edge D flip-flop, exclusive-or not unit XNOR 0 The output end of the double-edge D trigger is connected to a post-processing unit, and the post-processing unit outputs a random number;
the control ends of the first multiplexer, the second multiplexer, the third multiplexer, the fourth multiplexer, the fifth multiplexer, the sixth multiplexer and the seventh multiplexer are respectively connected with the same control signal.
In the dual-entropy source physical random number generator, an entropy source is formed by an exclusive-or unit XOR 1 Exclusive or unit XOR 2 Sum exclusive-or not unit XNOR 0 Mutually coupled components, exclusive-or units XOR 1 And exclusive or unit XOR 2 The structure is consistent. The control signal is used for controlling each multipleThe circuit selector works in a metastable state or a chaotic state, the metastable state is the control signal when the control signal is 0, and the chaotic state is the control signal when the control signal is 1.
When the control signal is 0, the entropy source operates in a metastable entropy source mode, i.e. exclusive-or unit XOR 1 And exclusive or unit XOR 2 Operating in a metastable state, in an exclusive-or not unit XNOR 0 Metastability can occur on both the rising and falling edges of the output signal. When the control signal is 1, the entropy source works in a chaotic entropy source mode, and the exclusive or unit XOR 1 Exclusive or unit XOR 2 Sum exclusive-or not unit XNOR 0 The chaotic signal can be output.
The dual-edge D trigger can quantize the output of the entropy source, and when the control signal is 0, the clock end of the dual-edge D trigger and the exclusive-or NOT unit XNOR 0 The D trigger is connected with the metastable state entropy source, and performs non-periodic sampling to sample the output of the metastable state entropy source; when the control signal is 1, the clock end is connected with the clock generating module, the clock generating module generates a 50MHz clock signal, and the double-edge D trigger periodically samples the output of the chaotic entropy source to generate 100 Mbit/s random numbers. The method and the device realize that the entropy sources work in different entropy source modes through the control signals. The random number generated by the dual-edge D trigger is processed by a post-processing module to obtain high-quality random number output, and the post-processing module can use the prior art such as Hash function post-processing or Von Neumann post-processing.
Compared with the prior art, the technical scheme provided by the invention has the following advantages: the dual-entropy source physical random number generator can enable the same structure to achieve two completely different entropy source modes, namely a metastable entropy source and a chaotic entropy source through adjusting control signals, the principles of the two entropy sources are completely different, the dual-entropy source random number generator independent of each other is achieved, the structure is simple, integration is easy, and the dual-entropy source physical random number generator has great practical significance.
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The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a block diagram of a dual entropy source physical random number generator according to the present invention;
FIG. 2 shows an exclusive OR unit XOR according to the present invention 1 Is a structural schematic diagram of (a);
FIG. 3 shows an exclusive OR unit XOR according to the present invention 2 Is a structural schematic diagram of (a);
FIG. 4 shows an exclusive OR unit XNOR according to the present invention 0 Is a schematic structural diagram of the (c).
In the figure: 1. a clock generation module; 2. a dual edge D flip-flop; 3. a post-processing unit; 4. a first exclusive-or gate; 5. a second exclusive-or gate; 6. an exclusive nor gate; 7. a control signal; 101. a first delay unit; 102. a second delay unit; 103. a third delay unit; 104. a fourth delay unit; 105. a fifth delay unit; 106. a sixth delay unit; 107. a seventh delay unit; 108. an eighth delay unit; 109. a ninth delay unit; 110. a tenth delay unit; 111. an eleventh delay unit; 112. a twelfth delay unit; 11. a first multiplexer; 12. a second multiplexer; 13. a third multiplexer; 14. a fourth multiplexer; 15. a fifth multiplexer; 16. a sixth multiplexer; 17. and a seventh multiplexer.
Detailed Description
In order that the above objects, features and advantages of the invention will be more clearly understood, a further description of the invention will be made. It should be noted that, without conflict, the embodiments of the present invention and features in the embodiments may be combined with each other.
In the description, it should be noted that the terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. It should be noted that, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms described above will be understood by those of ordinary skill in the art as the case may be.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced otherwise than as described herein; it will be apparent that the embodiments in the specification are only some, but not all, embodiments of the invention.
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
In one embodiment, as shown in FIG. 1, a dual entropy source physical random number generator is disclosed, comprising two exclusive-or units XOR 1 Sum XOR (exclusive OR) 2 An exclusive nor unit XNOR 0 The clock generation module 1, the double-edge D trigger 2 and the post-processing unit 3;
exclusive or unit XOR 1 The first delay unit 101 and the second delay unit 102 are respectively connected to the input end of the first multiplexer 11, and the input ends of the first delay unit 101 and the second delay unit 102 are connected in parallel and then used as exclusive-or units XOR 1 The output end of the first multiplexer 11 is connected to one input end of the first exclusive-or gate 4, the third delay unit 103 and the fourth delay unit 104 are respectively connected to the input end of the second multiplexer 12, the output end of the second multiplexer 12 is connected to the other input end of the first exclusive-or gate 4, and the input ends of the third delay unit 103 and the fourth delay unit 104 are connected in parallel and then serve as exclusive-or units XOR 1 The output end of the first exclusive or gate 4 is an exclusive or unit XOR 1 An output terminal of (a);
exclusive or unit XOR 2 By a second exclusive-or gate 5, four delay units and two multiplexer groupsThe fifth delay unit 105 and the sixth delay unit 106 are respectively connected to the input end of the third multiplexer 13, and the input ends of the fifth delay unit 105 and the sixth delay unit 106 are connected in parallel and then serve as an exclusive-or unit XOR 2 The output end of the third multiplexer 13 is connected to one input end of the second exclusive-OR gate 5, the seventh delay unit 107 and the eighth delay unit 108 are respectively connected to the input end of the fourth multiplexer 14, the output end of the fourth multiplexer 14 is connected to the other input end of the second exclusive-OR gate 5, and the input ends of the seventh delay unit 107 and the eighth delay unit 108 are connected in parallel and then serve as exclusive-OR units XOR 2 The output end of the second exclusive-or gate 5 is an exclusive-or unit XOR 2 An output terminal of (a);
exclusive nor unit XNOR 0 The output ends of the ninth delay unit 109 and the tenth delay unit 110 are respectively connected to the input end of the fifth multiplexer 15, and the input ends of the ninth delay unit 109 and the tenth delay unit 110 are connected in parallel and then used as an exclusive-or non-unit XNOR 0 The output end of the fifth multiplexer 15 is connected to one input end of the exclusive-or gate 6, the output ends of the eleventh delay unit 111 and the twelfth delay unit 112 are respectively connected to the input end of the sixth multiplexer 16, and the input ends of the eleventh delay unit 111 and the twelfth delay unit 112 are connected in parallel and then serve as an exclusive-or unit XNOR 0 The output end of the sixth multiplexer 16 is connected to the other input end of the exclusive-or gate 6, and the output end of the exclusive-or gate 6 is the exclusive-or unit XNOR 0 An output terminal of (a);
the delays of the first delay unit 101, the third delay unit 103, the fifth delay unit 105 and the seventh delay unit 107 are equal, the delays of the ninth delay unit 109 and the eleventh delay unit 111 are equal, and the first delay unit 101, the third delay unit 103, the fifth delay unit 105, the seventh delay unit 107, the ninth delay unit 109 and the eleventh delay unit 111 form a symmetrical circuit; the delays of the second delay unit 102, the fourth delay unit 104, the sixth delay unit 106, the eighth delay unit 108, the tenth delay unit 110 and the twelfth delay unit 112 are different from each other to form an asymmetric circuit;
exclusive or unit XOR 1 Exclusive or unit XOR 2 Sum exclusive-or not unit XNOR 0 Two inputs of any one unit are respectively from the outputs of the other two units, exclusive or unit XOR 1 Or exclusive or unit XOR 2 Is connected as an output of the entropy source to the data input of the double-edge D flip-flop 2, exclusive-or not unit XNOR 0 The output end of the clock generation module 1 is connected to the other input end of the seventh multiplexer 17, the output end of the double-edge D trigger 2 is connected to the post-processing unit 3, and the post-processing unit 3 outputs random numbers;
the control terminals of the first multiplexer 11, the second multiplexer 12, the third multiplexer 13, the fourth multiplexer 14, the fifth multiplexer 15, the sixth multiplexer 16 and the seventh multiplexer 17 are connected to the same control signal 7, respectively.
In which, in particular, the exclusive-or units XOR 1 The first delay unit 101 of (a) is connected to the 0 terminal of the first multiplexer 11, the second delay unit 102 is connected to the 1 terminal of the first multiplexer 11, the third delay unit 103 is connected to the 0 terminal of the second multiplexer 12, and the fourth delay unit 104 is connected to the 1 terminal of the second multiplexer 12. Exclusive or unit XOR 2 The fifth delay unit 105 of (a) is connected to the 0 terminal of the third multiplexer 13, the sixth delay unit 106 is connected to the 1 terminal of the third multiplexer 13, the seventh delay unit 107 is connected to the 0 terminal of the fourth multiplexer 14, and the eighth delay unit 108 is connected to the 1 terminal of the fourth multiplexer 14. Exclusive nor unit XNOR 0 The ninth delay unit 109 of (a) is connected to the 0 terminal of the fifth multiplexer 15, the tenth delay unit 110 is connected to the 1 terminal of the fifth multiplexer 15, the eleventh delay unit 111 is connected to the 0 terminal of the sixth multiplexer 16, and the twelfth delay unit 112 is connected to the 1 terminal of the sixth multiplexer 16. Exclusive nor unit XNOR 0 The output of the clock generation module 1 is connected to the 0 terminal of the seventh multiplexer 17 and the output of the clock generation module 1 is connected to the 1 terminal of the seventh multiplexer 17.
Wherein the exclusive-or unit XOR 1 Exclusive or unit XOR 2 Sum exclusive-or not unit XNOR 0 Two inputs of any one of the units respectively coming from outputs of the other two units, e.g. exclusive-or units XOR 1 The outputs of (2) can be respectively connected to exclusive-or units XOR 2 Is not in exclusive nor unit XNOR 0 Is exclusive-or unit XOR 2 The outputs of (2) can be respectively connected to exclusive-or units XOR 1 Is not in exclusive nor unit XNOR 0 Is not equal to the second input of the exclusive nor unit XNOR 0 The outputs of (2) can be respectively connected to exclusive-or units XOR 1 Is connected to the second input of the exclusive-or unit XOR 2 Is provided. The connection mode is only one of the connection modes, and other connection modes can be adopted, so long as two inputs of any one unit are respectively output from the other two units.
In the dual-entropy source physical random number generator, an entropy source is formed by an exclusive-or unit XOR 1 Exclusive or unit XOR 2 Sum exclusive-or not unit XNOR 0 Mutually coupled components, exclusive-or units XOR 1 And exclusive or unit XOR 2 The structure is consistent. The control signal 7 is used for controlling each multiplexer to work in a metastable state or a chaotic state, the metastable state is the control signal 7 when the control signal 7 is 0, and the chaotic state is the control signal 7 when the control signal 7 is 1.
When the control signal 7 is 0, the entropy source operates in a metastable entropy source mode, i.e. exclusive-or unit XOR 1 And exclusive or unit XOR 2 Operating in a metastable state, in an exclusive-or not unit XNOR 0 Metastability can occur on both the rising and falling edges of the output signal. When the control signal 7 is 1, the entropy source operates in a chaotic entropy source mode, and the exclusive-or unit XOR 1 Exclusive or unit XOR 2 Sum exclusive-or not unit XNOR 0 The chaotic signal can be output.
The dual-edge D flip-flop 2 can quantize the output of the entropy source, and when the control signal 7 is 0, the clock end of the dual-edge D flip-flop 2 and the exclusive-or NOT unit XNOR 0 The D trigger is connected with the metastable state entropy source, and performs non-periodic sampling to sample the output of the metastable state entropy source; when (when)The control signal 7 is 1, the clock end is connected with the clock generation module 1, the clock generation module 1 generates a 50MHz clock signal, and the double-edge D trigger 2 periodically samples the output of the chaotic entropy source to generate 100 Mbit/s random numbers. The application realizes that the entropy sources work in different entropy source modes through the control signal 7. The random number generated by the dual-edge D flip-flop 2 is processed by a post-processing module to obtain a high-quality random number output, and the post-processing module can use the prior art such as hash function post-processing or von neumann post-processing.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Although described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the embodiments, and they should be construed as covering the scope of the appended claims.
Claims (1)
1. A dual-entropy source physical random number generator is characterized by comprising two exclusive-or units XOR 1 Sum XOR (exclusive OR) 2 An exclusive nor unit XNOR 0 The clock generation module (1), the double-edge D trigger (2) and the post-processing unit (3);
exclusive or unit XOR 1 Consists of a first exclusive-OR gate (4), four delay units and two multiplexers, wherein the first delay unit (101) and the second delay unit (102) are respectively connected to the input end of the first multiplexer (11), and the input ends of the first delay unit (101) and the second delay unit (102) are connected in parallel and then used as an exclusive-OR unit XOR 1 The output end of the first multiplexer (11) is connected to one input end of the first exclusive-OR gate (4), the third delay unit (103) and the fourth delay unit (104) are respectively connected to the input end of the second multiplexer (12), the output end of the second multiplexer (12) is connected to the other input end of the first exclusive-OR gate (4), and the inputs of the third delay unit (103) and the fourth delay unit (104)The parallel terminals are used as exclusive-or units XOR 1 The output end of the first exclusive OR gate (4) is an exclusive OR unit XOR 1 An output terminal of (a);
exclusive or unit XOR 2 Consists of a second exclusive-OR gate (5), four delay units and two multiplexers, wherein a fifth delay unit (105) and a sixth delay unit (106) are respectively connected to the input end of a third multiplexer (13), and the input ends of the fifth delay unit (105) and the sixth delay unit (106) are connected in parallel and then used as an exclusive-OR unit XOR 2 The output end of the third multiplexer (13) is connected to one input end of the second exclusive-OR gate (5), the seventh delay unit (107) and the eighth delay unit (108) are respectively connected to the input end of the fourth multiplexer (14), the output end of the fourth multiplexer (14) is connected to the other input end of the second exclusive-OR gate (5), and the input ends of the seventh delay unit (107) and the eighth delay unit (108) are connected in parallel and then used as an exclusive-OR unit XOR 2 The output end of the second exclusive OR gate (5) is an exclusive OR unit XOR 2 An output terminal of (a);
exclusive nor unit XNOR 0 The output ends of the ninth delay unit (109) and the tenth delay unit (110) are respectively connected to the input end of the fifth multiplexer (15), and the input ends of the ninth delay unit (109) and the tenth delay unit (110) are connected in parallel and then used as an exclusive or non-unit XNOR 0 The output end of the fifth multiplexer (15) is connected to one input end of the exclusive-or gate (6), the output ends of the eleventh delay unit (111) and the twelfth delay unit (112) are respectively connected to the input end of the sixth multiplexer (16), and the input ends of the eleventh delay unit (111) and the twelfth delay unit (112) are connected in parallel and then used as an exclusive-or non-unit XNOR 0 The output end of the sixth multiplexer (16) is connected to the other input end of the exclusive-or gate (6), the output end of the exclusive-or gate (6) is the exclusive-or unit XNOR 0 An output terminal of (a);
the delay of the first delay unit (101), the third delay unit (103), the fifth delay unit (105) and the seventh delay unit (107) are equal, the delay of the ninth delay unit (109) and the eleventh delay unit (111) are equal, and the first delay unit (101), the third delay unit (103), the fifth delay unit (105), the seventh delay unit (107), the ninth delay unit (109) and the eleventh delay unit (111) form a symmetrical circuit; the second delay unit (102), the fourth delay unit (104), the sixth delay unit (106), the eighth delay unit (108), the tenth delay unit (110) and the twelfth delay unit (112) form an asymmetric circuit in different delays;
exclusive or unit XOR 1 Exclusive or unit XOR 2 Sum exclusive-or not unit XNOR 0 Two inputs of any one unit are respectively from the outputs of the other two units, exclusive or unit XOR 1 Or exclusive or unit XOR 2 Is connected as an output of the entropy source to the data input of the double-edge D flip-flop (2), exclusive-or not unit XNOR 0 The output end of the double-edge D trigger (2) is connected to the post-processing unit (3), and the post-processing unit (3) outputs random numbers;
the control ends of the first multiplexer (11), the second multiplexer (12), the third multiplexer (13), the fourth multiplexer (14), the fifth multiplexer (15), the sixth multiplexer (16) and the seventh multiplexer (17) are respectively connected with the same control signal (7).
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| CN110750233A (en) * | 2019-09-19 | 2020-02-04 | 太原理工大学 | Random number generator based on two-input two-output logic gate asymmetric autonomous Boolean network |
| CN113672199A (en) * | 2021-08-27 | 2021-11-19 | 太原理工大学 | Multi-entropy source random number generator with physical unclonable function |
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