CN114902174A - Reconfigurable random number generator and implementation method thereof - Google Patents
Reconfigurable random number generator and implementation method thereof Download PDFInfo
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Abstract
A reconfigurable random number generator and a realization method thereof are provided, the generator comprises at least two ring oscillators, a sampling circuit, a counter and a logic control unit, the control end of the corresponding selector in each inverter group is electrically connected with the logic control unit and is used for receiving the reconfiguration signal of the logic control unit and completing the conduction of an electric signal channel between the appointed inverter in each inverter group and the selectors at the two sides of the designated inverter group; the output ends of the at least two ring oscillators are coupled with the input end of the counter; the output end of the counter is connected with the logic control unit; the sampling circuit obtains a sampled electrical signal from the at least two ring oscillators so as to output a random number based on the sampled electrical signal. The generator can improve the adaptability to the environment, and the performance of the circuit is optimal in the aspects of power consumption, area, efficiency of generating random numbers and the like.
Description
The invention relates to the technical field of random number generators, in particular to a reconfigurable random number generator and an implementation method thereof.
Random numbers are widely applied to the fields of engineering technology and scientific research such as cryptography, Monte Carlo simulation, spread spectrum communication, statistical research, artificial intelligence, neural networks and the like. Especially in the field of cryptography, according to Shannon Theory, the whole system will be absolutely secure and indecipherable, as long as it is guaranteed that the random number (key) used is completely random and of the same length as the information to be encrypted and is used once. Therefore, how to generate safe and reliable random numbers is of great significance to the whole cryptosystem, and further to national defense safety, financial development, social stability and private privacy of China.
At present, in the field of CMOS integrated circuits, true random number generators can be mainly classified into four types according to the difference of entropy sources: 1. based on ambient noise; 2. based on a chaotic model; 3. based on clock jitter; 4. a metastable circuit based true random number generator. First, the first type of thermal noise is a good source of random entropy because its spectral distribution is relatively uniform and does not vary with CMOS processes. In early integrated circuits, this approach was mostly used to extract random numbers. However, thermal noise is difficult to obtain, often requiring an ultra wide bandwidth, high gain amplifier to amplify the noise, and difficult to achieve quantization. The second type of chaos system equation based on deterministic description generates random numbers, which have long-term unpredictability due to the extreme sensitivity to initial conditions. However, the high-entropy true random number generator generally has a large area and power consumption due to the implementation of the chaotic map. The third type is to generate true random numbers using dithering (jitter) of a Ring Oscillator (Ring Oscillator, abbreviated as RO). The method has the advantages of being convenient and flexible to realize on an FPGA or an ASIC. The principle is to sample a fast jittered clock with a clock of slow jittering frequency. The fourth category is that the broadband amplifier has large resource consumption and power consumption. Secondly, latches in a metastable state or Static Random Access Memory (SRAM) can also be used to generate true random numbers, however, the true random generator of the entropy source typically requires a complex post-processing unit.
As a random number generator widely used in the industry, although a ring oscillator-based random number generator has the advantages of easy implementation and small area, the mechanism is susceptible to process variations, temperature and voltage variations (PVT), which causes bias in random number output and affects entropy.
In view of the above, overcoming the drawbacks of the prior art is an urgent problem in the art.
[ summary of the invention ]
The technical problem to be solved by the embodiment of the invention is that although the random number generator based on the ring oscillator in the prior art has the advantages of easy implementation, small area and the like, the mechanism is easily influenced by process differences, temperature and voltage changes, so that the random number output is biased, and the entropy value is influenced.
The embodiment of the invention adopts the following technical scheme:
in a first aspect, the present invention provides a reconfigurable random number generator, including at least two ring oscillators, a sampling circuit, a counter, and a logic control unit, specifically:
the ring oscillator comprises n inverter groups, each inverter group is composed of at least two inverters arranged in parallel and two selectors arranged on the input side and the output side of the inverters respectively; wherein n is a natural number;
the control end of the corresponding selector in each inverter group is electrically connected with the logic control unit and is used for receiving the reconstruction signal of the logic control unit and completing the conduction of the electric signal channel between the appointed inverter in each inverter group and the selectors on the two sides of the appointed inverter;
the output ends of the at least two ring oscillators are coupled with the input end of the counter; the output end of the counter is connected with the logic control unit; the sampling circuit acquires sampled electrical signals from the at least two ring oscillators so as to output random numbers according to the sampled electrical signals.
Preferably, the logic control unit obtains the difference between the oscillation frequencies of the at least two ring oscillators through the counter, and is configured to send a reconstruction signal to each selector in the ring oscillators, so that the difference between the oscillation frequencies of the ring oscillators is smaller than a preset threshold by adjusting the inverters selected to pass through in the inverter group.
Preferably, the output terminals of the at least two ring oscillators are coupled to the input terminal of the counter, and specifically include:
the output ends of the at least two ring oscillators are respectively connected with different input ports of the counter, so that the counter can count the oscillation frequencies corresponding to the different ring oscillators; or,
the output ends of the at least two ring oscillators are connected with at least two input ends of the counting selector, the output end of the counting selector is connected with the input end of the counter, so that the logic control unit controls the corresponding relation between the input end and the output end of the counting selector, and the ring oscillators are sequentially counted according to the oscillating frequency.
Preferably, the ring oscillator further includes a nand gate, and a cascade is formed between inverter groups in the ring oscillator, specifically:
the first input end of the NAND gate is connected with an enable signal; the second input end of the NAND gate is connected with the output port of the inverter group at the tail end of the cascade; and the output end of the NAND gate is used for being connected with the input port of the inverter group positioned at the cascade header.
Preferably, in the random number generator, a random number source is formed by a first ring oscillator and a second ring oscillator, and the sampling circuit is formed by n D flip-flops, specifically:
the output end of each inverter group in the first ring oscillator is also connected with a signal input port of a D trigger;
the output end of each inverter group in the second ring oscillator is also connected with a clock input port of a D trigger;
the electric signals of the output ports of the n D triggers in the sampling circuit form a random number.
Preferably, the ring oscillator further includes m general inverters, specifically:
the m common inverters and the n inverter groups are cascaded according to a preset arrangement sequence;
wherein, the preset arrangement sequence comprises:
the m ordinary inverters are cascaded, and the n inverter groups are cascaded; the m common inverters after the cascade connection and the n inverters after the cascade connection are connected in series; or,
cascading the ordinary inverters and the inverter groups at intervals, wherein the distance of the intervals is determined according to the proportional relation between the m ordinary inverters and the n inverter groups; or,
and the cascade connection of the common inverters and the inverter groups is completed between the m common inverters and the n inverter groups according to a random sequencing mode.
Preferably, the random number generator comprises a random number source composed of a third ring oscillator and a fourth ring oscillator, the sampling circuit comprises p D flip-flops, where n is equal to or greater than p is equal to or less than m + n, specifically:
the output end of a designated inverter and/or an inverter group in the third ring oscillator is also respectively connected with a signal input port of a D trigger;
the output end of the appointed inverter group and/or inverter in the fourth ring oscillator is also respectively connected with a clock input port of a D flip-flop;
the electric signals of the output ports of the n D triggers in the sampling circuit form a random number.
Preferably, when the random number generator operates in the physical unclonable function mode, the logic control unit is further configured to obtain excitation signals of one or more ring oscillators, specifically:
the logic control unit converts the excitation signal into a reconstructed signal of the corresponding one or more ring oscillators;
and the logic control unit acquires the output oscillation frequency of one or more ring oscillators triggered by the excitation signal and calculates and obtains a physical unclonable output result according to the corresponding oscillation frequency or the difference value of the oscillation frequencies.
Preferably, the excitation signal of the ring oscillator is specifically a data source for a specified inverter group output in the ring oscillator as a result of calculating the physical unclonable output.
Preferably, the calculating according to the corresponding oscillation frequency or the difference between the oscillation frequencies to obtain the physical unclonable output result specifically includes:
if the difference of the oscillation frequencies is larger than 0, outputting 0, and if the difference of the oscillation frequencies is smaller than 0, outputting 1; or,
if the difference of the oscillation frequencies is larger than 0, outputting 1, and if the difference of the oscillation frequencies is smaller than 0, outputting 0; or,
and taking the designated length parameter value after the oscillation frequency decimal point as an integral value to be output.
Preferably, the inverter is one or more of a TTL inverter, a CMOS inverter, an HPM disturb effect inverter, or a starvation inverter.
Preferably, when the at least two ring oscillators include a first ring oscillator, a second ring oscillator, and a third ring oscillator,
the first ring oscillator and the second ring oscillator form a random number source, and the second ring oscillator and the third ring oscillator form a random number source; or,
the first ring oscillator and the third ring oscillator form a random number source, and the second ring oscillator and the third ring oscillator form a random number source; or,
the first ring oscillator and the second ring oscillator form a random number source, and the first ring oscillator and the third ring oscillator form a random number source.
In a second aspect, the present invention provides a method for implementing a reconfigurable random number generator, using the reconfigurable random number generator according to the first aspect, the method comprising:
the logic control unit acquires the oscillation frequency of the at least two ring oscillators through the counter;
the logic control unit determines a first ring oscillator and a second ring oscillator which are used as a random number source, and analyzes the difference value of the oscillation frequency of the first ring oscillator and the second ring oscillator;
if the oscillation frequency is greater than a preset threshold value, the logic control unit sends a reconstruction signal to the first ring oscillator and/or the second ring oscillator so as to control selectors in the first ring oscillator and the second ring oscillator and complete the conduction operation of a designated inverter signal channel in a corresponding inverter group;
and adjusting the reconstruction signal by the logic control unit one or more times to enable the difference value of the oscillation frequencies of the first ring oscillator and the second ring oscillator to be smaller than a preset threshold value.
Preferably, the adjusting, by the one or more times logic control unit, the reconstruction signal so that the oscillation frequency difference between the first ring oscillator and the second ring oscillator is smaller than a preset threshold specifically includes:
through adjusting the reconstruction signal for many times, the traversal of the selection control of the inverters used for electric signal conduction in each inverter group is completed one by one;
if the difference value of the oscillation frequencies of the first ring oscillator and the second ring oscillator can be reduced in each adjustment of the reconstruction signal, the reconstruction signal at the moment is kept as the reconstruction signal in the current state, the oscillation frequency difference corresponding to the reconstruction signal in the current state is used for comparing with the oscillation frequency difference under the reconstruction signal after the next adjustment, and the reconstruction signal with the smaller oscillation frequency difference is taken to be updated as the reconstruction signal in the current state;
and stopping the traversal process until the difference value of the oscillation frequencies of the first ring oscillator and the second ring oscillator is smaller than a preset threshold value.
Preferably, when a third ring oscillator is further included, and the first ring oscillator and the third ring oscillator constitute another random number source, the method further includes:
after the one or more times of adjustment of the logic control unit on the reconstruction signal is completed, so that the difference value of the oscillation frequencies of the first ring oscillator and the second ring oscillator is smaller than a preset threshold value, the one or more times of adjustment of the logic control unit on the reconstruction signal of the third ring oscillator is performed, so that the difference value of the oscillation frequencies of the first ring oscillator and the third ring oscillator is smaller than the preset threshold value.
Compared with the prior art, the embodiment of the invention has the beneficial effects that:
the reconfigurable ring oscillator provided by the invention can realize the calculation of the oscillation frequency difference between output signals of different ring oscillators through the counter, transmit the result to the logic control unit, and further adjust the phase inverter group in the associated ring oscillator based on the logic control unit, thereby obtaining the output of the ring oscillator meeting the conditions.
Further, in a preferred implementation of the present invention, a solution for realizing a physical unclonable output result based on the reconfigurable ring oscillator is also provided, and the solution implementation still depends on the core innovation points of the present invention, namely, the inverter group structure, and the reconfiguration control of each inverter group in the ring oscillator by the logic control unit.
In the invention, the reconfigurable function of each inverter group can keep the difference of the oscillation frequencies of the output data of at least two ring oscillators for outputting random numbers within a preset threshold value, thereby reducing the bias for generating random sequences, improving the adaptability to the environment, and optimizing the performance of the circuit in the aspects of power consumption, area, efficiency for generating random numbers and the like.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a reconfigurable random number generator according to an embodiment of the present invention;
FIG. 2 is a block diagram of an inverter group of a reconfigurable random number generator according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an operating state structure of an inverter group in the reconfigurable random number generator according to the embodiment of the present invention;
FIG. 4 is a schematic diagram of an operating state structure of an inverter group in the reconfigurable random number generator according to the embodiment of the present invention;
FIG. 5 is a schematic diagram of an alternate reconfigurable random number generator architecture provided by embodiments of the present invention;
FIG. 6 is a schematic diagram of an alternative reconfigurable random number generator architecture provided by embodiments of the present invention;
FIG. 7 is a schematic diagram of a ring oscillator according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of another ring oscillator according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of an alternative reconfigurable random number generator architecture provided by embodiments of the present invention;
FIG. 10 is a schematic diagram of yet another reconfigurable random number generator architecture provided by an embodiment of the present invention;
FIG. 11 is a flow chart illustrating a method for implementing a reconfigurable random number generator according to an embodiment of the present invention;
FIG. 12 is a flow chart illustrating a method for implementing a reconfigurable random number generator according to an embodiment of the present invention;
FIG. 13 is a flow chart illustrating a method for implementing a reconfigurable random number generator according to an embodiment of the present invention;
FIG. 14 is a block diagram of a specific reconfigurable random number generator according to an embodiment of the present invention;
FIG. 15 is a schematic diagram of a current starved inverter according to an embodiment of the present invention;
FIG. 16 is a diagram of a D flip-flop according to an embodiment of the present invention;
FIG. 17 is a timing diagram of a D flip-flop according to an embodiment of the present invention;
fig. 18 is a flowchart illustrating a method for performing reconstructed signal locking according to an embodiment of the present invention.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the description of the present invention, the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "top", "bottom", and the like indicate orientations or positional relationships based on those shown in the drawings, and are for convenience only to describe the present invention without requiring the present invention to be necessarily constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1:
the ring oscillator includes n inverter groups each of which is composed of at least two inverters arranged in parallel, and two selectors respectively arranged on an input side (i.e., a left side of the inverters arranged in parallel as shown in fig. 2) and an output side (i.e., a right side of the inverters arranged in parallel as shown in fig. 2) of the inverters, as shown in fig. 2; wherein n is a natural number. The n has a certain correlation with the actual random number to be generated, and in general, the larger the number of the random number is, the larger the value of the corresponding n will be.
Here, the parallel inverters are described to mean a technique that selectors disposed at both sides of the inverters selectively turn on at least two parallel inverters to conduct an electric signal path, and in an inverter group, the other inverters are in a state of blocking the electric signal path with respect to the electric signal conducting inverter because the selectors disposed before and after the corresponding inverter do not designate an interface connected thereto to be turned on.
And the control end of the corresponding selector in each inverter group is electrically connected with the logic control unit and is used for receiving the reconstruction signal of the logic control unit and completing the conduction of the electric signal channel between the appointed inverter in each inverter group and the selectors on the two sides of the appointed inverter. For example, in the inverter group shown in fig. 3, the inverter with the reference number 1 is selected to enter the electrical channel conducting state by the control of the selector, and the other inverters with the reference numbers 2-x are in the electrical channel blocking state; as shown in fig. 4, the inverter group selects the inverter numbered 2 to enter the electrical channel conducting state and the other inverters numbered 1, 3-x to be in the electrical channel blocking state through the control of the selector. It should be noted that, in the embodiment of the present invention, the control function of the selector is a technical content that has already been matured in the field, and the innovation point of the present invention is to use the control function into the technical solution of the overall structure set forth in the embodiment of the present invention.
The output ends of the at least two ring oscillators are coupled with the input end of the counter; the output end of the counter is connected with the logic control unit; the sampling circuit obtains a sampled electrical signal from the at least two ring oscillators so as to output a random number based on the sampled electrical signal.
The reconfigurable ring oscillator provided by the embodiment of the invention can realize the calculation of the oscillation frequency difference between output signals of different ring oscillators through the counter, transmit the calculation as a result to the logic control unit, and further adjust the associated inverter group (which can be understood as a control signal for outputting a random number) in the ring oscillator based on the logic control unit, thereby obtaining the output of the ring oscillator meeting the condition.
In the embodiment of the invention, the reconfigurable function of each inverter group can keep the difference of the oscillation frequencies of the output data of at least two ring oscillators for outputting random numbers within a preset threshold value, thereby reducing the bias for generating random sequences, improving the adaptability to the environment, and optimizing the performance of the circuit in the aspects of power consumption, area, efficiency for generating random numbers and the like.
In the embodiment of the present invention, the logic control unit obtains the oscillation frequency difference between the at least two ring oscillators through the counter, and is configured to send a reconstruction signal to each selector in the ring oscillator (the reconstruction signal is used to select gating of parallel inverters configured in each inverter group, and when more than 2 inverters are provided for a single inverter group, the reconstruction signal sent to each inverter group should be greater than 1bit), so as to adjust the inverters selected to pass through in the inverter group to complete that the oscillation frequency difference between the ring oscillators is smaller than a preset threshold or a minimum value in a range. The preset threshold is an empirical value, and can be verified by testing the repeatability of the random number, and the obtained oscillation frequency difference value can be set as a parameter value of the preset threshold when the repeatability of the random number meets the specified requirement. In particular, it can be verified in the early stage that the random number generated within the range of the frequency difference between the two inverters can pass the random number standard test (for example, NIST random number test standard).
In the embodiment of the present invention, the implementation manner of coupling the output terminals of the at least two ring oscillators and the input terminal of the counter may be various, for example: the counter itself includes a plurality of counting input ports, similar to the connection structure shown in fig. 1, the counter can simultaneously count the output oscillation frequencies of at least two ring oscillators, and the output ends of the at least two ring oscillators are respectively connected to different input ports of the counter, so that the counter can count the oscillation frequencies corresponding to different ring oscillators; in practical applications, the number of counters does not directly correspond to the output of the random numbers to be generated, and a counter (as shown in fig. 1) may be provided for each output of the random numbers, or only one counter may be used for a plurality of random numbers when the counter is strong enough. While as a more practical cost solution, the corresponding counter is more apt to be a single count input port device, there is another possible solution, as shown in fig. 5, which specifically includes:
the output ends of the at least two ring oscillators are connected with at least two input ends of the counting selector, the output end of the counting selector is connected with the input end of the counter, so that the logic control unit controls the corresponding relation between the input end and the output end of the counting selector, and the ring oscillators are sequentially counted according to the oscillating frequency.
As shown in fig. 1 and fig. 5, in order to perform enable control of a ring oscillator, a nand gate is usually further disposed on an input port side of the ring oscillator, and a cascade connection mode is formed between inverter groups in the ring oscillator, specifically:
the first input end of the NAND gate is connected with an enable signal; the second input end of the nand gate is connected with the output port of the inverter group at the end of the cascade (for example, the inverter group at the rightmost side in fig. 5); the output of the nand gate is used to connect to the input port of the inverter group located at the cascade header (e.g., the leftmost inverter group in fig. 5).
In the embodiment of the present invention, a random number source is formed by a first ring oscillator and a second ring oscillator in the random number generator, and the sampling circuit is formed by n D flip-flops, as shown in fig. 6, specifically:
the output end of each inverter group in the first ring oscillator is also connected with a signal input port of a D trigger; the output end of each inverter group in the second ring oscillator is also connected with a clock input port of a D trigger; the electric signals of the output ports of the n D triggers in the sampling circuit form a random number.
In a specific implementation manner of the present invention, in addition to the implementation manner of cascading by a single inverter group similar to the example of fig. 1, fig. 5, and fig. 6, an embodiment of the present invention further provides an implementation manner of a ring oscillator similar to that shown in fig. 7 and fig. 8, where the ring oscillator further includes m general inverters (i.e., in fig. 8 and fig. 7, the general inverters cascaded with the inverter group) specifically:
the m common inverters and the n inverter groups are cascaded according to a preset arrangement sequence;
wherein, the preset arrangement sequence comprises:
in a first way, as shown in fig. 7, the m ordinary inverters are cascaded, and the n inverter groups are cascaded; and completing the cascade connection between the m ordinary inverters after the cascade connection and the n inverters after the cascade connection.
In the second mode, as shown in fig. 8, the normal inverters and the inverter groups are cascaded in a mutually spaced manner, wherein the mutual spacing distance is determined according to the proportional relationship between the m normal inverters and the n inverter groups. It should be noted that m and n are both natural numbers, and the values of n and n corresponding to fig. 5 may be adjusted according to the requirements of the respective application scenarios, and do not necessarily indicate that the values of the two in the respective scenarios need to be consistent.
And thirdly, between the m ordinary inverters and the n inverter groups, completing the cascade connection of the ordinary inverters and the inverter groups according to a random sequencing mode. It should be noted that, the regular mutual interval cascade formation structure of the second three-phase comparison mode is not set according to a specified rule, and the third mode can bring more possibilities from certain implementation possibilities, which can be understood as further weakening uncertainty in the process of manufacturing by the random sorting mode, so that a ring oscillator with oscillation frequency characteristics exceeding the regular mutual interval arrangement can be found in the later test process. The random ordering is relative to a designed circuit, and for the manufactured reconfigurable random number generator, the arrangement relation between the inverter group in the corresponding ring oscillator and the common inverter is a determined relation.
Aiming at the above proposed structure of introducing a common inverter into the cascade structure of the inverter group to form a composite cascade structure, therefore, a random number source is formed by a third ring oscillator and a fourth ring oscillator in the random number generator, the random number generator further comprises a sampling circuit, wherein the sampling circuit is formed by p D flip-flops, wherein n is not less than p is not less than m + n, as shown in fig. 9, specifically:
the output end of a designated inverter and/or an inverter group in the third ring oscillator is also respectively connected with a signal input port of a D trigger; the output end of the appointed inverter group and/or inverter in the fourth ring oscillator is also respectively connected with a clock input port of a D flip-flop; the electric signals of the output ports of the n D triggers in the sampling circuit form a random number. As can be seen from fig. 9, the structure adopts an implementation manner that p is equal to n, that is, the output port of each inverter group is still used to extract an electrical signal as a basis for generating a random number; and for an implementation where p ═ m + n, reference may be made to the structure shown in fig. 10. It should be noted that the structure similar to that shown in fig. 9 and fig. 10 is only made to present a key difference structure through the simplest illustration, and a feasible scheme is made, the structure similar to that shown in fig. 9 and fig. 10 may add a nand gate to the above-mentioned extension scheme to complete the enable signal control, or may also adopt a single input port counter extension implementation scheme similar to that shown in fig. 5, so that the alternatives proposed in the extension schemes in the embodiments of the present invention may be organically combined in the implementations of the present invention, which is not described in detail herein.
It should be further explained that the first, second, third and fourth designations used in the embodiments of the present invention are only for convenience of description and are also intended to distinguish between the objects and individuals described, and besides, they are not intended to be limited in any way, and should not be construed to limit the scope of the present invention.
As a new information security mechanism, physically unclonable Functions (hereinafter, referred to as "PUFs") have attracted much attention from the industry and have been industrially applied. The physical unclonable function can be widely applied to security authentication and key generation mechanisms, can resist various physical attacks including invasive attacks, and has the advantages of low cost and high security.
In fact, the industry began to integrate true random number generators and physical unclonable function modules as independent circuits in one chip as the security base of security modules, such as the security chip "ChipDNA" by the american letter corporation (Maxim).
The reconfigurable random number generator can be further multiplexed into a physical unclonable function, circuit multiplexing is realized, and resources are saved; the invention can carry out reconstruction processing on the ring oscillators, and is used for adjusting the relative frequency of the two ring oscillators, removing the inherent bias caused by deterministic noise (such as manufacturing difference) or PVT (physical verification test), thereby ensuring the randomness of the output random number. On the other hand, when the reconfigurable random number generator provided by the embodiment of the invention is further multiplexed into a physical unclonable function, specifically:
the logic control unit is also used for acquiring excitation signals of one or more ring oscillators (for example, the excitation signals of one or more ring oscillators are directly input to the logic control unit through an upper computer, the excitation signals can be represented as selection of work output of a designated reflector group in each ring oscillator, so that the combination form of the reflector groups working in the ring oscillators can be dynamically changed by adjusting the excitation signals to enable the ring oscillators to meet the requirements of specific environments), and the logic control unit converts the excitation signals into reconstruction signals of the corresponding one or more ring oscillators;
and the logic control unit acquires the output oscillation frequency of one or more ring oscillators triggered by the excitation signal and calculates and obtains a physical unclonable output result according to the corresponding oscillation frequency or the difference value of the oscillation frequencies.
In the above preferred implementation of the present invention, a solution for achieving a physical unclonable output result based on the reconfigurable ring oscillator is proposed, and the solution implementation still depends on the core innovation points of the present invention, namely, the inverter group structure, and the reconfiguration control of each inverter group in the ring oscillator by the logic control unit.
In a specific implementation process, in order to meet a physical unclonable output result requirement meeting an expected requirement, a counter and a logic control unit are usually matched to complete reconstruction of each inverter group in the ring oscillator, so that the difference between the oscillation frequencies of the two ring oscillators forming the oscillation frequency difference is preferably large. The reason is that, at this time, the relative frequency difference is not derived from the jitter but from a fixed factor such as a manufacturing difference. Thus, the characteristics of the Physically Unclonable Function (PUF) circuit are now met. For a 64-stage reconfigurable ring oscillator (i.e., comprising 64 inverter groups), the configuration signals are combined to 2 64 Inside is provided withThe fixed output generated by the configuration signal of the fixed output can be used for mechanisms such as key generation.
And according to the corresponding oscillation frequency or the difference value of the oscillation frequency, calculating to obtain a physical unclonable output result, which specifically comprises the following steps:
if the difference of the oscillation frequencies is larger than 0, outputting 0, and if the difference of the oscillation frequencies is smaller than 0, outputting 1; or,
if the difference value of the oscillation frequencies is larger than 0, outputting 1, and if the difference value of the oscillation frequencies is smaller than 0, outputting 0; or,
and taking the designated length parameter value after the oscillation frequency decimal point as an integral value to be output.
As a more complete implementation of the present invention, as shown in FIG. 11, the process of the method aggregates a true random number pattern and a physical unclonable pattern, and can select between the two working patterns during the implementation of a particular method. As shown in fig. 11, the corresponding method process includes:
in step 101, the logic control unit performs frequency statistics on at least two ring oscillators through a counter to obtain a frequency difference. At this time, according to the operation mode set in the logic control unit, if the operation mode is a true random number mode, the process proceeds to step 102, and if the operation mode is a physical unclonable mode, the process proceeds to step 104.
In step 102, the logic control unit adjusts the reconfiguration signal one or more times to gate different inverters, so that the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator is smaller than a preset threshold.
In step 103, oscillator jitter caused by phase noise of the two ring oscillators is sampled to generate random numbers.
In step 104, the multiple-time logic control unit adjusts the reconstruction signal to gate different inverters, so as to obtain the oscillation frequency or the frequency difference of the ring oscillator each time.
In step 105, a physical unclonable output result is calculated according to the corresponding oscillation frequency or the difference of the oscillation frequencies.
The specific method procedures in each mode will be specifically described in embodiment 2, and are not described in detail in the embodiments of the present invention.
Example 2:
the embodiment of the invention provides an implementation method of a reconfigurable random number generator, which uses the reconfigurable random number generator in the embodiment 1, and as shown in fig. 12, the implementation method comprises the following steps:
in step 201, the logic control unit obtains the oscillation frequencies of the at least two ring oscillators through the counter.
In step 202, the logic control unit determines a first ring oscillator and a second ring oscillator as a source of random numbers and analyzes a difference in oscillation frequency between the first ring oscillator and the second ring oscillator.
In step 203, if the oscillation frequency is greater than the preset threshold, the logic control unit sends a reconfiguration signal to the first ring oscillator and/or the second ring oscillator so as to control a selector in the first ring oscillator and the second ring oscillator to complete a conduction operation of a designated inverter signal channel in a corresponding inverter group.
In step 204, the logic control unit adjusts the reconfiguration signal one or more times so that the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator is smaller than a preset threshold.
The reconfigurable ring oscillator implementation method provided by the embodiment of the invention can realize the calculation of the oscillation frequency difference between output signals of different ring oscillators through the counter, transmit the result to the logic control unit, and further adjust the associated inverter group in the ring oscillator based on the logic control unit, thereby obtaining the ring oscillator output meeting the conditions.
With reference to the embodiment of the present invention, for the adjustment of the reconfiguration signal by the one or more logic control units, so that the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator is smaller than the preset threshold, as shown in fig. 12, the method specifically includes:
in step 2041, the selective control of the inverters for electrical signal conduction in each inverter group is traversed one by adjusting the reconstruction signal multiple times.
In step 2042, each time the reconstruction signal is adjusted, if the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator can be caused to decrease, the reconstruction signal at this time is kept as the reconstruction signal in the current state, and the oscillation frequency difference corresponding to the reconstruction signal in the current state is used for comparing with the oscillation frequency difference under the reconstruction signal after the next adjustment, and the reconstruction signal with the smaller oscillation frequency difference is updated to the reconstruction signal in the current state.
In step 2043, the traversal process is stopped until the difference between the oscillation frequencies of the first and second ring oscillators is less than a preset threshold.
It should be noted that, because the contents of information interaction, execution process, and the like between the modules and units in the device are based on the same concept as the processing method embodiment of the present invention, specific contents may refer to the description in the method embodiment of the present invention, and are not described herein again.
Example 3:
on the basis of the embodiment 1 and the embodiment 2, the embodiment of the invention will further explain details of the implementation process of the complete scheme by combining an example situation in a specific implementation process and a corresponding figure. Compared with the structure that at least two inverters are adopted to form the inverter group in the embodiment 1, the current starvation type inverters are further adopted to form the corresponding inverter group in the embodiment of the invention, so that the performance is further improved.
The configurable random number generator circuit configuration is shown in FIG. 14. It mainly comprises two ring oscillators (ring oscillator RO1 and ring oscillator RO2), a counter, a set of D flip-flops, and a parallel-to-serial interface circuit (it can be seen that the parallel-to-serial interface circuit is not directly introduced in the implementation of embodiment 1, because, as an alternative implementation, the parallel-to-serial interface circuit is electrically connectedThe path is not necessarily realized by integrating the technical solutions of the embodiments of the present invention, and may also be realized by combining with peripheral circuits), and a set of control logic (C) 0 ～C 2n-1 ，EN…)。
The control logic is responsible for the conversion of the operating mode of the ring oscillator. The reconfigurable random number generator in the embodiment of the invention has two working modes: a random number generator schema and a physical unclonable function schema.
As shown in fig. 14, two ring oscillators RO1, RO2 each consist of 1 NAND gate (NAND1, NAND2) and n inverter groups (IVs0 to IVsn-1, IVsn to IVs2 n-1); each inverter group is composed of a multiplexer (an arbitrary multiplexer is taken as an example in the figure) and a current starved inverter, and can be based on the reconstructed signal (C) 0 ～C 2n-1 ) Reconstructing to reduce the influence of process deviation, voltage variation and temperature variation (PVT) on the circuit and ensure the high entropy of the random number generator and the high reliability of the physical unclonable function circuit; n D flip-flops (D) 0 ～D n-1 ) Forming a sampling circuit, sampling oscillator jitter caused by phase noise of the two ring oscillators, and generating random numbers; the counting selection circuit is used for detecting the working state of the ring oscillator in a random number generator mode and generating a physical unclonable function output in a physical unclonable function mode; the logic control unit is used for configuring the circuit working state (random number mode or physical unclonable function mode) and reconstructing a signal (C) according to the output of the counting circuit 0 ～C 2n-1 ) And reconstructing the ring oscillator. Through the logic processing control circuit, the two reconfigurable current starvation type ring oscillators can be used as a high-entropy random number generator or a physical unclonable function. The parallel-serial port output circuit is used for outputting the random number generated by the random number generator in a serial mode.
In a true random number operating mode, the dither noise of two current starvation type ring oscillators operating in a subthreshold interval are mutually sampled to generate a high entropy random number. Wherein the current starvation typeThe ring oscillator works in a subthreshold region, noise of each stage of the current starvation type ring oscillator is larger, and entropy of generated random numbers is higher; in addition, the working current of the phase inverter can be conveniently controlled when the ring oscillator works in the subthreshold region, so that the charging and discharging time of the phase inverter is controlled, the frequency of the ring oscillator is controlled, and meanwhile, the power consumption of the ring oscillator is controlled and reduced. The random number generation process is as follows: sub-threshold region ring oscillator can reconstruct signal C through reconstruction 0 ～C 2n-1 Reconstruction inverter group (IVs) 0 ～IVs n-1 ，IVs n ～IVs 2n-1 ) Thereby selecting different current starved inverters to form the oscillator, and further adjusting the oscillation frequency f of the ring oscillator RO1 ，f RO2 . Frequency f of two sets of ring oscillators RO1 ，f RO2 Calculating the frequency difference through a bidirectional counter; the logic processing control circuit analyzes the frequency difference, and if the frequency difference does not meet a preset threshold, the reconstructed signal C is changed 0 ～C 2n-1 Thereby adjusting the output frequency of the ring oscillator; when f is RO1 ，f RO2 If the frequency counting difference is smaller than a preset threshold value, fixing the reconstruction signal; the output of the reconstructed inverter at each of the two ring oscillators is then used as a D flip-flop (D) 0 ～D n-1 ) The data signal and the clock signal of the sampling device, thereby completing the sampling; using oscillator jitter due to phase noise, D flip-flops (D) 0 ～D n-1 ) Continuously and parallelly outputting random numbers; and then outputs the serial true random number bit stream through the parallel-to-parallel interface circuit.
When operating in a physically unclonable function mode, C 0 ～C 2n-1 An incentive to be a physical unclonable function; extracting oscillation frequency difference of output ends of two cascaded oscillators through a counter due to random deviation generated in the manufacturing process of the integrated circuit; further obtaining the output of the physical unclonable function; excitation C by changing the exponential space 0 ～C 2n-1， The physical unclonable function is based on a certain stimulus C 0 ～C 2n-1 A unique response is generated.
The random number generator is an indispensable important component of the existing information security system, and a physical unclonable function is used for security authentication or key generation, so that the random number generator is used for replacing the existing key storage and security authentication mechanism based on a volatile memory, and can effectively resist various physical attacks such as invasive attack and the like. The invention can configure the same circuit as a random number generator or a physical unclonable function, thereby realizing circuit multiplexing and saving resources; the invention can carry out reconstruction processing on the ring oscillators, is used for adjusting the relative frequency of the two ring oscillators, and removes the inherent bias caused by deterministic noise (such as manufacturing difference) or PVT (physical vapor transport) so as to ensure the randomness of the output random number; the embodiment of the invention uses the current starvation type inverter to construct the random number generator, and has better energy efficiency ratio; the embodiment of the invention enables the current starvation type inverter to work in a Zero temperature state (Zero-TC), thereby further reducing the temperature influence.
The implementation principle of the parallel interface circuit described above is further explained in conjunction with the reconfigurable random number generator shown in fig. 14 according to an embodiment of the present invention as follows:
the parallel-parallel connection interface circuit comprises n D triggers and (n-1) data selectors MUX;
the clock control end CLK of N D flip-flops is connected with a clock signal Nf0, and the data selection control end of (N-1) the data selector MUX is connected with a clock signal f 0;
the input end D of the first D trigger is connected with a parallel input signal P0, the output end Q is connected with one input end of the first data selector MUX, the output end of the first data selector is connected with the input end D of the second D trigger, the output end of the second D trigger is connected with one input end of the second data selector, and so on, the output end of the (N-1) th D trigger is connected with one input end of the (N-1) th data selector MUX, the output end of the (N-1) th data selector MUX is connected with the input end D of the Nth D trigger, and the output end Q of the Nth D trigger is a serial output signal; the parallel output signals P1, P2 … … PN are in turn connected to the other input of the (N-1) data selectors MUX.
The inverter shown in fig. 15 is adjusted to be a current starvation type inverter adopted in the embodiment of the present invention, and includes 2 PMOS devices M1 and M2, and2 NMOS devices M3 and M4; m1 source connected to high supply voltage V dd (ii) a The drain of M1 is connected with the source of M2, the drain of M2 is connected with the drain of M3, the source of M3 is connected with the drain of M4, and the source of M4 is grounded; m1 gate connected with bias voltage V p The gate of M4 is connected to bias voltage V n (ii) a The gates of M2 and M3 are input ends V i The drains of M2 and M3 are output ends V o . Wherein the bias voltage V P And V n The inverter is made to operate in a Zero-temperature state (Zero-Tc) so that the random number generator is not susceptible to temperature. The model principle is as follows: the frequency of the ring oscillator RO1, RO2 is determined by the delay of each stage of inverters:
wherein, C 0 Is the total circuit load, V dd Is the power supply voltage, eta is the inverter circuit constant, I D Is a saturation current; further, saturation current I D Is composed of
Wherein, the channel length W, the channel width L, and the gate-source voltage V GS Grid capacitor C OX Threshold voltage V t And carrier mobility μ is channel length, channel width, gate-source voltage, gate capacitance, threshold voltage, and carrier mobility, respectively; further, the switching current temperature coefficient of the saturation current at the temperature T is:
the coefficient needs to be as small as possible to reduce the temperature effect on the saturation current, so in the design, the bias voltage V P And V n The following principles need to be followed: i.e. the circuit can normally switch, V is required GS As small as possible.
As shown in fig. 16, a D flip-flop (D) according to an embodiment of the present invention is provided 0 ～ Dn-1 ) The structure schematic diagram includes 2 AND gates (AND _1, AND _2), 2 NOR gates (NOR _1, NOR _2), 1 inverter (inverter), 1 capacitor C AND1 resistor R in the D flip-flop.
The clock control signal CLK is respectively input into one input end of an AND gate AND _1 AND one input end of an AND gate AND _2 through a capacitor C, a resistor R is connected on a connecting line between the capacitor C AND the AND gate AND _1 AND the AND gate AND _2, AND the other end of the resistor R is grounded;
the input end of the inverter is connected with an input signal D, AND the output end of the inverter is connected with an AND gate AND _ 1; the input end of the AND gate AND _1 is respectively connected with the output end of the inverter AND one input end of the AND gate AND _ 2; the input end of the AND gate AND _2 is respectively connected with the input signal D AND the AND gate AND _1, AND the output end of the AND gate AND _2 is connected with one input end of the NOR gate NOR _ 2; the input end of the NOR gate NOR _1 is respectively connected with the output end of the NOR gate NOR _2 of the output end of the AND gate AND _1, the output end of the NOR gate NOR _2 is connected with one input end of the NOR gate NOR _2, AND meanwhile, the output signal Q of the D flip-flop is output; the input end of the NOR gate NOR _2 is respectively connected with the output end of the NOR gate NOR _1 of the output end of the AND gate AND _2, the output end of the NOR gate NOR _1 is connected with one input end of the NOR gate NOR _1, AND simultaneously the output signal of the D flip-flop is output
The timing diagram of the D flip-flop when generating the random signal is shown in fig. 17. During the first clock period, the two oscillators generate a trigger signal and a clock control signal with similar frequencies to be input to a D terminal and a CLK terminal respectively, signals on the CLK and the D do not completely correspond due to deviation caused by jitter noise, in the first clock period, a rising edge of the CLK corresponds to a high level on the D, a 1 is output, a falling edge of the CLK corresponds to a low level on the D, a 0 is output, and a rising edge of the next clock period corresponds to a low level on the D, and a 0 is output.
The frequencies of the two ring oscillators need to be as close as possible to produce sufficient frequency jitter, generating high entropy random numbers. Control logic unit searches for optimal reconstructed signal C 0 -C 2n-1 Is shown in fig. 18. Initial stage, C 0 -C 2n-1 A set of initial values are preset, the ring oscillator RO1 is counted forward in the time t by the counter, and the ring oscillator RO2 is counted backward in the next time t to obtain Δ N1-N2, wherein N1 is the oscillation frequency count value of the ring oscillator R01, and N2 is the oscillation frequency count value of the ring oscillator R02; defining a variable i, and assigning an initial value of 0 to the variable i; first, for i-0, the signal C is reconstructed 0 Taking the inverse to obtain C 0 ', i.e., the other inverter within the selected inverter group; using a reconstructed signal C 0 ’～C 2n-1 Repeating the counting process to obtain delta N'; judging whether the delta N is smaller than the delta N', if so, retaining C 0 ～C 2n-1 And i + 1; if not, a smaller difference is obtained and the changed C is retained 0 ' and then making i +1, finally judging whether i is equal to n-1, if so, indicating that the traversal of the first n-1 inverters is completed to obtain a local optimal solution.
In the physically unclonable function mode, C 0 ～C 2n-1 The frequency value of the two oscillators is compared to generate a unique response under each input excitation; a typical response generation approach is: if f RO1 >f RO2 Then 0 is output, if f RO1 ≤f RO2 Outputting 1, and vice versa; unlike a true random number generator, the frequency difference is fed into the control logic and only those outputs that have a sufficiently large frequency difference can be marked as stable bit outputs, otherwise they will be discarded. Thereby improving the designed physical unclonable functionStability of the numbers.
In the circuit design, the aims of high speed and low power consumption are realized, and by combining the characteristics of the circuit, a delay unit is supposed to be adopted as a basic structure of an oscillator, and an E-TSPC type trigger is used as a counting unit of a bidirectional counter.
Example 4:
in the embodiment of the invention, a test result is also provided:
in order to preliminarily verify the actual effect of the scheme of the invention, the circuit of the scheme is realized by a pure digital circuit on the Xilinx Artix-7FPGA (a common inverter is used instead of a current starvation type inverter because only the common inverter is arranged in the FPGA), and an oscilloscope is used for testing the frequency of the RO of the two ring oscillators, so that whether the expected effect can be achieved by the reconstruction of the circuit of the scheme is observed.
Shown in the table are: the first action is the frequency and frequency difference of the ring oscillator RO automatically laid out and wired;
the second action automatically lays out the frequency difference of the ring oscillator RO of the wiring through the reconstruction process;
the third is the frequency difference of the ring oscillator RO subjected to the reconstruction process using manual placement and routing;
the result shows that the reconstruction process can greatly reduce the frequency difference of the two ring oscillators RO (the ring oscillator RO1 and the ring oscillator RO2), thereby improving the randomness of the output. Even in the case of automatic layout and wiring, a good effect can be obtained.
The randomness of the output is further tested, the test of NIST random test suit is successfully passed, and the randomness requirement is met.
Those of ordinary skill in the art will appreciate that all or part of the steps of the various methods of the embodiments may be implemented by associated hardware as instructed by a program, which may be stored on a computer-readable storage medium, which may include: a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic or optical disk, and the like.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (15)
- A reconfigurable random number generator is characterized by comprising at least two ring oscillators, a sampling circuit, a counter and a logic control unit, and specifically:the ring oscillator comprises n inverter groups, each inverter group is composed of at least two inverters arranged in parallel and two selectors arranged on the input side and the output side of the inverters respectively; wherein n is a natural number;the control end of the corresponding selector in each inverter group is electrically connected with the logic control unit and is used for receiving the reconstruction signal of the logic control unit and completing the conduction of the electric signal channel between the appointed inverter in each inverter group and the selectors on the two sides of the appointed inverter;the output ends of the at least two ring oscillators are coupled with the input end of the counter; the output end of the counter is connected with the logic control unit; the sampling circuit obtains a sampled electrical signal from the at least two ring oscillators so as to output a random number based on the sampled electrical signal.
- The reconfigurable random number generator of claim 1, wherein the logic control unit obtains the difference between the oscillation frequencies of the at least two ring oscillators through the counter, and sends a reconfiguration signal to each selector in the ring oscillators, so that the difference between the oscillation frequencies of the ring oscillators is smaller than a preset threshold value by adjusting the selected inverter in the inverter group.
- The reconfigurable random number generator of claim 1, wherein the outputs of the at least two ring oscillators are coupled to the inputs of the counter, specifically comprising:the output ends of the at least two ring oscillators are respectively connected with different input ports of the counter, so that the counter can count the oscillation frequencies corresponding to the different ring oscillators; or,the output ends of the at least two ring oscillators are connected with at least two input ends of the counting selector, the output end of the counting selector is connected with the input end of the counter, so that the logic control unit controls the corresponding relation between the input end and the output end of the counting selector, and the ring oscillators are sequentially counted according to the oscillating frequency.
- The reconfigurable random number generator of claim 1, wherein the ring oscillator further comprises a nand gate, and wherein sets of inverters in the ring oscillator are cascaded, in particular:the first input end of the NAND gate is connected with an enable signal; the second input end of the NAND gate is connected with the output port of the inverter group at the tail end of the cascade; and the output end of the NAND gate is used for being connected with the input port of the inverter group positioned at the cascade header.
- The reconfigurable random number generator of claim 4, wherein a random number source is formed by a first ring oscillator and a second ring oscillator in the random number generator, and the sampling circuit is formed by n D flip-flops, specifically:the output end of each inverter group in the first ring oscillator is also connected with a signal input port of a D trigger;the output end of each inverter group in the second ring oscillator is also connected with a clock input port of a D trigger;the electric signals of the output ports of the n D triggers in the sampling circuit form a random number.
- The reconfigurable random number generator of any of claims 1-3, wherein the ring oscillator further comprises m general inverters, specifically:the m common inverters and the n inverter groups are cascaded according to a preset arrangement sequence;wherein, the preset arrangement sequence comprises:the m ordinary inverters are cascaded, and the n inverter groups are cascaded; the m common inverters after the cascade connection and the n inverters after the cascade connection are connected in series; or,cascading the ordinary inverters and the inverter groups at intervals, wherein the distance of the intervals is determined according to the proportional relation between the m ordinary inverters and the n inverter groups; or,and the cascade connection of the common inverters and the inverter groups is completed between the m common inverters and the n inverter groups according to a random sequencing mode.
- The reconfigurable random number generator of claim 6, wherein a random number source is formed by a third ring oscillator and a fourth ring oscillator in the random number generator, and the sampling circuit is formed by p D flip-flops, wherein n ≦ p ≦ m + n, specifically:the output end of a designated inverter and/or an inverter group in the third ring oscillator is also respectively connected with a signal input port of a D trigger;the output end of the appointed inverter group and/or inverter in the fourth ring oscillator is also respectively connected with a clock input port of a D flip-flop;the electric signals of the output ports of the n D triggers in the sampling circuit form a random number.
- The reconfigurable random number generator of claim 1, wherein the logic control unit is further configured to obtain an excitation signal for one or more ring oscillators when the random number generator is operating in the physically unclonable function mode, in particular:the logic control unit converts the excitation signal into a reconstructed signal of the corresponding one or more ring oscillators;and the logic control unit acquires the output oscillation frequency of one or more ring oscillators triggered by the excitation signal and calculates and obtains a physical unclonable output result according to the corresponding oscillation frequency or the difference value of the oscillation frequencies.
- The reconfigurable random number generator of claim 8, wherein the ring oscillator excitation signal is a data source specific to a given set of inverters in the ring oscillator to output as a result of computing a physical unclonable output.
- The reconfigurable random number generator of claim 8 or 9, wherein the calculating a physical unclonable output result according to the corresponding oscillation frequency or the difference between the oscillation frequencies comprises:if the difference of the oscillation frequencies is larger than 0, outputting 0, and if the difference of the oscillation frequencies is smaller than 0, outputting 1; or,if the difference of the oscillation frequencies is larger than 0, outputting 1, and if the difference of the oscillation frequencies is smaller than 0, outputting 0; or,and taking the designated length parameter value after the oscillation frequency decimal point as an integral value to be output.
- The reconfigurable random number generator of claim 1, wherein the inverter is embodied as one or more of a TTL not gate inverter, a CMOS inverter, an HPM disturb effect inverter, or a starved inverter.
- The reconfigurable random number generator of claim 1, wherein when the at least two ring oscillators include a first ring oscillator, a second ring oscillator, and a third ring oscillator,the first ring oscillator and the second ring oscillator form a random number source, and the second ring oscillator and the third ring oscillator form a random number source; or,the first ring oscillator and the third ring oscillator form a random number source, and the second ring oscillator and the third ring oscillator form a random number source; or,the first ring oscillator and the second ring oscillator form a random number source, and the first ring oscillator and the third ring oscillator form a random number source.
- A method of implementing a reconfigurable random number generator, using a reconfigurable random number generator according to any of claims 1-12, the method comprising:the logic control unit acquires the oscillation frequencies of the at least two ring oscillators through the counter;the logic control unit determines a first ring oscillator and a second ring oscillator which are used as a random number source, and analyzes the difference value of the oscillation frequency of the first ring oscillator and the second ring oscillator;if the oscillation frequency is greater than a preset threshold value, the logic control unit sends a reconstruction signal to the first ring oscillator and/or the second ring oscillator so as to control selectors in the first ring oscillator and the second ring oscillator and complete the conduction operation of a designated inverter signal channel in a corresponding inverter group;and adjusting the reconstruction signal through the logic control unit one or more times to enable the difference value of the oscillation frequencies of the first ring oscillator and the second ring oscillator to be smaller than a preset threshold value.
- The method of claim 13, wherein adjusting the reconfiguration signal by the one or more logic control units such that the difference between the oscillation frequencies of the first and second ring oscillators is less than a predetermined threshold comprises:through adjusting the reconstruction signal for many times, the traversal of the selection control of the inverters used for electric signal conduction in each inverter group is completed one by one;if the difference value of the oscillation frequencies of the first ring oscillator and the second ring oscillator can be reduced in each adjustment of the reconstruction signal, the reconstruction signal at the moment is kept as the reconstruction signal in the current state, the oscillation frequency difference corresponding to the reconstruction signal in the current state is used for comparing with the oscillation frequency difference under the reconstruction signal after the next adjustment, and the reconstruction signal with the smaller oscillation frequency difference is taken to be updated as the reconstruction signal in the current state;and stopping the traversal process until the difference value of the oscillation frequencies of the first ring oscillator and the second ring oscillator is smaller than a preset threshold value.
- The method of claim 14, further comprising, if a third ring oscillator is included and the first ring oscillator and the third ring oscillator form another random number source:after the adjustment of the reconstruction signal by the one-time or multiple-time logic control unit is completed, so that the difference value of the oscillation frequencies of the first ring oscillator and the second ring oscillator is smaller than the preset threshold value, the adjustment of the reconstruction signal by the one-time or multiple-time logic control unit is performed on the third ring oscillator, so that the difference value of the oscillation frequencies of the first ring oscillator and the third ring oscillator is smaller than the preset threshold value.
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