WO2019218625A1 - 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 Download PDF

Info

Publication number
WO2019218625A1
WO2019218625A1 PCT/CN2018/116263 CN2018116263W WO2019218625A1 WO 2019218625 A1 WO2019218625 A1 WO 2019218625A1 CN 2018116263 W CN2018116263 W CN 2018116263W WO 2019218625 A1 WO2019218625 A1 WO 2019218625A1
Authority
WO
WIPO (PCT)
Prior art keywords
clock signal
pull
output
shift register
register unit
Prior art date
Application number
PCT/CN2018/116263
Other languages
English (en)
French (fr)
Inventor
罗皓
胡理科
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/470,534 priority Critical patent/US11610524B2/en
Priority to EP18887202.2A priority patent/EP3796296A4/en
Publication of WO2019218625A1 publication Critical patent/WO2019218625A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • Embodiments of the present disclosure relate to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • a pixel array such as a liquid crystal display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines interleaved therewith.
  • the driving of the gate lines can be realized by a gate driving circuit.
  • the gate drive circuit can be implemented by a bonded integrated drive circuit.
  • the gate driving circuit can be directly integrated on the thin film transistor array substrate to form a GOA (Gate-driver On Array) to perform gate lines. drive.
  • GOA Gate-driver On Array
  • a GOA composed of a plurality of cascaded shift register cells can be used to provide a switching state voltage signal for a plurality of rows of gate lines of a pixel array, thereby, for example, controlling a plurality of rows of gate lines to be sequentially turned on, and simultaneously by data lines to the pixel array.
  • the pixel unit of the corresponding row provides a data signal to control each pixel unit to display one frame of image.
  • Current display panels are increasingly using GOA technology to drive gate lines. GOA technology helps achieve narrow borders and reduces production costs.
  • At least one embodiment of the present disclosure provides a shift register unit including a first input circuit, an output circuit, and a first output pull-down circuit; wherein the first input circuit is configured to perform a pull-up node in response to a first clock signal Charging, and resetting the pull-up node in response to the first clock signal; the output circuit is configured to output a second clock signal to an output under control of a level of the pull-up node; The first output pull-down circuit is configured to noise reduce the output in response to a third clock signal.
  • a shift register unit provided in an embodiment of the present disclosure further includes a second input circuit, wherein the second input circuit is configured to perform noise reduction on the pull-up node in response to a fourth clock signal.
  • the shift register unit provided in an embodiment of the present disclosure further includes a first pull-down node control circuit and a second output pull-down circuit; wherein the first pull-down node control circuit is configured to be at the pull-up node Under the control of the level, the level of the pull-down node is controlled; the second output pull-down circuit is configured to perform noise reduction on the output end under the control of the level of the pull-down node.
  • the shift register unit provided in an embodiment of the present disclosure further includes a second pull-down node control circuit; the second pull-down node control circuit is configured to perform a level of the pull-down node in response to the second clock signal control.
  • the first input circuit includes a first transistor; a gate of the first transistor is configured to be connected to a first clock signal terminal to receive the first A clock signal, the first pole of the first transistor being configured to be coupled to the first input to receive the first input signal, the second pole of the first transistor being configured to be coupled to the pull up node.
  • the output circuit includes a second transistor and a first capacitor; a gate of the second transistor is configured to be connected to the pull-up node, a first pole of the second transistor is configured to be coupled to the second clock signal terminal to receive the second clock signal, a second pole of the second transistor is configured to be coupled to the output terminal; The pole is configured to be coupled to the gate of the second transistor, and the second pole of the first capacitor is configured to be coupled to the second pole of the second transistor.
  • the first output pull-down circuit includes a third transistor; a gate of the third transistor is configured to be connected to a third clock signal terminal to receive the first a three clock signal, a first pole of the third transistor is configured to be coupled to the output, and a second pole of the third transistor is configured to be coupled to the first voltage terminal to receive the first voltage.
  • the second input circuit includes a fourth transistor; a gate of the fourth transistor is configured to be connected to a fourth clock signal terminal to receive the fourth a clock signal, a first pole of the fourth transistor is configured to be coupled to the pull up node, and a second pole of the fourth transistor is configured to be coupled to the second input to receive a second input signal.
  • the first pull-down node control circuit includes a fifth transistor; a gate of the fifth transistor is configured to be connected to the pull-up node, A first pole of the fifth transistor is configured to be coupled to the pull down node, and a second pole of the fifth transistor is configured to be coupled to the first voltage terminal to receive the first voltage.
  • the second output pull-down circuit includes a sixth transistor; a gate of the sixth transistor is configured to be connected to the pull-down node, and the sixth transistor The first pole is configured to be coupled to the output, and the second pole of the sixth transistor is configured to be coupled to the first voltage terminal to receive the first voltage.
  • the second pull-down node control circuit includes a second capacitor; and the first pole of the second capacitor is configured to be connected to the pull-down node, where the The second pole of the second capacitor is configured to be coupled to the second clock signal terminal to receive the second clock signal.
  • At least one embodiment of the present disclosure also provides a gate driving circuit including the shift register unit of any of the embodiments of the present disclosure.
  • a gate driving circuit provided in an embodiment of the present disclosure includes a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; wherein the shift register unit includes In the case of a two-input circuit, the shift register unit further includes a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal for respectively using the first to fourth a clock signal is input to the first input circuit, the output circuit, the first output pull-down circuit, and the second input circuit; a first clock signal end of the 4n-3th stage shift register unit and the first a clock signal line is connected, a second clock signal terminal of the 4th-3th stage shift register unit is connected to the second clock signal line, a third clock signal terminal of the 4th-3th stage shift register unit, and the third a clock signal line is connected, a fourth clock signal terminal of the 4th-3th stage shift register unit is connected to the fourth clock signal line; a first clock signal terminal of the 4n-2th stage shift
  • At least one embodiment of the present disclosure also provides a display device including the gate driving circuit of any of the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a driving method of a shift register unit according to any one of the embodiments of the present disclosure.
  • the driving method further includes: a seventh stage, the The two input circuit performs noise reduction on the pull-up node in response to a fourth clock signal, and the second output pull-down circuit performs noise reduction on the output end under the control of the level of the pull-down node.
  • the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal have the same period
  • the phase of the second clock signal is one quarter of a cycle later than the phase of the first clock signal
  • the phase of the fourth clock signal is one quarter of a cycle later than the phase of the second clock signal
  • the phase of the third clock signal is one quarter of a cycle later than the phase of the fourth clock signal.
  • At least one embodiment of the present disclosure further provides a driving method of a shift register unit according to any one of the embodiments of the present disclosure.
  • the driving method includes: In a first stage, the second input circuit charges the pull-up node to a first level in response to the fourth clock signal, and the output circuit outputs a low level of the second clock signal to the output a second stage, the output circuit outputs a high level of the second clock signal to the output end; in a third stage, the output circuit outputs a high level of the second clock signal to the output a fourth stage, the output circuit outputs a low level of the second clock signal to the output end, and the first output pull-down circuit drops the output end in response to the third clock signal a fifth stage, the second input circuit resets the pull-up node in response to the fourth clock signal, and the first output pull-down circuit performs the output on the output end in response to the third clock signal a sixth stage, the second input circuit resets the
  • a driving method of a shift register unit includes: a seventh stage, the first input circuit performs noise reduction on the pull-up node in response to the first clock signal, where The two output pull-down circuit denoises the output terminal under the control of the level of the pull-down node.
  • the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal have the same period
  • the phase of the first clock signal is one quarter of a cycle later than the phase of the second clock signal
  • the phase of the third clock signal is one quarter of a cycle later than the phase of the first clock signal
  • the phase of the fourth clock signal is one quarter of a cycle later than the phase of the third clock signal.
  • FIG. 1 is a schematic block diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic block diagram of another shift register unit according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic block diagram of still another shift register unit according to an embodiment of the present disclosure.
  • FIG. 4 is a circuit diagram showing a specific implementation example of the shift register unit shown in FIG. 3;
  • FIG. 5 is a timing diagram of signals of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 6 is a timing diagram of signals of another shift register unit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic block diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a timing diagram of signals of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic block diagram of another display device according to an embodiment of the present disclosure.
  • the demand for display panels is also increasingly diversified.
  • some customers want the display panel to implement the pre-charging function to shorten the data writing time and improve the accuracy of data writing.
  • the gate drive circuit in the display panel wants the gate drive circuit in the display panel to have a circuit structure as simple as possible, using as few components as possible, in order to realize the wiring of the narrow bezel and the high-resolution display panel.
  • some customers want the display panel to scan both forward and reverse to achieve a two-way scan function so that the display panel can display an upright image whether it is being placed or placed upside down.
  • At least one embodiment of the present disclosure provides a shift register unit, a driving method thereof, a gate driving circuit, and a display device.
  • the number of transistors in the shift register unit is small, and the function of precharging can be realized without additional signal for controlling the precharge function compared with the conventional shift register unit, and the circuit structure is simplified, which is advantageous for achieving narrow border and high Resolution, cost reduction, for example, the shift register unit of at least one embodiment can realize a bidirectional scanning function without additionally adding a signal for controlling the scanning direction, which is advantageous for implementing narrow bezel wiring.
  • At least one embodiment of the present disclosure provides a shift register unit including a first input circuit, an output circuit, and a first output pull-down circuit.
  • the first input circuit is configured to charge a pull-up node in response to a first clock signal, and to reset the pull-up node in response to the first clock signal;
  • the output circuit configured to be on the pull-up
  • the second clock signal is output to the output under control of the level of the node;
  • the first output pull-down circuit is configured to noise reduce the output in response to the third clock signal.
  • FIG. 1 is a schematic block diagram of a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit 10 includes a first input circuit 100, an output circuit 200, and a first output pull-down circuit 300.
  • the first input circuit 100 is configured to charge the pull-up node PU in response to the first clock signal and to reset the pull-up node PU in response to the first clock signal.
  • the first input circuit 100 is connected to the first clock signal terminal CK1 and the pull-up node PU, and is configured to enable the pull-up node PU and the first provided first under the control of the first clock signal provided by the first clock signal terminal CK1.
  • the input terminal is electrically connected, so that the high-level signal outputted by the first input terminal can charge the pull-up node PU, so that the voltage of the pull-up node PU increases to control the output circuit 200 to be turned on.
  • the first input circuit 100 It is further configured to reset the low-level signal outputted by the first input terminal to the pull-up node PU under the control of the first clock signal provided by the first clock signal terminal CK1, so that the voltage of the pull-up node PU is lowered to control
  • the output circuit 200 is turned off.
  • the first input is connected to a trigger signal line or an output Output of the upper stage shift register unit 10 adjacent to the stage shift register unit 10 of the first input circuit 100.
  • the first input signal provided at the first input is a trigger signal provided to the shift register unit 10 of the stage.
  • the first input circuit 100 can both charge the pull-up node PU and reset the pull-up node PU, so that the shift register unit 10 does not need to be separately set and pulled up.
  • the reset circuit of the node PU simplifies the circuit structure.
  • the output circuit 200 is configured to output a second clock signal to the output terminal Output of the shift register unit 10 under the control of the level of the pull-up node PU as an output signal of the shift register unit 10 to drive, for example,
  • the output terminal is connected to the gate line.
  • the output circuit 200 is connected to the second clock signal terminal CK2, the pull-up node PU, and the output terminal Output, and is configured to be turned on under the control of the level of the pull-up node PU, so that the second clock signal terminal CK2 and the output terminal Output
  • the second clock signal input to the second clock signal terminal CK2 can be output to the output terminal Output.
  • the first output pull-down circuit 300 is configured to noise-reject the output Output in response to the third clock signal.
  • the first output pull-down circuit 300 and the third clock signal terminal CK3, the output terminal Output, and the first voltage terminal (for example, the first voltage terminal may be a low voltage terminal, so that the first voltage outputted by the first voltage terminal is a low voltage Connecting, configured to electrically connect the output terminal Output and the first voltage terminal under the control of the third clock signal provided by the third clock signal terminal CK3, so that the first voltage terminal can output the first voltage of the low level Noise reduction is performed on the output of the output.
  • FIG. 2 is a schematic block diagram of another shift register unit according to an embodiment of the present disclosure.
  • the shift register unit 10 further includes a second input circuit 400, and other structures in the shift register unit 10 (for example, the first input circuit 100, the output circuit 200, and the first output pull-down circuit 300) ) is substantially the same as the shift register unit 10 shown in FIG. 1.
  • the second input circuit 400 is configured to perform noise reduction on the pull-up node PU in response to the fourth clock signal.
  • the second input circuit 400 is connected to the fourth clock signal terminal CK4 and the pull-up node PU, configured to enable the pull-up node PU and the second provided second under the control of the fourth clock signal provided by the fourth clock signal terminal CK4.
  • the input terminal is electrically connected, so that the low-level signal outputted by the second input terminal can reduce the noise of the pull-up node PU.
  • the second input terminal is connected to an output terminal Output or a trigger signal line of the next-stage shift register unit 10 adjacent to the shift register unit 10 of the present stage including the second input circuit 400.
  • the second input circuit 400 and the first input circuit 100 cooperate with each other, alternately denoise or reset the pull-up node PU, and perform noise reduction on the pull-up node PU.
  • the reset time includes a time when the second clock signal is at a high level, thereby ensuring that the pull-up node PU remains low to avoid a defect such as a glitch due to the signal of the output terminal due to the second clock signal.
  • the second input circuit 400 is similar to or symmetrically disposed with the circuit structure of the first input circuit 100, passing clock signals (first clock signal, second clock signal, third clock signal, and fourth clock signal) and input signals (eg, The first input signal and the second input signal cooperate with each other, and the shift register unit 10 can be used for bidirectional scanning, so that the control signal can be reduced, which is advantageous for narrow bezel and high resolution.
  • the forward scanning is performed using the display panel of the shift register unit 10
  • the trigger signal or the signal supplied from the shift register unit 10 of the previous stage is input from the first input terminal, and its operation is as described above.
  • the trigger signal or the signal supplied from the shift register unit 10 of the next stage is caused to be input from the second input.
  • the second input circuit 400 is configured to charge the pull-up node PU in response to the fourth clock signal, and reset the pull-up node PU in response to the fourth clock signal; and the first input circuit 100 is configured to respond to the first A clock signal denoises the pull-up node PU.
  • the circuit does not require additional signals (for example, scan direction control signals) to achieve bidirectional scanning, simplifying circuit structure and scanning control.
  • the directions of the forward scan and the reverse scan are relative, and the scan along any one of the first directions in the bidirectional scan may be referred to as a forward scan, and the edge and the A scan in a second direction that is opposite in one direction is called a reverse scan.
  • the first direction represents the direction from the first row of gate lines of the display panel to the direction of the last row of gate lines of the display panel
  • the second direction may represent the first scan from the last row of the display panel to the first of the display panel.
  • the direction of the grid lines may be referred to as a forward scan
  • FIG. 3 is a schematic block diagram of another shift register unit according to an embodiment of the present disclosure.
  • the shift register unit 10 of this embodiment further includes a first pull-down node control circuit 500, a second pull-down node control circuit 600, and a second output pull-down circuit 700, other structures of the shift register unit 10 (eg, The first input circuit 100, the output circuit 200, the first output pull-down circuit 300, and the second input circuit 400) are substantially the same as the shift register unit 10 shown in FIG. 2.
  • the first pull-down node control circuit 500 is configured to control the level of the pull-down node PD under the control of the level of the pull-up node PU.
  • the first pull-down node control circuit 500 is coupled to the pull-up node PU and the pull-down node PD, configured to cause the pull-down node PD and the additionally provided low voltage terminal (eg, first) under the control of the level of the pull-up node PU
  • the voltage terminal is electrically connected so that the low-level signal output from the low-voltage terminal can control the level of the pull-down node PD, for example, the level of the pull-down node PD is low.
  • the second pull-down node control circuit 600 is configured to control the level of the pull-down node PD in response to the second clock signal.
  • the second pull-down node control circuit 600 is connected to the second clock signal terminal CK2 and the pull-down node PD, and is configured to make the level of the pull-down node PD follow the control of the second clock signal provided by the second clock signal terminal CK2.
  • the level of the second clock signal changes, for example, the level of the pull-down node PD is alternated to a high level and a low level.
  • the second output pull-down circuit 700 is configured to perform noise reduction on the output terminal under the control of the level of the pull-down node PD.
  • the second output pull-down circuit 700 is connected to the pull-down node PD and the output terminal Output, and is configured to make the output terminal Output and the additionally provided low voltage terminal (for example, the first voltage terminal) under the control of the level of the pull-down node PD. Connected so that the low level signal output from the low voltage side can be used to noise the output of the output.
  • the second output pull-down circuit 700 and the first output pull-down circuit 300 cooperate with each other to alternately reduce the noise of the output terminal, for example, to achieve double pull-down of the output terminal, so that the duty ratio of the transistor used for the pull-down is less than 50%, improving the reliability of the circuit and the display panel using the circuit.
  • each transistor is an N-type transistor as an example, but this does not constitute a limitation on the embodiment of the present disclosure.
  • each transistor for example, the first to sixth transistors T1 to T6 described below
  • the "active level" indicates high. Level.
  • the present disclosure is not limited thereto, and when each transistor (for example, the first to sixth transistors T1-T6 described below) is a P-type transistor, the "active level" indicates a low level.
  • the shift register unit 10 includes first to sixth transistors T1-T6, a first capacitor C1, and a second capacitor C2.
  • the first input circuit 100 can be implemented as a first transistor T1.
  • the gate of the first transistor T1 is configured to be connected to the first clock signal terminal CK1 to receive the first clock signal
  • the first electrode of the first transistor T1 is configured to be connected to the first input terminal Input1 to receive the first input signal
  • first The second pole of transistor T1 is configured to be coupled to pull up node PU.
  • the first transistor T1 is turned on when the first clock signal is at an active level (eg, a high level), electrically connecting the first input terminal Input1 and the pull-up node PU, so that the pull-up node PU can be charged or reset.
  • the pull-up node PU can be charged when the first input signal is at a high level, and the pull-up node PU can be reset when the first input signal is at a low level.
  • the first transistor T1 is turned on when the first clock signal is at an active level, thereby making the first input terminal Input1 An input signal is used to denoise the pull-up node PU.
  • the output circuit 200 can be implemented as a second transistor T2 and a first capacitor C1.
  • the gate of the second transistor T2 is configured to be connected to the pull-up node PU
  • the first pole of the second transistor T2 is configured to be connected to the second clock signal terminal CK2 to receive the second clock signal
  • the second pole configuration of the second transistor T2 Connected to the output of the output.
  • the first pole of the first capacitor C1 is configured to be connected to the gate of the second transistor T2
  • the second pole of the first capacitor C1 is configured to be connected to the second pole of the second transistor T2.
  • the first capacitor C1 may be a capacitor device fabricated on a display panel by a process, for example, by fabricating a special capacitor electrode, which may pass through a metal layer or a semiconductor layer (eg, doped polysilicon). And so on, and the first capacitor C1 can also be a parasitic capacitance between the transistors, which can be realized by the transistor itself and other devices and circuits.
  • the first capacitor C1 is a parasitic capacitance, so the output circuit 200 includes only the second transistor T2 without a specially fabricated capacitive device. This simplifies the process, reduces production costs, and increases production efficiency.
  • the first output pull-down circuit 300 can be implemented as a third transistor T3.
  • the gate of the third transistor T3 is configured to be connected to the third clock signal terminal CK3 to receive the third clock signal
  • the first pole of the third transistor T3 is configured to be connected to the output terminal Output
  • the second pole of the third transistor T3 is configured as And connecting to the first voltage terminal VGL to receive the first voltage.
  • the first voltage terminal VGL is configured to provide a DC low level signal (eg, a low level portion that is lower than or equal to the clock signal), such as ground
  • the DC low level signal is referred to as a first voltage, and the following embodiments The same as this, no longer repeat them.
  • the third clock signal is at an active level
  • the third transistor T3 is turned on, so that the output terminal Output and the first voltage terminal VGL are electrically connected, thereby reducing the output of the output terminal to be at a low level.
  • the second input circuit 400 can be implemented as a fourth transistor T4.
  • the gate of the fourth transistor T4 is configured to be connected to the fourth clock signal terminal CK4 to receive the fourth clock signal
  • the first electrode of the fourth transistor T4 is configured to be connected to the pull-up node PU
  • the second transistor of the fourth transistor T4 is configured. Connected to the second input terminal Input2 to receive the second input signal.
  • the fourth transistor T4 is turned on when the fourth clock signal is at an active level (for example, a high level), so that the second input terminal Input2 and the pull-up node PU are electrically connected, so that the pull-up node PU can be noise-reduced.
  • the fourth transistor T4 when the display panel of the shift register unit 10 is used for reverse scanning, the fourth transistor T4 is turned on when the fourth clock signal is at an active level, thereby outputting by using the second input terminal Input2.
  • the second input signal of the high level charges the pull-up node PU, and the pull-up node PU can also be reset by using the second input signal of the low level output by the second input terminal Input2.
  • the first pull-down node control circuit 500 can be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is configured to be connected to the pull-up node PU
  • the first pole of the fifth transistor T5 is configured to be connected to the pull-down node PD
  • the second pole of the fifth transistor T5 is configured to be connected to the first voltage terminal VGL. Receiving the first voltage.
  • the fifth transistor T5 is turned on to electrically connect the pull-down node PD and the first voltage terminal VGL, thereby pulling down the level of the pull-down node PD to be at a low level.
  • the second pull-down node control circuit 600 can be implemented as a second capacitor C2.
  • the first pole of the second capacitor C2 is configured to be connected to the pull-down node PD, and the second pole of the second capacitor C2 is configured to be connected to the second clock signal terminal CK2 to receive the second clock signal.
  • the pull-down node PD In the case where the fifth transistor T5 is turned off, the pull-down node PD is in a floating state, and the level of the pull-down node PD varies with the level of the second clock signal due to the bootstrap effect of the second capacitor C2, for example, when When the level of the second clock signal alternates between a high level and a low level, the level of the pull-down node PD alternates to a high level and a low level, and accordingly controls the sixth transistor T6 to be turned on later. cutoff.
  • the second output pull-down circuit 700 can be implemented as a sixth transistor T6.
  • the gate of the sixth transistor T6 is configured to be connected to the pull-down node PD, the first pole of the sixth transistor T6 is configured to be connected to the output terminal Output, and the second pole of the sixth transistor T6 is configured to be connected to the first voltage terminal VGL for receiving The first voltage.
  • the level of the pull-down node PD is an active level (for example, a high level)
  • the sixth transistor T6 is turned on, electrically connecting the output terminal Output and the first voltage terminal VGL, thereby performing noise reduction on the output terminal, so that It is at a low level.
  • the level of the pull-down node PD and the level of the third clock signal may be alternated to an active level, so that the sixth transistor T6 and the third transistor T3 are alternately turned on to achieve double pull-down of the output terminal, ensuring the output end. Output is at a low level.
  • the sixth transistor T6 and the third transistor T3 are subjected to about 50% of stress during the entire frame scanning process, which can alleviate the performance degradation of the device and prevent the threshold voltage from shifting.
  • the pull-up node PU and the pull-down node PD do not represent actual components, but rather represent convergence points of associated electrical connections in the circuit diagram.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor, a field effect transistor, or other switching device having the same characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described.
  • the transistors in the embodiments of the present disclosure are all described by taking an N-type transistor as an example.
  • the first pole of the transistor is the drain and the second pole is the source.
  • the present disclosure includes but is not limited thereto.
  • one or more transistors in the shift register unit 10 provided by the embodiment of the present disclosure may also adopt a P-type transistor.
  • the first pole of the transistor is the source and the second pole is the drain.
  • each transistor eg, first to sixth transistors T1-T6 described below
  • the poles of each transistor of a selected type are referenced to the implementation of the present disclosure.
  • the respective poles of the respective transistors in the example are connected, and the first voltage terminal VGL is configured to provide a DC high level signal (eg, a high level portion higher than or equal to the clock signal).
  • IGZO Indium Gallium Zinc Oxide
  • LTPS low temperature polysilicon
  • amorphous silicon for example, hydrogenation non-hydrogenation
  • FIG. 5 is a timing diagram of signals of a shift register unit according to an embodiment of the present disclosure.
  • the working principle of the shift register unit 10 shown in FIG. 4 will be described below with reference to the signal timing diagram shown in FIG. 5.
  • each transistor is an N-type transistor, but the embodiment of the present disclosure is not limited thereto. this.
  • CK1, CK2, CK3, CK4, STV, Input1, Input2, etc. are used to indicate the corresponding signal terminals, and are also used to respectively represent the first clock signal, the second clock signal, and the third clock. Signal, fourth clock signal, trigger signal, etc.
  • the shift register Unit 10 can perform the following operations separately.
  • the level of the first clock signal CK1 and the level of the third clock signal being CK3 are at a high level, and the level of the second clock signal CK2 and the level of the fourth clock signal CK4 are at a low level.
  • the first input terminal Input1 provides a first input signal Input1 of a high level.
  • the first transistor T1 is turned on by the high level of the first clock signal CK1, and the first input signal Input1 starts to charge the pull-up node PU, so that the potential of the pull-up node PU is raised, and finally the pull-up node PU It is charged to the first level and the first level is high.
  • the fifth transistor T5 is turned on, so that the pull-down node PD is connected to the first power supply terminal VGL, so that the pull-down node PD is at a low level.
  • the second transistor T2 is also turned on, and outputs the second clock signal CK2 to the output terminal Output.
  • the third transistor T3 is turned on by the high level of the third clock signal CK3, and outputs the first voltage (provided by the first voltage terminal VGL) to the output terminal Output. Since the level of the second clock signal CK2 and the level of the first voltage are both low in the first phase 1, the level of the output terminal is also low. Since the level of the fourth clock signal CK4 is at a low level, the fourth transistor T4 is turned off.
  • the sixth transistor T6 is turned off by the low level of the pull-down node PD.
  • the level of the first clock signal CK1 is maintained at a high level
  • the level of the second clock signal CK2 is changed to a high level
  • the level of the third clock signal CK3 is changed to a low level
  • fourth The level of the clock signal CK4 is kept low.
  • the second transistor T2 remains turned on, and the high level of the second clock signal CK2 is output to the output terminal Output. Since the level of the second clock signal CK2 becomes a high level, the level of the output terminal Output becomes High level. Due to the bootstrap effect of the first capacitor C1, in order to keep the voltage difference between the two poles of the first capacitor C1 unchanged, the potential of the pull-up node PU is further pulled high.
  • the level of the pull-up node PU is the second level, the second level is also the high level, and the second level is higher than the first level. thus.
  • the second transistor T2 is sufficiently turned on. Since the level of the pull-up node PU is further pulled up to the second level, the level of the pull-up node PU is higher than the level of the gate of the first transistor T1 (ie, the level of the first clock signal CK1), A transistor T1 is saturated and turned off.
  • the fifth transistor T5 is kept turned on by the high level of the pull-up node PU, so that the pull-down node PD is still at a low level. Since the level of the third clock signal CK3 becomes a low level, the third transistor T3 is turned off. At this time, the fourth transistor T4 and the sixth transistor T6 are both turned off.
  • the level of the first clock signal CK1 becomes a low level
  • the level of the second clock signal CK2 remains at a high level
  • the level of the third clock signal CK3 remains at a low level
  • the fourth The level of the clock signal CK4 becomes a high level.
  • the first transistor T1 is turned off.
  • the pull-up node PU maintains the level of the previous stage (ie, the second level)
  • the second transistor T2 remains turned on
  • the high level of the second clock signal CK2 continues to be output to the output terminal Output.
  • the fifth transistor T5 is kept turned on by the high level of the pull-up node PU, so that the level of the pull-down node PD is still low.
  • the sixth transistor T6 remains off.
  • the third transistor T3 Since the level of the third clock signal CK3 is maintained at a low level, the third transistor T3 remains off. Although the level of the fourth clock signal CK4 becomes a high level, the second input signal terminal Input2 provides a high level signal, but at this time, the level of the pull-up node PU is the second level, which is higher than that of the fourth transistor T4. The level of the gate (i.e., the level of the fourth clock signal CK4), and thus the fourth transistor T4 is saturated and turned off.
  • the level of the first clock signal CK1 is kept at a low level
  • the level of the second clock signal CK2 is changed to a low level
  • the level of the third clock signal CK3 is changed to a high level
  • fourth The level of the clock signal CK4 is maintained at a high level.
  • the second transistor T2 is kept turned on, and the output terminal Output is pulled down by the second transistor T2, so that the level of the output terminal is low, and the first capacitor C1 is maintained due to the bootstrap effect of the first capacitor C1.
  • the voltage difference between the two poles is constant, the level of the pull-up node PU becomes the first level, and the level of the second input signal Input2 is high because the level of the fourth clock signal CK4 is maintained at the high level.
  • Level when the level of the pull-up node PU becomes the first level, the fourth transistor T4 is turned on, and the second input signal Input2 can be charged in the pull-up phase PU to maintain the pull-up node PU at the first level. At this time, the pull-up node PU can still turn on the second transistor T2. That is to say, in the present disclosure, the second transistor T2 can pull up the output terminal, and can also pull down the output terminal.
  • the second transistor T2 is a thin film transistor having a large size, and thus the pull-down time is short. Since the level of the third clock signal CK3 becomes a high level, the third transistor T3 is turned on. The third transistor T3 also pulls down the output terminal and maintains it to output a low level, so that the accuracy of the output signal is high. Since the second transistor T2 can realize the potential of the fast pull-down output terminal, the third transistor T3 and the sixth transistor T6 for the potential of the pull-down output terminal can be appropriately reduced or adopted, which is advantageous for narrow frame and high resolution. rate. The fifth transistor T5 remains turned on, so that the level of the pull-down node PD remains at a low level. The first transistor T1 and the sixth transistor T6 are kept off.
  • the level of the first clock signal CK1 becomes a high level, and the level of the second clock signal CK2 remains at a low level.
  • the first transistor T1 is turned on, and the first input terminal Input1 provides a low level signal, thereby resetting the pull-up node PU, so that the level of the pull-up node PU becomes a low level.
  • the second transistor T2 and the fifth transistor T5 are turned off by the low level of the pull-up node PU. Since the level of the third clock signal CK3 is at a high level, the third transistor T3 remains turned on, and the output terminal Output is noise-reduced by the first voltage of the first voltage terminal.
  • the level of the fourth clock signal CK4 becomes a low level, and the fourth transistor T4 is turned off.
  • the pull-down node PD maintains the level of the previous stage (ie, the fourth stage 4) (ie, the low level), and the sixth transistor T6 remains off.
  • the level of the first clock signal CK1 is maintained at a high level, the first transistor T1 remains turned on, and the level of the pull-up node PU is maintained at a low level to reduce the second clock signal CK2.
  • the high level affects the pull-up node PU through the parasitic capacitance, thereby avoiding glitch and other defects in the output terminal output signal.
  • the level of the third clock signal CK3 becomes a low level, and the third transistor T3 is turned off.
  • the fourth clock signal CK4 is kept at a low level, and the fourth transistor T4 is turned off. Since the level of the pull-up node PU is low, the second transistor T2 and the fifth transistor T5 remain off.
  • the level of the second clock signal CK2 becomes a high level, and the level of the pull-down node PD also becomes a high level due to the bootstrap effect of the second capacitor C2, thereby turning on the sixth transistor T6, using the first voltage
  • the first voltage of the terminal reduces the noise of the output terminal.
  • the level of the fourth clock signal CK4 becomes a high level, the fourth transistor T4 is turned on, and the second input terminal Input2 provides a low level signal to maintain the low level of the pull-up node PU, thereby The influence of the high level of the second clock signal CK2 on the pull-up node PU by the parasitic capacitance is reduced, and the signal of the output terminal Output is prevented from generating glitch and the like.
  • the level of the first clock signal CK1 becomes a low level, and the first transistor T1 is turned off.
  • the third clock signal CK3 is kept at a low level, and the third transistor T3 is turned off.
  • the second transistor T2 and the fifth transistor T5 remain off.
  • the level of the second clock signal CK2 is maintained at a high level, and the sixth transistor T6 is kept turned on to reduce the noise of the output terminal by the first voltage of the first voltage terminal.
  • the level of the pull-down node PD changes with the level of the second clock signal CK2, and the level of the third clock signal CK3 and the level of the pull-down node PD are inverted from each other, thereby making the first
  • the six-transistor T6 and the third transistor T3 are alternately turned on to continuously reduce the noise of the output terminal, and maintain the low level of the output terminal.
  • This double pull-down approach improves the reliability of the circuit and the display panel in which the circuit is employed.
  • the sixth transistor T6 and the third transistor T3 are subjected to about 50% of stress during the entire frame scanning process, which can alleviate the performance degradation of the device and prevent the threshold voltage from shifting.
  • the sixth transistor T6 and the third transistor T3 only serve to hold, so the sixth transistor
  • the size of the T6 and the third transistor T3 can be appropriately reduced, which not only can reduce power consumption, but also can reduce the installation space of the circuit, and is advantageous for achieving a narrow bezel and high resolution.
  • the first transistor T1 and the fourth transistor T4 are alternately turned on to perform noise reduction on the pull-up node PU, maintaining The low level of the pull-up node PU. In this way, the influence of the high level of the second clock signal CK2 on the pull-up node PU through the parasitic capacitance can be reduced, and the signal of the output terminal Output can be prevented from generating glitch and the like. Moreover, the first transistor T1 and the fourth transistor T4 are subjected to about 50% of stress during the entire frame scanning process, which can alleviate the performance degradation of the device and prevent the threshold voltage from shifting.
  • the shift register unit 10 when the shift register unit 10 performs forward scanning, its working principle is as described above for the first stage 1 to the seventh stage 7.
  • the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 have the same period.
  • the phase of the second clock signal CK2 is one quarter cycle later than the phase of the first clock signal CK1
  • the phase of the fourth clock signal CK4 is four quarters later than the phase of the second clock signal CK2.
  • the phase of the third clock signal CK3 is one quarter cycle later than the phase of the fourth clock signal CK4.
  • the first clock signal CK1 and the fourth clock signal CK4 are inverted from each other, and the second clock signal CK2 and the third clock signal CK3 are inverted from each other.
  • the signals of the first input terminal 1, the output terminal Output and the second input terminal Input2 are the output signals of the three adjacent cascaded shift register units 10, and any two adjacent shifts.
  • the output signals of the bit register unit 10 partially overlap each other and the overlap time is half of the pulse width of the clock signal to achieve the function of precharging.
  • the shift register unit 10 does not require an additional signal, and the connection relationship between the plurality of shift register units 10 is simplified, which is advantageous for achieving a narrow bezel and high resolution.
  • the shift register unit 10 when the shift register unit 10 performs reverse scanning, its signal timing diagram is as shown in FIG. 6, and its working principle is similar to that of the forward scanning, and the trigger signal to be supplied to the shift register unit 10 of the stage is similar. It can be input by the second input terminal Input2, and will not be described here.
  • the phase relationship between the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 and the phase between each other during forward scanning is different.
  • the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 have the same period.
  • the phase of the first clock signal CK1 is one quarter cycle later than the phase of the second clock signal CK2
  • the phase of the third clock signal CK3 is one quarter later than the phase of the first clock signal CK1
  • the phase of CK4 is one quarter of a cycle later than the phase of the third clock signal CK3.
  • the first clock signal CK1 and the fourth clock signal CK4 are inverted from each other, and the second clock signal CK2 and the third clock signal CK3 are inverted from each other.
  • the shift register unit 10 matches the timing of the above four clock signals and the trigger signal supplied to the shift register unit 10, and the bidirectional scan function can be realized without additional signals (for example, the scan direction control signal).
  • the above four clock signals can be generated by the timing controller T-CON, which is easy to implement.
  • At least one embodiment of the present disclosure also provides a gate driving circuit.
  • the gate drive circuit includes the shift register unit of any of the embodiments of the present disclosure.
  • the number of transistors in the gate driving circuit is small, and the function of precharging can be realized without additionally adding a signal for controlling the precharging function, and the circuit structure is simplified, which is advantageous for achieving a narrow bezel and high resolution, and reducing cost, for example,
  • the gate driving circuit of at least one embodiment can realize a bidirectional scanning function without additionally adding a signal for controlling the scanning direction, which is advantageous for implementing narrow bezel wiring.
  • FIG. 7 is a schematic block diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the gate driving circuit 20 includes a plurality of cascaded shift register units (SR1, SR2, SR3, SR4, . . . , SRn).
  • the number of multiple shift register units is not limited and can be determined according to actual needs. For example, for a display device having a resolution of 640 ⁇ 480, the number of shift register units may be 480, and correspondingly, for a display device having a resolution of 1920 ⁇ 1440, the number of shift register units may be 1440.
  • the shift register unit employs the shift register unit 10 described in any of the embodiments of the present disclosure.
  • the shift register unit 10 of any of the embodiments of the present disclosure may be employed in part or all of the shift register unit.
  • the gate driving circuit 20 can be directly integrated on the array substrate of the display device by a process similar to that of the thin film transistor to realize a progressive scan driving function.
  • each shift register unit has a first input terminal Input1, a second input terminal Input2, first to fourth clock signal terminals CK1-CK4, a first voltage terminal VGL, and an output terminal Output.
  • the output of the shift register unit of each stage is connected to the second input terminal Input2 of the adjacent shift register unit.
  • the output of each stage shift register unit is connected to the first input terminal Input1 of the adjacent next stage shift register unit.
  • the first input terminal Input1 of the first stage shift register unit is configured to be connected to the trigger signal line STV to receive the trigger signal STV; the second stage of the last stage shift register unit
  • the input terminal Input2 is configured to be connected to the trigger signal line STV to receive a corresponding signal, such as the trigger signal STV, and when the trigger signal STV is at an active level, the first clock signal CK1 is also an active level.
  • the gate driving circuit realizes the reverse scanning, the trigger signal STV is supplied to the second input terminal Input2 of the last stage shift register unit, and the corresponding signal is supplied to the first input terminal Input1 of the first stage shift register unit.
  • the second clock signal CK2 is also an active level.
  • the gate driving circuit 20 further includes a first clock signal line CK_1, a second clock signal line CK_2, a third clock signal line CK_3, and a fourth clock signal line CK_4.
  • every four shift register units are one cascade repeating unit, and the specific connection manner is as follows, and the cascade manner of other shift register units is similar.
  • the first clock signal terminal CK1 of the 4th-3th stage shift register unit (for example, the first stage shift register unit SR1) is connected to the first clock signal line CK_1, and the 4th-3th stage shift register unit is the second clock signal.
  • the terminal CK2 is connected to the second clock signal line CK_2, the third clock signal terminal CK3 of the 4n-3th stage shift register unit is connected to the third clock signal line CK_3, and the fourth clock signal terminal CK4 of the 4n-3th stage shift register unit is connected. It is connected to the fourth clock signal line CK_4.
  • the first clock signal terminal CK1 of the 4th-2th stage shift register unit (for example, the second stage shift register unit SR2) is connected to the second clock signal line CK_2, and the second clock signal of the 4n-2th stage shift register unit
  • the terminal CK2 is connected to the fourth clock signal line CK_4
  • the third clock signal terminal CK3 of the 4th-2th stage shift register unit is connected to the first clock signal line CK_1
  • the fourth clock signal terminal CK4 of the 4th-2th stage shift register unit is connected. It is connected to the third clock signal line CK_3.
  • the first clock signal terminal CK1 of the 4n-1th stage shift register unit (for example, the third stage shift register unit SR3) is connected to the fourth clock signal line CK_4, and the 4n-1th stage shift register unit is connected to the second clock signal.
  • the terminal CK2 is connected to the third clock signal line CK_3, the third clock signal terminal CK3 of the 4n-1th stage shift register unit is connected to the second clock signal line CK_2, and the fourth clock signal terminal CK4 of the 4n-1th stage shift register unit is connected. It is connected to the first clock signal line CK_1.
  • the first clock signal terminal CK1 of the 4th-stage shift register unit (for example, the fourth-stage shift register unit SR4) is connected to the third clock signal line CK_3, and the second clock signal terminal CK2 and the fourth-stage shift register unit are connected.
  • a clock signal line CK_1 is connected, a fourth clock signal terminal CK3 of the 4nth stage shift register unit is connected to the fourth clock signal line CK_4, and a fourth clock signal terminal CK4 and a second clock signal line CK_2 of the 4th stage shift register unit are connected. .
  • n is an integer greater than 0.
  • the signals provided by the first clock signal line CK_1, the second clock signal line CK_2, the third clock signal line CK_3, and the fourth clock signal line CK_4 have different phase relationships with each other during forward scanning and reverse scanning. For details, refer to the description of the working principle of the shift register unit 10, and details are not described herein again.
  • the gate driving circuit 20 may further include a timing controller T-CON configured to, for example, provide a first clock signal, a second clock signal, a third clock signal, and The fourth clock signal, the timing controller T-CON can also be configured to provide a trigger signal.
  • a timing controller T-CON configured to, for example, provide a first clock signal, a second clock signal, a third clock signal, and The fourth clock signal, the timing controller T-CON can also be configured to provide a trigger signal.
  • the timing signals of the plurality of clock signals provided by the timing controller T-CON are different from each other. In different examples, more clock signals, such as 6, 8, etc., may also be provided depending on the configuration. The disclosure does not limit this.
  • the gate drive circuit 20 further includes a first voltage line VGL1 to provide a first voltage to each of the shift register cells.
  • the gate driving circuit 20 can be disposed on one side of the display panel.
  • the display panel includes a plurality of rows of gate lines, and the output terminals of the shift register units of the gate driving circuit 20 can be configured to be sequentially connected with the plurality of rows of gate lines for outputting gates to the respective gate lines. Scan the signal.
  • the gate driving circuit 20 can also be disposed on both sides of the display panel to implement bilateral driving.
  • the embodiment of the present disclosure does not limit the manner in which the gate driving circuit 20 is disposed.
  • the gate drive circuit 20 may be disposed on one side of the display panel for driving odd-numbered gate lines, and the gate drive circuit 20 may be disposed on the other side of the display panel for driving even-numbered gate lines.
  • FIG. 8 is a timing diagram of signals of a gate driving circuit according to an embodiment of the present disclosure.
  • the high-level pulse widths of the clock signals supplied from the first clock signal line CK_1, the second clock signal line CK_2, the third clock signal line CK_3, and the fourth clock signal line CK_4 are both t1.
  • the output signals of any two adjacent shift register units partially overlap each other and have an overlap time of t2.
  • the gate driving circuit 20 can realize the pre-charging function without additionally adding a signal for controlling the pre-charging function, and the connection relationship between the plurality of shift register units is simplified, which is advantageous for realizing a narrow bezel and a high resolution.
  • At least one embodiment of the present disclosure also provides a display device.
  • the display device includes the gate drive circuit of any of the embodiments of the present disclosure.
  • the gate drive circuit of the display device has a small number of transistors, and the function of precharging can be realized without additionally adding a signal for controlling the precharge function, and the circuit structure is simplified, which is advantageous for achieving narrow frame and high resolution, and reducing cost.
  • the gate driving circuit in the display device of at least one embodiment can implement a bidirectional scanning function without additionally adding a signal for controlling the scanning direction, which is advantageous for implementing narrow bezel wiring.
  • FIG. 9 is a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • the display device 30 includes a gate driving circuit 20, which is a gate driving circuit according to any of the embodiments of the present disclosure.
  • the display device 30 can be a liquid crystal display (LCD) panel, an LCD TV, a display, an Organic Light-Emitting Diode (OLED) panel, an OLED TV, an electronic paper display device, a mobile phone, a tablet computer, Any of the products or components having a display function, such as a notebook computer, a digital photo frame, a navigator, and the like, are not limited in the embodiments of the present disclosure.
  • LCD liquid crystal display
  • OLED Organic Light-Emitting Diode
  • OLED Organic Light-Emitting Diode
  • FIG. 10 is a schematic block diagram of another display device according to an embodiment of the present disclosure.
  • the display device 30 includes a display panel 3000, a gate driver 3010, a timing controller 3020, and a data driver 3030.
  • the display panel 3000 includes a plurality of scan lines GL, a plurality of data lines DL, and a plurality of pixel units P defined according to the plurality of scan lines GL and the plurality of data lines DL;
  • the gate driver 3010 is configured to drive the plurality of scan lines GL;
  • the data driver 3030 is for driving a plurality of data lines DL;
  • the timing controller 3020 is for processing the image data RGB input from the outside of the display device 30, and supplies the processed image data RGB to the data driver 3030.
  • the timing controller 3020 also uses The scan control signal GCS and the data control signal DCS are output to the gate driver 3010 and the data driver 3030 to control the gate driver 3010 and the data driver 3030.
  • gate driver 3010 includes gate drive circuit 20 as provided in any of the above embodiments.
  • the output terminal Output of the plurality of shift register units in the gate driving circuit 20 is connected in one-to-one correspondence with the plurality of scanning lines GL.
  • the plurality of scanning lines GL are connected to the pixel units P arranged in a plurality of rows.
  • the output terminal Output of each stage of the shift register unit in the gate driving circuit 20 sequentially outputs signals to the plurality of scanning lines GL to enable the progressive scanning of the plurality of rows of pixel units P in the display panel 3000.
  • the gate driver 3010 may be implemented as a semiconductor chip or may be integrated in the display panel 3000 to constitute a GOA circuit.
  • the data driver 3030 converts the digital image data RGB input from the timing controller 3020 into a data signal according to a plurality of data control signals DCS derived from the timing controller 3020 using the reference gamma voltage.
  • the data driver 3030 supplies the converted data signals to the plurality of data lines DL.
  • the data driver 3030 can be implemented as a semiconductor chip.
  • the timing controller 3020 processes the externally input image data RGB to match the size and resolution of the display panel 3000, and then supplies the processed image data to the data driver 3030.
  • the timing controller 3020 generates a plurality of scan control signals GCS and a plurality of data control signals DCS using synchronization signals (for example, a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) input from the outside of the display device 30. .
  • the timing controller 3020 supplies the generated scan control signal GCS and data control signal DCS to the gate driver 3010 and the data driver 3030, respectively, for control of the gate driver 3010 and the data driver 3030.
  • the display device 30 may also include other components, such as signal decoding circuits, voltage conversion circuits, etc., which may be, for example, conventional conventional components, and will not be described in detail herein.
  • At least one embodiment of the present disclosure also provides a driving method of a shift register unit, which can be used to drive a shift register unit provided by any embodiment of the present disclosure.
  • the driving method By using the driving method, the function of pre-charging can be realized without additionally adding a signal for controlling the pre-charging function, and the circuit structure adopted is simplified, which is advantageous for realizing narrow bezel and high resolution, and reducing cost, for example, at least one
  • the bidirectional scanning function can be realized without additionally adding a signal for controlling the scanning direction, which is advantageous for implementing narrow bezel wiring.
  • the driving method of the shift register unit 10 includes the following operations:
  • the first input circuit 100 charges the pull-up node PU to the first level in response to the first clock signal, and the output circuit 200 outputs the low level of the second clock signal to the output terminal Output;
  • the output circuit 200 outputs a high level of the second clock signal to the output terminal Output;
  • the output circuit 200 outputs a high level of the second clock signal to the output terminal Output;
  • the output circuit 200 outputs a low level of the second clock signal to the output terminal Output, and the first output pull-down circuit 300 performs noise reduction on the output terminal Output in response to the third clock signal;
  • the first input circuit 100 resets the pull-up node PU in response to the first clock signal, and the first output pull-down circuit 300 performs noise reduction on the output terminal in response to the third clock signal;
  • the first input circuit 100 resets the pull-up node PU in response to the first clock signal, and the second output pull-down circuit 700 denoises the output terminal under the control of the level of the pull-down node PD.
  • the level of the pull-up node PU becomes the second level, and the second level is higher than the first level.
  • the level of the pull-up node PU remains at the second level.
  • the level of the pull-up node PU becomes the first level due to the bootstrap effect of the first capacitor C1.
  • the level of the pull-up node PU is pulled down to a low level.
  • the driving method of the shift register unit 10 further includes:
  • the second input circuit 400 performs noise reduction on the pull-up node PU in response to the fourth clock signal
  • the second output pull-down circuit 700 performs noise reduction on the output terminal under the control of the level of the pull-down node PD.
  • the second input circuit 400 is responsive to the fourth clock signal to maintain the level of the pull-up node PU at the first level.
  • the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal have the same period, and the phase of the second clock signal is one quarter cycle later than the phase of the first clock signal, and the fourth clock The phase of the signal is one quarter of a cycle later than the phase of the second clock signal, and the phase of the third clock signal is one quarter of a cycle later than the phase of the fourth clock signal.
  • the shift register unit 10 when the display panel of the shift register unit 10 is used for reverse scanning, in the case where the shift register unit 10 includes the second output pull-down circuit 700, the shift register unit 10
  • the driving method includes the following operations:
  • the second input circuit 400 charges the pull-up node PU to the first level in response to the fourth clock signal, and the output circuit 200 outputs the low level of the second clock signal to the output terminal Output;
  • the output circuit 200 outputs a high level of the second clock signal to the output terminal Output;
  • the output circuit 200 outputs a high level of the second clock signal to the output terminal Output;
  • the output circuit 200 outputs a low level of the second clock signal to the output terminal Output, and the first output pull-down circuit 300 performs noise reduction on the output terminal Output in response to the third clock signal;
  • the second input circuit 400 resets the pull-up node PU in response to the fourth clock signal, and the first output pull-down circuit 300 performs noise reduction on the output terminal in response to the third clock signal;
  • the second input circuit 400 resets the pull-up node PU in response to the fourth clock signal, and the second output pull-down circuit 700 denoises the output terminal under the control of the level of the pull-down node PD.
  • the level of the pull-up node PU becomes the second level, and the second level is higher than the first level.
  • the level of the pull-up node PU remains at the second level.
  • the level of the pull-up node PU becomes the first level due to the bootstrap effect of the first capacitor C1.
  • the level of the pull-up node PU is pulled down to a low level.
  • the driving method of the shift register unit 10 further includes:
  • the first input circuit 100 denoises the pull-up node PU in response to the first clock signal
  • the second output pull-down circuit 700 denoises the output terminal under the control of the level of the pull-down node PD.
  • the first input circuit 100 is responsive to the fourth clock signal to maintain the level of the pull-up node PU at the first level.
  • the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal have the same period, and the phase ratio of the first clock signal
  • the phase of the second clock signal is one quarter of a cycle later
  • the phase of the third clock signal is one quarter of a cycle later than the phase of the first clock signal
  • the phase of the fourth clock signal is four quarters later than the phase of the third clock signal.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Shift Register Type Memory (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置，该移位寄存器单元(10)包括第一输入电路(100)、输出电路(200)和第一输出下拉电路(300)。所述第一输入电路(100)配置为响应于第一时钟信号(CK1)对上拉节点(PU)进行充电，以及响应于所述第一时钟信号(CK1)对所述上拉节点(PU)进行复位；所述输出电路(200)配置为在所述上拉节点(PU)的电平的控制下，将第二时钟信号(CK2)输出至输出端(Output)；所述第一输出下拉电路(300)配置为响应于第三时钟信号(CK3)对所述输出端(Output)进行降噪。

Description

移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
本申请要求于2018年05月16日递交的中国专利申请第201810470216.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置。
背景技术
在显示技术领域，例如液晶显示面板的像素阵列通常包括多行栅线和与之交错的多列数据线。对栅线的驱动可以通过栅极驱动电路实现。例如，栅极驱动电路可以通过绑定的集成驱动电路实现。近几年随着非晶硅薄膜晶体管或氧化物薄膜晶体管制备工艺的不断提高，也可以将栅极驱动电路直接集成在薄膜晶体管阵列基板上构成GOA(Gate-driver On Array)来对栅线进行驱动。例如，可以采用由多个级联的移位寄存器单元构成的GOA为像素阵列的多行栅线提供开关态电压信号，从而例如控制多行栅线依序打开，并且同时由数据线向像素阵列中对应行的像素单元提供数据信号，以控制各像素单元显示一帧图像。目前的显示面板越来越多地采用GOA技术来对栅线进行驱动。GOA技术有助于实现窄边框，并且可以降低生产成本。
发明内容
本公开至少一个实施例提供一种移位寄存器单元，包括第一输入电路、输出电路和第一输出下拉电路；其中，所述第一输入电路配置为响应于第一时钟信号对上拉节点进行充电，以及响应于所述第一时钟信号对所述上拉节点进行复位；所述输出电路配置为在所述上拉节点的电平的控制下，将第二时钟信号输出至输出端；所述第一输出下拉电路配置为响应于第三时钟信号对所述输出端进行降噪。
例如，在本公开一实施例提供的移位寄存器单元还包括第二输入电路，其中，所述第二输入电路配置为响应于第四时钟信号对所述上拉节点进行降噪。
例如，在本公开一实施例提供的移位寄存器单元还包括第一下拉节点控制电路和第二输出下拉电路；其中，所述第一下拉节点控制电路配置为在所述上拉节点的电平的控制下，对下拉节点的电平进行控制；所述第二输出下拉电路配置为在所述下拉节点的电平的控制下，对所述输出端进行降噪。
例如，在本公开一实施例提供的移位寄存器单元还包括第二下拉节点控制电路；所述第二下拉节点控制电路配置为响应于所述第二时钟信号对所述下拉节点的电平进行控制。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一输入电路包括第一晶体管；所述第一晶体管的栅极配置为和第一时钟信号端连接以接收所述第一时钟信号，所述第一晶体管的第一极配置为和第一输入端连接以接收第一输入信号，所述第一晶体管的第二极配置为和所述上拉节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出电路包括第二晶体管和第一电容；所述第二晶体管的栅极配置为和所述上拉节点连接，所述第二晶体管的第一极配置为和第二时钟信号端连接以接收所述第二时钟信号，所述第二晶体管的第二极配置为和所述输出端连接；所述第一电容的第一极配置为和所述第二晶体管的栅极连接，所述第一电容的第二极配置为和所述第二晶体管的第二极连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一输出下拉电路包括第三晶体管；所述第三晶体管的栅极配置为和第三时钟信号端连接以接收所述第三时钟信号，所述第三晶体管的第一极配置为和所述输出端连接，所述第三晶体管的第二极配置为和第一电压端连接以接收第一电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二输入电路包括第四晶体管；所述第四晶体管的栅极配置为和第四时钟信号端连接以接收所述第四时钟信号，所述第四晶体管的第一极配置为和所述上拉节点连接，所述第四晶体管的第二极配置为和第二输入端连接以接收第二输入信号。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一下拉节点控制电路包括第五晶体管；所述第五晶体管的栅极配置为和所述上拉节点连接，所述第五晶体管的第一极配置为和所述下拉节点连接，所述第五晶体管的第二极配置为和第一电压端连接以接收第一电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二输出下拉电路包括第六晶体管；所述第六晶体管的栅极配置为和所述下拉节点连接，所述 第六晶体管的第一极配置为和所述输出端连接，所述第六晶体管的第二极配置为和第一电压端连接以接收第一电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二下拉节点控制电路包括第二电容；所述第二电容的第一极配置为和所述下拉节点连接，所述第二电容的第二极配置为和第二时钟信号端连接以接收所述第二时钟信号。
本公开至少一个实施例还提供一种栅极驱动电路，包括本公开任一实施例所述的移位寄存器单元。
例如，在本公开一实施例提供的栅极驱动电路包括第一时钟信号线、第二时钟信号线、第三时钟信号线和第四时钟信号线；其中，在所述移位寄存器单元包括第二输入电路的情形下，所述移位寄存器单元还包括第一时钟信号端、第二时钟信号端、第三时钟信号端和第四时钟信号端，分别用于将所述第一至第四时钟信号输入所述第一输入电路、所述输出电路、所述第一输出下拉电路和所述第二输入电路；第4n-3级移位寄存器单元的第一时钟信号端和所述第一时钟信号线连接，第4n-3级移位寄存器单元的第二时钟信号端和所述第二时钟信号线连接，第4n-3级移位寄存器单元的第三时钟信号端和所述第三时钟信号线连接，第4n-3级移位寄存器单元的第四时钟信号端和所述第四时钟信号线连接；第4n-2级移位寄存器单元的第一时钟信号端和所述第二时钟信号线连接，第4n-2级移位寄存器单元的第二时钟信号端和所述第四时钟信号线连接，第4n-2级移位寄存器单元的第三时钟信号端和所述第一时钟信号线连接，第4n-2级移位寄存器单元的第四时钟信号端和所述第三时钟信号线连接；第4n-1级移位寄存器单元的第一时钟信号端和所述第四时钟信号线连接，第4n-1级移位寄存器单元的第二时钟信号端和所述第三时钟信号线连接，第4n-1级移位寄存器单元的第三时钟信号端和所述第二时钟信号线连接，第4n-1级移位寄存器单元的第四时钟信号端和所述第一时钟信号线连接；第4n级移位寄存器单元的第一时钟信号端和所述第三时钟信号线连接，第4n级移位寄存器单元的第二时钟信号端和所述第一时钟信号线连接，第4n级移位寄存器单元的第三时钟信号端和所述第四时钟信号线连接，第4n级移位寄存器单元的第四时钟信号端和所述第二时钟信号线连接；n为大于0的整数。
本公开至少一个实施例还提供一种显示装置，包括本公开任一实施例所述的栅极驱动电路。
本公开至少一个实施例还提供一种本公开任一实施例所述的移位寄存器 单元的驱动方法，在所述移位寄存器单元包括第二输出下拉电路的情形下，所述驱动方法包括：第一阶段，所述第一输入电路响应于所述第一时钟信号对所述上拉节点充电至第一电平，所述输出电路输出所述第二时钟信号的低电平至所述输出端；第二阶段，所述输出电路输出所述第二时钟信号的高电平至所述输出端；第三阶段，所述输出电路输出所述第二时钟信号的高电平至所述输出端；第四阶段，所述输出电路输出所述第二时钟信号的低电平至所述输出端，且所述第一输出下拉电路响应于所述第三时钟信号对所述输出端进行降噪；第五阶段，所述第一输入电路响应于所述第一时钟信号对所述上拉节点进行复位，所述第一输出下拉电路响应于所述第三时钟信号对所述输出端进行降噪；第六阶段，所述第一输入电路响应于所述第一时钟信号对所述上拉节点进行复位，所述第二输出下拉电路在所述下拉节点的电平的控制下对所述输出端进行降噪。
例如，在本公开一实施例提供的移位寄存器单元的驱动方法中，在所述移位寄存器单元还包括第二输入电路的情况下，所述驱动方法还包括：第七阶段，所述第二输入电路响应于第四时钟信号对所述上拉节点进行降噪，所述第二输出下拉电路在所述下拉节点的电平的控制下对所述输出端进行降噪。
例如，在本公开一实施例提供的移位寄存器单元的驱动方法中，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号具有相同的周期，所述第二时钟信号的相位比所述第一时钟信号的相位晚四分之一个周期，所述第四时钟信号的相位比所述第二时钟信号的相位晚四分之一个周期，所述第三时钟信号的相位比所述第四时钟信号的相位晚四分之一个周期。
本公开至少一个实施例还提供一种本公开任一实施例所述的移位寄存器单元的驱动方法，在所述移位寄存器单元包括第二输出下拉电路的情形下，所述驱动方法包括：第一阶段，所述第二输入电路响应于所述第四时钟信号对所述上拉节点充电至第一电平，所述输出电路输出所述第二时钟信号的低电平至所述输出端；第二阶段，所述输出电路输出所述第二时钟信号的高电平至所述输出端；第三阶段，所述输出电路输出所述第二时钟信号的高电平至所述输出端；第四阶段，所述输出电路输出所述第二时钟信号的低电平至所述输出端，且所述第一输出下拉电路响应于所述第三时钟信号对所述输出端进行降噪；第五阶段，所述第二输入电路响应于所述第四时钟信号对所述上拉节点进行复位，所述第一输出下拉电路响应于所述第三时钟信号对所述输出端进行降噪； 第六阶段，所述第二输入电路响应于所述第四时钟信号对所述上拉节点进行复位，所述第二输出下拉电路在所述下拉节点的电平的控制下对所述输出端进行降噪。
例如，在本公开一实施例提供的移位寄存器单元的驱动方法包括：第七阶段，所述第一输入电路响应于所述第一时钟信号对所述上拉节点进行降噪，所述第二输出下拉电路在所述下拉节点的电平的控制下对所述输出端进行降噪。
例如，在本公开一实施例提供的移位寄存器单元的驱动方法中，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号具有相同的周期，所述第一时钟信号的相位比所述第二时钟信号的相位晚四分之一个周期，所述第三时钟信号的相位比所述第一时钟信号的相位晚四分之一个周期，所述第四时钟信号的相位比所述第三时钟信号的相位晚四分之一个周期。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一实施例提供的一种移位寄存器单元的示意框图；
图2为本公开一实施例提供的另一种移位寄存器单元的示意框图；
图3为本公开一实施例提供的又一种移位寄存器单元的示意框图；
图4为图3中所示的移位寄存器单元的一种具体实现示例的电路图；
图5为本公开一实施例提供的一种移位寄存器单元的信号时序图；
图6为本公开一实施例提供的另一种移位寄存器单元的信号时序图；
图7为本公开一实施例提供的一种栅极驱动电路的示意框图；
图8为本公开一实施例提供的一种栅极驱动电路的信号时序图；
图9为本公开一实施例提供的一种显示装置的示意框图；以及
图10本公开一实施例提供的另一种显示装置的示意框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的 本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着显示面板相关产品的应用越来越多，对显示面板的需求也日益多样化。例如，一部分客户希望显示面板能实现预充电的功能，以缩短数据写入时间，提高数据写入的准确性。例如，另一部分客户希望显示面板中的栅极驱动电路具有尽量简单的电路结构，采用尽量少的元器件，以便于实现窄边框和高分辨率显示面板的布线。例如，再一部分客户希望显示面板既能正向扫描又能反向扫描，以实现双向扫描功能，以使显示面板无论正放还是倒放，都能显示正立的图像。这些多样化的需求对栅极驱动电路的设计提出了挑战。
本公开至少一实施例提供一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置。该移位寄存器单元中的晶体管数量少，与传统移位寄存器单元相比不需要额外增加用于控制预充电功能的信号即可实现预充电的功能，电路结构简化，有利于实现窄边框和高分辨率，降低成本，例如，至少一个实施例的移位寄存器单元不需要额外增加用于控制扫描方向的信号即可以实现双向扫描功能，有利于实现窄边框布线。
下面，将参考附图详细地说明本公开的实施例。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
本公开至少一实施例提供一种移位寄存器单元，包括第一输入电路、输出电路和第一输出下拉电路。所述第一输入电路配置为响应于第一时钟信号对上拉节点进行充电，以及响应于所述第一时钟信号对所述上拉节点进行复位；所述输出电路配置为在所述上拉节点的电平的控制下，将第二时钟信号输出至输 出端；所述第一输出下拉电路配置为响应于第三时钟信号对所述输出端进行降噪。
图1为本公开一实施例提供的一种移位寄存器单元的示意框图。参考图1，该移位寄存器单元10包括第一输入电路100、输出电路200和第一输出下拉电路300。
第一输入电路100配置为响应于第一时钟信号对上拉节点PU进行充电，以及响应于第一时钟信号对上拉节点PU进行复位。例如，第一输入电路100与第一时钟信号端CK1和上拉节点PU连接，配置为在第一时钟信号端CK1提供的第一时钟信号的控制下使上拉节点PU和另外提供的第一输入端电连接，从而可以使第一输入端输出的高电平信号对上拉节点PU进行充电，以使得上拉节点PU的电压增加以控制输出电路200导通，另外，第一输入电路100还被配置为在第一时钟信号端CK1提供的第一时钟信号的控制下使第一输入端输出的低电平信号对上拉节点PU进行复位，以使得上拉节点PU的电压降低以控制输出电路200关闭。例如，第一输入端连接到触发信号线或者与包含该第一输入电路100的本级移位寄存器单元10相邻的上一级移位寄存器单元10的输出端Output。第一输入端提供的第一输入信号为提供给该级移位寄存器单元10的触发信号。
在本公开实施例提供的移位寄存器单元中，第一输入电路100既可以对上拉节点PU充电，又可以对上拉节点PU复位，从而使该移位寄存器单元10不需要单独设置上拉节点PU的复位电路，简化了电路结构。
输出电路200配置为在上拉节点PU的电平的控制下，将第二时钟信号输出至该移位寄存器单元10的输出端Output，作为该移位寄存器单元10的输出信号，以驱动例如与该输出端Output连接的栅线。例如，输出电路200与第二时钟信号端CK2、上拉节点PU和输出端Output连接，配置为在上拉节点PU的电平的控制下导通，使第二时钟信号端CK2和输出端Output电连接，从而可以将输入第二时钟信号端CK2的第二时钟信号输出至输出端Output。
第一输出下拉电路300配置为响应于第三时钟信号对输出端Output进行降噪。例如，第一输出下拉电路300与第三时钟信号端CK3、输出端Output以及第一电压端(例如，第一电压端可以为低电压端，从而第一电压端输出的第一电压为低电压)连接，配置为在第三时钟信号端CK3提供的第三时钟信号的控制下使输出端Output和该第一电压端电连接，从而可以使第一电压端输出 的低电平的第一电压对输出端Output进行降噪。
图2为本公开一实施例提供的另一种移位寄存器单元的示意框图。参考图2，该实施例中，移位寄存器单元10还包括第二输入电路400，移位寄存器单元10中的其他结构(例如，第一输入电路100、输出电路200和第一输出下拉电路300)与图1中所示的移位寄存器单元10基本上相同。
第二输入电路400配置为响应于第四时钟信号对上拉节点PU进行降噪。例如，第二输入电路400与第四时钟信号端CK4和上拉节点PU连接，配置为在第四时钟信号端CK4提供的第四时钟信号的控制下使上拉节点PU和另外提供的第二输入端电连接，从而可以使第二输入端输出的低电平信号对上拉节点PU进行降噪。例如，第二输入端连接到与包含该第二输入电路400的本级移位寄存器单元10相邻的下一级移位寄存器单元10的输出端Output或触发信号线。例如，在需要使上拉节点PU保持低电位的阶段，第二输入电路400和第一输入电路100彼此配合，交替对上拉节点PU进行降噪或复位，且对上拉节点PU进行降噪或复位的时间包括第二时钟信号处于高电平的时间，从而确保上拉节点PU保持低电位，以避免由于第二时钟信号而输出端Output的信号产生毛刺等不良。
例如，第二输入电路400与第一输入电路100的电路结构相似或对称设置，通过时钟信号(第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号)和输入信号(例如，第一输入信号和第二输入信号)的相互配合，该移位寄存器单元10可以用于双向扫描，从而可以减少了控制信号，利于窄边框和高分辨率。当采用该移位寄存器单元10的显示面板进行正向扫描时，使触发信号或由上一级移位寄存器单元10提供的信号由第一输入端输入，其操作如上所述。在另一个示例中，当采用该移位寄存器单元10的显示面板进行反向扫描时，使触发信号或由下一级移位寄存器单元10提供的信号改由第二输入端输入。此时，第二输入电路400配置为响应于第四时钟信号对上拉节点PU进行充电，以及响应于第四时钟信号对上拉节点PU进行复位；而第一输入电路100配置为响应于第一时钟信号对上拉节点PU进行降噪。该电路不需要额外的信号(例如，扫描方向控制信号)即可以实现双向扫描功能，简化了电路结构及扫描控制方式。
需要说明的是，本公开的各实施例中，正向扫描和反向扫描的方向是相对的，可以将双向扫描中沿任意一个第一方向的扫描称为正向扫描，将沿与该第 一方向相对的第二方向的扫描称为反向扫描。例如，若第一方向表示从显示面板的第一行栅线扫描至显示面板的最后一行栅线的方向，则第二方向则可以表示从显示面板的最后一行栅线扫描至显示面板的第一行栅线的方向。
图3为本公开一实施例提供的另一种移位寄存器单元的示意框图。参考图3，该实施例的移位寄存器单元10还包括第一下拉节点控制电路500、第二下拉节点控制电路600和第二输出下拉电路700，该移位寄存器单元10的其他结构(例如，第一输入电路100、输出电路200、第一输出下拉电路300和第二输入电路400)与图2中所示的移位寄存器单元10基本上相同。
第一下拉节点控制电路500配置为在上拉节点PU的电平的控制下，对下拉节点PD的电平进行控制。例如，第一下拉节点控制电路500与上拉节点PU和下拉节点PD连接，配置为在上拉节点PU的电平的控制下使下拉节点PD和另外提供的低电压端(例如，第一电压端)电连接，从而可以使低电压端输出的低电平信号对下拉节点PD的电平进行控制，例如，使下拉节点PD的电平为低电平。
第二下拉节点控制电路600配置为响应于第二时钟信号对下拉节点PD的电平进行控制。例如，第二下拉节点控制电路600与第二时钟信号端CK2和下拉节点PD连接，配置为在第二时钟信号端CK2提供的第二时钟信号的控制下，使下拉节点PD的电平随着第二时钟信号的电平而变化，例如，使下拉节点PD的电平交替为高电平和低电平。
第二输出下拉电路700配置为在下拉节点PD的电平的控制下，对输出端Output进行降噪。例如，第二输出下拉电路700与下拉节点PD和输出端Output连接，配置为在下拉节点PD的电平的控制下使输出端Output和另外提供的低电压端(例如，第一电压端)电连接，从而可以使低电压端输出的低电平信号对输出端Output进行降噪。例如，第二输出下拉电路700和第一输出下拉电路300彼此配合，交替对输出端Output进行降噪，例如实现对输出端Output的双下拉，从而使用于下拉的晶体管的工作占空比都小于50％，提高该电路和采用该电路的显示面板的可靠性。
图4为图3中所示的移位寄存器单元的一种具体实现示例的电路图。在下面的说明中以各晶体管为N型晶体管为例进行说明，但这并不构成对本公开实施例的限制。同时，在本公开下面对于各实施例的描述中，以各晶体管(例如，下面描述的第一至第六晶体管T1-T6)均为N型晶体管为例，因此，“有效电 平”表示高电平。但本公开不限于此，当各晶体管(例如，下面描述的第一至第六晶体管T1-T6)均为P型晶体管时，“有效电平”则表示低电平。
参考图4，该移位寄存器单元10包括第一至第六晶体管T1-T6、第一电容C1和第二电容C2。
第一输入电路100可以实现为第一晶体管T1。第一晶体管T1的栅极配置为和第一时钟信号端CK1连接以接收第一时钟信号，第一晶体管T1的第一极配置为和第一输入端Input1连接以接收第一输入信号，第一晶体管T1的第二极配置为和上拉节点PU连接。第一晶体管T1在第一时钟信号为有效电平(例如，高电平)时导通，使第一输入端Input1和上拉节点PU电连接，从而可以对上拉节点PU进行充电或复位。例如，在第一晶体管T1导通的情形下，第一输入信号为高电平时可以对上拉节点PU进行充电，而第一输入信号为低电平时可以对上拉节点PU进行复位。例如，在另一个示例中，当采用该移位寄存器单元10的显示面板进行反向扫描时，第一晶体管T1在第一时钟信号为有效电平时导通，从而使第一输入端Input1的第一输入信号对上拉节点PU进行降噪。
输出电路200可以实现为第二晶体管T2和第一电容C1。第二晶体管T2的栅极配置为和上拉节点PU连接，第二晶体管T2的第一极配置为和第二时钟信号端CK2连接以接收第二时钟信号，第二晶体管T2的第二极配置为和输出端Output连接。第一电容C1的第一极配置为和第二晶体管T2的栅极连接，第一电容C1的第二极配置为和第二晶体管T2的第二极连接。当上拉节点PU为有效电平(例如，高电平)时，第二晶体管T2导通，从而将第二时钟信号输出至输出端Output。
需要说明的是，第一电容C1可以是通过工艺制程制作在显示面板上的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现，并且，第一电容C1也可以是晶体管之间的寄生电容，可以通过晶体管本身与其他器件、线路来实现。例如，在一个示例中，第一电容C1为寄生电容，因此输出电路200只包括第二晶体管T2，而无特别制作的电容器件。这样可以简化工艺，降低生产成本，提高生产效率。
第一输出下拉电路300可以实现为第三晶体管T3。第三晶体管T3的栅极配置为和第三时钟信号端CK3连接以接收第三时钟信号，第三晶体管T3的第 一极配置为和输出端Output连接，第三晶体管T3的第二极配置为和第一电压端VGL连接以接收第一电压。例如，第一电压端VGL配置为提供直流低电平信号(例如低于或等于时钟信号的低电平部分)，例如接地，将该直流低电平信号称为第一电压，以下各实施例与此相同，不再赘述。当第三时钟信号为有效电平时，第三晶体管T3导通，使输出端Output和第一电压端VGL电连接，从而对输出端Output进行降噪，使其处于低电平。
第二输入电路400可以实现为第四晶体管T4。第四晶体管T4的栅极配置为和第四时钟信号端CK4连接以接收第四时钟信号，第四晶体管T4的第一极配置为和上拉节点PU连接，第四晶体管T4的第二极配置为和第二输入端Input2连接以接收第二输入信号。第四晶体管T4在第四时钟信号为有效电平(例如，高电平)时导通，使第二输入端Input2和上拉节点PU电连接，从而可以对上拉节点PU进行降噪。例如，在另一个示例中，当采用该移位寄存器单元10的显示面板进行反向扫描时，第四晶体管T4在第四时钟信号为有效电平时导通，从而利用第二输入端Input2输出的高电平的第二输入信号对上拉节点PU进行充电，另外，还可以利用第二输入端Input2输出的低电平的第二输入信号对上拉节点PU进行复位。
第一下拉节点控制电路500可以实现为第五晶体管T5。第五晶体管T5的栅极配置为和上拉节点PU连接，第五晶体管T5的第一极配置为和下拉节点PD连接，第五晶体管T5的第二极配置为和第一电压端VGL连接以接收第一电压。当上拉节点PU为有效电平时，第五晶体管T5导通，使下拉节点PD和第一电压端VGL电连接，从而对下拉节点PD的电平进行下拉，使其处于低电平。
第二下拉节点控制电路600可以实现为第二电容C2。第二电容C2的第一极配置为和下拉节点PD连接，第二电容C2的第二极配置为和第二时钟信号端CK2连接以接收第二时钟信号。在第五晶体管T5截止的情形下，下拉节点PD处于浮置状态，由于第二电容C2的自举效应，下拉节点PD的电平会随着第二时钟信号的电平而变化，例如，当第二时钟信号的电平在高电平和低电平之间交替变化时，下拉节点PD的电平交替变为高电平和低电平，相应地控制后面所述的第六晶体管T6导通和截止。
第二输出下拉电路700可以实现为第六晶体管T6。第六晶体管T6的栅极配置为和下拉节点PD连接，第六晶体管T6的第一极配置为和输出端Output 连接，第六晶体管T6的第二极配置为和第一电压端VGL连接以接收第一电压。当下拉节点PD的电平为有效电平(例如，高电平)时，第六晶体管T6导通，使输出端Output和第一电压端VGL电连接，从而对输出端Output进行降噪，使其处于低电平。例如，下拉节点PD的电平和第三时钟信号的电平可以交替为有效电平，从而使第六晶体管T6和第三晶体管T3交替导通，以实现对输出端Output的双下拉，确保输出端Output处于低电平。并且，第六晶体管T6和第三晶体管T3在整帧扫描过程中受约50％的应力，这样可以减缓器件的性能退化，防止阈值电压偏移。
需要注意的是，在本公开的各个实施例的说明中，上拉节点PU和下拉节点PD并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，在本公开的实施例中的晶体管均以N型晶体管为例进行说明，此时，晶体管的第一极是漏极，第二极是源极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器单元10中的一个或多个晶体管也可以采用P型晶体管，此时，晶体管第一极是源极，第二极是漏极。例如，在另一些实施例中，当各晶体管(例如，下面描述的第一至第六晶体管T1-T6)均为P型晶体管时，将选定类型的各晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接，且第一电压端VGL配置为提供直流高电平信号(例如高于或等于时钟信号的高电平部分)。当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
图5为本公开一实施例提供的一种移位寄存器单元的信号时序图。下面结合图5所示的信号时序图，对图4所示的移位寄存器单元10的工作原理进行说明，并且这里以各个晶体管为N型晶体管为例进行说明，但是本公开的实施例不限于此。在图中以及下面的描述中，CK1、CK2、CK3、CK4、STV、Input1、 Input2等既用于表示相应的信号端，也用于分别表示第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号和触发信号等。
在图5所示的第一阶段1、第二阶段2、第三阶段3、第四阶段4、第五阶段5、第六阶段6以及第七阶段7共七个阶段中，该移位寄存器单元10可以分别进行如下操作。
在第一阶段1，第一时钟信号CK1的电平和第三时钟信号为CK3的电平为高电平，第二时钟信号CK2的电平和第四时钟信号CK4的电平为低电平。第一输入端Input1提供高电平的第一输入信号Input1。第一晶体管T1在第一时钟信号CK1的高电平的作用下导通，第一输入信号Input1开始对上拉节点PU进行充电，从而使上拉节点PU的电位升高，最终上拉节点PU被充电至第一电平，且第一电平为高电平。由于上拉节点PU的电平为高电平，第五晶体管T5导通，从而下拉节点PD与第一电源端VGL连接，从而下拉节点PD处于低电平。第二晶体管T2也导通，将第二时钟信号CK2输出至输出端Output。第三晶体管T3在第三时钟信号CK3的高电平的作用下导通，将第一电压(第一电压端VGL提供)输出至输出端Output。由于在第一阶段1，第二时钟信号CK2的电平和第一电压的电平均为低电平，因此输出端Output的电平也为低电平。由于第四时钟信号CK4的电平为低电平，第四晶体管T4截止。第六晶体管T6在下拉节点PD的低电平的作用下截止。
在第二阶段2，第一时钟信号CK1的电平保持为高电平，第二时钟信号CK2的电平变为高电平，第三时钟信号CK3的电平变为低电平，第四时钟信号CK4的电平保持为低电平。第二晶体管T2仍然保持导通，将第二时钟信号CK2的高电平输出至输出端Output，由于第二时钟信号CK2的电平变为高电平，因此，输出端Output的电平变为高电平。由于第一电容C1的自举效应，为了保持第一电容C1两极之间的电压差不变，上拉节点PU的电位被进一步拉高。例如，此时上拉节点PU的电平为第二电平，第二电平也为高电平，且第二电平高于第一电平。由此。第二晶体管T2充分导通。由于上拉节点PU的电平被进一步拉高至第二电平，使得上拉节点PU的电平高于第一晶体管T1栅极的电平(即第一时钟信号CK1的电平)，第一晶体管T1被饱和截止。第五晶体管T5在上拉节点PU的高电平的作用下保持导通，使下拉节点PD仍然为低电平。由于，第三时钟信号CK3的电平变为低电平，第三晶体管T3截止。此时，第四晶体管T4和第六晶体管T6均截止。
在第三阶段3，第一时钟信号CK1的电平变为低电平，第二时钟信号CK2的电平保持为高电平，第三时钟信号CK3的电平保持为低电平，第四时钟信号CK4的电平变为高电平。此时，第一晶体管T1截止。上拉节点PU保持上一阶段的电平(即第二电平)，第二晶体管T2保持导通，第二时钟信号CK2的高电平继续输出到输出端Output。第五晶体管T5在上拉节点PU的高电平的作用下保持导通，使下拉节点PD的电平仍然为低电平。第六晶体管T6保持截止。由于第三时钟信号CK3的电平保持为低电平，第三晶体管T3保持截止。虽然第四时钟信号CK4的电平变为高电平，第二输入信号端Input2提供高电平信号，然而此时上拉节点PU的电平为第二电平，高于第四晶体管T4的栅极的电平(即第四时钟信号CK4的电平)，因此第四晶体管T4被饱和截止。
在第四阶段4，第一时钟信号CK1的电平保持为低电平，第二时钟信号CK2的电平变为低电平，第三时钟信号CK3的电平变为高电平，第四时钟信号CK4的电平保持为高电平。此时，第二晶体管T2保持导通，输出端Output通过第二晶体管T2完成下拉，从而输出端Output的电平为低电平，由于第一电容C1的自举效应，为了保持第一电容C1两极之间的电压差不变，上拉节点PU的电平变为第一电平，另外，由于第四时钟信号CK4的电平保持为高电平，第二输入信号Input2的电平为高电平，当上拉节点PU的电平变为第一电平时，第四晶体管T4导通，第二输入信号Input2可以上拉阶段PU进行充电，以使上拉节点PU维持在第一电平，此时上拉节点PU仍然能使第二晶体管T2导通。也就是说，在本公开中，第二晶体管T2可以对输出端Output进行上拉，也可以对输出端Output进行下拉。例如，第二晶体管T2为尺寸较大的薄膜晶体管，因此下拉时间短。由于第三时钟信号CK3的电平变为高电平，第三晶体管T3导通。第三晶体管T3也对输出端Output进行下拉，并使其维持输出低电平，使得输出信号的精度高。由于第二晶体管T2可以实现快速下拉输出端Output的电位，从而可以适当减小或者采用最小尺寸的用于下拉输出端Output的电位的第三晶体管T3和第六晶体管T6，利于窄边框和高分辨率。第五晶体管T5保持导通，使下拉节点PD的电平仍然为低电平。第一晶体管T1和第六晶体管T6保持截止。
在第五阶段5，第一时钟信号CK1的电平变为高电平，第二时钟信号CK2的电平保持为低电平。此时，第一晶体管T1导通，第一输入端Input1提供低 电平信号，从而对上拉节点PU进行复位，使上拉节点PU的电平变为低电平。第二晶体管T2和第五晶体管T5在上拉节点PU的低电平的作用下截止。由于第三时钟信号CK3的电平为高电平，第三晶体管T3保持导通，利用第一电压端的第一电压对输出端Output进行降噪。第四时钟信号CK4的电平变为低电平，第四晶体管T4截止。下拉节点PD保持上一阶段(即第四阶段4)的电平(即低电平)，第六晶体管T6保持截止。
在第六阶段6，第一时钟信号CK1的电平保持为高电平，第一晶体管T1保持导通，维持上拉节点PU的电平为低电平，以减小第二时钟信号CK2的高电平通过寄生电容对上拉节点PU的影响，从而避免输出端Output的信号产生毛刺等不良。第三时钟信号CK3的电平变为低电平，第三晶体管T3截止。第四时钟信号CK4保持为低电平，第四晶体管T4截止。由于上拉节点PU的电平为低电平，第二晶体管T2和第五晶体管T5保持截止。第二时钟信号CK2的电平变为高电平，由于第二电容C2的自举效应，下拉节点PD的电平也变为高电平，从而使第六晶体管T6导通，利用第一电压端的第一电压对输出端Output进行降噪。
在第七阶段7，第四时钟信号CK4的电平变为高电平，第四晶体管T4导通，第二输入端Input2提供低电平信号，以维持上拉节点PU的低电平，从而减小第二时钟信号CK2的高电平通过寄生电容对上拉节点PU的影响，避免输出端Output的信号产生毛刺等不良。第一时钟信号CK1的电平变为低电平，第一晶体管T1截止。第三时钟信号CK3保持为低电平，第三晶体管T3、截止。由于上拉节点PU的电平为低电平，第二晶体管T2、第五晶体管T5保持截止。第二时钟信号CK2的电平保持为高电平，第六晶体管T6保持导通，以利用第一电压端的第一电压对输出端Output进行降噪。
在第七阶段7之后的后续阶段，下拉节点PD的电平随着第二时钟信号CK2的电平而变化，第三时钟信号CK3的电平和下拉节点PD的电平彼此反相，从而使第六晶体管T6和第三晶体管T3交替导通，以对输出端Output持续降噪，维持输出端Output的低电平。这种双下拉的方式可以提高该电路和采用该电路的显示面板的可靠性。并且，第六晶体管T6和第三晶体管T3在整帧扫描过程中受约50％的应力，这样可以减缓器件的性能退化，防止阈值电压偏移。由于在第四阶段4，第二时钟信号CK2的电平变为低电平时，输出端Output通过第二晶体管T2完成下拉，第六晶体管T6和第三晶体管T3只起保持作用，因 此第六晶体管T6和第三晶体管T3的尺寸可以适当减小，不仅可以降低功耗，还可以减小该电路的设置空间，有利于实现窄边框和高分辨率。
在第七阶段7之后的后续阶段，由于第一时钟信号CK1和第四时钟信号CK4彼此反相，第一晶体管T1和第四晶体管T4交替导通，以对上拉节点PU进行降噪，维持上拉节点PU的低电平。这样可以减小第二时钟信号CK2的高电平通过寄生电容对上拉节点PU的影响，避免输出端Output的信号产生毛刺等不良。并且，第一晶体管T1和第四晶体管T4在整帧扫描过程中受约50％的应力，这样可以减缓器件的性能退化，防止阈值电压偏移。
例如，该移位寄存器单元10进行正向扫描时，其工作原理如上对第一阶段1至第七阶段7的相关描述。第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3和第四时钟信号CK4具有相同的周期。而且，如图5所示，第二时钟信号CK2的相位比第一时钟信号CK1的相位晚四分之一个周期，第四时钟信号CK4的相位比第二时钟信号CK2的相位晚四分之一个周期，第三时钟信号CK3的相位比第四时钟信号CK4的相位晚四分之一个周期。第一时钟信号CK1和第四时钟信号CK4彼此反相，第二时钟信号CK2和第三时钟信号CK3彼此反相。
例如，在正向扫描时，第一输入端Input1、输出端Output和第二输入端Input2的信号为3个相邻的级联的移位寄存器单元10的输出信号，任意2个相邻的移位寄存器单元10的输出信号彼此部分重叠且重叠时间为时钟信号高电平脉宽的一半，以实现预充电的功能。与传统的具有预充电功能的电路相比，该移位寄存器单元10不需要额外增加的信号，多个移位寄存器单元10之间的连接关系简化，有利于实现窄边框和高分辨率。
例如，该移位寄存器单元10进行反向扫描时，其信号时序图如图6所示，其工作原理与正向扫描时的工作原理类似，将提供给该级移位寄存器单元10的触发信号改由第二输入端Input2输入即可，此处不再赘述。
需要注意的是，在反向扫描时，第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3和第四时钟信号CK4彼此之间的相位关系与正向扫描时彼此之间的相位关系不同。如图6所示，第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3和第四时钟信号CK4具有相同的周期。第一时钟信号CK1的相位比第二时钟信号CK2的相位晚四分之一个周期，第三时钟信号CK3的相位比第一时钟信号CK1的相位晚四分之一个周期，第四时钟信号CK4的相 位比第三时钟信号CK3的相位晚四分之一个周期。第一时钟信号CK1和第四时钟信号CK4彼此反相，第二时钟信号CK2和第三时钟信号CK3彼此反相。
该移位寄存器单元10通过上述四个时钟信号和提供给该级移位寄存器单元10的触发信号的时序匹配，不需要额外的信号(例如，扫描方向控制信号)即可以实现双向扫描功能，简化了电路结构及扫描控制方式。例如，上述四个时钟信号可以通过时序控制器T-CON产生，易于实现。
本公开至少一实施例还提供一种栅极驱动电路。该栅极驱动电路包括本公开任一实施例所述的移位寄存器单元。该栅极驱动电路中的晶体管数量少，不需要额外增加用于控制预充电功能的信号即可实现预充电的功能，电路结构简化，有利于实现窄边框和高分辨率，降低成本，例如，至少一个实施例的栅极驱动电路不需要额外增加用于控制扫描方向的信号即可以实现双向扫描功能，有利于实现窄边框布线。
图7为本公开一实施例提供的一种栅极驱动电路的示意框图。参考图7，该栅极驱动电路20包括多个级联的移位寄存器单元(SR1、SR2、SR3、SR4、···、SRn)。多个移位寄存器单元的数量不受限制，可以根据实际需求而定。例如，对于分辨率640×480的显示装置，移位寄存器单元的数量可以为480，对应地，对于分辨率为1920×1440的显示装置，移位寄存器单元的数量可以为1440。例如，移位寄存器单元采用本公开任一实施例所述的移位寄存器单元10。例如，在栅极驱动电路20中，可以部分或全部移位寄存器单元采用本公开任一实施例所述的移位寄存器单元10。例如，该栅极驱动电路20可以采用与薄膜晶体管同样制程的工艺直接集成在显示装置的阵列基板上，以实现逐行扫描驱动功能。
例如，每个移位寄存器单元具有第一输入端Input1、第二输入端Input2、第一至第四时钟信号端CK1-CK4、第一电压端VGL和输出端Output。例如，除第一级以外，每一级移位寄存器单元的输出端Output与相邻上一级移位寄存器单元的第二输入端Input2连接。例如，除最后一级以外，每一级移位寄存器单元的输出端Output与相邻下一级移位寄存器单元的第一输入端Input1连接。例如，当栅极驱动电路实现正向扫描时，第一级移位寄存器单元的第一输入端Input1配置为与触发信号线STV连接以接收触发信号STV；最后一级移位寄存器单元的第二输入端Input2配置为与触发信号线STV连接以接收对应的信号，例如触发信号STV，且触发信号STV为有效电平时，第一时钟信号CK1 也为有效电平。当栅极驱动电路实现反向扫描时，向上述最后一级移位寄存器单元的第二输入端Input2提供触发信号STV，向上述第一级移位寄存器单元的第一输入端Input1提供对应的信号，例如触发信号STV，且触发信号STV为有效电平时，第二时钟信号CK2也为有效电平。
例如，该栅极驱动电路20还包括第一时钟信号线CK_1、第二时钟信号线CK_2、第三时钟信号线CK_3和第四时钟信号线CK_4。例如，在栅极驱动电路20中，每4个移位寄存器单元为一个级联重复单元，具体连接方式如下，其他移位寄存器单元的级联方式以此类推。
第4n-3级移位寄存器单元(例如，第一级移位寄存器单元SR1)的第一时钟信号端CK1和第一时钟信号线CK_1连接，第4n-3级移位寄存器单元第二时钟信号端CK2和第二时钟信号线CK_2连接，第4n-3级移位寄存器单元第三时钟信号端CK3和第三时钟信号线CK_3连接，第4n-3级移位寄存器单元第四时钟信号端CK4和第四时钟信号线CK_4连接。
第4n-2级移位寄存器单元(例如，第二级移位寄存器单元SR2)的第一时钟信号端CK1和第二时钟信号线CK_2连接，第4n-2级移位寄存器单元第二时钟信号端CK2和第四时钟信号线CK_4连接，第4n-2级移位寄存器单元第三时钟信号端CK3和第一时钟信号线CK_1连接，第4n-2级移位寄存器单元第四时钟信号端CK4和第三时钟信号线CK_3连接。
第4n-1级移位寄存器单元(例如，第三级移位寄存器单元SR3)的第一时钟信号端CK1和第四时钟信号线CK_4连接，第4n-1级移位寄存器单元第二时钟信号端CK2和第三时钟信号线CK_3连接，第4n-1级移位寄存器单元第三时钟信号端CK3和第二时钟信号线CK_2连接，第4n-1级移位寄存器单元第四时钟信号端CK4和第一时钟信号线CK_1连接。
第4n级移位寄存器单元(例如，第四级移位寄存器单元SR4)的第一时钟信号端CK1和第三时钟信号线CK_3连接，第4n级移位寄存器单元第二时钟信号端CK2和第一时钟信号线CK_1连接，第4n级移位寄存器单元第三时钟信号端CK3和第四时钟信号线CK_4连接，第4n级移位寄存器单元第四时钟信号端CK4和第二时钟信号线CK_2连接。
这里，n为大于0的整数。
在正向扫描和反向扫描时，第一时钟信号线CK_1、第二时钟信号线CK_2、第三时钟信号线CK_3和第四时钟信号线CK_4提供的信号彼此之间的相位关 系有所不同，具体参见移位寄存器单元10的工作原理的描述，此处不再赘述。
例如，该栅极驱动电路20还可以包括时序控制器T-CON，时序控制器T-CON例如配置为向各级移位寄存器单元提供第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号，时序控制器T-CON还可以配置为提供触发信号。需要注意的是，在正向扫描和反向扫描时，时序控制器T-CON提供的多个时钟信号彼此之间的相位关系有所不同。在不同的示例中，根据不同的配置，还可以提供更多的时钟信号，例如6个、8个等。本公开对此不作限制。
例如，该栅极驱动电路20还包括第一电压线VGL1，以向各个移位寄存器单元提供第一电压。
例如，当采用该栅极驱动电路20驱动一显示面板时，可以将该栅极驱动电路20设置于显示面板的一侧。例如，该显示面板包括多行栅线，栅极驱动电路20中的各级移位寄存器单元的输出端Output可以配置为依序和多行栅线连接，以用于向各行栅线输出栅极扫描信号。当然，还可以分别在显示面板的两侧设置该栅极驱动电路20，以实现双边驱动，本公开的实施例对栅极驱动电路20的设置方式不作限定。例如，可以在显示面板的一侧设置栅极驱动电路20以用于驱动奇数行栅线，而在显示面板的另一侧设置栅极驱动电路20以用于驱动偶数行栅线。
图8为本公开一实施例提供的一种栅极驱动电路的信号时序图。参考图8，第一时钟信号线CK_1、第二时钟信号线CK_2、第三时钟信号线CK_3和第四时钟信号线CK_4提供的时钟信号的高电平脉宽均为t1。任意2个相邻的移位寄存器单元的输出信号彼此部分重叠且重叠时间为t2。例如，在该示例中，栅极驱动电路20设置于显示面板的一侧以进行单边驱动，预充电时间(重叠时间)为t2＝t1*1/2。例如，在其他示例中，2个栅极驱动电路20分别设置于显示面板的两侧以进行双边驱动，则预充电时间(重叠时间)为t2＝t1*3/4，以进一步延长预充电时间。该栅极驱动电路20不需要额外增加用于控制预充电功能的信号即可实现预充电功能，且多个移位寄存器单元之间的连接关系简化，有利于实现窄边框和高分辨率。
本公开至少一实施例还提供一种显示装置。该显示装置包括本公开任一实施例所述的栅极驱动电路。该显示装置中的栅极驱动电路的晶体管数量少，不需要额外增加用于控制预充电功能的信号即可实现预充电的功能，电路结构简化，有利于实现窄边框和高分辨率，降低成本，例如，至少一个实施例的显示 装置中的栅极驱动电路不需要额外增加用于控制扫描方向的信号即可以实现双向扫描功能，有利于实现窄边框布线。
图9为本公开一实施例提供的一种显示装置的示意框图。参考图9，显示装置30包括栅极驱动电路20，栅极驱动电路20为本公开任一实施例所述的栅极驱动电路。
例如，显示装置30可以为液晶显示(Liquid Crystal Display,LCD)面板、LCD电视、显示器、有机发光二极管(Organic Light-Emitting Diode,OLED)面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不作限制。显示装置30的技术效果可以参考上述实施例中关于移位寄存器单元10和栅极驱动电路20的相应描述，这里不再赘述。
图10本公开一实施例提供的另一种显示装置的示意框图。参考图10，显示装置30包括显示面板3000、栅极驱动器3010、定时控制器3020和数据驱动器3030。显示面板3000包括多条扫描线GL、多条数据线DL和根据多条扫描线GL和多条数据线DL交叉限定的多个像素单元P；栅极驱动器3010用于驱动多条扫描线GL；数据驱动器3030用于驱动多条数据线DL；定时控制器3020用于处理从显示装置30外部输入的图像数据RGB，向数据驱动器3030提供处理后的图像数据RGB，另外，定时控制器3020还用于向栅极驱动器3010和数据驱动器3030输出扫描控制信号GCS和数据控制信号DCS，以对栅极驱动器3010和数据驱动器3030进行控制。
例如，栅极驱动器3010包括上述任一实施例中提供的栅极驱动电路20。栅极驱动电路20中的多个移位寄存器单元的输出端Output与多条扫描线GL一一对应连接。多条扫描线GL与排列为多行的像素单元P对应连接。栅极驱动电路20中的各级移位寄存器单元的输出端Output依序输出信号到多条扫描线GL，以使显示面板3000中的多行像素单元P实现逐行扫描。例如，栅极驱动器3010可以实现为半导体芯片，也可以集成在显示面板3000中以构成GOA电路。
例如，数据驱动器3030使用参考伽玛电压根据源自定时控制器3020的多个数据控制信号DCS将从定时控制器3020输入的数字图像数据RGB转换成数据信号。数据驱动器3030向多条数据线DL提供转换的数据信号。例如，数据驱动器3030可以实现为半导体芯片。
例如，定时控制器3020对外部输入的图像数据RGB进行处理以匹配显示面板3000的大小和分辨率，然后向数据驱动器3030提供处理后的图像数据。定时控制器3020使用从显示装置30外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多条扫描控制信号GCS和多条数据控制信号DCS。定时控制器3020分别向栅极驱动器3010和数据驱动器3030提供产生的扫描控制信号GCS和数据控制信号DCS，以用于栅极驱动器3010和数据驱动器3030的控制。
该显示装置30还可以包括其他部件，例如信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法，可以用于驱动本公开任一实施例提供的移位寄存器单元。利用该驱动方法，不需要额外增加用于控制预充电功能的信号即可实现预充电的功能，且采用的电路结构简化，有利于实现窄边框和高分辨率，降低成本，例如，在至少一个实施例中，不需要额外增加用于控制扫描方向的信号即可以实现双向扫描功能，有利于实现窄边框布线。
例如，在一个实施例中，在移位寄存器单元10包括第二输出下拉电路700的情形下，该移位寄存器单元10的驱动方法包括如下操作：
第一阶段，第一输入电路100响应于第一时钟信号对上拉节点PU充电至第一电平，输出电路200输出第二时钟信号的低电平至输出端Output；
第二阶段，输出电路200输出第二时钟信号的高电平至输出端Output；
第三阶段，输出电路200输出第二时钟信号的高电平至输出端Output；
第四阶段，输出电路200输出第二时钟信号的低电平至输出端Output，且第一输出下拉电路300响应于第三时钟信号对输出端Output进行降噪；
第五阶段，第一输入电路100响应于第一时钟信号对上拉节点PU进行复位，第一输出下拉电路300响应于第三时钟信号对输出端Output进行降噪；
第六阶段，第一输入电路100响应于第一时钟信号对上拉节点PU进行复位，第二输出下拉电路700在下拉节点PD的电平的控制下对输出端Output进行降噪。
例如，在第二阶段，由于第一电容C1的自举效应，上拉节点PU的电平变为第二电平，第二电平比第一电平高。在第三阶段，上拉节点PU的电平保持为第二电平。在第四阶段，由于第一电容C1的自举效应，上拉节点PU的 电平变为第一电平。在第五阶段，上拉节点PU的电平被下拉至低电平。
例如，在一个示例中，在移位寄存器单元10还包括第二输入电路400的情况下，该移位寄存器单元10的驱动方法还包括：
第七阶段，第二输入电路400响应于第四时钟信号对上拉节点PU进行降噪，第二输出下拉电路700在下拉节点PD的电平的控制下对输出端Output进行降噪。
例如，在第四阶段，第二输入电路400响应于第四时钟信号以将上拉节点PU的电平保持在第一电平。
例如，第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号具有相同的周期，第二时钟信号的相位比第一时钟信号的相位晚四分之一个周期，第四时钟信号的相位比第二时钟信号的相位晚四分之一个周期，第三时钟信号的相位比第四时钟信号的相位晚四分之一个周期。
例如，在另一个实施例中，当采用该移位寄存器单元10的显示面板进行反向扫描时，在移位寄存器单元10包括第二输出下拉电路700的情形下，该移位寄存器单元10的驱动方法包括如下操作：
第一阶段，第二输入电路400响应于第四时钟信号对上拉节点PU充电至第一电平，输出电路200输出第二时钟信号的低电平至输出端Output；
第二阶段，输出电路200输出第二时钟信号的高电平至输出端Output；
第三阶段，输出电路200输出第二时钟信号的高电平至输出端Output；
第四阶段，输出电路200输出第二时钟信号的低电平至输出端Output，且第一输出下拉电路300响应于第三时钟信号对输出端Output进行降噪；
第五阶段，第二输入电路400响应于第四时钟信号对上拉节点PU进行复位，第一输出下拉电路300响应于第三时钟信号对输出端Output进行降噪；
第六阶段，第二输入电路400响应于第四时钟信号对上拉节点PU进行复位，第二输出下拉电路700在下拉节点PD的电平的控制下对输出端Output进行降噪。
例如，在第二阶段，由于第一电容C1的自举效应，上拉节点PU的电平变为第二电平，第二电平比第一电平高。在第三阶段，上拉节点PU的电平保持为第二电平。在第四阶段，由于第一电容C1的自举效应，上拉节点PU的电平变为第一电平。在第五阶段，上拉节点PU的电平被下拉至低电平。
例如，在一个示例中，当采用该移位寄存器单元10的显示面板进行反向 扫描时，该移位寄存器单元10的驱动方法还包括：
第七阶段，第一输入电路100响应于第一时钟信号对上拉节点PU进行降噪，第二输出下拉电路700在下拉节点PD的电平的控制下对输出端Output进行降噪。
例如，在第四阶段，第一输入电路100响应于第四时钟信号以将上拉节点PU的电平保持在第一电平。
例如，当采用该移位寄存器单元10的显示面板进行反向扫描时，第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号具有相同的周期，第一时钟信号的相位比第二时钟信号的相位晚四分之一个周期，第三时钟信号的相位比第一时钟信号的相位晚四分之一个周期，第四时钟信号的相位比第三时钟信号的相位晚四分之一个周期。
需要说明的是，关于该驱动方法的详细描述以及技术效果可以参考本公开的实施例中对于移位寄存器单元10和栅极驱动电路20的相应描述，这里不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种移位寄存器单元，包括第一输入电路、输出电路和第一输出下拉电路；其中，
    所述第一输入电路配置为响应于第一时钟信号对上拉节点进行充电，以及响应于所述第一时钟信号对所述上拉节点进行复位；
    所述输出电路配置为在所述上拉节点的电平的控制下，将第二时钟信号输出至输出端；
    所述第一输出下拉电路配置为响应于第三时钟信号对所述输出端进行降噪。
  2. 根据权利要求1所述的移位寄存器单元，还包括第二输入电路，
    其中，所述第二输入电路配置为响应于第四时钟信号对所述上拉节点进行降噪。
  3. 根据权利要求1或2所述的移位寄存器单元，还包括第一下拉节点控制电路和第二输出下拉电路；其中，
    所述第一下拉节点控制电路配置为在所述上拉节点的电平的控制下，对下拉节点的电平进行控制；
    所述第二输出下拉电路配置为在所述下拉节点的电平的控制下，对所述输出端进行降噪。
  4. 根据权利要求3所述的移位寄存器单元，还包括第二下拉节点控制电路；其中，
    所述第二下拉节点控制电路配置为响应于所述第二时钟信号对所述下拉节点的电平进行控制。
  5. 根据权利要求1-4任一所述的移位寄存器单元，其中，所述第一输入电路包括第一晶体管；
    所述第一晶体管的栅极配置为和第一时钟信号端连接以接收所述第一时钟信号，所述第一晶体管的第一极配置为和第一输入端连接以接收第一输入信号，所述第一晶体管的第二极配置为和所述上拉节点连接。
  6. 根据权利要求1-5任一所述的移位寄存器单元，其中，所述输出电路包括第二晶体管和第一电容；
    所述第二晶体管的栅极配置为和所述上拉节点连接，所述第二晶体管的第 一极配置为和第二时钟信号端连接以接收所述第二时钟信号，所述第二晶体管的第二极配置为和所述输出端连接；
    所述第一电容的第一极配置为和所述第二晶体管的栅极连接，所述第一电容的第二极配置为和所述第二晶体管的第二极连接。
  7. 根据权利要求1-6任一所述的移位寄存器单元，其中，所述第一输出下拉电路包括第三晶体管；
    所述第三晶体管的栅极配置为和第三时钟信号端连接以接收所述第三时钟信号，所述第三晶体管的第一极配置为和所述输出端连接，所述第三晶体管的第二极配置为和第一电压端连接以接收第一电压。
  8. 根据权利要求2所述的移位寄存器单元，其中，所述第二输入电路包括第四晶体管；
    所述第四晶体管的栅极配置为和第四时钟信号端连接以接收所述第四时钟信号，所述第四晶体管的第一极配置为和所述上拉节点连接，所述第四晶体管的第二极配置为和第二输入端连接以接收第二输入信号。
  9. 根据权利要求3或4所述的移位寄存器单元，其中，所述第一下拉节点控制电路包括第五晶体管；
    所述第五晶体管的栅极配置为和所述上拉节点连接，所述第五晶体管的第一极配置为和所述下拉节点连接，所述第五晶体管的第二极配置为和第一电压端连接以接收第一电压。
  10. 根据权利要求3或4所述的移位寄存器单元，其中，所述第二输出下拉电路包括第六晶体管；
    所述第六晶体管的栅极配置为和所述下拉节点连接，所述第六晶体管的第一极配置为和所述输出端连接，所述第六晶体管的第二极配置为和第一电压端连接以接收第一电压。
  11. 根据权利要求4所述的移位寄存器单元，其中，所述第二下拉节点控制电路包括第二电容；
    所述第二电容的第一极配置为和所述下拉节点连接，所述第二电容的第二极配置为和第二时钟信号端连接以接收所述第二时钟信号。
  12. 一种栅极驱动电路，包括如权利要求1-11任一所述的移位寄存器单元。
  13. 根据权利要求12所述的栅极驱动电路，还包括第一时钟信号线、第二时钟信号线、第三时钟信号线和第四时钟信号线；其中，
    在所述移位寄存器单元包括第二输入电路的情形下，所述移位寄存器单元还包括第一时钟信号端、第二时钟信号端、第三时钟信号端和第四时钟信号端，分别用于将所述第一至第四时钟信号输入所述第一输入电路、所述输出电路、所述第一输出下拉电路和所述第二输入电路；
    第4n-3级移位寄存器单元的第一时钟信号端和所述第一时钟信号线连接，第4n-3级移位寄存器单元的第二时钟信号端和所述第二时钟信号线连接，第4n-3级移位寄存器单元的第三时钟信号端和所述第三时钟信号线连接，第4n-3级移位寄存器单元的第四时钟信号端和所述第四时钟信号线连接；
    第4n-2级移位寄存器单元的第一时钟信号端和所述第二时钟信号线连接，第4n-2级移位寄存器单元的第二时钟信号端和所述第四时钟信号线连接，第4n-2级移位寄存器单元的第三时钟信号端和所述第一时钟信号线连接，第4n-2级移位寄存器单元的第四时钟信号端和所述第三时钟信号线连接；
    第4n-1级移位寄存器单元的第一时钟信号端和所述第四时钟信号线连接，第4n-1级移位寄存器单元的第二时钟信号端和所述第三时钟信号线连接，第4n-1级移位寄存器单元的第三时钟信号端和所述第二时钟信号线连接，第4n-1级移位寄存器单元的第四时钟信号端和所述第一时钟信号线连接；
    第4n级移位寄存器单元的第一时钟信号端和所述第三时钟信号线连接，第4n级移位寄存器单元的第二时钟信号端和所述第一时钟信号线连接，第4n级移位寄存器单元的第三时钟信号端和所述第四时钟信号线连接，第4n级移位寄存器单元的第四时钟信号端和所述第二时钟信号线连接；
    n为大于0的整数。
  14. 一种显示装置，包括如权利要求12或13所述的栅极驱动电路。
  15. 一种如权利要求1-11任一项所述的移位寄存器单元的驱动方法，在所述移位寄存器单元包括第二输出下拉电路的情形下，所述驱动方法包括：
    第一阶段，所述第一输入电路响应于所述第一时钟信号对所述上拉节点充电至第一电平，所述输出电路输出所述第二时钟信号的低电平至所述输出端；
    第二阶段，所述输出电路输出所述第二时钟信号的高电平至所述输出端；
    第三阶段，所述输出电路输出所述第二时钟信号的高电平至所述输出端；
    第四阶段，所述输出电路输出所述第二时钟信号的低电平至所述输出端，且所述第一输出下拉电路响应于所述第三时钟信号对所述输出端进行降噪；
    第五阶段，所述第一输入电路响应于所述第一时钟信号对所述上拉节点进 行复位，所述第一输出下拉电路响应于所述第三时钟信号对所述输出端进行降噪；
    第六阶段，所述第一输入电路响应于所述第一时钟信号对所述上拉节点进行复位，所述第二输出下拉电路在所述下拉节点的电平的控制下对所述输出端进行降噪。
  16. 根据权利要求15所述的移位寄存器单元的驱动方法，在所述移位寄存器单元还包括第二输入电路的情况下，所述驱动方法还包括：
    第七阶段，所述第二输入电路响应于第四时钟信号对所述上拉节点进行降噪，所述第二输出下拉电路在所述下拉节点的电平的控制下对所述输出端进行降噪。
  17. 根据权利要求16所述的移位寄存器单元的驱动方法，其中，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号具有相同的周期，所述第二时钟信号的相位比所述第一时钟信号的相位晚四分之一个周期，所述第四时钟信号的相位比所述第二时钟信号的相位晚四分之一个周期，所述第三时钟信号的相位比所述第四时钟信号的相位晚四分之一个周期。
  18. 一种如权利要求2-11任一项所述的移位寄存器单元的驱动方法，在所述移位寄存器单元包括第二输出下拉电路的情形下，所述驱动方法包括：
    第一阶段，所述第二输入电路响应于所述第四时钟信号对所述上拉节点充电至第一电平，所述输出电路输出所述第二时钟信号的低电平至所述输出端；
    第二阶段，所述输出电路输出所述第二时钟信号的高电平至所述输出端；
    第三阶段，所述输出电路输出所述第二时钟信号的高电平至所述输出端；
    第四阶段，所述输出电路输出所述第二时钟信号的低电平至所述输出端，且所述第一输出下拉电路响应于所述第三时钟信号对所述输出端进行降噪；
    第五阶段，所述第二输入电路响应于所述第四时钟信号对所述上拉节点进行复位，所述第一输出下拉电路响应于所述第三时钟信号对所述输出端进行降噪；
    第六阶段，所述第二输入电路响应于所述第四时钟信号对所述上拉节点进行复位，所述第二输出下拉电路在所述下拉节点的电平的控制下对所述输出端进行降噪。
  19. 根据权利要求18所述的移位寄存器单元的驱动方法，还包括：
    第七阶段，所述第一输入电路响应于所述第一时钟信号对所述上拉节点进 行降噪，所述第二输出下拉电路在所述下拉节点的电平的控制下对所述输出端进行降噪。
  20. 根据权利要求19所述的移位寄存器单元的驱动方法，其中，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号具有相同的周期，所述第一时钟信号的相位比所述第二时钟信号的相位晚四分之一个周期，所述第三时钟信号的相位比所述第一时钟信号的相位晚四分之一个周期，所述第四时钟信号的相位比所述第三时钟信号的相位晚四分之一个周期。
PCT/CN2018/116263 2018-05-16 2018-11-19 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 WO2019218625A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US16/470,534 US11610524B2 (en) 2018-05-16 2018-11-19 Shift register unit and driving method thereof, gate drive circuit and display device
EP18887202.2A EP3796296A4 (en) 2018-05-16 2018-11-19 SHIFT REGISTER UNIT, ITS DRIVE METHOD, GATE DRIVE CIRCUIT AND DISPLAY DEVICE

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810470216.2 2018-05-16
CN201810470216.2A CN110503927B (zh) 2018-05-16 2018-05-16 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置

Publications (1)

Publication Number Publication Date
WO2019218625A1 true WO2019218625A1 (zh) 2019-11-21

Family

ID=68539425

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/116263 WO2019218625A1 (zh) 2018-05-16 2018-11-19 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置

Country Status (4)

Country Link
US (1) US11610524B2 (zh)
EP (1) EP3796296A4 (zh)
CN (1) CN110503927B (zh)
WO (1) WO2019218625A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022089067A1 (zh) * 2020-10-26 2022-05-05 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动方法，栅极驱动电路和显示装置
CN114882848A (zh) * 2022-05-13 2022-08-09 重庆惠科金渝光电科技有限公司 栅极驱动电路及显示装置

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111341261B (zh) * 2020-04-14 2022-06-17 合肥京东方显示技术有限公司 移位寄存器及其驱动方法、信号驱动电路及显示装置
CN114120923B (zh) * 2020-08-26 2022-11-25 深圳市柔宇科技股份有限公司 扫描驱动电路及显示面板
CN113539185B (zh) * 2021-07-29 2022-12-23 合肥京东方卓印科技有限公司 显示装置、栅极驱动电路、移位寄存单元及其驱动方法
CN113741726B (zh) * 2021-07-30 2022-06-03 惠科股份有限公司 驱动电路、四级驱动电路及显示面板
CN115035871B (zh) * 2022-06-28 2024-04-05 上海中航光电子有限公司 显示面板和显示装置
CN115641818A (zh) * 2022-10-26 2023-01-24 厦门天马显示科技有限公司 移位寄存单元、扫描驱动电路、显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102930814A (zh) * 2012-10-29 2013-02-13 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置与显示装置
CN104575436A (zh) * 2015-02-06 2015-04-29 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示装置
CN104867435A (zh) * 2015-03-18 2015-08-26 友达光电股份有限公司 移位暂存器及移位暂存电路
CN105405417A (zh) * 2014-09-05 2016-03-16 乐金显示有限公司 移位寄存器及使用移位寄存器的显示装置
US20160210925A1 (en) * 2015-01-20 2016-07-21 Samsung Display Co., Ltd. Gate driver and display device having the same
CN106531048A (zh) * 2016-11-29 2017-03-22 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示面板和驱动方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI421872B (zh) * 2009-03-24 2014-01-01 Au Optronics Corp 能降低耦合效應之移位暫存器
CN101783124B (zh) * 2010-02-08 2013-05-08 北京大学深圳研究生院 栅极驱动电路单元、栅极驱动电路及显示装置
JP5774911B2 (ja) * 2011-06-01 2015-09-09 株式会社ジャパンディスプレイ 表示装置
CN103065578B (zh) * 2012-12-13 2015-05-13 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路和显示装置
KR20140141190A (ko) * 2013-05-31 2014-12-10 삼성디스플레이 주식회사 스테이지 회로 및 이를 이용한 주사 구동부
WO2016068038A1 (ja) * 2014-10-28 2016-05-06 シャープ株式会社 単位シフトレジスタ回路、シフトレジスタ回路、単位シフトレジスタ回路の制御方法及び表示装置
CN104332146B (zh) * 2014-11-12 2016-09-28 合肥鑫晟光电科技有限公司 移位寄存器单元、移位寄存器、栅极驱动电路和显示装置
CN104715733A (zh) * 2015-04-09 2015-06-17 京东方科技集团股份有限公司 移位寄存器单元、驱动电路和方法、阵列基板和显示装置
CN104766580B (zh) * 2015-04-23 2017-08-01 合肥京东方光电科技有限公司 移位寄存器单元及驱动方法、栅极驱动电路和显示装置
CN105118417B (zh) * 2015-09-25 2017-07-25 京东方科技集团股份有限公司 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
CN105261341B (zh) * 2015-11-11 2017-11-03 昆山龙腾光电有限公司 一种栅极驱动电路及显示装置
CN105609136A (zh) * 2016-01-04 2016-05-25 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
KR102428239B1 (ko) * 2016-04-05 2022-08-01 엘지디스플레이 주식회사 게이트구동부 및 이를 포함하는 표시장치
CN106297697B (zh) * 2016-08-29 2017-09-15 京东方科技集团股份有限公司 移位寄存器及其操作方法
CN106448600B (zh) * 2016-10-26 2018-05-18 京东方科技集团股份有限公司 移位寄存器及其驱动方法
CN106782282A (zh) * 2017-02-23 2017-05-31 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示面板及驱动方法
CN106940977B (zh) * 2017-05-16 2019-07-19 京东方科技集团股份有限公司 移位寄存器、阵列基板栅极驱动电路和显示装置
CN109243351B (zh) * 2017-07-10 2021-01-15 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN107316600A (zh) * 2017-07-21 2017-11-03 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN107358927B (zh) * 2017-07-31 2019-07-23 武汉华星光电半导体显示技术有限公司 一种扫描驱动电路及装置
CN107689219A (zh) * 2017-09-12 2018-02-13 昆山龙腾光电有限公司 栅极驱动电路及其显示装置
CN108389539B (zh) * 2018-03-15 2020-06-16 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN108182905B (zh) * 2018-03-27 2021-03-30 京东方科技集团股份有限公司 开关电路、控制单元、显示装置、栅极驱动电路及方法
CN109410825B (zh) * 2019-01-04 2020-11-13 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路及其驱动方法和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102930814A (zh) * 2012-10-29 2013-02-13 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置与显示装置
CN105405417A (zh) * 2014-09-05 2016-03-16 乐金显示有限公司 移位寄存器及使用移位寄存器的显示装置
US20160210925A1 (en) * 2015-01-20 2016-07-21 Samsung Display Co., Ltd. Gate driver and display device having the same
CN104575436A (zh) * 2015-02-06 2015-04-29 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示装置
CN104867435A (zh) * 2015-03-18 2015-08-26 友达光电股份有限公司 移位暂存器及移位暂存电路
CN106531048A (zh) * 2016-11-29 2017-03-22 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示面板和驱动方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3796296A4

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022089067A1 (zh) * 2020-10-26 2022-05-05 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动方法，栅极驱动电路和显示装置
US11830410B2 (en) 2020-10-26 2023-11-28 Chengdu Boe Optoelectronics Technology Co., Ltd. Gate driving unit, gate driving method, gate driving circuit and display device
CN114882848A (zh) * 2022-05-13 2022-08-09 重庆惠科金渝光电科技有限公司 栅极驱动电路及显示装置

Also Published As

Publication number Publication date
CN110503927B (zh) 2020-11-10
CN110503927A (zh) 2019-11-26
EP3796296A1 (en) 2021-03-24
EP3796296A4 (en) 2022-01-19
US11610524B2 (en) 2023-03-21
US20210358361A1 (en) 2021-11-18

Similar Documents

Publication Publication Date Title
US11328672B2 (en) Shift register unit and driving method thereof, gate driving circuit, and display device
JP7366753B2 (ja) シフトレジスタユニットおよびその駆動方法、ゲート駆動回路および表示装置
WO2019218625A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
US11176871B2 (en) Shift register unit and driving method thereof, gate driving circuit and display device
JP7315469B2 (ja) シフトレジスタユニットおよびその駆動方法、ゲート駆動回路および表示装置
US11087855B2 (en) Shift register unit and driving method, gate drive circuit and display device
CN108281124B (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
WO2019184339A1 (zh) 移位寄存器单元、栅极驱动电路、显示装置以及驱动方法
CN108806628B (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
WO2019205745A1 (zh) 移位寄存器单元、栅极驱动电路及显示装置
US20200051507A1 (en) Shift Register Unit, Gate Drive Circuit, Display Device and Driving Method
WO2018171133A1 (zh) 移位寄存器单元、栅极驱动电路以及驱动方法
US11227524B2 (en) Shift register unit and driving method thereof, gate driving circuit and driving method thereof, and display device
WO2020015569A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
JP2021531490A (ja) シフトレジスタユニットおよびその駆動方法、ゲート駆動回路および表示装置
WO2017059792A1 (zh) 移位寄存器单元、栅线驱动装置以及驱动方法
WO2019184354A1 (zh) 移位寄存器单元及驱动方法、栅极驱动电路及显示装置
WO2018209937A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2019056795A1 (zh) 移位寄存器单元、驱动装置、显示装置以及驱动方法
WO2019056803A1 (zh) 移位寄存器单元、栅极驱动电路、显示装置以及驱动方法
JP2021513666A (ja) シフトレジスタユニット、ゲート駆動回路、表示装置及び駆動方法
WO2020097816A1 (zh) 移位寄存器单元及驱动方法、栅极驱动电路、显示装置
US20230410735A1 (en) Shift register and driving method thereof, driving circuit, display substrate and device
WO2021081703A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
CN111696490A (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18887202

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2018887202

Country of ref document: EP

Effective date: 20201216