WO2019179334A1 - 移位寄存器单元及其驱动方法、栅极驱动电路 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路 Download PDF

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Publication number
WO2019179334A1
WO2019179334A1 PCT/CN2019/077817 CN2019077817W WO2019179334A1 WO 2019179334 A1 WO2019179334 A1 WO 2019179334A1 CN 2019077817 W CN2019077817 W CN 2019077817W WO 2019179334 A1 WO2019179334 A1 WO 2019179334A1
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WIPO (PCT)
Prior art keywords
pull
node
switch tube
noise reduction
clock signal
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PCT/CN2019/077817
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English (en)
French (fr)
Inventor
许志财
孙佳
肖利军
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京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/609,574 priority Critical patent/US10825538B2/en
Publication of WO2019179334A1 publication Critical patent/WO2019179334A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a driving method thereof, and a gate driving circuit.
  • a gate driving circuit integrated on an array substrate by using GOA technology includes a plurality of shift register units, each shift register unit corresponding to a gate line on the array substrate, and implementing the gate line by outputting a gate driving signal Drive.
  • the shift register unit can control the potential of the pull-down node in the shift register unit by the clock signal, thereby controlling the gate drive signal of the shift register unit.
  • the output is in a floating state with no output.
  • the clock signal is in a high state during the hold period, the leakage current in the shift register unit is easily increased, thereby causing the characteristics of the thin film transistor in the shift register unit to be forwardly shifted; and when the clock signal is low.
  • the shift register unit loses the noise reduction capability, which in turn causes the shift register unit to output an abnormality.
  • An object of the present disclosure is to provide a shift register unit, a driving method thereof, and a gate driving circuit.
  • a first aspect of the present disclosure provides a shift register unit comprising:
  • a pull-up node control circuit respectively connected to the input signal terminal, the pull-up node, the reset terminal, the first level input terminal and the pull-down node;
  • a pull-down node control circuit respectively connected to the first clock signal input end, the pull-up node, the first level input end, and the pull-down node;
  • An output circuit respectively connected to the second clock signal input end, the pull-up node, the pull-down node, the gate drive signal output end, the first level input end and the reset end;
  • noise reduction adjustment circuit respectively connected to the pull-down node and the first level input terminal, wherein the noise reduction adjustment circuit is configured to: control a reduction in a noise reduction period in a holding period of the shift register unit The rate of rise of the potential of the pull-down node; during the non-noise reduction period in the hold period, the control reduces the rate of decrease of the potential of the pull-down node.
  • the noise reduction adjustment circuit includes a second capacitor, a first end of the second capacitor is connected to the pull-down node, and a second end of the second capacitor is connected to the first level input end.
  • the noise reduction adjustment circuit further includes a first resistor, and the second end of the second capacitor is connected to the first level input terminal through the first resistor.
  • the shift register unit further includes:
  • a first enhanced noise reduction circuit respectively connected to the input signal end, the first clock signal input end and the pull-up node, wherein the first enhanced noise reduction circuit is configured to: input at the first clock signal Controlling the conduction or disconnection of the electrical connection between the input signal terminal and the pull-up node under the control of the terminal; and/or,
  • a second enhanced noise reduction circuit respectively connected to the gate driving signal output end, the first level input end and the first clock signal input end, wherein the second enhanced noise reduction circuit is used for: Under the control of the first clock signal input terminal, the control turns on or off the electrical connection between the gate drive signal output terminal and the first level input terminal.
  • the pull-up node control circuit is configured to: under the control of the input signal end, control to turn on or off an electrical connection between the pull-up node and the input signal end, at the reset end Controlling, turning on or off the electrical connection between the pull-up node and the first level input terminal, under the control of the pull-down node, controlling to turn on or off the pull-up node and Electrical connection between the first level inputs;
  • the output circuit is configured to: control, under the control of the pull-up node, to electrically connect or disconnect an electrical connection between the second clock signal input end and the gate drive signal output end; Controlling, by the node, turning on or off an electrical connection between the gate drive signal output end and the first level input terminal; under the control of the reset end, controlling to turn on or off the An electrical connection between the gate drive signal output and the first level input.
  • the pull-up node control circuit includes: a first switch tube, a second switch tube, and a third switch tube; wherein
  • the gate of the first switch tube and the second pole of the first switch tube are both connected to the input signal end, and the first pole of the first switch tube is connected to the pull-up node;
  • a gate of the second switch tube is connected to the reset end, a first pole of the second switch tube is connected to the first level input end, and a second pole of the second switch tube is Pull-up node connection;
  • a gate of the third switch tube is connected to the pull-down node, a first pole of the third switch tube is connected to the first level input end, and a second pole of the third switch tube is Pull up the node connection.
  • the output circuit includes: a fourth switch tube, a fifth switch tube, and a sixth switch tube;
  • a gate of the fourth switch tube is connected to the pull-up node, a first pole of the fourth switch tube is connected to the gate drive signal output end, and a second pole of the fourth switch tube is Connecting the second clock signal input end;
  • a gate of the fifth switch tube is connected to the pull-down node, a first pole of the fifth switch tube is connected to the first level input end, and a second pole of the fifth switch tube is The gate drive signal output terminal is connected;
  • a gate of the sixth switch tube is connected to the reset end, a first pole of the sixth switch tube is connected to the first level input end, and a second pole of the sixth switch tube is The gate drive signal output is connected.
  • the pull-down node control circuit includes: a seventh switch tube, an eighth switch tube, a ninth switch tube, and a tenth switch tube;
  • the gate of the seventh switch tube and the second pole of the seventh switch tube are both connected to the first clock signal input end, and the first pole of the seventh switch tube is connected to the pull-down control node;
  • a gate of the eighth switch tube is connected to the pull-up node, a first pole of the eighth switch tube is connected to the first level input end, and a second pole of the eighth switch tube is Pull down the control node connection;
  • a gate of the ninth switch tube is connected to the pull-down control node, a first pole of the ninth switch tube is connected to the pull-down node, and a second pole of the ninth switch tube is connected to the first clock Signal input connection;
  • a gate of the tenth switch tube is connected to the pull-up node, a first pole of the tenth switch tube is connected to the first level input end, and a second pole of the tenth switch tube is The drop-down node is connected.
  • the first enhanced noise reduction circuit includes an eleventh switch tube, a gate of the eleventh switch tube is connected to the first clock signal input end, and a first pole of the eleventh switch tube a pull-up node connection, the second pole of the eleventh switch tube is connected to the input signal end;
  • the second enhanced noise reduction circuit includes a twelfth switch tube, a gate of the twelfth switch tube is connected to the first clock signal input end, and a first pole of the twelfth switch tube and the first The level input terminal is connected, and the second pole of the twelfth switch tube is connected to the gate drive signal output end.
  • the capacitor circuit includes a first capacitor, a first end of the first capacitor is connected to the pull-up node, and a second end of the first capacitor is connected to the gate drive signal output end.
  • the first clock signal input from the first clock signal input terminal is a low level
  • the second clock signal input from the second clock signal input end is a high power Flat
  • the reset signal input from the reset terminal is at a low level
  • the first clock signal input from the first clock signal input terminal is at a high level
  • from the The second clock signal input to the second clock signal input terminal is at a low level
  • the reset signal input from the reset terminal is at a low level.
  • a second aspect of the present disclosure provides a gate driving circuit including the above shift register unit.
  • a third aspect of the present disclosure provides a driving method of a shift register unit, which is applied to the shift register unit, and the driving method includes:
  • the noise reduction adjustment circuit controls a decrease rate of the potential of the pull-down node during the noise reduction period in the hold period; the noise reduction adjustment circuit controls the decrease rate of the potential of the pull-down node during the non-noise reduction period in the hold period .
  • a first clock signal of a low level is applied to the input end of the first clock signal, and a second clock signal of a high level is applied to the input end of the second clock signal, and a reset signal of a low level is applied to the reset terminal; and a first clock signal of a high level is applied to the input end of the first clock signal during the non-noise reduction period, and is applied to the input end of the second clock signal a second clock signal of a low level, and a reset signal of a low level is applied to the reset terminal.
  • FIG. 1 is a schematic block diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a timing chart of operation of a shift register unit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of potentials of corresponding PD points when the noise reduction adjustment circuit takes different values according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of resistance in a noise reduction adjustment circuit according to an embodiment of the present disclosure.
  • One working cycle of the shift register unit in the related art includes: an input period, an output period, a reset period, and a hold period, wherein the input period, the output period, and the reset period mainly implement the following functions: first through the shift register unit The gate driving signal output terminal outputs a gate driving signal to a corresponding gate line on the array substrate, and then resets the gate driving signal to a gate turn-off voltage; during the holding period, the portion of the shift register unit is controlled by the clock signal
  • the thin film transistor operates such that the potential of the gate drive signal output can be maintained at the gate turn-off voltage.
  • the shift register unit may set a square wave signal having a high and a low level during a hold period of the clock signal according to an actual working condition, or may set a low level signal of the clock signal at a hold period of a direct current or DC high level signal.
  • the shift register unit is prone to the following problems:
  • the first problem is that the clock signal is at a high level, which may cause serious leakage of the thin film transistor associated with the clock signal in the shift register unit, which makes the thin film transistor prone to threshold voltage drift in long-term use, resulting in a shift register.
  • the output of the unit is abnormal, creating a reliability problem.
  • the second problem is that the clock signal is at a low level, which may cause the thin film transistor used in the shift register unit to implement the noise reduction function to be in an off state, thereby causing the shift register unit to lose the noise reduction capability, resulting in abnormal output of the shift register unit.
  • the shift register unit can only be controlled for a part of the time.
  • the noise-reducing thin film transistor is turned on, and the shift register unit has the capability of reducing noise. It can be seen that the shift register unit in the related art also has a problem that the noise reduction time is short and noise is likely to occur.
  • the shift register unit includes: a pull-up node control circuit, a pull-down node control circuit 2, a capacitor circuit 4, and an output. a circuit 3 and a noise reduction adjustment circuit 5; wherein the pull-up node control circuit 1 is respectively connected to the input signal terminal INPUT, the pull-up node PU, the reset terminal RESET, the first level input terminal VSS, and the pull-down node PD; the pull-down node control circuit 2 is respectively connected to the first clock signal input terminal CLKB, the pull-up node PU, the first level input terminal VSS and the pull-down node PD; the first end of the capacitor circuit 4 is connected to the pull-up node PU, and the second end of the capacitor circuit 4 Connected to the gate drive signal output terminal OUTPUT; the output circuit 3 and the second clock signal input terminal CLK, the pull-up node PU, the pull-down node PD,
  • one working cycle of the above shift register unit includes: an input period P1, an output period P2, a reset period P3, and a hold period P4, and the working process of the shift register unit in one duty cycle is :
  • the pull-up node control circuit 1 controls the input signal terminal INPUT to electrically connect with the pull-up node PU to pull the potential of the pull-up node PU high; the control of the pull-up node PU
  • the pull-down node control circuit 2 controls the pull-down node PD and the first level input terminal VSS to be electrically connected.
  • the output circuit 3 controls the second clock signal input terminal CLK to be electrically connected with the gate drive signal output terminal OUTPUT to enable the gate drive signal output.
  • the terminal OUTPUT outputs a gate driving signal and further increases the potential of the pull-up node PU; under the control of the pull-up node PU, the pull-down node control circuit 2 continues to control the pull-down node PD and the first level input terminal VSS to be electrically connected.
  • the pull-up node control circuit 1 controls the pull-up node PU to be electrically connected to the first level input terminal VSS, pulling the potential of the pull-up node PU low; at the first clock signal Under the control of the input terminal CLKB and the low-potential pull-up node PU, the pull-down node control circuit 2 controls the first clock signal input terminal CLKB to be electrically connected to the pull-down node PD to pull the potential of the pull-down node PD high; the pull-down node at the high potential Under the control of the PD, the pull-up node control circuit 1 controls the pull-up node PU to be electrically connected to the first level input terminal VSS; under the control of the high-potential pull-down node PD, the output circuit 3 controls the gate drive signal output terminal OUTPUT and The first level input terminal VSS is electrically connected, so that the gate driving signal output terminal OUTPUT does not output the gate driving signal; under the control
  • the pull-down node control circuit 2 controls the potential of the pull-down node PD and (input by the first clock signal input terminal CLKB) A clock signal is synchronously changed; further, the hold period P4 includes a noise reduction period M1 and a non-noise reduction period M2.
  • the potential of the pull-down node PD changes to a high potential following the first clock signal, and the high potential
  • the pull-down node PD can electrically connect the gate driving signal output terminal OUTPUT with the first level input terminal VSS through the control output circuit 3, and can control the pull-up node control circuit 1 to bring the pull-up node PU and the first level input terminal
  • the VSS is electrically connected to achieve noise reduction of the shift register unit.
  • the potential of the pull-down node PD changes to a low level following the first clock signal, so that the thin film transistors in the modules connected to the pull-down node PD do not generate high leakage, thereby reducing the thin film transistors.
  • the pull-up node PU is at a low potential, and under the control of the low-potential pull-up node PU, the output circuit 3 controls the gate driving signal output terminal OUTPUT and the second clock signal input terminal CLK to be non-powered. The connection further causes the gate driving signal output terminal OUTPUT not to output the gate driving signal.
  • the noise reduction adjustment circuit 5 regulates the rate of change of the potential of the pull-down node PD, specifically, during the noise reduction period in the holding period P4, the rate of increase of the potential of the pull-down node PD is controlled to decrease; During the non-noise reduction period in the hold period P4, the control reduces the rate of decrease of the potential of the pull-down node PD.
  • the shift register unit provided by the embodiment of the present disclosure includes a noise reduction adjustment circuit 5, and the noise reduction adjustment circuit 5 and the pull-down node PD and the A level input terminal VSS is connected for controlling a rising rate of the potential of the pull-down node PD during the noise reduction period in the holding period P4, and controlling the potential of the pull-down node PD during the non-noise reduction period in the holding period P4 Rate of decline.
  • the shift register unit provided by the embodiment of the present disclosure can cause the potential of the pull-down node PD to slowly rise from a low potential to a high potential in the noise reduction period, thereby achieving a guaranteed shift in comparison with the shift register unit in the related art.
  • the noise reduction capability of the bit register unit improves the leakage resistance of the shift register unit; and in the non-noise reduction period, the potential of the pull-down node PD is slowly lowered from a high potential to a low potential, thereby realizing a shift in guarantee
  • the shift register unit provided by the embodiment of the present disclosure can ensure the noise reduction capability and the occurrence of the leakage condition during the holding period P4, which not only makes the characteristics of the thin film transistor in the shift register unit stable during long-term use.
  • the threshold voltage offset is not easy to occur, and the shift register unit can maintain good noise reduction performance throughout the sustain period P4, thereby ensuring the operational stability of the shift register unit.
  • the noise reduction adjustment circuit 5 includes a noise reduction capacitor C2, and the first end of the noise reduction capacitor C2 and the pull-down node PD Connected, the second end of the noise reduction capacitor C2 is connected to the first level input terminal VSS.
  • the noise reduction adjustment circuit 5 includes the noise reduction capacitor C2
  • the potential of the pull-down node PD follows the change of the first clock signal to a high potential, and the noise reduction capacitor C2 needs to be simultaneously charged.
  • the time when the pull-down node PD becomes a high level is prolonged, and the rising rate of the potential of the pull-down node PD is slowed down.
  • the noise reduction capacitor C2 can store a certain amount of charge, thereby prolonging the time when the pull-down node PD becomes a low level, The rate of decrease in the potential of the pull-down node PD is slowed down.
  • the noise reduction capacitor C2 can slow down the rise rate of the potential of the pull-down node PD during the noise reduction period, and can The non-noise reduction period slows down the falling rate of the potential of the pull-down node PD, so that the shift register unit can have both the noise reduction capability and the occurrence of leakage during the entire holding period P4, thereby ensuring that the shift register unit can be more Stable job.
  • the noise reduction adjustment circuit 5 may further include a noise reduction resistor R, and the second end of the noise reduction capacitor C2 is connected to the first level input terminal VSS through the noise reduction resistor R.
  • the noise reduction adjustment circuit 5 further includes a noise reduction resistor R connected between the noise reduction capacitor C2 and the first level input terminal VSS, the noise reduction resistor R has a current limiting function, thereby further reducing the shift. The generation of leakage conditions in the register unit.
  • the shift register unit can be adjusted to achieve different noise reduction and leakage resistance by adjusting the values of the noise reduction capacitor C2 and the noise reduction resistor R, as shown in FIG.
  • the first curve 101, the second curve 102, the third curve 103, and the fourth curve 104 can be adjusted to achieve different noise reduction and leakage resistance by adjusting the values of the noise reduction capacitor C2 and the noise reduction resistor R, as shown in FIG.
  • the first curve 101, the second curve 102, the third curve 103, and the fourth curve 104 can be adjusted to achieve different noise reduction and leakage resistance by adjusting the values of the noise reduction capacitor C2 and the noise reduction resistor R, as shown in FIG.
  • the first curve 101, the second curve 102, the third curve 103, and the fourth curve 104 can be adjusted to achieve different noise reduction and leakage resistance by adjusting the values of the noise reduction capacitor C2 and the noise reduction resistor R, as shown in FIG.
  • the first curve 101, the second curve 102, the third curve 103, and the fourth curve 104 can be
  • the fifth curve 105 and the sixth curve 106 are waveform diagrams of the pull-down node PD in the holding period P4 under different values of the noise reduction capacitor C2 and the noise reduction resistor R, respectively; wherein the first curve 101 corresponds to noise reduction When the capacitor C2 and the noise reduction resistor R are both 0, the pull-down node PD is in the curve corresponding to the holding period P4, and it can be seen that when the noise reduction capacitor C2 and the noise reduction resistor R are both 0, the first curve 101 corresponding to the pull-down node PD
  • the A region non-noise reduction period
  • the noise reduction period can be quickly changed from a low level to a low level, resulting in the shift register unit having substantially no noise reduction capability during the non-noise reduction period, and the first curve 101 is in the B region (
  • the noise reduction period can be quickly changed from a low level to a high level, resulting in an increase in leakage of the shift register unit during the noise reduction period.
  • the other five curves can be correspondingly obtained.
  • the capacitance and noise reduction resistance of the noise reduction capacitor C2 are gradually increased.
  • the second curve 102 to the sixth curve 106 can be correspondingly obtained, that is, the value of the noise reduction capacitor C2 and the resistance value of the noise reduction resistor R are larger, and the curve corresponding to the pull-down node PD is in the A region.
  • the shift register unit has both noise reduction capability and leakage resistance during the hold period P4.
  • the noise reduction resistor R can be prepared in various manners, as shown in FIG. 5, by making an ITO pattern between the corresponding gate GATE and the source/drain metal electrode SD, and adjusting the shape of the ITO pattern.
  • the resistance of the noise reduction resistor R formed.
  • an ITO pattern is formed between the gate GATE and the source/drain metal electrode SD through the via VIA, and the formed ITO pattern can be further patterned to become a serpentine trace by adjusting the serpentine trace
  • the width and length are used to adjust the resistance of the noise reduction resistor R.
  • the shift register unit provided by the above embodiment further includes: a first enhanced noise reduction circuit 6 and/or a second enhanced noise reduction circuit 7 , wherein the first enhanced noise reduction circuit 6 respectively The input signal terminal INPUT, the first clock signal input terminal CLKB and the pull-up node PU are connected, and the first enhanced noise reduction circuit 6 is configured to: control the conduction or disconnection of the input signal terminal under the control of the first clock signal input terminal CLKB An electrical connection between the INPUT and the pull-up node PU; a second enhanced noise reduction circuit 7 connected to the gate drive signal output terminal OUTPUT, the first level input terminal VSS and the first clock signal input terminal CLKB, respectively, the second enhancement
  • the noise reduction circuit 7 is configured to control to electrically connect or disconnect the electrical connection between the gate drive signal output terminal OUTPUT and the first level input terminal VSS under the control of the first clock signal input terminal CLKB.
  • the first enhanced noise reduction circuit 6 is capable of controlling the electrical connection between the input signal terminal INPUT and the pull-up node PU under the control of the first clock signal input terminal CLKB during the input period P1 and the reset period P3,
  • the potential of the pull-up node PU can be pulled higher in the input period P1 and pulled lower in the reset period P3, thereby achieving more effective control of the potential of the pull-up node PU, and the shift register is improved.
  • the noise reduction capability of the unit ensures the stability of the shift register unit operation.
  • the first enhanced noise reduction circuit 6 is also capable of controlling the conduction input signal terminal INPUT and the pull-up during a partial period in the hold period P4 (for example, a period in which the first clock signal input from the first clock signal input terminal CLKB is at a high level)
  • the electrical connection between the nodes PU enables the potential of the pull-up node PU to be pulled low during the partial period, thereby better improving the noise reduction capability of the shift register unit and ensuring the stability of the operation of the shift register unit.
  • the second enhanced noise reduction circuit 7 is capable of controlling between the on-gate driving signal output terminal OUTPUT and the first level input terminal VSS under the control of the first clock signal input terminal CLKB during the input period P1 and the reset period P3
  • the electrical connection enables the potential of the gate drive signal output terminal OUTPUT to be pulled lower in the input period P1 and the reset period P3, thereby achieving more effective control of the potential of the gate drive signal output terminal OUTPUT, thereby improving the shift
  • the noise reduction capability of the register unit ensures the stability of the shift register unit operation.
  • the second enhanced noise reduction circuit 7 is also capable of controlling the electrical connection between the on-gate driving signal output terminal OUTPUT and the first level input terminal VSS during a partial period in the sustain period P4 such that the gate driving signal output terminal The potential of the OUTPUT can be pulled low during this period of time, thereby better improving the noise reduction capability of the shift register unit and ensuring the stability of the operation of the shift register unit.
  • the pull-up node control circuit 1 provided by the above embodiment is configured to: under the control of the input signal terminal INPUT, control to electrically connect or disconnect the electrical connection between the pull-up node PU and the input signal terminal INPUT, at the reset end. Under the control of RESET, the control turns on or off the electrical connection between the pull-up node PU and the first level input terminal VSS, and controls the conduction or disconnection of the pull-up node PU and the first under the control of the pull-down node PD. Electrical connection between level inputs VSS.
  • the pull-up node control circuit 1 is configured to control the electrical connection between the pull-up node PU and the input signal terminal INPUT under the control of the input signal terminal INPUT, except for the input period P1. In other periods, the pull-up node control circuit 1 is configured to control the electrical connection between the pull-up node PU and the input signal terminal INPUT under the control of the input signal terminal INPUT.
  • the pull-up node control circuit 1 is configured to control the electrical connection between the turn-up pull-up node PU and the first level input terminal VSS under the control of the reset terminal RESET, and under the control of the pull-down node PD Controlling the electrical connection between the pull-up node PU and the first level input terminal VSS.
  • the pull-up node control circuit 1 is configured to control the electrical connection between the pull-up node PU and the first level input terminal VSS under the control of the reset terminal RESET, and at the pull-down node Under the control of the PD, the electrical connection between the pull-up node PU and the first level input terminal VSS is controlled.
  • the pull-up node control circuit 1 is configured to control the pull-up node PU and the first level input terminal VSS to periodically electrically and disconnect the electrical connection under the control of the pull-down node PD.
  • the output circuit 3 provided by the above embodiment is configured to: under the control of the pull-up node PU, control to turn on or off the electrical connection between the second clock signal input terminal CLK and the gate drive signal output terminal OUTPUT; Controlling, by the control of the pull-down node PD, turning on or off the electrical connection between the gate drive signal output terminal OUTPUT and the first level input terminal VSS; controlling or turning on or off the gate under the control of the reset terminal RESET An electrical connection between the pole drive signal output terminal OUTPUT and the first level input terminal VSS.
  • the output circuit 3 is configured to control the electrical connection between the second clock signal input terminal CLK and the gate driving signal output terminal OUTPUT under the control of the pull-up node PU,
  • the output circuit 3 is for controlling the disconnection of the electrical connection between the second clock signal input terminal CLK and the gate drive signal output terminal OUTPUT under the control of the pull-up node PU.
  • the output circuit 3 is further configured to control the electrical connection between the off gate driving signal output terminal OUTPUT and the first level input terminal VSS under the control of the pull-down node PD during the reset period P3, the output circuit 3 is further configured to control the electrical connection between the on-gate driving signal output terminal OUTPUT and the first level input terminal VSS under the control of the pull-down node PD, and the output circuit 3 is further used in the holding period P4. Under the control of the pull-down node PD, the control gate drive signal output terminal OUTPUT and the first level input terminal VSS are periodically electrically and disconnected electrically connected.
  • the output circuit 3 is further configured to control the electrical connection between the on-gate driving signal output terminal OUTPUT and the first level input terminal VSS under the control of the reset terminal RESET; during the input period P1 and In the output period P2, the output circuit 3 is further configured to control the electrical connection between the off gate drive signal output terminal OUTPUT and the first level input terminal VSS under the control of the reset terminal RESET. It can be seen that the output circuit 3 provided by the above embodiment can electrically connect the gate driving signal output terminal OUTPUT with the first level input terminal VSS and the reset terminal RESET under the control of the pull-down node PD during the reset period P3.
  • the pull-up node control circuit 1 includes: a first switch tube T1, a second switch tube T2, and a third switch tube T3; wherein, the gate of the first switch tube T1 and the first The second pole of the switch tube T1 is connected to the input signal terminal INPUT, the first pole of the first switch tube T1 is connected to the pull-up node PU; the gate of the second switch tube T2 is connected to the reset terminal RESET, and the second switch tube T2
  • the first pole is connected to the first level input terminal VSS, the second pole of the second switch transistor T2 is connected to the pull-up node PU; the gate of the third switch transistor T3 is connected to the pull-down node PD, and the third switch transistor T3
  • the first pole is connected to the first level input terminal VSS, and the second pole of the third switching transistor T3 is connected to the pull-up node PU.
  • the input signal terminal INPUT controls the on and off of the first switch transistor T1, thereby controlling whether the input signal terminal INPUT is electrically connected to the pull-up node PU;
  • the reset terminal RESET controls the conduction and the turn-off of the second switch transistor T2, thereby
  • the pull-up node PD is controlled to be electrically connected to the first level input terminal VSS;
  • the pull-down node PD controls the on and off of the third switch transistor T3, thereby controlling whether the pull-up node PU and the first level input terminal VSS are electrically connected.
  • the output circuit 3 includes: a fourth switch tube T4, a fifth switch tube T5 and a sixth switch tube T6; wherein the gate of the fourth switch tube T4 is connected to the pull-up node PU, and the fourth switch tube T4
  • the first pole is connected to the gate driving signal output terminal OUTPUT, the second pole of the fourth switching transistor T4 is connected to the second clock signal input terminal CLK; the gate of the fifth switching transistor T5 is connected to the pull-down node PD, and the fifth switch
  • the first pole of the tube T5 is connected to the first level input terminal VSS, the second pole of the fifth switch tube T5 is connected to the gate drive signal output terminal OUTPUT, and the gate of the sixth switch tube T6 is connected to the reset terminal RESET.
  • the first pole of the six-switching tube T6 is connected to the first level input terminal VSS, and the second pole of the sixth switching transistor T6 is connected to the gate driving signal output terminal OUTPUT.
  • the pull-up node PU controls the turn-on and turn-off of the fourth switch T4, thereby controlling whether the second clock signal input terminal CLK and the gate drive signal output terminal OUTPUT are electrically connected;
  • the pull-down node PD controls the fifth switch transistor. Turning on and off of T5, thereby controlling whether the gate drive signal output terminal OUTPUT is electrically connected to the first level input terminal VSS;
  • the reset terminal RESET controls the on and off of the sixth switch transistor T6, thereby controlling the gate drive signal output. Whether the terminal OUTPUT is electrically connected to the first level input terminal VSS.
  • the pull-down node control circuit 2 includes: a seventh switch tube T7, an eighth switch tube T8, a ninth switch tube T9, and a tenth switch tube T10; wherein, the gate of the seventh switch tube T7 and the seventh switch The second pole of the tube T7 is connected to the first clock signal input terminal CLKB, the first pole of the seventh switch tube T7 is connected to the pull-down control node PD_CN; the gate of the eighth switch tube T8 is connected to the pull-up node PU, and the eighth The first pole of the switch tube T8 is connected to the first level input terminal VSS, the second pole of the eighth switch tube T8 is connected to the pull-down control node PD_CN, and the gate of the ninth switch tube T9 is connected to the pull-down control node PD_CN, the ninth The first pole of the switch tube T9 is connected to the pull-down node PD, the second pole of the ninth switch tube T9 is connected to the first clock signal input terminal CLKB, and the gate of the ninth switch tube T10
  • the first clock signal input terminal CLKB controls the on and off of the seventh switch transistor T7, thereby controlling whether the first clock signal input terminal CLKB and the pull-down control node PD_CN are electrically connected; the pull-up node PU controls the eighth switch transistor T8.
  • the pull-down control node PD_CN controls the on and off of the ninth switch transistor T9, thereby controlling the first clock signal input terminal CLKB and Whether the pull-down node PD is electrically connected; the pull-up node PU controls the on and off of the tenth switch T10, thereby controlling whether the first level input terminal VSS and the pull-down node PD are electrically connected.
  • the pull-down control node PD_CN is electrically connected to the first level input terminal VSS, and the potential of the pull-down control node PD_CN is controlled to be low.
  • the seventh switch transistor T7 is turned on, and under the control of the pull-up node PU, the eighth switch transistor T8 is turned off, so that the potential of the pull-down control node PD_CN is High potential
  • the tenth switch T10 is turned off, under the control of the high-potential pull-down control node PD_CN
  • the ninth switch T9 is turned on, thereby causing the pull-down node PD and the first clock signal
  • the input terminal CLKB is electrically connected to cause the potential of the pull-down node PD to become high.
  • the seventh switching transistor T7 and the ninth switching transistor T9 are periodically turned on and off, so that the potential of the pull-down control node PD_CN and the first clock signal input terminal
  • the potential of the first clock signal input by CLKB is the same, and the potential of the pull-down node PD is the same as the potential of the first clock signal input by the first clock signal input terminal CLKB.
  • the first enhanced noise reduction circuit 6 includes an eleventh switch tube T11, the gate of the eleventh switch tube T11 is connected to the first clock signal input terminal CLKB, and the eleventh switch tube T11 is One pole is connected to the pull-up node PU, and the second pole of the eleventh switch transistor T11 is connected to the input signal terminal INPUT; specifically, the first clock signal input terminal CLKB controls the turn-on and turn-off of the eleventh switch transistor T11, thereby Control whether the input signal terminal INPUT is electrically connected to the pull-up node PU.
  • the second enhanced noise reduction circuit 7 includes a twelfth switch tube T12, the gate of the twelfth switch tube T12 is connected to the first clock signal input terminal CLKB, and the twelfth switch tube T12 is One pole is connected to the first level input terminal VSS, and the second pole of the twelfth switch transistor T12 is connected to the gate drive signal output terminal OUTPUT.
  • the first clock signal input terminal CLKB controls the on and off of the twelfth switch transistor T12, thereby controlling whether the gate drive signal output terminal OUTPUT is electrically connected to the first level input terminal VSS.
  • the capacitor circuit 4 provided by the above embodiment includes a first capacitor C1, a first end of the first capacitor C1 is connected to the pull-up node, and a second end of the first capacitor C1 is coupled to a gate driving signal. The output is connected.
  • each of the switching transistors is an N-type transistor, and the first extreme source and the second extreme drain are taken as an example for description.
  • the circuit design of each of the above switching tubes may also be a P-type transistor, and each switching tube is a P-type transistor is also within the protection scope of the present application.
  • the first level signal input by the first level input terminal VSS can be selected as a low level signal, and the first level input terminal VSS can be connected to the negative pole of the power source, but is not limited thereto.
  • the embodiment of the present disclosure further provides a gate driving circuit, including the shift register unit provided by the above embodiment.
  • the gate driving circuit includes a plurality of shift register units, wherein the N-1th gate drive signal output end corresponding to the N-1th shift register unit corresponds to the Nth shift register unit
  • the N input signal terminal is connected, and the Nth reset terminal corresponding to the Nth shift register unit is connected to the N+1th gate drive signal output end corresponding to the N+1th shift register unit, wherein N is greater than or equal to An integer of 2.
  • the noise reduction adjustment circuit 5 can slowly increase the potential of the pull-down node PD from a low potential to a high potential during the noise reduction period, thereby achieving assurance
  • the noise reduction capability of the shift register unit improves the leakage resistance of the shift register unit; and in the non-noise reduction period, the potential of the pull-down node PD is slowly lowered from a high potential to a low potential, thereby achieving a guaranteed shift
  • the bit register unit maintains a certain level of noise reduction while resisting leakage.
  • the gate driving circuit provided by the embodiment of the present disclosure includes the above-mentioned shift register unit, it is also possible to ensure the noise reduction capability and the occurrence of the leakage current during the holding period P4, thereby ensuring the gate driving well.
  • the working stability of the circuit is also possible to ensure the noise reduction capability and the occurrence of the leakage current during the holding period P4, thereby ensuring the gate driving well.
  • a complete panel is prepared by a process such as film formation, exposure, etching, and the like.
  • the embodiment of the present disclosure further provides a driving method of a shift register unit, which is applied to the shift register unit provided by the above embodiment, and the driving method includes: a noise reduction adjusting circuit 5 during a noise reduction period in the holding period P4 The control reduces the rate of rise of the potential of the pull-down node PD; during the non-noise reduction period in the hold period P4, the noise reduction adjustment circuit 5 controls to decrease the rate of decrease of the potential of the pull-down node PD.
  • one working cycle of the shift register unit includes an input period P1, an output period P2, a reset period P3, and a hold period P4, and the driving method for driving the shift register unit to work in one duty cycle includes:
  • the pull-up node control circuit 1 controls the input signal terminal INPUT to electrically connect with the pull-up node PU to pull the potential of the pull-up node PU high; the control of the pull-up node PU
  • the pull-down node control circuit 2 controls the pull-down node PD and the first level input terminal VSS to be electrically connected.
  • the output circuit 3 controls the second clock signal input terminal CLK to be electrically connected with the gate drive signal output terminal OUTPUT to enable the gate drive signal output.
  • the terminal OUTPUT outputs a gate driving signal and further increases the potential of the pull-up node PU; under the control of the pull-up node PU, the pull-down node control circuit 2 continues to control the pull-down node PD and the first level input terminal VSS to be electrically connected.
  • the pull-up node control circuit 1 controls the pull-up node PU to be electrically connected to the first level input terminal VSS, pulling the potential of the pull-up node PU low; at the first clock signal Under the control of the input terminal CLKB and the low-potential pull-up node PU, the pull-down node control circuit 2 controls the first clock signal input terminal CLKB to be electrically connected to the pull-down node PD to pull the potential of the pull-down node PD high; the pull-down node at the high potential Under the control of the PD, the pull-up node control circuit 1 controls the pull-up node PU to be electrically connected to the first level input terminal VSS; under the control of the high-potential pull-down node PD, the output circuit 3 controls the gate drive signal output terminal OUTPUT and The first level input terminal VSS is electrically connected, so that the gate driving signal output terminal OUTPUT does not output the gate driving signal; under the control
  • the pull-down node control circuit 2 controls the potential of the pull-down node PD and the first input (of the first clock signal input terminal CLKB)
  • the clock signal is synchronously changed; further, the hold period P4 includes a noise reduction period M1 and a non-noise reduction period M2.
  • the potential of the pull-down node PD follows the first clock signal to change to a high potential, and the high potential pull-down
  • the node PD can electrically connect the gate driving signal output terminal OUTPUT to the first level input terminal VSS through the control output circuit 3, and can control the pull-up node control circuit 1 to bring up the pull-up node PU and the first level input terminal VSS. Electrically connected to achieve noise reduction of the shift register unit.
  • the potential of the pull-down node PD changes to a low level following the first clock signal, so that the thin film transistors in the modules connected to the pull-down node PD do not generate high leakage, thereby reducing the thin film transistors.
  • the pull-up node PU is at a low potential, and under the control of the low-potential pull-up node PU, the output circuit 3 controls the gate driving signal output terminal OUTPUT and the second clock signal input terminal CLK to be non-powered. The connection further causes the gate driving signal output terminal OUTPUT not to output the gate driving signal.
  • the noise reduction adjustment circuit 5 regulates the rate of change of the potential of the pull-down node PD, specifically, during the noise reduction period in the holding period P4, the rate of increase of the potential of the pull-down node PD is controlled to decrease; During the non-noise reduction period in the hold period P4, the control reduces the rate of decrease of the potential of the pull-down node PD.
  • the rising rate of the potential of the pull-down node PD can be controlled during the noise reduction period in the holding period P4, and the non-noise reduction period in the holding period P4 Controlling the rate of decrease of the potential of the pull-down node PD; therefore, when the above-described shift register unit is driven by the driving method provided by the embodiment of the present disclosure, the potential of the pull-down node PD can be slowly increased from the low potential during the noise reduction period Up to a high potential, thereby improving the anti-leakage capability of the shift register unit while ensuring the noise reduction capability of the shift register unit; and in the non-noise reduction period, the potential of the pull-down node PD is slowly lowered from a high potential to a low level.
  • the potential is such that a certain noise reduction capability is maintained while ensuring the leakage resistance of the shift register unit.
  • the noise reduction capability of the shift register unit can be ensured in the holding period P4, and the occurrence of leakage is reduced, which not only makes the process in long-term use.
  • the characteristics of the thin film transistor in the shift register unit are stable, the threshold voltage shift is not easy to occur, and the shift register unit can maintain good noise reduction performance throughout the holding period P4, thereby ensuring a good shift.
  • the working stability of the register unit is not only made the process in long-term use.

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Abstract

一种移位寄存器单元及其驱动方法、栅极驱动电路。所述移位寄存器单元包括：上拉节点控制模块（1）、下拉节点控制模块（2）、电容模块（4）、输出模块（3）和降噪调节模块（5）；其中降噪调节模块（5）分别与下拉节点（PD）和第一电平输入端(VSS)连接，所述降噪调节模块（5）用于：在保持时段中的降噪时段，控制降低所述下拉节点（PD）的电位的上升速率；在保持时段中的非降噪时段，控制降低所述下拉节点（PD）的电位的下降速率

Description

移位寄存器单元及其驱动方法、栅极驱动电路
相关申请的交叉引用
本申请主张在2018年3月19日在中国提交的中国专利申请No.201810223962.1的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器单元及其驱动方法、栅极驱动电路。
背景技术
随着显示技术的不断发展，越来越多的显示装置采用阵列基板行驱动(英文：Gate On Array，以下简称GOA)技术，这种GOA技术是直接将栅极驱动电路集成在阵列基板的非显示区域上，在缩小了阵列基板的边框宽度的同时，还降低了生产成本，减少了生产工序。利用GOA技术集成在阵列基板上的栅极驱动电路包括若干个移位寄存器单元，每个移位寄存器单元对应阵列基板上的一条栅线，并通过输出栅极驱动信号来实现对该条栅线的驱动。
相关技术中的移位寄存器单元的每个工作周期中，在保持时段，移位寄存器单元能够通过时钟信号控制移位寄存器单元中的下拉节点的电位，进而控制移位寄存器单元的栅极驱动信号输出端处于没有输出的悬浮状态。但是在保持时段中当时钟信号处于高电平的状态时，容易导致移位寄存器单元中的漏电增加，进而使得移位寄存器单元中的薄膜晶体管的特性正向偏移；而当时钟信号处于低电平的状态时，会使得移位寄存器单元失去降噪能力，进而容易导致移位寄存器单元输出异常。
发明内容
本公开的目的在于提供一种移位寄存器单元及其驱动方法、栅极驱动电路。
本公开的第一方面提供一种移位寄存器单元，包括：
上拉节点控制电路，分别与输入信号端、上拉节点、复位端、第一电平输入端和下拉节点连接；
下拉节点控制电路，分别与第一时钟信号输入端、所述上拉节点、所述第一电平输入端和所述下拉节点连接；
电容电路，分别与所述上拉节点和栅极驱动信号输出端连接；
输出电路，分别与第二时钟信号输入端、所述上拉节点、所述下拉节点、所述栅极驱动信号输出端、所述第一电平输入端和所述复位端连接；
降噪调节电路，分别与所述下拉节点和所述第一电平输入端连接，所述降噪调节电路用于：在所述移位寄存器单元的保持时段中的降噪时段，控制降低所述下拉节点的电位的上升速率；在所述保持时段中的非降噪时段，控制降低所述下拉节点的电位的下降速率。
进一步地，所述降噪调节电路包括第二电容，所述第二电容的第一端与所述下拉节点连接，所述第二电容的第二端与所述第一电平输入端连接。
进一步地，所述降噪调节电路还包括第一电阻，所述第二电容的第二端通过所述第一电阻与所述第一电平输入端连接。
进一步地，所述移位寄存器单元还包括：
第一增强降噪电路，分别与所述输入信号端、所述第一时钟信号输入端和所述上拉节点连接，所述第一增强降噪电路用于：在所述第一时钟信号输入端的控制下，控制导通或断开所述输入信号端和所述上拉节点之间的电连接；和/或，
第二增强降噪电路，分别与所述栅极驱动信号输出端、所述第一电平输入端和所述第一时钟信号输入端连接，所述第二增强降噪电路用于：在所述第一时钟信号输入端的控制下，控制导通或断开所述栅极驱动信号输出端和所述第一电平输入端之间的电连接。
进一步地，所述上拉节点控制电路用于：在所述输入信号端的控制下，控制导通或断开所述上拉节点和所述输入信号端之间的电连接，在所述复位端的控制下，控制导通或断开所述上拉节点和所述第一电平输入端之间的电连接，在所述下拉节点的控制下，控制导通或断开所述上拉节点和所述第一 电平输入端之间的电连接；
所述输出电路用于：在所述上拉节点的控制下，控制导通或断开所述第二时钟信号输入端与所述栅极驱动信号输出端之间的电连接；在所述下拉节点的控制下，控制导通或断开所述栅极驱动信号输出端和所述第一电平输入端之间的电连接；在所述复位端的控制下，控制导通或断开所述栅极驱动信号输出端和所述第一电平输入端之间的电连接。
进一步地，所述上拉节点控制电路包括：第一开关管、第二开关管和第三开关管；其中，
所述第一开关管的栅极和所述第一开关管的第二极均与所述输入信号端连接，所述第一开关管的第一极与所述上拉节点连接；
所述第二开关管的栅极与所述复位端连接，所述第二开关管的第一极与所述第一电平输入端连接，所述第二开关管的第二极与所述上拉节点连接；
所述第三开关管的栅极与所述下拉节点连接，所述第三开关管的第一极与所述第一电平输入端连接，所述第三开关管的第二极与所述上拉节点连接。
进一步地，所述输出电路包括：第四开关管、第五开关管和第六开关管；其中，
所述第四开关管的栅极与所述上拉节点连接，所述第四开关管的第一极与所述栅极驱动信号输出端连接，所述第四开关管的第二极与所述第二时钟信号输入端连接；
所述第五开关管的栅极与所述下拉节点连接，所述第五开关管的第一极与所述第一电平输入端连接，所述第五开关管的第二极与所述栅极驱动信号输出端连接；
所述第六开关管的栅极与所述复位端连接，所述第六开关管的第一极与所述第一电平输入端连接，所述第六开关管的第二极与所述栅极驱动信号输出端连接。
进一步地，所述下拉节点控制电路包括：第七开关管、第八开关管、第九开关管和第十开关管；其中，
所述第七开关管的栅极和所述第七开关管的第二极均与所述第一时钟信 号输入端连接，所述第七开关管的第一极与下拉控制节点连接；
所述第八开关管的栅极与所述上拉节点连接，所述第八开关管的第一极与所述第一电平输入端连接，所述第八开关管的第二极与所述下拉控制节点连接；
所述第九开关管的栅极与所述下拉控制节点连接，所述第九开关管的第一极与所述下拉节点连接，所述第九开关管的第二极与所述第一时钟信号输入端连接；
所述第十开关管的栅极与所述上拉节点连接，所述第十开关管的第一极与所述第一电平输入端连接，所述第十开关管的第二极与所述下拉节点连接。
进一步地，第一增强降噪电路包括第十一开关管，所述第十一开关管的栅极与所述第一时钟信号输入端连接，所述第十一开关管的第一极与所述上拉节点连接，所述第十一开关管的第二极与所述输入信号端连接；
第二增强降噪电路包括第十二开关管，所述第十二开关管的栅极与所述第一时钟信号输入端连接，所述第十二开关管的第一极与所述第一电平输入端连接，所述第十二开关管的第二极与所述栅极驱动信号输出端连接。
进一步地，所述电容电路包括第一电容，所述第一电容的第一端与所述上拉节点连接，所述第一电容的第二端与所述栅极驱动信号输出端连接。
进一步地，在所述降噪时段，从所述第一时钟信号输入端所输入的第一时钟信号为低电平，从所述第二时钟信号输入端所输入的第二时钟信号为高电平，并且从所述复位端输入的复位信号为低电平；以及在所述非降噪时段，从所述第一时钟信号输入端所输入的第一时钟信号为高电平，从所述第二时钟信号输入端所输入的第二时钟信号为低电平，并且从所述复位端输入的复位信号为低电平。
基于上述移位寄存器单元的技术方案，本公开的第二方面提供一种栅极驱动电路，包括上述移位寄存器单元。
基于上述移位寄存器单元的技术方案，本公开的第三方面提供一种移位寄存器单元的驱动方法，应用于上述移位寄存器单元，所述驱动方法包括：
在保持时段中的降噪时段，降噪调节电路控制降低下拉节点的电位的上 升速率；在保持时段中的非降噪时段，所述降噪调节电路控制降低所述下拉节点的电位的下降速率。
进一步地，在所述降噪时段，向所述第一时钟信号输入端施加低电平的第一时钟信号，向所述第二时钟信号输入端施加高电平的第二时钟信号，并且向所述复位端施加低电平的复位信号；以及在所述非降噪时段，向所述第一时钟信号输入端施加高电平的第一时钟信号，向所述第二时钟信号输入端施加低电平的第二时钟信号，并且向所述复位端施加低电平的复位信号。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的移位寄存器单元的模块示意图；
图2为本公开实施例提供的移位寄存器单元的工作时序图；
图3为本公开实施例提供的移位寄存器单元的结构示意图；
图4为本公开实施例提供的降噪调节电路取不同值时对应的PD点的电位示意图；
图5为本公开实施例提供的降噪调节电路中的电阻示意图。
具体实施方式
为了进一步说明本公开实施例提供的移位寄存器单元及其驱动方法、栅极驱动电路，下面结合说明书附图进行详细描述。
相关技术中的移位寄存器单元的一个工作周期依次包括：输入时段、输出时段、复位时段和保持时段，其中在输入时段、输出时段和复位时段主要实现如下功能：先通过移位寄存器单元中的栅极驱动信号输出端输出栅极驱动信号至阵列基板上对应的栅线，然后再将栅极驱动信号复位至栅极关断电压；在保持时段，通过时钟信号控制移位寄存器单元中的部分薄膜晶体管工作，从而使得栅极驱动信号输出端的电位能够保持在栅极关断电压。
相关技术中，移位寄存器单元根据实际工作情况的不同，可设置时钟信号在保持时段为具有高、低电平的方波信号，也可设置时钟信号在保持时段为直流的低电平信号或直流的高电平信号。但是无论时钟信号在保持阶段为哪种类型的信号，均会导致移位寄存器单元容易出现如下问题：
问题一，时钟信号处于高电平，可能导致移位寄存器单元中与时钟信号相关联的薄膜晶体管出现严重的漏电情况，进而使得在长期使用中，薄膜晶体管容易出现阈值电压漂移，导致移位寄存器单元的输出异常，产生信赖性问题。
问题二，时钟信号处于低电平，可能导致移位寄存器单元中用于实现降噪功能的薄膜晶体管处于截止状态，进而使得移位寄存器单元失去降噪能力，导致移位寄存器单元输出异常。
除上述问题之外，由于为了保证移位寄存器单元的正常工作，时钟信号在整个工作周期中，会在高电平和低电平之间变化，使得移位寄存器单元仅能够在部分时间内控制用于降噪的薄膜晶体管导通，进而使移位寄存单元具有降噪能力，可见，相关技术中的移位寄存器单元还存在降噪时间较短，容易出现噪声的问题。
基于上述问题的存在，本公开实施例提供了一种移位寄存器单元，如图1所示，该移位寄存器单元包括：上拉节点控制电路1、下拉节点控制电路2、电容电路4、输出电路3和降噪调节电路5；其中，上拉节点控制电路1分别与输入信号端INPUT、上拉节点PU、复位端RESET、第一电平输入端VSS和下拉节点PD连接；下拉节点控制电路2分别与第一时钟信号输入端CLKB、上拉节点PU、第一电平输入端VSS和下拉节点PD连接；电容电路4的第一端与上拉节点PU连接，电容电路4的第二端与栅极驱动信号输出端OUTPUT连接；输出电路3分别与第二时钟信号输入端CLK、上拉节点PU、下拉节点PD、栅极驱动信号输出端OUTPUT、第一电平输入端VSS和复位端RESET连接；降噪调节电路5分别与下拉节点PD和第一电平输入端VSS连接，且降噪调节电路5用于：在保持时段P4中的降噪时段，控制降低下拉节点PD的电位的上升速率；在保持时段P4中的非降噪时段，控制降低下拉节点PD 的电位的下降速率。
具体地，如图2所示，上述移位寄存器单元的一个工作周期依次包括：输入时段P1、输出时段P2、复位时段P3和保持时段P4，在一个工作周期内移位寄存器单元的工作过程为：
在输入时段P1，在输入信号端INPUT的控制下，上拉节点控制电路1控制输入信号端INPUT与上拉节点PU电连接，将上拉节点PU的电位拉高；在上拉节点PU的控制下，下拉节点控制电路2控制下拉节点PD和第一电平输入端VSS电连接。
在输出时段P2，在第二时钟信号输入端CLK和上拉节点PU的控制下，输出电路3控制第二时钟信号输入端CLK与栅极驱动信号输出端OUTPUT电连接，使栅极驱动信号输出端OUTPUT输出栅极驱动信号，并将上拉节点PU的电位进一步拉高；在上拉节点PU的控制下，下拉节点控制电路2继续控制下拉节点PD和第一电平输入端VSS电连接。
在复位时段P3，在复位端RESET的控制下，上拉节点控制电路1控制上拉节点PU与第一电平输入端VSS电连接，将上拉节点PU的电位拉低；在第一时钟信号输入端CLKB和低电位的上拉节点PU的控制下，下拉节点控制电路2控制第一时钟信号输入端CLKB与下拉节点PD电连接，将下拉节点PD的电位拉高；在高电位的下拉节点PD的控制下，上拉节点控制电路1控制上拉节点PU与第一电平输入端VSS电连接；在高电位的下拉节点PD的控制下，输出电路3控制栅极驱动信号输出端OUTPUT与第一电平输入端VSS电连接，使栅极驱动信号输出端OUTPUT不输出栅极驱动信号；在复位端RESET的控制下，输出电路3控制栅极驱动信号输出端OUTPUT与第一电平输入端VSS电连接。
在保持时段P4，在第一时钟信号输入端CLKB和低电位的上拉节点PU的控制下，下拉节点控制电路2控制下拉节点PD的电位与(由第一时钟信号输入端CLKB输入的)第一时钟信号同步变化；进一步地，该保持时段P4包括降噪时段M1和非降噪时段M2，在降噪时段M1中，下拉节点PD的电位跟随第一时钟信号变化为高电位，高电位的下拉节点PD能够通过控制输 出电路3使栅极驱动信号输出端OUTPUT与第一电平输入端VSS电连接，并能够通过控制上拉节点控制电路1使上拉节点PU与第一电平输入端VSS电连接，从而实现对移位寄存器单元的降噪作用。在非降噪时段M2，下拉节点PD的电位跟随第一时钟信号变化为低电位，使得与下拉节点PD连接的各模块中的薄膜晶体管均不会产生较高的漏电，从而降低了各薄膜晶体管特性正向偏移的风险。另外，在该保持时段P4中，上拉节点PU处于低电位，在低电位的上拉节点PU的控制下，输出电路3控制栅极驱动信号输出端OUTPUT与第二时钟信号输入端CLK不电连接，进一步使得栅极驱动信号输出端OUTPUT不输出栅极驱动信号。
此外，在该保持时段P4中，降噪调节电路5对下拉节点PD的电位的变化速率进行调控，具体地，在保持时段P4中的降噪时段，控制降低下拉节点PD的电位的上升速率；在保持时段P4中的非降噪时段，控制降低下拉节点PD的电位的下降速率。
结合上述实施例提供的移位寄存器单元的结构和具体工作过程可知，本公开实施例提供的移位寄存器单元中，包括降噪调节电路5，该降噪调节电路5分别与下拉节点PD和第一电平输入端VSS连接，用于在保持时段P4中的降噪时段，控制降低下拉节点PD的电位的上升速率，在保持时段P4中的非降噪时段，控制降低下拉节点PD的电位的下降速率。因此，本公开实施例提供的移位寄存器单元相比于相关技术中的移位寄存器单元，能够在降噪时段中，使下拉节点PD的电位由低电位缓慢上升至高电位，从而实现在保证移位寄存器单元的降噪能力的同时，提升了移位寄存器单元的抗漏电能力；而且在非降噪时段中，使下拉节点PD的电位由高电位缓慢下降至低电位，从而实现在保证移位寄存器单元的抗漏电能力的同时，保持一定的降噪能力。
可见，本公开实施例提供的移位寄存器单元能够在保持时段P4既保证降噪能力，又减少漏电情况的发生，不仅使得在长期使用的过程中，移位寄存器单元中的薄膜晶体管的特性稳定，不容易发生阈值电压偏移，还使得移位寄存器单元在整个保持时段P4均能够保持良好的降噪性能，从而很好地保证 了移位寄存器单元的工作稳定性。
上述实施例提供的降噪调节电路5的具体结构多种多样，可选地，如图3所示，降噪调节电路5包括降噪电容C2，降噪电容C2的第一端与下拉节点PD连接，降噪电容C2的第二端与第一电平输入端VSS连接。
具体地，当上述降噪调节电路5包括降噪电容C2时，在降噪时段，下拉节点PD的电位跟随第一时钟信号变化为高电位的过程中，需要同时对降噪电容C2进行充电，从而延长了下拉节点PD变为高电平的时间，减缓了下拉节点PD的电位的上升速率。在非降噪时段，下拉节点PD的电位跟随第一时钟信号变化为低电位的过程中，由于降噪电容C2能够存储一定量的电荷，从而延长了下拉节点PD变为低电平的时间，减缓了下拉节点PD的电位的下降速率。因此，当上述降噪调节电路5包括降噪电容C2时，相比于相关技术中的移位寄存器单元，降噪电容C2能够在降噪时段减缓下拉节点PD的电位的上升速率，并能够在非降噪时段减缓了下拉节点PD的电位的下降速率，从而使得移位寄存器单元能够在整个保持时段P4中既具有降噪能力，又能够减少漏电情况的发生，保证了移位寄存器单元能够更稳定的工作。
进一步地，上述实施例提供的降噪调节电路5还可以包括降噪电阻R，且降噪电容C2的第二端通过降噪电阻R与第一电平输入端VSS连接。
具体地，当上述降噪调节电路5还包括连接在降噪电容C2和第一电平输入端VSS之间的降噪电阻R时，该降噪电阻R具有限流作用，从而进一步减少移位寄存器单元中漏电情况的产生。
值得注意的是，可通过调节降噪电容C2和降噪电阻R的取值，来使得移位寄存器单元能够实现不同的降噪能力和抗漏电能力，如图4所示，图4中绘制的第一条曲线101、第二条曲线102、第三条曲线103、第四条曲线104。第五条曲线105和第六条曲线106，是分别代表不同降噪电容C2值和降噪电阻R值下，下拉节点PD在保持时段P4的波形图；其中，第一条曲线101对应降噪电容C2和降噪电阻R均为0时，下拉节点PD在保持时段P4对应的曲线，能够看出在降噪电容C2和降噪电阻R均为0时，下拉节点PD对应的第一曲线101在A区域(非降噪时段)能够快速地由高电平变为低电平，导 致在该非降噪时段，移位寄存器单元基本不具备降噪能力，而且第一曲线101在B区域(降噪时段)能够快速地由低电平变为高电平，导致在该降噪时段，会增加移位寄存器单元的漏电。
在改变降噪电容C2的容值和降噪电阻R的阻值后，能够对应得到其他的五条曲线，从图4中能够看出，在逐渐增大降噪电容C2的容值和降噪电阻R的阻值时，能够对应得到第二曲线102至第六曲线106，即降噪电容C2的容值和降噪电阻R的阻值的取值越大，下拉节点PD对应的曲线在A区域的下降速率越慢，在B区域的上升速率越慢，从而使得下拉节点PD在非降噪时间内具有较高的取值，在降噪时间内具有较低的取值，很好地保证了移位寄存器单元在保持时段P4既具有降噪能力，又具有抗漏电能力。
进一步地，上述降噪电阻R可以通过多种方式制备，如图5所示，可通过在对应的栅极GATE和源漏金属电极SD之间制作ITO图形，并通过调节ITO图形的形状来调节所形成的降噪电阻R的阻值。具体地，通过过孔VIA在栅极GATE和源漏金属电极SD之间形成ITO图形，并可以进一步对形成的ITO图形进行构图，将其变为蛇形走线，通过调节蛇形走线的宽度和长度，来调节降噪电阻R的阻值。
进一步地，请继续参阅图1，上述实施例提供的移位寄存器单元还包括：第一增强降噪电路6和/或第二增强降噪电路7，其中，第一增强降噪电路6分别与输入信号端INPUT、第一时钟信号输入端CLKB和上拉节点PU连接，第一增强降噪电路6用于：在第一时钟信号输入端CLKB的控制下，控制导通或断开输入信号端INPUT和上拉节点PU之间的电连接；第二增强降噪电路7，分别与栅极驱动信号输出端OUTPUT、第一电平输入端VSS和第一时钟信号输入端CLKB连接，第二增强降噪电路7用于：在第一时钟信号输入端CLKB的控制下，控制导通或断开栅极驱动信号输出端OUTPUT和第一电平输入端VSS之间的电连接。
具体地，第一增强降噪电路6能够在输入时段P1和复位时段P3，在第一时钟信号输入端CLKB的控制下，控制导通输入信号端INPUT和上拉节点PU之间的电连接，使得上拉节点PU的电位能够在输入时段P1更好地被拉 高，并在复位时段P3更好地被拉低，从而实现对上拉节点PU的电位更有效的控制，提升了移位寄存器单元的降噪能力，保证了移位寄存器单元工作的稳定性。第一增强降噪电路6还能够在保持时段P4中的部分时段(例如：第一时钟信号输入端CLKB输入的第一时钟信号处于高电平的时段)控制导通输入信号端INPUT和上拉节点PU之间的电连接，使得上拉节点PU的电位能够在该部分时段中被拉低，从而更好地提升移位寄存器单元的降噪能力，保证了移位寄存器单元工作的稳定性。
第二增强降噪电路7能够在输入时段P1和复位时段P3，在第一时钟信号输入端CLKB的控制下，控制导通栅极驱动信号输出端OUTPUT和第一电平输入端VSS之间的电连接，使得栅极驱动信号输出端OUTPUT的电位能够在输入时段P1和复位时段P3更好地被拉低，从而实现对栅极驱动信号输出端OUTPUT的电位更有效的控制，提升了移位寄存器单元的降噪能力，保证了移位寄存器单元工作的稳定性。此外，第二增强降噪电路7还能够在保持时段P4中的部分时段控制导通栅极驱动信号输出端OUTPUT和第一电平输入端VSS之间的电连接，使得栅极驱动信号输出端OUTPUT的电位能够在该部分时段中被拉低，从而更好地提升移位寄存器单元的降噪能力，保证了移位寄存器单元工作的稳定性。
进一步地，上述实施例提供的上拉节点控制电路1用于：在输入信号端INPUT的控制下，控制导通或断开上拉节点PU和输入信号端INPUT之间的电连接，在复位端RESET的控制下，控制导通或断开上拉节点PU和第一电平输入端VSS之间的电连接，在下拉节点PD的控制下，控制导通或断开上拉节点PU和第一电平输入端VSS之间的电连接。
具体地，在输入时段P1，上拉节点控制电路1用于在输入信号端INPUT的控制下，控制导通上拉节点PU与输入信号端INPUT之间的电连接，在除输入时段P1之外的其它时段，上拉节点控制电路1用于在输入信号端INPUT的控制下，控制断开上拉节点PU与输入信号端INPUT之间的电连接。在复位时段P3，上拉节点控制电路1用于在复位端RESET的控制下，控制导通上拉节点PU和第一电平输入端VSS之间的电连接，以及在下拉节点PD的 控制下，控制导通上拉节点PU和第一电平输入端VSS之间的电连接。在输入时段P1和输出时段P2，上拉节点控制电路1用于在复位端RESET的控制下，控制断开上拉节点PU和第一电平输入端VSS之间的电连接，以及在下拉节点PD的控制下，控制断开上拉节点PU和第一电平输入端VSS之间的电连接。在保持时段P4，上拉节点控制电路1用于在下拉节点PD的控制下，控制上拉节点PU和第一电平输入端VSS周期性地电连接与断开电连接。
进一步地，上述实施例提供的输出电路3用于：在上拉节点PU的控制下，控制导通或断开第二时钟信号输入端CLK与栅极驱动信号输出端OUTPUT之间的电连接；在下拉节点PD的控制下，控制导通或断开栅极驱动信号输出端OUTPUT和第一电平输入端VSS之间的电连接；在复位端RESET的控制下，控制导通或断开栅极驱动信号输出端OUTPUT和第一电平输入端VSS之间的电连接。
具体地，在输入时段P1和输出时段P2，输出电路3用于在上拉节点PU的控制下，控制导通第二时钟信号输入端CLK与栅极驱动信号输出端OUTPUT之间的电连接，在复位时段P3和保持时段P4，输出电路3用于在上拉节点PU的控制下，控制断开第二时钟信号输入端CLK与栅极驱动信号输出端OUTPUT之间的电连接。在输入时段P1和输出时段P2，输出电路3还用于在下拉节点PD的控制下，控制断开栅极驱动信号输出端OUTPUT和第一电平输入端VSS之间的电连接，在复位时段P3，输出电路3还用于在下拉节点PD的控制下，控制导通栅极驱动信号输出端OUTPUT和第一电平输入端VSS之间的电连接，在保持时段P4，输出电路3还用于在下拉节点PD的控制下，控制栅极驱动信号输出端OUTPUT和第一电平输入端VSS周期性地电连接与断开电连接。
另外，在复位时段P3，输出电路3还用于在复位端RESET的控制下，控制导通栅极驱动信号输出端OUTPUT和第一电平输入端VSS之间的电连接；在输入时段P1和输出时段P2，输出电路3还用于在复位端RESET的控制下，控制断开栅极驱动信号输出端OUTPUT和第一电平输入端VSS之间的电连接。可见，上述实施例提供的输出电路3在复位时段P3，既能够在下 拉节点PD的控制下，将栅极驱动信号输出端OUTPUT与第一电平输入端VSS电连接，又能够在复位端RESET的控制下，将栅极驱动信号输出端OUTPUT与第一电平输入端VSS电连接更好地保证了在复位时段P3，栅极驱动信号输出端OUTPUT不会输出栅极驱动信号，保证了移位寄存器单元工作的稳定性。
请继续参阅图3，上述实施例提供的上拉节点控制电路1包括：第一开关管T1、第二开关管T2和第三开关管T3；其中，第一开关管T1的栅极和第一开关管T1的第二极均与输入信号端INPUT连接，第一开关管T1的第一极与上拉节点PU连接；第二开关管T2的栅极与复位端RESET连接，第二开关管T2的第一极与第一电平输入端VSS连接，第二开关管T2的第二极与上拉节点PU连接；第三开关管T3的栅极与下拉节点PD连接，第三开关管T3的第一极与第一电平输入端VSS连接，第三开关管T3的第二极与上拉节点PU连接。
具体地，输入信号端INPUT控制第一开关管T1的导通与截止，从而控制输入信号端INPUT与上拉节点PU是否电连接；复位端RESET控制第二开关管T2的导通与截止，从而控制上拉节点PU与第一电平输入端VSS是否电连接；下拉节点PD控制第三开关管T3的导通与截止，从而控制上拉节点PU与第一电平输入端VSS是否电连接。
上述实施例提供的输出电路3包括：第四开关管T4、第五开关管T5和第六开关管T6；其中，第四开关管T4的栅极与上拉节点PU连接，第四开关管T4的第一极与栅极驱动信号输出端OUTPUT连接，第四开关管T4的第二极与第二时钟信号输入端CLK连接；第五开关管T5的栅极与下拉节点PD连接，第五开关管T5的第一极与第一电平输入端VSS连接，第五开关管T5的第二极与栅极驱动信号输出端OUTPUT连接；第六开关管T6的栅极与复位端RESET连接，第六开关管T6的第一极与第一电平输入端VSS连接，第六开关管T6的第二极与栅极驱动信号输出端OUTPUT连接。
更详细的说，上拉节点PU控制第四开关管T4的导通与截止，从而控制第二时钟信号输入端CLK与栅极驱动信号输出端OUTPUT是否电连接；下拉节点PD控制第五开关管T5的导通与截止，从而控制栅极驱动信号输出端 OUTPUT与第一电平输入端VSS是否电连接；复位端RESET控制第六开关管T6的导通与截止，从而控制栅极驱动信号输出端OUTPUT与第一电平输入端VSS是否电连接。
上述实施例提供的下拉节点控制电路2包括：第七开关管T7、第八开关管T8、第九开关管T9和第十开关管T10；其中，第七开关管T7的栅极和第七开关管T7的第二极均与第一时钟信号输入端CLKB连接，第七开关管T7的第一极与下拉控制节点PD_CN连接；第八开关管T8的栅极与上拉节点PU连接，第八开关管T8的第一极与第一电平输入端VSS连接，第八开关管T8的第二极与下拉控制节点PD_CN连接；第九开关管T9的栅极与下拉控制节点PD_CN连接，第九开关管T9的第一极与下拉节点PD连接，第九开关管T9的第二极与第一时钟信号输入端CLKB连接；第十开关管T10的栅极与上拉节点PU连接，第十开关管T10的第一极与第一电平输入端VSS连接，第十开关管T10的第二极与下拉节点PD连接。
具体地，第一时钟信号输入端CLKB控制第七开关管T7的导通与截止，从而控制第一时钟信号输入端CLKB与下拉控制节点PD_CN是否电连接；上拉节点PU控制第八开关管T8的导通与截止，从而控制下拉控制节点PD_CN与第一电平输入端VSS是否电连接；下拉控制节点PD_CN控制第九开关管T9的导通与截止，从而控制第一时钟信号输入端CLKB与下拉节点PD是否电连接；上拉节点PU控制第十开关管T10的导通与截止，从而控制第一电平输入端VSS与下拉节点PD是否电连接。
更详细地说，在输入时段P1和输出时段P2，在第一时钟信号输入端CLKB的控制下，第七开关管T7导通，在上拉节点PU的控制下，第八开关管T8导通，从而使得下拉控制节点PD_CN与第一电平输入端VSS电连接，控制下拉控制节点PD_CN的电位为低电位。在复位时段P3，在第一时钟信号输入端CLKB的控制下，第七开关管T7导通，在上拉节点PU的控制下，第八开关管T8截止，从而使得下拉控制节点PD_CN的电位为高电位，在上拉节点PU的控制下，第十开关管T10截止，在高电位的下拉控制节点PD_CN的控制下，第九开关管T9的导通，从而使得下拉节点PD与第一时钟信号输 入端CLKB电连接，使下拉节点PD得电位变为高电位。在保持时段P4，在第一时钟信号输入端CLKB的控制下，第七开关管T7和第九开关管T9周期性的导通和截止，使得下拉控制节点PD_CN的电位与第一时钟信号输入端CLKB输入的第一时钟信号的电位相同，下拉节点PD的电位与第一时钟信号输入端CLKB输入的第一时钟信号的电位相同。
进一步地，上述实施例提供的第一增强降噪电路6包括第十一开关管T11，第十一开关管T11的栅极与第一时钟信号输入端CLKB连接，第十一开关管T11的第一极与上拉节点PU连接，第十一开关管T11的第二极与输入信号端INPUT连接；具体地，第一时钟信号输入端CLKB控制第十一开关管T11的导通与截止，从而控制输入信号端INPUT与上拉节点PU是否电连接。
进一步地，上述实施例提供的第二增强降噪电路7包括第十二开关管T12，第十二开关管T12的栅极与第一时钟信号输入端CLKB连接，第十二开关管T12的第一极与第一电平输入端VSS连接，第十二开关管T12的第二极与栅极驱动信号输出端OUTPUT连接。具体地，第一时钟信号输入端CLKB控制第十二开关管T12的导通与截止，从而控制栅极驱动信号输出端OUTPUT与第一电平输入端VSS是否电连接。
进一步地，上述实施例提供的电容电路4包括第一电容C1，所述第一电容C1的第一端与所述上拉节点连接，所述第一电容C1的第二端与栅极驱动信号输出端连接。
需要说明的是，在本公开实施例中以各个开关管为N型晶体管，且第一极为源极，第二极为漏极为例进行说明。上述各个开关管也可以为P型晶体管，且各个开关管为P型晶体管的电路设计也在本申请的保护范围之内。另外，正常工作情况下，由第一电平输入端VSS输入的第一电平信号可选为低电平信号，即可将第一电平输入端VSS与电源负极连接，但不仅限于此。
本公开实施例还提供了一种栅极驱动电路，包括上述实施例提供的移位寄存器单元。
具体地，上述栅极驱动电路包括若干个移位寄存器单元，其中第N-1个 移位寄存器单元对应的第N-1栅极驱动信号输出端，与第N个移位寄存器单元对应的第N输入信号端连接，第N个移位寄存器单元对应的第N复位端，与第N+1个移位寄存器单元对应的第N+1栅极驱动信号输出端连接，其中N为大于或等于2的整数。
由于上述实施例提供的移位寄存器单元中，包括降噪调节电路5，该降噪调节电路5能够在降噪时段中，使下拉节点PD的电位由低电位缓慢上升至高电位，从而实现在保证移位寄存器单元的降噪能力的同时，提升了移位寄存器单元的抗漏电能力；而且在非降噪时段中，使下拉节点PD的电位由高电位缓慢下降至低电位，从而实现在保证移位寄存器单元的抗漏电能力的同时，保持一定的降噪能力。因此，本公开实施例提供的栅极驱动电路在包括上述移位寄存器单元时，同样能够实现在保持时段P4既保证降噪能力，又减少漏电情况的发生，从而很好地保证了栅极驱动电路的工作稳定性。
值得注意，上述栅极驱动电路可通过如下方法制作：
基于上述实施例提供的移位寄存器单元的结构，建立满足实际需求的GOA模型；
使用仿真软件模拟建立的GOA模型，得到GOA模型中不同薄膜晶体管、降噪电容C2和降噪电阻R的参数；
根据上述模拟得到的参数，绘制GOA版图，并将GOA版图放置于面板版图中；
根据面板版图，通过成膜、曝光、刻蚀等工艺制备出完整的面板。
本公开实施例还提供了一种移位寄存器单元的驱动方法，应用于上述实施例提供的移位寄存器单元，所述驱动方法包括：在保持时段P4中的降噪时段，降噪调节电路5控制降低下拉节点PD的电位的上升速率；在保持时段P4中的非降噪时段，所述降噪调节电路5控制降低所述下拉节点PD的电位的下降速率。
具体地，上述移位寄存器单元的一个工作周期依次包括：输入时段P1、输出时段P2、复位时段P3和保持时段P4，在一个工作周期内驱动移位寄存器单元工作的驱动方法包括：
在输入时段P1，在输入信号端INPUT的控制下，上拉节点控制电路1控制输入信号端INPUT与上拉节点PU电连接，将上拉节点PU的电位拉高；在上拉节点PU的控制下，下拉节点控制电路2控制下拉节点PD和第一电平输入端VSS电连接。
在输出时段P2，在第二时钟信号输入端CLK和上拉节点PU的控制下，输出电路3控制第二时钟信号输入端CLK与栅极驱动信号输出端OUTPUT电连接，使栅极驱动信号输出端OUTPUT输出栅极驱动信号，并将上拉节点PU的电位进一步拉高；在上拉节点PU的控制下，下拉节点控制电路2继续控制下拉节点PD和第一电平输入端VSS电连接。
在复位时段P3，在复位端RESET的控制下，上拉节点控制电路1控制上拉节点PU与第一电平输入端VSS电连接，将上拉节点PU的电位拉低；在第一时钟信号输入端CLKB和低电位的上拉节点PU的控制下，下拉节点控制电路2控制第一时钟信号输入端CLKB与下拉节点PD电连接，将下拉节点PD的电位拉高；在高电位的下拉节点PD的控制下，上拉节点控制电路1控制上拉节点PU与第一电平输入端VSS电连接；在高电位的下拉节点PD的控制下，输出电路3控制栅极驱动信号输出端OUTPUT与第一电平输入端VSS电连接，使栅极驱动信号输出端OUTPUT不输出栅极驱动信号；在复位端RESET的控制下，输出电路3控制栅极驱动信号输出端OUTPUT与第一电平输入端VSS电连接。
在保持时段P4，在第一时钟信号输入端CLKB和低电位的上拉节点PU的控制下，下拉节点控制电路2控制下拉节点PD的电位与(第一时钟信号输入端CLKB输入的)第一时钟信号同步变化；进一步地，该保持时段P4包括降噪时段M1和非降噪时段M2，在降噪时段M1中，下拉节点PD的电位跟随第一时钟信号变化为高电位，高电位的下拉节点PD能够通过控制输出电路3使栅极驱动信号输出端OUTPUT与第一电平输入端VSS电连接，并能够通过控制上拉节点控制电路1使上拉节点PU与第一电平输入端VSS电连接，从而实现对移位寄存器单元的降噪作用。在非降噪时段M2，下拉节点PD的电位跟随第一时钟信号变化为低电位，使得与下拉节点PD连接的各 模块中的薄膜晶体管均不会产生较高的漏电，从而降低了各薄膜晶体管特性正向偏移的风险。另外，在该保持时段P4中，上拉节点PU处于低电位，在低电位的上拉节点PU的控制下，输出电路3控制栅极驱动信号输出端OUTPUT与第二时钟信号输入端CLK不电连接，进一步使得栅极驱动信号输出端OUTPUT不输出栅极驱动信号。
此外，在该保持时段P4中，降噪调节电路5对下拉节点PD的电位的变化速率进行调控，具体地，在保持时段P4中的降噪时段，控制降低下拉节点PD的电位的上升速率；在保持时段P4中的非降噪时段，控制降低下拉节点PD的电位的下降速率。
在利用本公开实施例提供的驱动方法驱动上述移位寄存器单元时，能够在保持时段P4中的降噪时段，控制降低下拉节点PD的电位的上升速率，在保持时段P4中的非降噪时段，控制降低下拉节点PD的电位的下降速率；因此，在利用本公开实施例提供的驱动方法驱动上述移位寄存器单元时，能够在降噪时段中，使下拉节点PD的电位由低电位缓慢上升至高电位，从而实现在保证移位寄存器单元的降噪能力的同时，提升了移位寄存器单元的抗漏电能力；而且在非降噪时段中，使下拉节点PD的电位由高电位缓慢下降至低电位，从而实现在保证移位寄存器单元的抗漏电能力的同时，保持一定的降噪能力。
可见，在利用本公开实施例提供的驱动方法驱动上述移位寄存器单元时，能够在保持时段P4既保证移位寄存器单元的降噪能力，又减少漏电情况的发生，不仅使得在长期使用的过程中，移位寄存器单元中的薄膜晶体管的特性稳定，不容易发生阈值电压偏移，还使得移位寄存器单元在整个保持时段P4均能够保持良好的降噪性能，从而很好的保证了移位寄存器单元的工作稳定性。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易 想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种移位寄存器单元，包括：
    上拉节点控制电路，分别与输入信号端、上拉节点、复位端、第一电平输入端和下拉节点连接；
    下拉节点控制电路，分别与第一时钟信号输入端、所述上拉节点、所述第一电平输入端和所述下拉节点连接；
    电容电路，分别与所述上拉节点和栅极驱动信号输出端连接；
    输出电路，分别与第二时钟信号输入端、所述上拉节点、所述下拉节点、所述栅极驱动信号输出端、所述第一电平输入端和所述复位端连接；
    降噪调节电路，分别与所述下拉节点和所述第一电平输入端连接，所述降噪调节电路用于：在所述移位寄存器单元的保持时段中的降噪时段，控制降低所述下拉节点的电位的上升速率；在所述保持时段中的非降噪时段，控制降低所述下拉节点的电位的下降速率。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述降噪调节电路包括第二电容，所述第二电容的第一端与所述下拉节点连接，所述第二电容的第二端与所述第一电平输入端连接。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述降噪调节电路还包括第一电阻，所述第二电容的第二端通过所述第一电阻与所述第一电平输入端连接。
  4. 根据权利要求1所述的移位寄存器单元，其中，所述移位寄存器单元还包括：
    第一增强降噪电路，分别与所述输入信号端、所述第一时钟信号输入端和所述上拉节点连接，所述第一增强降噪电路用于：在所述第一时钟信号输入端的控制下，控制导通或断开所述输入信号端和所述上拉节点之间的电连接；
    和/或，
    第二增强降噪电路，分别与所述栅极驱动信号输出端、所述第一电平输 入端和所述第一时钟信号输入端连接，所述第二增强降噪电路用于：在所述第一时钟信号输入端的控制下，控制导通或断开所述栅极驱动信号输出端和所述第一电平输入端之间的电连接。
  5. 根据权利要求1所述的移位寄存器单元，其中，
    所述上拉节点控制电路用于：在所述输入信号端的控制下，控制导通或断开所述上拉节点和所述输入信号端之间的电连接，在所述复位端的控制下，控制导通或断开所述上拉节点和所述第一电平输入端之间的电连接，在所述下拉节点的控制下，控制导通或断开所述上拉节点和所述第一电平输入端之间的电连接；
    所述输出电路用于：在所述上拉节点的控制下，控制导通或断开所述第二时钟信号输入端与所述栅极驱动信号输出端之间的电连接；在所述下拉节点的控制下，控制导通或断开所述栅极驱动信号输出端和所述第一电平输入端之间的电连接；在所述复位端的控制下，控制导通或断开所述栅极驱动信号输出端和所述第一电平输入端之间的电连接。
  6. 根据权利要求1～5任一项所述的移位寄存器单元，其中，所述上拉节点控制电路包括：第一开关管、第二开关管和第三开关管；其中，
    所述第一开关管的栅极和所述第一开关管的第二极均与所述输入信号端连接，所述第一开关管的第一极与所述上拉节点连接；
    所述第二开关管的栅极与所述复位端连接，所述第二开关管的第一极与所述第一电平输入端连接，所述第二开关管的第二极与所述上拉节点连接；
    所述第三开关管的栅极与所述下拉节点连接，所述第三开关管的第一极与所述第一电平输入端连接，所述第三开关管的第二极与所述上拉节点连接。
  7. 根据权利要求1～5任一项所述的移位寄存器单元，其中，所述输出电路包括：第四开关管、第五开关管和第六开关管；其中，
    所述第四开关管的栅极与所述上拉节点连接，所述第四开关管的第一极与所述栅极驱动信号输出端连接，所述第四开关管的第二极与所述第二时钟信号输入端连接；
    所述第五开关管的栅极与所述下拉节点连接，所述第五开关管的第一极 与所述第一电平输入端连接，所述第五开关管的第二极与所述栅极驱动信号输出端连接；
    所述第六开关管的栅极与所述复位端连接，所述第六开关管的第一极与所述第一电平输入端连接，所述第六开关管的第二极与所述栅极驱动信号输出端连接。
  8. 根据权利要求1～5任一项所述的移位寄存器单元，其中，所述下拉节点控制电路包括：第七开关管、第八开关管、第九开关管和第十开关管；其中，
    所述第七开关管的栅极和所述第七开关管的第二极均与所述第一时钟信号输入端连接，所述第七开关管的第一极与下拉控制节点连接；
    所述第八开关管的栅极与所述上拉节点连接，所述第八开关管的第一极与所述第一电平输入端连接，所述第八开关管的第二极与所述下拉控制节点连接；
    所述第九开关管的栅极与所述下拉控制节点连接，所述第九开关管的第一极与所述下拉节点连接，所述第九开关管的第二极与所述第一时钟信号输入端连接；
    所述第十开关管的栅极与所述上拉节点连接，所述第十开关管的第一极与所述第一电平输入端连接，所述第十开关管的第二极与所述下拉节点连接。
  9. 根据权利要求4所述的移位寄存器单元，其中，
    第一增强降噪电路包括第十一开关管，所述第十一开关管的栅极与所述第一时钟信号输入端连接，所述第十一开关管的第一极与所述上拉节点连接，所述第十一开关管的第二极与所述输入信号端连接；
    第二增强降噪电路包括第十二开关管，所述第十二开关管的栅极与所述第一时钟信号输入端连接，所述第十二开关管的第一极与所述第一电平输入端连接，所述第十二开关管的第二极与所述栅极驱动信号输出端连接。
  10. 根据权利要求1所述的移位寄存器单元，其中，所述电容电路包括第一电容，所述第一电容的第一端与所述上拉节点连接，所述第一电容的第二端与所述栅极驱动信号输出端连接。
  11. 根据权利要求1所述的移位寄存器单元，其中，
    在所述降噪时段，从所述第一时钟信号输入端所输入的第一时钟信号为低电平，从所述第二时钟信号输入端所输入的第二时钟信号为高电平，并且从所述复位端输入的复位信号为低电平；以及
    在所述非降噪时段，从所述第一时钟信号输入端所输入的第一时钟信号为高电平，从所述第二时钟信号输入端所输入的第二时钟信号为低电平，并且从所述复位端输入的复位信号为低电平。
  12. 一种栅极驱动电路，包括多个如权利要求1～11中任一项所述的移位寄存器单元。
  13. 一种移位寄存器单元的驱动方法，应用于如权利要求1～11中任一项所述的移位寄存器单元，所述驱动方法包括：
    在所述保持时段中的降噪时段，降噪调节电路控制降低下拉节点的电位的上升速率；在保持时段中的非降噪时段，所述降噪调节电路控制降低所述下拉节点的电位的下降速率。
  14. 根据权利要求13所述的驱动方法，其中，
    在所述降噪时段，向所述第一时钟信号输入端施加低电平的第一时钟信号，向所述第二时钟信号输入端施加高电平的第二时钟信号，并且向所述复位端施加低电平的复位信号；以及
    在所述非降噪时段，向所述第一时钟信号输入端施加高电平的第一时钟信号，向所述第二时钟信号输入端施加低电平的第二时钟信号，并且向所述复位端施加低电平的复位信号。
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