WO2019179137A1 - 阵列基板及其制造方法、显示面板、电子装置 - Google Patents

阵列基板及其制造方法、显示面板、电子装置 Download PDF

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Publication number
WO2019179137A1
WO2019179137A1 PCT/CN2018/115655 CN2018115655W WO2019179137A1 WO 2019179137 A1 WO2019179137 A1 WO 2019179137A1 CN 2018115655 W CN2018115655 W CN 2018115655W WO 2019179137 A1 WO2019179137 A1 WO 2019179137A1
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Prior art keywords
electrode
insulating layer
substrate
forming
array substrate
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PCT/CN2018/115655
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English (en)
French (fr)
Inventor
金永珉
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京东方科技集团股份有限公司
绵阳京东方光电科技有限公司
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Priority to US16/339,157 priority Critical patent/US11367741B2/en
Publication of WO2019179137A1 publication Critical patent/WO2019179137A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Definitions

  • Embodiments of the present disclosure relate to an array substrate, a method of fabricating the same, a display panel, and an electronic device.
  • a display panel typically includes a plurality of sub-pixels arranged in an array, each sub-pixel including, for example, a thin film transistor and a capacitor.
  • each sub-pixel including, for example, a thin film transistor and a capacitor.
  • the resolution of display panels is constantly increasing.
  • the area occupied by each sub-pixel is relatively smaller, which puts higher requirements on the design of the capacitor structure, for example, in the display panel.
  • At least one embodiment of the present disclosure provides an array substrate, including:
  • a second electrode at least partially opposite to the first electrode in a direction of the first electrode facing away from the substrate substrate, and in a direction perpendicular to the substrate substrate;
  • the first electrode and the second electrode are electrically insulated from each other, and the first electrode and the second electrode form a capacitor structure in a region opposite to each other, and the capacitor structure includes a portion forming at least a portion of the first groove .
  • the capacitive structure includes a portion that forms a plurality of first grooves.
  • the array substrate further includes an insulating layer between the substrate substrate and the first electrode and including a second recess formed therein, the capacitor The structure is located at least on a sidewall of the second recess.
  • a portion of the capacitor structure forming at least a portion of the first recess at least partially overlaps a second recess in the insulating layer in a direction perpendicular to the base substrate .
  • the insulating layer is a laminated structure and includes at least two sub-insulating layers sequentially stacked from the base substrate, the second recess penetrating away from the insulating layer At least one sub-insulating layer on one side of the substrate substrate.
  • At least a portion of the sub-insulating layer of the insulating layer closest to a side of the substrate substrate is not penetrated by the second recess.
  • the insulating layer includes a plurality of second grooves
  • the capacitive structure includes a portion forming a plurality of first grooves, the plurality of first grooves and the plurality of One second groove corresponds to each other, and each of the plurality of first grooves is located in one of the plurality of second grooves.
  • the capacitor structure further includes a dielectric layer between the first electrode and the second electrode such that the first electrode and the second electrode are electrically connected to each other insulation.
  • the array substrate further includes a thin film transistor including an active layer, a gate, a source and a drain; the first electrode and the active layer, the gate Any one of the source and drain electrodes is disposed in the same layer; the second electrode is disposed in the same layer as one of the active layer, the gate, and the other of the source and drain electrodes.
  • the array substrate further includes a thin film transistor and a light emitting element, wherein the thin film transistor includes a drain, the light emitting element includes a pixel electrode, and the pixel electrode is electrically connected to the drain .
  • At least one embodiment of the present disclosure also provides a display panel including any of the above array substrates.
  • At least one embodiment of the present disclosure also provides an electronic device including any of the above array substrates.
  • At least one embodiment of the present disclosure further provides a method of fabricating an array substrate, including:
  • the first electrode and the second electrode are electrically insulated from each other, and the first electrode and the second electrode form a capacitor structure in a region opposite to each other, and the capacitor structure includes a portion forming at least a portion of the first groove .
  • the capacitive structure includes a portion that forms a plurality of first grooves.
  • the method further includes:
  • a portion of the capacitive structure forming the at least a portion of the first recess at least partially overlaps the second recess in a direction perpendicular to the substrate.
  • the capacitor structure is formed at least on a sidewall of the second recess.
  • the method further includes:
  • a source and a drain of the thin film transistor are simultaneously formed in a second patterning process of forming the second electrode.
  • At least one embodiment of the present disclosure also provides an array substrate, including:
  • An insulating layer on the substrate comprising a groove, the groove penetrating at least a portion of the insulating layer from a side of the insulating layer facing away from the substrate;
  • a capacitor structure at least on a sidewall of the recess, the capacitor structure including a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode.
  • the capacitive structure is also located on a bottom wall of the recess.
  • At least one embodiment of the present disclosure further provides a method of fabricating an array substrate, including:
  • 1 is a schematic cross-sectional structural view of an array substrate
  • FIG. 2 is a schematic cross-sectional structural view of an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a cross-sectional structural view of an array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic cross-sectional structural view of an array substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a cross-sectional structural diagram of an array substrate according to an embodiment of the present disclosure.
  • 6A-6G are schematic cross-sectional views of an array substrate according to an embodiment of the present disclosure.
  • the resolution of the display panel is constantly increasing.
  • the higher the resolution of the display panel the smaller the area occupied by each sub-pixel of the display panel. Accordingly, the area occupied by the capacitor structure in each sub-pixel is also smaller and smaller, and the capacitance capacity is also reduced. Therefore, it is one of the research topics in the display field to ensure the capacitance of the capacitor structure while improving the resolution of the display panel.
  • FIG. 1 is a schematic cross-sectional view of an array substrate 10.
  • the array substrate 10 includes a thin film transistor 19 and a capacitor structure 14.
  • the thin film transistor 19 includes an active layer 15, a gate 16, a source 17, a drain 18, and the like.
  • the capacitor structure 14 includes a first electrode 11, a second electrode 12, and a dielectric layer 13 between the first electrode 11 and the second electrode 12.
  • the first electrode 11 and the second electrode 12 of the capacitor structure 14 are both planar plate-like structures.
  • the area occupied by each sub-pixel of the array substrate 10 is relatively small, the area occupied by the capacitor structure 14 in each sub-pixel is correspondingly small, so that the areas of the first electrode 11 and the second electrode 12 opposite each other are correspondingly corresponding. It is small, so that it is possible to make the capacitance of the capacitor structure 14 too small to meet the product design requirements.
  • the vertical distance between the two electrodes is typically the thickness of the dielectric layer, or d is the size of the dielectric layer in a direction perpendicular to the first electrode and/or the second electrode. It can be seen from this formula that the capacitance is proportional to the opposing area between the two electrodes in the capacitor structure.
  • a dielectric layer material having a high dielectric constant K can be used.
  • a dielectric layer material having a high dielectric constant K includes ZrO 2 , HfO 2 , and the like.
  • dielectric layer materials having a high dielectric constant K generally require thin film deposition under high temperature conditions or using an Atomic Layer Deposition (ALD) method.
  • the current manufacturing process of the low-temperature polysilicon display panel or the manufacturing process of the organic light-emitting diode display panel cannot meet the high temperature conditions required for depositing a dielectric film having a high dielectric constant K, and the deposition rate of the atomic layer deposition method is low. Meet actual production efficiency requirements.
  • the capacitance C of the capacitor structure can be increased by lowering the thickness d of the dielectric layer.
  • the dielectric layer in the capacitor structure can also be used as a gate insulating layer of a thin film transistor in a display panel at the same time. Reducing the thickness d of the dielectric layer may cause leakage of a thin film transistor to generate a tunnel. The effect causes a driving problem, or may cause a flicker problem to cause a picture defect, thereby affecting the display effect of the display panel.
  • At least one embodiment of the present disclosure provides an array substrate including a substrate substrate, a first electrode, and a second electrode.
  • the first electrode is disposed on the base substrate; the second electrode is disposed on the first electrode and is at least partially opposed to the first electrode in a direction perpendicular to the substrate.
  • the first electrode and the second electrode are electrically insulated from each other, and the first electrode and/or the second electrode include portions forming at least a portion of the first groove in opposite regions.
  • At least one embodiment of the present disclosure provides an array substrate including a substrate substrate, an insulating layer, and a capacitor structure.
  • An insulating layer is on the substrate substrate and includes a recess. The recess penetrates at least a portion of the insulating layer from a side of the insulating layer that faces away from the base substrate.
  • a capacitor structure is at least located on a sidewall of the recess, the capacitor structure including a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode.
  • the first recess is formed by a portion of the first electrode, the second electrode, and/or the capacitor structure, and the bent portion is formed by the first electrode, the second electrode, and/or the capacitor structure.
  • at least one of the first electrode, the second electrode, and the capacitor structure has substantially the same size at each position, that is, the thickness is uniform.
  • the first electrode and the second electrode are increased in relative The relative area within the region, thereby increasing the capacitance of the capacitive structure formed by the first electrode and the second electrode.
  • FIG. 2 is a schematic cross-sectional view of an array substrate 100 according to an embodiment of the present disclosure.
  • FIG. 2 highlights a portion of the capacitor structure in the array substrate provided by the embodiment of the present disclosure.
  • the capacitor structure shown in FIG. 2 can be used to replace the capacitor structure shown in FIG. 1 to increase the capacitance.
  • the array substrate 100 can be an array substrate of various suitable types of display panels. This embodiment does not limit the specific type of the display panel to which the array substrate belongs.
  • the array substrate 100 includes a structure of a base substrate 101, a first electrode 102, and a second electrode 103.
  • the base substrate 101 may be, for example, a glass substrate, a quartz substrate, a plastic substrate, or other suitable material. This embodiment is not specifically limited.
  • the base substrate 101 may be a flexible substrate or a rigid substrate.
  • the first electrode 102 is disposed on the base substrate 101.
  • the second electrode 103 is disposed on the first electrode 102 and at least partially opposed to the first electrode 102 in a direction perpendicular to the base substrate 101.
  • the first electrode 102 and the second electrode 103 are electrically insulated from each other, and the first electrode 102 and the second electrode 103 include portions forming the first groove 104 in regions opposing each other.
  • the number of the first grooves 104 formed by the first electrode 102 and/or the second electrode 103 may be one, or may be plural.
  • the number of the first grooves 104 is not specifically limited in this embodiment.
  • first groove 104 formed by the first electrode 102 and/or the second electrode 103 may be, for example, a complete groove shape, or may constitute at least a part of the groove, for example, the first electrode 102 and/or the second.
  • the electrodes 103 form sidewalls of the grooves in regions opposite to each other.
  • the shape of the first groove 104 formed by the first electrode 102 and/or the second electrode 103 in this embodiment is not specifically limited.
  • the first electrode 102 and the second electrode 103 each include a first recess 104 as an example.
  • the first recess 102 is formed by a portion of the first electrode 102 to form the first recess 104.
  • the bent portion is formed by a portion of the second electrode 103 to form the first groove 104.
  • the first electrode 102 includes a portion 1042 forming a first recess 104 in a region opposite to the second electrode 103.
  • the second electrode 103 includes a portion 1043 that forms the first groove 104 in a region opposing the first electrode 102 from each other.
  • the first electrode 102 and the second electrode 103 form a capacitive structure 014 in regions opposite each other, and the capacitive structure 014 includes a portion 1040 that forms at least a portion of the first recess 104.
  • the material of the first electrode 102 and the second electrode 103 include a metal material including, for example, silver, aluminum, chromium, copper, molybdenum, titanium, an aluminum-niobium alloy, a copper-molybdenum alloy, a molybdenum-niobium alloy, a molybdenum crucible. The alloy or any combination thereof is not specifically limited in this embodiment.
  • the array substrate 100 further includes an insulating layer 105 disposed on the substrate substrate 101 between the substrate substrate 101 and the first electrode 102.
  • the insulating layer 105 includes, for example, a second groove 106 formed therein.
  • the first recess 104 of the first electrode 102 at least partially overlaps the second recess 106 in the insulating layer 105 in a direction perpendicular to the base substrate 101.
  • the first electrode 102 and the second electrode 103 are formed conformally on the bottom wall and the sidewall of the second groove 106.
  • the first electrode 102 when the first electrode 102 includes a portion forming the first recess 104, a portion of the first electrode 102 forming the first recess 104 is in a direction perpendicular to the base substrate 101 and in the insulating layer 105
  • the second grooves 106 at least partially overlap.
  • the portion of the first electrode 102 / the second electrode 103 that forms the first recess 104 overlaps at least the sidewall of the second recess 106 in the insulating layer 105 in a direction perpendicular to the base substrate 101.
  • the insulating layer 105 is a laminated structure and includes a first sub-insulating layer 1051, a second sub-insulating layer 1052, and a third sub-insulating layer 1053 which are sequentially stacked from the base substrate 101.
  • the second recess 106 of the insulating layer 105 penetrates at least one sub-insulating layer of the insulating layer 105 away from the side of the base substrate 101.
  • a recess may be formed in the third sub-insulating layer 1053 of the insulating layer 105 to constitute the second recess 106; or, a recess may be formed in the third sub-insulating layer 1053 and the second sub-insulating layer 1052 of the insulating layer 105.
  • the groove is configured to constitute the second groove 106; or alternatively, a groove may be formed in the third sub-insulating layer 1053, the second sub-insulating layer 1052, and the first sub-insulating layer 1051 of the insulating layer 105 to constitute the second groove 106.
  • the number of layers of the sub-insulating layer in the insulating layer 105 through which the second recess 106 penetrates is not specifically limited in this embodiment. It should be noted that the number of layers of the sub-insulating layer included in the insulating layer 105 includes, but is not limited to, three layers. For example, the number of layers of the sub-insulating layer included in the insulating layer 105 may be one layer, two layers, four layers or more, which is not specifically limited in this embodiment.
  • the second recess 106 may also extend through a portion of the sub-insulating layer.
  • a portion of the sub-insulating layer of the insulating layer 105 closest to the side of the substrate 101 is not penetrated by the second recess 106.
  • the thickness of the sub-insulating layer of the insulating layer 105 closest to the side of the substrate 101 is not etched by about one sixth to one third of the thickness of the sub-insulating layer.
  • the thickness of the sub-insulating layer on the side of the insulating layer 105 closest to the substrate 101 is about The thickness of the sub-insulating layer of the insulating layer 105 closest to the side of the substrate 101 is not etched.
  • the cross-sectional area of the portion of the first electrode 102 where the first groove 104 is formed, the cross-sectional shape, and the like are related to the depth of the second groove 106, etc., in a direction perpendicular to the base substrate 101. .
  • the area in the unit area in the direction of the base substrate 101 is correspondingly larger, and the relative area in the unit area of the first electrode 102 and the second electrode 103 is correspondingly increased.
  • the first electrode is The capacitance of the capacitor structure formed by 102 and the second electrode 103 is improved. Therefore, in the actual manufacturing process, the depth of the second recess 106 can be controlled, for example, by adjusting the thicknesses of the first sub-insulating layer 1051, the second sub-insulating layer 1052, and the third sub-insulating layer 1053 in the insulating layer 105, thereby The magnitude of the capacitance of each sub-pixel of the array substrate 100 is adjusted accordingly.
  • the array substrate 100 further includes a dielectric layer 107 disposed between the first electrode 102 and the second electrode 103 to electrically insulate the first electrode 102 and the second electrode 103.
  • the capacitor structure 014 includes a first electrode 102, a second electrode 103, and a dielectric layer 107 between the first electrode 102 and the second electrode 103.
  • the dielectric layer 107 includes a portion 108 forming a first recess, and a portion of the first recess 104 formed by the second electrode 103 forms a portion of the first recess 108 with the dielectric layer 107 in a direction perpendicular to the base substrate 101. At least partially overlap.
  • the second electrode 103 when the second electrode 103 includes a portion forming the first recess 104, a portion of the second electrode 103 forming the first recess 104 is in a direction perpendicular to the base substrate 101 and the dielectric layer 107 The portions 108 forming the first grooves at least partially overlap.
  • the material used for the dielectric layer 107 includes any suitable material such as silicon oxide, silicon nitride, silicon oxynitride, and the like, and is, for example, a material having a high dielectric constant, which is not specifically limited in this embodiment.
  • the array substrate 100 further includes a buffer layer 109, a barrier layer 110, a second insulating layer 111, an interlayer dielectric layer 112, and a flat layer 113.
  • a buffer layer 109 is provided on the base substrate 101.
  • the buffer layer 109 can prevent, for example, impurity ions and moisture or external air or the like from penetrating into the array substrate 100 through the base substrate 101, and the buffer layer 109 can planarize the surface of the base substrate 101.
  • the buffer layer 109 can also prevent, for example, diffusion of impurity ions in the base substrate 101 into a driving circuit layer including a thin film transistor which is formed later, and can prevent characteristics such as threshold voltage and leakage current of the thin film transistor element from being affected.
  • the material used for the buffer layer 109 includes any suitable material such as SiNx, SiOx, and the like, which is not specifically limited in this embodiment. For example, the thickness of the buffer layer 109 is approximately But it is not limited to this.
  • the barrier layer 110 is disposed on the buffer layer 109.
  • the barrier layer 110 of the array substrate 100 can be used, for example, to prevent the active layer formed in the array substrate from being exposed to external light to generate photo-generated carriers, thereby causing undesirable leakage current.
  • the material for the barrier layer 110 include a metal material (e.g., silver, chrome, etc.), SiNx, SiOx, or any other suitable material, which is not specifically limited in this embodiment.
  • the second insulating layer 111 is disposed between the barrier layer 110 and the insulating layer 105.
  • An example of the material of the second insulating layer 111 includes any suitable material such as polyimide, which is not specifically limited in this embodiment.
  • the distance from the bottom of the second recess 106 in the insulating layer 105 to the base substrate 101 is greater than or equal to the distance from the upper surface of the second insulating layer 111 to the base substrate 101. That is, the second recess 106 in the insulating layer 105 does not penetrate the second insulating layer 111, so that a short circuit phenomenon between the first electrode 102 and the barrier layer 110 can be avoided.
  • the interlayer dielectric layer 112 is disposed on the second electrode 103 and covers the second electrode 103 to form a protection for the second electrode 103.
  • the flat layer 113 is disposed on the interlayer dielectric layer 112.
  • the material for the interlayer dielectric layer 112 and the planarization layer 113 include SiNx, SiOx, or any other suitable material, which is not specifically limited in this embodiment.
  • the entire structure of the array substrate 100 is not shown for clarity. In order to realize the necessary functions of the array substrate, those skilled in the art can set other structures (not shown) according to specific application scenarios, which are not limited in the embodiments of the present disclosure.
  • the first electrode 102 and the second electrode 103 in a direction perpendicular to the base substrate 101, include portions forming the first groove 104 in opposite regions.
  • the first electrode 102 and the second electrode 103 are designed such that the first electrode 102 and the second electrode 103 include a portion constituting the first groove 104, compared to the array substrate composed of the flat surface electrode, which is increased.
  • the opposing areas of the first electrode 102 and the second electrode 103 in the regions opposite to each other increase the capacitance of the capacitance of the array substrate 100 composed of the first electrode 102 and the second electrode 103.
  • FIG. 3 is a schematic cross-sectional view of an array substrate 200 according to another embodiment of the present disclosure.
  • the number of the first grooves 104 formed by the first electrode 102, the second electrode 103, and/or the capacitor structure is two.
  • the structure of the array substrate 200 of this example may be substantially the same as the structure of the array substrate 100 described in FIG. 2 except that the number of the first grooves 104 in the first electrode 102 and the second electrode 103 in the array substrate 200 is different. It should be noted that the number of the first grooves 104 in the first electrode 102 and the second electrode 103 in the array substrate 200 may be more, not limited to two.
  • the first electrode 102, the second electrode 103, and the capacitor structure 014 of the array substrate 200 include two first recesses 104 in regions opposite to each other.
  • the two first grooves 104 are disposed in close proximity.
  • the insulating layer 105 is disposed on the base substrate 101 and located between the base substrate 101 and the first electrode 102.
  • the insulating layer 105 includes two second grooves 106 formed therein, and the first electrode 102 constitutes two first
  • the groove 104 at least partially overlaps the two second grooves 106 in the insulating layer 105 in a direction perpendicular to the base substrate 101, respectively.
  • the capacitive structure 014 is conformally formed on the second recess 106.
  • a dielectric layer 107 is disposed between the first electrode 102 and the second electrode 103 to electrically insulate the first electrode 102 and the second electrode 103 from each other.
  • the dielectric layer 107 includes a portion 108 that forms two first recesses, and a portion 1043 of the two first recesses 104 formed by the second electrode 103 forms two layers with the dielectric layer 107 in a direction perpendicular to the base substrate 101.
  • the portions 108 of the first recesses at least partially overlap, respectively.
  • the relative areas of each other in the unit area of the first electrode 102 and the second electrode 103 are further increased, thereby further improving The capacitance of the array substrate 200 composed of the first electrode 102 and the second electrode 103.
  • FIG. 4 is a schematic cross-sectional view of an array substrate 300 according to another embodiment of the present disclosure.
  • the structure of the array substrate 300 of the example is the same as that described in FIG. 2 except for the shape of the second electrode 103 in the array substrate 300.
  • the structure of the array substrate 100 may be substantially the same.
  • the capacitor structure shown in FIG. 4 is located on the sidewall of the second recess 106, and no capacitive structure is provided on the bottom wall of the second recess 106.
  • the first electrode 102 of the array substrate 300 includes a portion forming a first recess 104
  • the second electrode 103 of the array substrate 300 includes a portion forming a portion of the first recess 104, and is formed in the second electrode 103.
  • a portion of the first recess 104 at least partially overlaps a portion of the first electrode 102 that forms the first recess 104 in a direction perpendicular to the base substrate 101.
  • the insulating layer 105 is disposed on the base substrate 101 between the base substrate 101 and the first electrode 102, and the insulating layer 105 includes a second groove 106 formed therein, the first electrode 102 forming a portion of the first groove 104
  • the second groove 106 in the insulating layer 105 at least partially overlaps in a direction perpendicular to the base substrate 101.
  • a dielectric layer 107 is disposed between the first electrode 102 and the second electrode 103 to electrically insulate the first electrode 102 and the second electrode 103.
  • the dielectric layer 107 includes a portion 108 forming a first recess 104, and a portion 1043 of the second electrode 103 forming the first recess 104 forms a first recess with the dielectric layer 107 in a direction perpendicular to the base substrate 101. Portions 108 of 104 at least partially overlap.
  • the first electrode 102 includes a portion that forms the first groove 104
  • the second electrode 103 includes a portion that forms the first groove 104
  • the portion 1043 of the second electrode 103 that forms the first groove 104 is The portion 1042 of the first electrode 102 forming the first groove 104 at least partially overlaps in a direction perpendicular to the base substrate 101.
  • the first electrode 102 and the second electrode 103 respectively include portions forming the first groove 104 in regions opposing each other.
  • the shape of the portion of the first electrode 102 and/or the second electrode 103 forming the first groove 104 is not particularly limited in this embodiment, as long as the shape of the groove can increase the first electrode 102 and the second electrode 103.
  • the relative areas of each other in the direction perpendicular to the base substrate 101 may be sufficient.
  • FIG. 5 is a cross-sectional structural view of the array substrate 400 according to the embodiment.
  • the array substrate 400 can serve as an array substrate for various suitable types of display panels.
  • the array substrate 400 is an array substrate of an OLED display device as an example.
  • the array substrate 400 includes a first electrode 102, a second electrode 103, a driving circuit structure 405, a light-emitting element 409, and the like.
  • the capacitor structure 014 includes a first electrode 102, a second electrode 103, and a dielectric layer 107.
  • the driving circuit structure 405 can be, for example, a transistor.
  • the driving circuit structure 405 is a thin film transistor (ie, a driving transistor) as an example.
  • the thin film transistor 405 can be, for example, a top gate thin film transistor or a bottom gate thin film transistor. This embodiment does not limit the specific type of the thin film transistor 405.
  • the thin film transistor 405 is used as a top-gate thin film transistor. As shown in FIG. 5, the thin film transistor 405 includes an active layer 401, a gate 402, a drain 403, a source 404, and the like. For example, the dielectric layer 107 serves as a gate insulating layer of the thin film transistor 405 at the same time.
  • the active layer 401 may include an amorphous silicon material, a polysilicon material, a metal oxide semiconductor material (for example, indium gallium zinc oxide (IGZO)), or any other suitable material, which is not specifically limited in this embodiment.
  • IGZO indium gallium zinc oxide
  • the array substrate 400 is a low temperature polysilicon thin film transistor array substrate or a high temperature polysilicon thin film transistor array substrate, for example, a rapid thermal annealing (RTA) method, a solid phase crystallization (SPC) method, or an excimer laser annealing (ELA) method may be employed.
  • RTA rapid thermal annealing
  • SPC solid phase crystallization
  • ESA excimer laser annealing
  • the amorphous silicon active layer 101 is crystallized into the polysilicon active layer 101 by a metal induced crystallizing (MIC) method, a metal induced lateral crystallization (MILC) method, continuous lateral solidification (SLS), or the like.
  • MIC metal induced crystallizing
  • MILC metal induced lateral crystallization
  • SLS continuous lateral solidification
  • the first electrode 102 is disposed in the same layer as the gate 402 of the thin film transistor 405.
  • the first electrode 102 and the gate electrode 402 can be simultaneously formed by the same patterning process.
  • the second electrode 103 is disposed in the same layer as the source 404 and the drain 403 of the thin film transistor 405.
  • the second electrode 103 and the source 404 and the drain 403 may be simultaneously formed by the same patterning process.
  • the first electrode 102 may be disposed in the same layer as the active layer 401 of the thin film transistor 405, and the second electrode 103 may be in the same layer as the gate 402 or the drain 403/source 404 of the thin film transistor 405. Settings.
  • the first electrode 102 may be disposed in the same layer as the gate 402 of the thin film transistor 405, and the second electrode 103 may be coupled to the active layer 401 or the drain 403 of the thin film transistor 405.
  • Source 404 is set in the same layer.
  • the third sub-insulating layer 1053 may also serve as a gate insulating layer of the thin film transistor 405 in the array substrate 400, and examples of the material of the third sub-insulating layer 1053 include any suitable material such as SiNx, SiOx, or the like.
  • the third sub-insulating layer 1053 is used as the gate insulating layer of the thin film transistor 405, since the active layer 401 is ion-doped with the gate insulating layer as a mask in a subsequent manufacturing process, the third sub-insulating layer is used.
  • the thickness range of 1053 can be limited to a certain range.
  • the thickness of the third sub-insulating layer 1053 may be less than 150 nanometers.
  • the first sub-insulating layer 1051 in the insulating layer 105 may be increased.
  • the thickness of the second sub-insulating layer 1052 The change in the thickness parameter of the first sub-insulating layer 1051 and the second sub-insulating layer 1052 generally does not adversely affect the characteristics of the array substrate 400 composed of the first sub-insulating layer 1051 and the second sub-insulating layer 1052.
  • the relationship between the depth of the second groove 106 in the insulating layer 105 and the thicknesses of the first sub-insulating layer 1051 and the second sub-insulating layer 1052 can be experimentally obtained.
  • the thickness of the first sub-insulating layer 1051 is approximately
  • the thickness of the second sub-insulating layer 1052 is approximately
  • the light-emitting element 409 is an organic light-emitting diode, and the light-emitting element 409 includes, for example, a pixel electrode 406, a counter electrode 408, and an organic functional layer 407 interposed between the pixel electrode 406 and the counter electrode 408.
  • the pixel electrode 406 is electrically connected to the source 404 of the thin film transistor 405.
  • the pixel electrode 406 can also be electrically connected to the drain 403 of the thin film transistor 405, so that the thin film transistor 405 in each sub-pixel unit of the array substrate 400 can be a pixel. Electrode 406 applies a signal.
  • the material of the pixel electrode 406 includes a transparent conductive material, and the transparent conductive material may be any suitable material such as indium tin oxide or indium zinc oxide.
  • the counter electrode 408 can be configured, for example, as a common electrode of the array substrate 400.
  • the pixel electrode 406 can serve as the anode of the light-emitting element 409, and the counter electrode 408 can serve as the cathode of the light-emitting element 409.
  • the pixel electrode 406 may be the cathode of the light-emitting element 409, and the counter electrode 408 may serve as the anode of the light-emitting element 409.
  • the organic functional layer 407 includes, for example, an organic light emitting layer, and may further include one or more of a hole transporting layer, a hole injecting layer, an electron transporting layer, and an electron injecting layer, as needed.
  • the entire structure of the array substrate 400 is not shown for clarity. In order to realize the necessary functions of the array substrate, those skilled in the art can set other structures (not shown) according to specific application scenarios, which are not limited in the embodiments of the present disclosure.
  • the array substrate 400 includes a first electrode 102, a second electrode 103, a thin film transistor 405, a light-emitting element 409, and the like.
  • the first electrode 102 and the second electrode 103 are bent so that the first electrode 102 and the second electrode 103 respectively include a portion forming the first groove 104, compared to the array substrate composed of the flat surface electrode.
  • the relative area of the first electrode 102 and the second electrode 103 in a unit area in a region opposite to each other is increased, and the capacitance of the array substrate 400 composed of the first electrode 102 and the second electrode 103 is improved, thereby facilitating
  • the array substrate 400 is designed in high resolution to improve display quality.
  • another embodiment of the present disclosure further provides a display panel including any of the array substrates described in the above embodiments.
  • the display panel may be, for example, a liquid crystal display panel or an organic light emitting diode display panel or the like.
  • the technical effects of the display panel refer to the technical effects of any of the array substrates described in the foregoing embodiments, and details are not described herein again.
  • another embodiment of the present disclosure further provides an electronic device including any of the array substrates described in the above embodiments.
  • the electronic device can be, for example, a display device, a television, a digital camera, a mobile phone, a watch, a tablet, a notebook computer, a navigator, or the like, any product or component including an array substrate.
  • a display device for example, a television, a digital camera, a mobile phone, a watch, a tablet, a notebook computer, a navigator, or the like, any product or component including an array substrate.
  • Another embodiment of the present disclosure provides a method of fabricating an array substrate, comprising: forming an insulating layer on a substrate; forming a recess in the insulating layer, the recess being away from the substrate from the insulating layer One side of the substrate extends through at least a portion of the insulating layer; and a capacitive structure is conformally formed on at least a sidewall of the recess, the forming the capacitive structure including forming a first electrode, forming a second electrode, and forming the a dielectric layer between the first electrode and the second electrode.
  • FIG. 6A to FIG. 6G are schematic cross-sectional structural diagrams of the array substrate 200 according to the embodiment.
  • the substrate substrate 101 is first provided.
  • the substrate substrate 101 may be, for example, a glass substrate, a quartz substrate, a plastic substrate, or other suitable material.
  • This embodiment is not specifically limited.
  • the base substrate 101 may also be a flexible substrate such as polyimide. When a flexible substrate is used, it can be placed on the backsheet glass to facilitate the fabrication of the various layers.
  • a buffer layer 109 may be deposited on the base substrate 101 by, for example, chemical vapor deposition, physical vapor deposition, or the like, and the buffer layer 109 may prevent impurity ions and moisture or outside air from penetrating through the substrate 101, for example.
  • the buffer layer 109 can also planarize the surface of the substrate 101, for example.
  • the buffer layer 109 can also prevent, for example, diffusion of impurity ions in the base substrate 101 into a circuit layer including a thin film transistor which is formed later, and which prevents influence on characteristics such as a threshold voltage and a leakage current of the thin film transistor element.
  • Examples of the material for the buffer layer 109 include SiNx, SiOx, or any other suitable material, which is not limited in this embodiment.
  • the barrier layer 110 may be deposited on the buffer layer 109 by, for example, chemical vapor deposition, physical vapor deposition, or the like.
  • the barrier layer 110 can be used to prevent the subsequently formed active layer in the array substrate from being exposed to external light to generate photo-generated carriers, thereby causing undesirable leakage current.
  • the material for the barrier layer 110 include a metal material (e.g., silver, chrome, etc.), SiNx, SiOx, or any other suitable material, which is not specifically limited in this embodiment.
  • the second insulating layer 111 may be deposited on the barrier layer 110 by, for example, chemical vapor deposition, physical vapor deposition, or the like.
  • An example of the material of the second insulating layer 111 includes any suitable material such as polyimide, which is not specifically limited in this embodiment.
  • the first sub-insulating layer 1051, the second sub-insulating layer 1052, and the third sub-insulating layer 1053 may be sequentially deposited on the second insulating layer 111 by chemical vapor deposition, physical vapor deposition, or the like to form an insulating layer.
  • Layer 105 For example, according to product design requirements, the first sub-insulating layer 1051, the second sub-insulating layer 1052, and the third sub-insulating layer 1053 of a desired thickness can be respectively obtained by controlling parameters such as deposition time and deposition rate.
  • the number of layers of the sub-insulating layer included in the insulating layer 105 includes, but is not limited to, three layers.
  • the number of layers of the sub-insulating layer included in the insulating layer 105 may be one layer, two layers, four layers or more according to product design requirements.
  • the layer is not specifically limited in this embodiment.
  • Examples of the material for the first sub-insulating layer 1051, the second sub-insulating layer 1052, and the third sub-insulating layer 1053 include SiNx, SiOx, or other suitable materials, which is not limited in this embodiment.
  • a photoresist layer (not shown) is formed on the entire surface of the third sub-insulating layer 1053, and the photoresist layer is patterned by photolithography processing including an exposure process and a development process to A photoresist pattern having a desired shape is formed on the third sub-insulating layer 1053. Then, the third sub-insulating layer 1053, the second sub-insulating layer 1052, and the first sub-insulating layer 1051 are simultaneously etched by using the photoresist pattern as an etch mask to be etched by the third sub-insulating layer 1053 and the second sub-layer. Two second grooves 106 are formed in the insulating layer 105 composed of the insulating layer 1052 and the first sub-insulating layer 1051.
  • the two second grooves 106 are formed side by side with each other.
  • the etching method includes, for example, dry etching, for example, by controlling parameters such as etching time, etching rate, etc., the depth of the second groove 106 can be controlled such that the formed second groove 106 penetrates at least the insulating layer 105 away from the substrate. At least one sub-insulating layer on one side of the substrate 101 does not penetrate the second insulating layer 111.
  • the second groove 106 includes a bottom wall BS and a side wall SS.
  • a metal layer may be deposited on the third sub-insulating layer 1053 by, for example, chemical vapor deposition, physical vapor deposition, or the like, and then patterned by a photolithography process to form a third sub-insulating layer 1053.
  • a first electrode 102 including two first grooves 104 is formed thereon.
  • the portion 1042 of the first electrode 102 including the two second grooves 104 is conformally formed along the two second grooves 106 of the insulating layer 105, respectively.
  • Examples of the material for the first electrode 102 include silver, aluminum, chromium, copper, molybdenum, titanium, an aluminum-niobium alloy, a copper-molybdenum alloy, a molybdenum-niobium alloy, a molybdenum-niobium alloy, or any combination thereof.
  • the first electrode has the same shape as the second groove 106.
  • a metal layer may be deposited on the third sub-insulating layer 1053 by, for example, chemical vapor deposition, physical vapor deposition, or the like, and then patterned by a photolithography process to insulate the third sub-layer.
  • a first electrode 102 is formed on the layer 1053.
  • the first electrode 102 includes a portion in which the first recess 104 is formed, and the portion 1042 of the first electrode 102 forming the first recess 104 is conformally formed along the at least one second recess 106.
  • the first electrode 102 may be, for example, chemical vapor deposition, physical vapor deposition, or the like.
  • the method deposits a dielectric layer film.
  • the dielectric layer film is then patterned by a photolithography process to form a dielectric layer 107 on the second electrode 103.
  • the formed dielectric layer 107 includes a portion 108 forming two first recesses 104, forming two A portion 108 of a recess is formed conformally along portions of the first electrode 102 that form the two first recesses 104, respectively.
  • An example of the material for the dielectric layer 107 includes any suitable material such as silicon oxide, silicon nitride, silicon oxynitride, and the like, and is, for example, a high-k material, which is not specifically limited in this embodiment.
  • the dielectric layer 107 has the same shape as the second groove.
  • a metal layer may be deposited on the dielectric layer 107 by, for example, chemical vapor deposition, physical vapor deposition, or the like, and then patterned by a photolithography process to form a second layer on the dielectric layer 107.
  • the formed second electrode 103 is at least partially opposed to the first electrode 102 in a direction perpendicular to the base substrate 101, and the second electrode 103 and the first electrode 102 are electrically insulated from each other by the dielectric layer 107.
  • the second electrode 103 includes a portion 1043 forming two first grooves 104, and a portion of the second electrode 103 forming the two second grooves 104 along a portion of the dielectric layer 107 forming the two first grooves 104 108 formation of conformal respectively.
  • the material for the second electrode 103 include silver, aluminum, chromium, copper, molybdenum, titanium, an aluminum-niobium alloy, a copper-molybdenum alloy, a molybdenum-niobium alloy, a molybdenum-niobium alloy, or any combination thereof.
  • the capacitive structure 014 has a portion 140 that forms a first recess 104.
  • a metal layer may be deposited on the dielectric layer 107 by, for example, chemical vapor deposition, physical vapor deposition, or the like, and then patterned by a patterning process to form a second electrode on the dielectric layer 107.
  • the second electrode 103 includes a portion forming the first recess 104, and the portion 1043 of the second electrode 103 formed with the first recess 104 is conformal with the portion 108 of the dielectric layer 107 forming the at least one first recess Formation.
  • the second electrode 103 may be, for example, by chemical vapor deposition, physical vapor deposition, or the like.
  • An interlayer dielectric film 112 is deposited, and then the interlayer dielectric film is patterned by a photolithography process to form an interlayer dielectric layer 112.
  • the interlayer dielectric layer 112 covers the second electrode 103 to form a protection for the second electrode 103.
  • Examples of the material for the interlayer dielectric layer 112 include SiNx, SiOx or any other suitable material, which is not used in this embodiment. Specifically limited.
  • a flat layer film is deposited on the interlayer dielectric layer 112, and then the flat layer film is patterned by a patterning process to form a flat layer 113.
  • the material for the flat layer 113 include SiNx, SiOx, or any other suitable material, which is not specifically limited in this embodiment.
  • the first electrode 102 and the second electrode 103 are designed to make the first electrode 102 and the second electrode in a direction perpendicular to the base substrate 101.
  • the electrodes 103 respectively include portions that form the two first grooves 104.
  • the method increases the relative area of the first electrode 102 and the second electrode 103 in the regions opposite to each other, and is improved by the first electrode 102 and the second electrode 103.
  • the capacitance of the array substrate 200 is provided by at least one embodiment of the present disclosure.

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Abstract

一种阵列基板及其制造方法、显示面板、电子装置，该阵列基板包括衬底基板(101)、第一电极(102)、第二电极(103)。第一电极(102)设置在衬底基板(101)上，第二电极(103)设置在第一电极(102)上且在垂直于衬底基板(101)的方向上与第一电极(102)至少部分相对；第一电极(102)与第二电极(103)电绝缘，且第一电极(102)和第二电极(103)在相对的区域构成电容结构(014)，电容结构(014)包括形成至少部分第一凹槽(104)的部分。

Description

阵列基板及其制造方法、显示面板、电子装置
相关申请的交叉引用
本专利申请要求于2018年3月22日递交的中国专利申请第201810240944.4号，名称为“阵列基板及其制造方法、显示面板、电子装置”的优先权，在此全文引用上述中国专利申请公开的内容以作为本公开的实施例的一部分。
技术领域
本公开的实施例涉及一种阵列基板及其制造方法、显示面板、电子装置。
背景技术
液晶显示面板、有机发光二极管显示面板等由于具有轻薄化、抗震性好、视角广、对比度高等特点，已广泛应用于各种显示装置中。例如，显示面板通常包括阵列排布的多个子像素，每个子像素例如包括薄膜晶体管和电容等结构。例如，随着显示技术的发展以及消费者对显示面板的显示画质的需求，显示面板的分辨率在不断提高。相应地，每个子像素所占的面积相对越来越小，这对显示面板中例如电容结构的设计等方面提出了更高的要求。
发明内容
本公开至少一实施例提供一种阵列基板，包括：
衬底基板；
第一电极，在所述衬底基板上；
第二电极，在所述第一电极的背离所述衬底基板的一侧，且在垂直于所述衬底基板的方向上与所述第一电极至少部分相对；其中，
所述第一电极与所述第二电极彼此电绝缘，且所述第一电极和所述第二电极在彼此相对的区域构成电容结构，所述电容结构包括形成至少部分第一凹槽的部分。
在本公开一个或多个实施例中，所述电容结构包括形成多个第一凹槽的部分。
在本公开一个或多个实施例中，阵列基板还包括绝缘层，所述绝缘层位于所述衬底基板和所述第一电极之间且包括形成在其中的第二凹槽，所述电容结构至少位于所述第二凹槽的侧壁上。
在本公开一个或多个实施例中，所述电容结构的形成至少部分第一凹槽的部分在垂直于所述衬底基板的方向上与所述绝缘层中的第二凹槽至少部分重叠。
在本公开一个或多个实施例中，所述绝缘层为叠层结构且包括从所述衬底基板依次层叠的至少两个子绝缘层，所述第二凹槽贯穿所述绝缘层的远离所述衬底基板一侧的至少一个子绝缘层。
在本公开一个或多个实施例中，所述绝缘层的最靠近所述衬底基板一侧的所述子绝缘层的至少一部分未被所述第二凹槽贯穿。
在本公开一个或多个实施例中，所述绝缘层包括多个第二凹槽，所述电容结构包括形成多个第一凹槽的部分，所述多个第一凹槽和所述多个第二凹槽一一对应，所述多个第一凹槽中的每个位于所述多个第二凹槽中的一个内。
在本公开一个或多个实施例中，所述电容结构还包括位于所述第一电极和所述第二电极之间的介电层以使得所述第一电极与所述第二电极彼此电绝缘。
在本公开一个或多个实施例中，阵列基板还包括薄膜晶体管，所述薄膜晶体管包括有源层、栅极、源漏极；所述第一电极与所述有源层、所述栅极、所述源漏极中的任意一个同层设置；所述第二电极与所述有源层、所述栅极、所述源漏极中的另两个中的一个同层设置。
在本公开一个或多个实施例中，阵列基板还包括薄膜晶体管和发光元件，其中，所述薄膜晶体管包括漏极，所述发光元件包括像素电极，所述像素电极与所述漏极电连接。
本公开至少一实施例还提供一种显示面板，包括上述任一阵列基板。
本公开至少一实施例还提供一种电子装置，包括上述任一阵列基板。
本公开至少一实施例还提供一种阵列基板的制造方法，包括：
提供衬底基板；
在所述衬底基板上形成第一电极；
在所述第一电极上形成第二电极，所述第二电极在垂直于所述衬底基板 的方向上与所述第一电极至少部分相对；其中，
所述第一电极与所述第二电极彼此电绝缘，且所述第一电极和所述第二电极在彼此相对的区域构成电容结构，所述电容结构包括形成至少部分第一凹槽的部分。
在本公开一个或多个实施例中，所述电容结构包括形成多个第一凹槽的部分。
在本公开一个或多个实施例中，该方法还包括：
在形成所述第一电极之前，在所述衬底基板上形成绝缘层薄膜，对所述绝缘层薄膜进行刻蚀以形成包括第二凹槽的绝缘层；其中，
所述电容结构的形成所述至少部分第一凹槽的部分在垂直于所述衬底基板的方向上与所述第二凹槽至少部分重叠。
在本公开一个或多个实施例中，所述电容结构至少形成在所述第二凹槽的侧壁上。
在本公开一个或多个实施例中，该方法还包括：
在形成所述第一电极的第一次构图工艺中同时形成薄膜晶体管的栅极；
在形成所述第二电极的第二次构图工艺中同时形成所述薄膜晶体管的源极和漏极。
本公开至少一实施例还提供一种阵列基板，包括：
衬底基板；
绝缘层，位于所述衬底基板上，包括凹槽，所述凹槽从所述绝缘层背离所述衬底基板的一侧贯穿至少部分所述绝缘层；
电容结构，至少位于所述凹槽的侧壁上，所述电容结构包括第一电极、第二电极和位于所述第一电极和所述第二电极之间的介电层。
在本公开一个或多个实施例中，所述电容结构还位于所述凹槽的底壁上。
本公开至少一实施例还提供一种阵列基板的制造方法，包括：
在衬底基板上形成绝缘层；
在所述绝缘层中形成凹槽，所述凹槽从所述绝缘层背离所述衬底基板的一侧贯穿至少部分所述绝缘层；
至少在所述凹槽的侧壁上共形地形成电容结构，形成所述电容结构包括形成第一电极、形成第二电极和形成位于所述第一电极和所述第二电极之间 的介电层。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种阵列基板的剖面结构示意图；
图2为本公开一实施例提供的阵列基板的剖面结构示意图；
图3为本公开一实施例提供的阵列基板的剖面结构示意图；
图4为本公开一实施例提供的阵列基板的剖面结构示意图；
图5为本公开一实施例提供的阵列基板的剖面结构示意图；以及
图6A-图6G为本公开一实施例提供的阵列基板在制造过程中的剖面结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着显示技术的发展和社会发展的需求，为了提高显示面板的显示画质，显示面板的分辨率在不断地提高。显示面板的分辨率越高，显示面板的每个子像素所占的面积相对越小。相应地，每个子像素内的电容结构所占的面积也越来越小，电容容量也会因此下降。因此，在提高显示面板分辨率的同时保证电容结构的电容量成为显示领域研究的课题之一。
例如，图1为一种阵列基板10的剖面结构示意图，如图1所示，该阵列基板10包括薄膜晶体管19和电容结构14等结构。例如，薄膜晶体管19包括有源层15、栅极16、源极17、漏极18等结构。电容结构14包括第一电极11、第二电极12以及位于第一电极11和第二电极12之间的介电层13等结构。如图1所示，电容结构14的第一电极11和第二电极12均为平面板状结构。当该阵列基板10的每个子像素所占的面积相对较小时，每个子像素内的电容结构14所占的面积相应也较小，因此第一电极11和第二电极12彼此相对的面积也相应较小，从而有可能使得电容结构14的电容量太小而无法满足产品设计需求。
电容量可以表示为C＝K×(A/d)，其中，C为电容量，K为介电层的介电常数，A为电容结构中两个电极的彼此相对面积，d为电容结构中两个电极之间的垂直距离。例如，d通常为介电层的厚度，或者d为在垂直于第一电极和/或第二电极的方向上的介电层的尺寸。由该公式可以看出，电容量与电容结构中两个电极之间的正对面积成正比。
为了在提高显示面板分辨率的同时不减小电容结构的电容量，一方面，例如可以使用具有高介电常数K的介电层材料。例如，高介电常数K的介电层材料包括ZrO 2、HfO 2等。但是，具有高介电常数K的介电层材料通常需要在高温条件下或者使用原子层沉积(Atomic Layer Deposition，ALD)方法进行薄膜沉积。然而，目前的低温多晶硅显示面板的制造工艺或者有机发光二极管显示面板的制造工艺等无法满足沉积高介电常数K的介电薄膜所需的高温条件，而且原子层沉积方法镀膜速率较低，无法满足实际的生产效率要求。
另一方面，例如可以通过降低介电层的厚度d从而可以提高电容结构的电容量C。但是，在实际的制造工艺中，电容结构中的介电层例如通常还可以同时作为显示面板中薄膜晶体管的栅绝缘层，降低介电层的厚度d有可能 会导致薄膜晶体管产生漏电流产生隧道效应而带来驱动问题，或者可能会带来闪烁问题导致出现画面不良现象，从而影响显示面板的显示效果。
本公开至少一个实施例提供一种阵列基板，该阵列基板包括衬底基板、第一电极和第二电极。第一电极设置在衬底基板上；第二电极设置在第一电极上且在垂直于衬底基板的方向上与第一电极至少部分相对。第一电极与第二电极彼此电绝缘，且第一电极和/或第二电极在相对的区域内包括形成至少部分第一凹槽的部分。
本公开至少一个实施例提供一种阵列基板，包括衬底基板、绝缘层和电容结构。绝缘层位于所述衬底基板上，包括凹槽。所述凹槽从所述绝缘层背离所述衬底基板的一侧贯穿至少部分所述绝缘层。电容结构至少位于所述凹槽的侧壁上，所述电容结构包括第一电极、第二电极和位于所述第一电极和所述第二电极之间的介电层。
例如，本公开的实施例中，第一凹槽由第一电极、第二电极和/或电容结构的一部分来形成，通过第一电极、第二电极和/或电容结构形成弯折部分来形成。例如，本公开的实施例中，第一电极、第二电极和电容结构至少之一在各个位置处具有大致相同的尺寸，即，厚度均一。
在本公开至少一个实施例提供的阵列基板中，通过在第一电极和/或第二电极相对的区域内形成至少部分第一凹槽的部分，增大了第一电极和第二电极在相对区域内的相对面积，从而增大了由该第一电极和第二电极构成的电容结构的电容量。
下面通过几个具体的实施例对本公开进行说明。为了保持本公开实施例以下的说明清楚且简明，可能省略已知功能和已知部件的详细说明。当本公开实施例的任一部件在一个以上的附图中出现时，该部件在每个附图中可以由相同的参考标号表示。
图2为本公开一实施例提供的一种阵列基板100的剖面结构示意图。图2着重示出了本公开实施例提供的阵列基板中的电容结构部分，图2所示的电容结构可用于替换图1所示的电容结构，以增加电容量。例如，该阵列基板100可以为各种适当类型的显示面板的阵列基板，本实施例不限定阵列基板所属的显示面板的具体类型。如图2所示，该阵列基板100包括衬底基板101、第一电极102和第二电极103等结构。
如图2所示，衬底基板101例如可以是玻璃基板、石英基板、塑料基板或其它适合材料的基板，本实施例对此不做具体的限定。例如，衬底基板101可以为柔性基板，也可以为刚性基板。
如图2所示，第一电极102设置在衬底基板101上。第二电极103设置在第一电极102上且在垂直于衬底基板101的方向上与第一电极102至少部分相对。第一电极102与第二电极103彼此电绝缘，且第一电极102和第二电极103在彼此相对的区域内包括形成第一凹槽104的部分。例如，第一电极102和/或第二电极103形成的第一凹槽104的数量例如可以是一个，也可以是多个，本实施例对第一凹槽104的数量不做具体限定。另外，第一电极102和/或第二电极103形成的第一凹槽104例如可以是完整的凹槽状，也可以是构成凹槽的至少一部分，例如，第一电极102和/或第二电极103在彼此相对的区域内形成凹槽的侧壁。本实施例对第一电极102和/或第二电极103形成的第一凹槽104的形状不做具体限定。本实施例以第一电极102和第二电极103均包括一个第一凹槽104为例进行介绍。
例如，通过部分的第一电极102形成弯折结构进而形成第一凹槽104。例如，通过部分的第二电极103形成弯折结构进而形成第一凹槽104。例如，如图2所示，第一电极102在于第二电极103相对的区域内包括形成第一凹槽104的部分1042。例如，如图2所示，第二电极103在与第一电极102彼此相对的区域内包括形成第一凹槽104的部分1043。例如，如图2所示，第一电极102和第二电极103在彼此相对的区域构成电容结构014，电容结构014包括形成至少部分第一凹槽104的部分1040。例如，第一电极102和第二电极103的材料的示例包括金属材料，该金属材料例如包括银、铝、铬、铜、钼、钛、铝钕合金、铜钼合金、钼钽合金、钼钕合金或任何它们的任意组合，本实施例对此不做具体限定。
例如，如图2所示，该阵列基板100还包括绝缘层105，绝缘层105设置在衬底基板101上且位于衬底基板101和第一电极102之间。该绝缘层105例如包括形成在其中的第二凹槽106。如图2所示，第一电极102的第一凹槽104在垂直于衬底基板101的方向上与绝缘层105中的第二凹槽106至少部分重叠。如图2所示，第二凹槽106的底壁和侧壁上均共形的形成有第一电极102和第二电极103。在一个示例中，当第一电极102包括形成第一凹 槽104的部分时，第一电极102的形成第一凹槽104的部分在垂直于衬底基板101的方向上与绝缘层105中的第二凹槽106至少部分重叠。例如，第一电极102/第二电极103的形成第一凹槽104的部分在垂直于衬底基板101的方向上至少与绝缘层105中的第二凹槽106的侧壁重叠。
例如，如图2所示，绝缘层105为叠层结构且包括从衬底基板101依次层叠的第一子绝缘层1051、第二子绝缘层1052和第三子绝缘层1053。绝缘层105的第二凹槽106贯穿绝缘层105中远离衬底基板101一侧的至少一个子绝缘层。例如，可以在绝缘层105的第三子绝缘层1053中形成凹槽以构成第二凹槽106；或者，可以在绝缘层105的第三子绝缘层1053和第二子绝缘层1052中形成凹槽以构成第二凹槽106；又或者，可以在绝缘层105的第三子绝缘层1053、第二子绝缘层1052和第一子绝缘层1051中形成凹槽以构成第二凹槽106。本实施例对第二凹槽106贯穿的绝缘层105中的子绝缘层的层数不做具体限定。值得注意的是，绝缘层105包括的子绝缘层的层数包括但不限于三层。例如，根据产品设计需求，绝缘层105包括的子绝缘层的层数可以是一层、两层、四层或者更多层，本实施例对此不做具体限定。本公开的实施例中，还可以第二凹槽106还可以贯穿子绝缘层的一部分。例如，为了利于阵列基板的制作以及性能稳定，绝缘层105的最靠近衬底基板101一侧的子绝缘层的一部分未被第二凹槽106贯穿。例如，绝缘层105的最靠近衬底基板101一侧的子绝缘层的未被刻蚀的厚度约为该子绝缘层的厚度的六分之一至三分之一。例如，绝缘层105的最靠近衬底基板101一侧的子绝缘层的厚度约为
Figure PCTCN2018115655-appb-000001
绝缘层105的最靠近衬底基板101一侧的子绝缘层的未被刻蚀的厚度约为
Figure PCTCN2018115655-appb-000002
例如，如图2所示，在垂直于衬底基板101的方向上，第一电极102的形成第一凹槽104的部分的横截面积与截面形状等与第二凹槽106的深度等相关。例如，绝缘层105中的第二凹槽106的深度越深，在绝缘层105之后形成的第一电极102的形成第一凹槽104的部分的深度也会越深，第一电极102在垂直于衬底基板101的方向上的单位面积内的面积对应地也会越大，第一电极102与第二电极103单位面积内的相对面积也会相应地增大，因此，由该第一电极102与第二电极103构成的电容结构的电容量会得到提高。因此，在实际的制造过程中，例如可以通过调整绝缘层105中第一子绝缘层 1051、第二子绝缘层1052、第三子绝缘层1053的厚度从而控制第二凹槽106的深度，从而相应地调节阵列基板100的每个子像素的电容量的大小。
如图2所示，该阵列基板100还包括介电层107，介电层107设置在第一电极102和第二电极103之间以使第一电极102和第二电极103电绝缘。电容结构014包括第一电极102、第二电极103和位于第一电极102和第二电极103之间的介电层107。介电层107包括形成第一凹槽的部分108，由第二电极103形成第一凹槽104的部分在垂直于衬底基板101的方向上与介电层107形成第一凹槽108的部分至少部分重叠。在一个示例中，当第二电极103包括形成第一凹槽104的部分时，第二电极103的形成第一凹槽104的部分在垂直于衬底基板101的方向上与介电层107的形成第一凹槽的部分108至少部分重叠。例如，用于该介电层107的材料包括氧化硅、氮化硅、氮氧化硅等任意适合的材料，又例如为高介电系数材料，本实施例对此不做具体的限定。
如图2所示，在一个示例中，该阵列基板100还包括缓冲层109、阻隔层110、第二绝缘层111、层间介电层112和平坦层113等结构。
如图2所示，缓冲层109设置在衬底基板101上。缓冲层109例如可以防止杂质离子和湿气或者外部空气等通过衬底基板101渗入到阵列基板100中，并且缓冲层109可以平坦化衬底基板101的表面。该缓冲层109例如还可以防止衬底基板101中的杂质离子扩散到之后形成的包括薄膜晶体管等驱动电路层之中，防止对薄膜晶体管元件的阈值电压和漏电流等特性产生影响。用于该缓冲层109的材料的示例包括SiNx、SiOx等任意适合的材料，本实施例对此不做具体限定。例如，缓冲层109的厚度约为
Figure PCTCN2018115655-appb-000003
但不限于此。
例如，阻隔层110设置在缓冲层109上。该阵列基板100的阻隔层110例如可以用于避免阵列基板中后续形成的有源层受到外部光线照射产生光生载流子进而造成不希望的漏电流。用于阻隔层110的材料的示例包括金属材料(例如银、铬等)、SiNx、SiOx或任何其它适合的材料，本实施例对此不做具体限定。
例如，第二绝缘层111设置在阻隔层110和绝缘层105之间。第二绝缘层111的材料的示例包括聚酰亚胺等任意适合的材料，本实施例对此不做具体限定。绝缘层105中的第二凹槽106的底部到衬底基板101的距离大于或 等于第二绝缘层111的上表面到衬底基板101的距离。也即绝缘层105中的第二凹槽106不会贯穿第二绝缘层111，从而可以避免第一电极102与阻隔层110之间发生短路现象。例如，层间介电层112设置在第二电极103上且覆盖第二电极103以对第二电极103形成保护。例如，平坦层113设置在层间介电层112上。用于层间介电层112和平坦层113的材料的示例包括SiNx、SiOx或任何其它适合的材料，本实施例对此不做具体限定。
需要说明的是，为表示清楚，并没有给出该阵列基板100的全部结构。为实现阵列基板的必要功能，本领域技术人员可以根据具体应用场景进行设置其他未示出的结构，本公开的实施例对此不做限制。
在本公开至少一个实施例提供的阵列基板100中，在垂直于衬底基板101的方向上，第一电极102和第二电极103在相对的区域内包括形成第一凹槽104的部分。相比于由平板面状电极构成的阵列基板，通过对第一电极102和第二电极103进行设计以使第一电极102和第二电极103包括构成第一凹槽104的部分，增大了第一电极102和第二电极103在彼此相对区域内的相对面积，从而提高了由该第一电极102和第二电极103构成的阵列基板100的电容的电容量。
图3为本公开另一实施例提供的阵列基板200的剖面结构示意图。如图3所示，阵列基板200中，第一电极102、第二电极103和/或电容结构构成的第一凹槽104的数量为两个。除了阵列基板200中第一电极102和第二电极103中第一凹槽104的数量不同外，该示例的阵列基板200的结构与图2中描述的阵列基板100的结构可以基本上相同。需要说明的是，阵列基板200中第一电极102和第二电极103中第一凹槽104的数量可以为更多个，不限于两个。
如图3所示，该阵列基板200的第一电极102、第二电极103和电容结构014在彼此相对的区域内包括两个第一凹槽104。例如，两个第一凹槽104紧邻设置。绝缘层105设置在衬底基板101上且位于衬底基板101和第一电极102之间，绝缘层105包括形成在其中的两个第二凹槽106，第一电极102构成的两个第一凹槽104在垂直于衬底基板101的方向上与绝缘层105中的两个第二凹槽106分别至少部分重叠。例如，电容结构014共形地形成在第二凹槽106上。介电层107设置在第一电极102和第二电极103之间以使第 一电极102和第二电极103彼此电绝缘。介电层107包括形成两个第一凹槽的部分108，由第二电极103形成两个第一凹槽104的部分1043在垂直于衬底基板101的方向上与介电层107的形成两个第一凹槽的部分108分别至少部分重叠。
例如，当产品的设计满足阵列基板200中包括多个例如两个第一凹槽104时，第一电极102和第二电极103的单位面积内的彼此相对面积得到进一步的增大，从而进一步提高了由该第一电极102和第二电极103构成的阵列基板200的电容量。
图4为本公开另一实施例提供的阵列基板300的剖面结构示意图，参考图4，除了阵列基板300中第二电极103的形状外，该示例的阵列基板300的结构与图2中描述的阵列基板100的结构可以基本上相同。图4中示出的电容结构位于第二凹槽106的侧壁上，第二凹槽106的底壁上不设置电容结构。
如图4所示，阵列基板300的第一电极102包括形成第一凹槽104的部分，阵列基板300的第二电极103包括形成部分第一凹槽104的部分，且第二电极103中形成第一凹槽104的部分在垂直于衬底基板101的方向上与第一电极102的形成第一凹槽104的部分至少部分重叠。绝缘层105设置在衬底基板101上且位于衬底基板101和第一电极102之间，绝缘层105包括形成在其中的第二凹槽106，第一电极102形成第一凹槽104的部分在垂直于衬底基板101的方向上与绝缘层105中的第二凹槽106至少部分重叠。介电层107设置在第一电极102和第二电极103之间以使第一电极102和第二电极103电绝缘。介电层107包括形成第一凹槽104的部分108，第二电极103的形成第一凹槽104的部分1043在垂直于衬底基板101的方向上与介电层107形成的第一凹槽104的部分108至少部分重叠。
在另一个示例中，第一电极102包括形成第一凹槽104的部分，第二电极103包括形成第一凹槽104的部分，且第二电极103的形成第一凹槽104的部分1043在垂直于衬底基板101的方向上与第一电极102的形成第一凹槽104的部分1042至少部分重叠。或者，也可以是第一电极102和第二电极103在彼此相对的区域内分别包括形成第一凹槽104的部分。本实施例对第一电极102和/或第二电极103的形成第一凹槽104的部分的形状不做具体限制， 只要该凹槽的形状可以增大第一电极102和第二电极103在垂直于衬底基板101的方向上的彼此的相对面积即可。
本公开另一实施例提供一种阵列基板400，图5示出了根据本实施例提供的阵列基板400的剖面结构示意图。例如，该阵列基板400可以作为各种适当类型的显示面板的阵列基板。
如图5所示，本实施例以阵列基板400为OLED显示装置的阵列基板为例进行介绍。该阵列基板400包括第一电极102、第二电极103、驱动电路结构405、发光元件409等结构。电容结构014包括第一电极102、第二电极103和介电层107。驱动电路结构405例如可以是晶体管，在本实施例中，以驱动电路结构405为薄膜晶体管(即驱动晶体管)为例进行介绍。该薄膜晶体管405例如可以为顶栅型薄膜晶体管或者底栅型薄膜晶体管，本实施例不限制薄膜晶体管405的具体类型。本实施例以薄膜晶体管405为顶栅型薄膜晶体管为例进行介绍，如图5所示，该薄膜晶体管405包括有源层401、栅极402、漏极403、源极404等结构。例如，介电层107同时作为薄膜晶体管405的栅绝缘层。
例如，有源层401可以包括非晶硅材料、多晶硅材料、金属氧化物半导体材料(例如氧化铟镓锌(IGZO))或任何其它适合的材料，本实施例对此不做具体限定。例如，当该阵列基板400为低温多晶硅薄膜晶体管阵列基板或高温多晶硅薄膜晶体管阵列基板时，例如可以通过快速热退火(RTA)方法、固相结晶(SPC)方法、准分子激光退火(ELA)方法、金属诱导结晶(MIC)方法、金属诱导横向结晶(MILC)方法、连续横向固化(SLS)等方法将非晶硅有源层101结晶化为多晶硅有源层101。
如图5所示，第一电极102与薄膜晶体管405的栅极402同层设置，在制造过程中，第一电极102和栅极402可以采用同一构图工艺同时形成。第二电极103与薄膜晶体管405的源极404和漏极403同层设置，在制造过程中，第二电极103与源极404和漏极403可以采用同一构图工艺同时形成。或者，在另一个示例中，也可以是第一电极102与薄膜晶体管405的有源层401同层设置，第二电极103与薄膜晶体管405的栅极402或者漏极403/源极404同层设置。例如，当薄膜晶体管405为底栅型薄膜晶体管时，第一电极102可以与薄膜晶体管405的栅极402同层设置，第二电极103可以与薄 膜晶体管405的有源层401或者漏极403/源极404同层设置。
在一个示例中，第三子绝缘层1053也可以作为阵列基板400中的薄膜晶体管405的栅绝缘层，第三子绝缘层1053的材料的示例包括SiNx、SiOx等任意适合的材料。例如，当第三子缘层1053作为薄膜晶体管405的栅绝缘层时，由于在后续的制造工艺中需要以栅绝缘层为掩模对有源层401进行离子掺杂，因此第三子绝缘层1053的厚度范围可限定在一定范围内。例如第三子绝缘层1053的厚度可小于150纳米。例如，当需要增大绝缘层105中第二凹槽106的深度以相应增大第一电极102和第二电极103之间的相对面积时，可以增大绝缘层105中第一子绝缘层1051和第二子绝缘层1052的厚度。第一子绝缘层1051和第二子绝缘层1052的厚度参数的改变，对由该第一子绝缘层1051和第二子绝缘层1052构成的阵列基板400的特性通常不会产生不利的影响。例如，可以通过实验得到绝缘层105中第二凹槽106的深度与第一子绝缘层1051和第二子绝缘层1052的厚度之间的关系。例如，第一子绝缘层1051的厚度约为
Figure PCTCN2018115655-appb-000004
例如，第二子绝缘层1052的厚度约为
Figure PCTCN2018115655-appb-000005
如图5所示，发光元件409为有机发光二极管，该发光元件409例如包括像素电极406、对电极408以及介于像素电极406和对电极408之间的有机功能层407。像素电极406与薄膜晶体管405的源极404电连接，当然，像素电极406也可以和薄膜晶体管405的漏极403电连接，从而该阵列基板400的每个子像素单元内的薄膜晶体管405可以为像素电极406施加信号。像素电极406的材料包括透明导电材料，该透明导电材料例如可以为氧化铟锡、氧化铟锌等任意适合的材料。对电极408例如可以配置为该阵列基板400的公共电极。例如，像素电极406可以作为该发光元件409的阳极，对电极408可以作为该发光元件409的阴极。当然，也可以是像素电极406作为该发光元件409的阴极，对电极408作为该发光元件409的阳极。
有机功能层407例如包括有机发光层，并且根据需要还可以进一步包括空穴传输层、空穴注入层、电子传输层和电子注入层中的一个或多个。
需要说明的是，为表示清楚，并没有给出该阵列基板400的全部结构。为实现阵列基板的必要功能，本领域技术人员可以根据具体应用场景进行设置其他未示出的结构，本公开的实施例对此不做限制。
在本公开至少一个实施例提供的阵列基板400中，该阵列基板400包括 第一电极102、第二电极103、薄膜晶体管405、发光元件409等结构。相比于由平板面状电极构成的阵列基板，通过对第一电极102和第二电极103进行弯折设计以使第一电极102和第二电极103分别包括形成第一凹槽104的部分，增大了第一电极102和第二电极103在彼此相对区域内的单位面积内的相对面积，提高了由该第一电极102和第二电极103构成的阵列基板400的电容量，从而有利于该阵列基板400在高分辨率方面的设计，提高显示质量。
本实施例提供的阵列基板400的其它技术效果可参见上述实施例描述的任一阵列基板的技术效果，在此不再赘述。
例如，本公开另一实施例还提供一种显示面板，该显示面板包括上述实施例描述的任一阵列基板。该显示面板例如可以是液晶显示面板或者有机发光二极管显示面板等。该显示面板的技术效果，可参见上述实施例描述的任一阵列基板的技术效果，在此不再赘述。
例如，本公开另一实施例还提供一种电子装置，该电子装置包括上述实施例描述的任一阵列基板。该电子装置例如可以是显示装置、电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何包括阵列基板的产品或者部件。该电子装置的技术效果，可参见上述实施例描述的阵列基板的技术效果，在此不再赘述。
本公开另一实施例提供一种阵列基板的制造方法，包括：在衬底基板上形成绝缘层；在所述绝缘层中形成凹槽，所述凹槽从所述绝缘层背离所述衬底基板的一侧贯穿至少部分所述绝缘层；以及至少在所述凹槽的侧壁上共形地形成电容结构，形成所述电容结构包括形成第一电极、形成第二电极和形成位于所述第一电极和所述第二电极之间的介电层。
本公开另一实施例提供一种阵列基板的制造方法，该阵列基板包括上述实施例描述的任一阵列基板。本实施例以阵列基板200的制造方法为例进行说明，图6A-图6G为本实施例提供的阵列基板200在制造过程中的剖面结构示意图。
如图6A所示，首先提供衬底基板101，衬底基板101例如可以是玻璃基板、石英基板、塑料基板或其它适合材料的基板，本实施例对此不做具体限定。例如，衬底基板101还可以为聚酰亚胺等柔性衬底。当采用柔性衬底时， 可将其放置在背板玻璃上以利各膜层的制作。
如图6A所示，在衬底基板101上例如可以通过化学气相沉积、物理气相沉积等方法沉积缓冲层109，缓冲层109例如可以防止杂质离子和湿气或者外部空气等通过衬底基板101渗入到阵列基板中，同时该缓冲层109例如还可以平坦化衬底基板101的表面。该缓冲层109例如还可以防止衬底基板101中的杂质离子扩散到之后形成的包括薄膜晶体管等电路层之中，防止对薄膜晶体管元件的阈值电压和漏电流等特性产生影响。用于该缓冲层109的材料的示例包括SiNx、SiOx或任意其它适合的材料，本实施例对此不做限定。
如图6A所示，在缓冲层109上例如可以通过化学气相沉积、物理气相沉积等方法沉积阻隔层110。例如，该阻隔层110可以用于避免阵列基板中后续形成的有源层受到外部光线照射产生光生载流子进而造成不希望的漏电流。用于阻隔层110的材料的示例包括金属材料(例如银、铬等)、SiNx、SiOx或任何其它适合的材料，本实施例对此不做具体限定。
如图6A所示，在阻隔层110上例如可以通过化学气相沉积、物理气相沉积等方法沉积第二绝缘层111。第二绝缘层111的材料的示例包括聚酰亚胺等任意适合的材料，本实施例对此不做具体限定。
如图6B所示，在第二绝缘层111上例如可以通过化学气相沉积、物理气相沉积等方法依次沉积第一子绝缘层1051、第二子绝缘层1052、第三子绝缘层1053以构成绝缘层105。例如，根据产品设计需求，可以通过控制沉积时间、沉积速率等参数分别得到所需厚度的第一子绝缘层1051、第二子绝缘层1052、第三子绝缘层1053。当然，绝缘层105包括的子绝缘层的层数包括但不限于三层，例如，根据产品设计需求，绝缘层105包括的子绝缘层的层数可以是一层、两层、四层或者多层，本实施例对此不做具体限定。用于第一子绝缘层1051、第二子绝缘层1052、第三子绝缘层1053的材料的示例包括SiNx、SiOx或其它适合的材料，本实施例对此不做限定。
如图6C所示，在第三子绝缘层1053的整个表面上形成光刻胶层(图中未示出)，通过包括曝光工序以及显影工序的光刻法处理对光刻胶层构图，以在第三子绝缘层1053上形成具有所需形状的光刻胶图案。然后利用上述光刻胶图案作为蚀刻掩模对第三子绝缘层1053、第二子绝缘层1052、第一子绝 缘层1051同时进行刻蚀，以在由第三子绝缘层1053、第二子绝缘层1052、第一子绝缘层1051构成的绝缘层105中形成两个第二凹槽106。例如，两个第二凹槽106彼此并列形成。刻蚀方法例如包括干法刻蚀，例如通过控制刻蚀时间、刻蚀速率等参数可以控制第二凹槽106的深度，从而使得形成的第二凹槽106至少贯穿绝缘层105中远离衬底基板101一侧的至少一个子绝缘层，且不会贯穿第二绝缘层111。如图6C所示，第二凹槽106包括底壁BS和侧壁SS。
如图6D所示，在第三子绝缘层1053上例如可以通过化学气相沉积、物理气相沉积等方法沉积金属层，然后通过光刻工艺对该金属层进行构图，以在第三子绝缘层1053上形成包括两个第一凹槽104的第一电极102。第一电极102的包括两个第二凹槽104的部分1042沿着绝缘层105的两个第二凹槽106分别共形的形成。用于第一电极102的材料的示例包括银、铝、铬、铜、钼、钛、铝钕合金、铜钼合金、钼钽合金、钼钕合金或任何它们的任意组合。例如，如图6D所示，第一电极具有与第二凹槽106形状相同的部分。
例如，在另一个示例中，在第三子绝缘层1053上例如可以通过化学气相沉积、物理气相沉积等方法沉积金属层，然后通过光刻工艺对该金属层进行构图，以在第三子绝缘层1053上形成第一电极102。该第一电极102包括形成有第一凹槽104的部分，且第一电极102的形成第一凹槽104的部分1042沿着至少一个第二凹槽106共形的形成。
如图6E所示，在第三子绝缘层1053上形成具有形成两个第一凹槽104的部分的第一电极102之后，在第一电极102上例如可以通过化学气相沉积、物理气相沉积等方法沉积介电层薄膜。然后通过光刻工艺对该介电层薄膜进行构图，以在第二电极103上形成介电层107，形成的介电层107包括形成两个第一凹槽104的部分108，形成两个第一凹槽的部分108沿着第一电极102的形成两个第一凹槽104的部分1042分别共形的形成。用于介电层107的材料的示例包括氧化硅、氮化硅、氮氧化硅等任意适合的材料，又例如为高介电系数材料，本实施例对此不做具体的限定。例如，如图6E所示，介电层107具有与第二凹槽形状相同的部分。
如图6F所示，在介电层107上例如可以通过化学气相沉积、物理气相沉积等方法沉积金属层，然后通过光刻工艺对该金属层进行构图，以在介电 层107上形成第二电极103。形成的第二电极103在垂直于衬底基板101的方向上与第一电极102至少部分相对，且第二电极103与第一电极102通过介电层107彼此电绝缘。第二电极103包括形成两个第一凹槽104的部分1043，且第二电极103的形成两个第二凹槽104的部分沿着介电层107的形成两个第一凹槽104的部分108分别共形的形成。用于第二电极103的材料的示例包括银、铝、铬、铜、钼、钛、铝钕合金、铜钼合金、钼钽合金、钼钕合金或任何它们的任意组合。如图6F所示，电容结构014具有形成第一凹槽104的部分140。
在另一个示例中，在介电层107上例如可以通过化学气相沉积、物理气相沉积等方法沉积金属层，然后通过构图工艺对该金属层进行构图，以在介电层107上形成第二电极103。该第二电极103包括形成第一凹槽104的部分，且第二电极103的形成有第一凹槽104的部分1043与介电层107中的形成至少一个第一凹槽的部分108共形的形成。
如图6G所示，在介电层107上形成包括形成两个第一凹槽104的部分1043的第二电极103之后，在第二电极103上例如可以通过化学气相沉积、物理气相沉积等方法沉积层间介电薄膜112，然后通过光刻工艺对该层间介电薄膜进行构图以形成层间介电层112。层间介电层112覆盖第二电极103以对第二电极103形成保护，用于层间介电层112的材料的示例包括SiNx、SiOx或任何其它适合的材料，本实施例对此不做具体限定。
在层间介电层112上沉积平坦层薄膜，然后通过构图工艺对该平坦层薄膜进行构图以形成平坦层113。用于平坦层113的材料的示例包括SiNx、SiOx或任何其它适合的材料，本实施例对此不做具体限定。
在本公开至少一个实施例提供的阵列基板200的制造方法中，在垂直于衬底基板101的方向上，通过对第一电极102和第二电极103进行设计以使第一电极102和第二电极103分别包括形成两个第一凹槽104的部分。相比于由平板面状电极形成的阵列基板，该方法增大了第一电极102和第二电极103在彼此相对区域内的相对面积，提高了由该第一电极102和第二电极103构成的阵列基板200的电容量。
在不冲突的情况下，本公开的各个实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板；
    第一电极，在所述衬底基板上；
    第二电极，在所述第一电极的背离所述衬底基板的一侧，且在垂直于所述衬底基板的方向上与所述第一电极至少部分相对；其中，
    所述第一电极与所述第二电极彼此电绝缘，且所述第一电极和所述第二电极在彼此相对的区域构成电容结构，所述电容结构包括形成至少部分第一凹槽的部分。
  2. 如权利要求1所述的阵列基板，其中，所述电容结构包括形成多个第一凹槽的部分。
  3. 如权利要求1或2所述的阵列基板，还包括绝缘层，其中，所述绝缘层位于所述衬底基板和所述第一电极之间且包括形成在其中的第二凹槽，所述电容结构至少位于所述第二凹槽的侧壁上。
  4. 如权利要求3所述的阵列基板，其中，所述电容结构的形成至少部分第一凹槽的部分在垂直于所述衬底基板的方向上与所述绝缘层中的第二凹槽至少部分重叠。
  5. 如权利要求3所述的阵列基板，其中，所述绝缘层为叠层结构且包括从所述衬底基板依次层叠的至少两个子绝缘层，所述第二凹槽贯穿所述绝缘层的远离所述衬底基板一侧的至少一个子绝缘层。
  6. 如权利要求5所述的阵列基板，其中，所述绝缘层的最靠近所述衬底基板一侧的所述子绝缘层的至少一部分未被所述第二凹槽贯穿。
  7. 如权利要求3所述的阵列基板，其中，所述绝缘层包括多个第二凹槽，所述电容结构包括形成多个第一凹槽的部分，所述多个第一凹槽和所述多个第二凹槽一一对应，所述多个第一凹槽中的每个位于所述多个第二凹槽中的一个内。
  8. 如权利要求1-7任一项所述的阵列基板，其中，所述电容结构还包括位于所述第一电极和所述第二电极之间的介电层以使得所述第一电极与所述第二电极彼此电绝缘。
  9. 如权利要求1-8任一项所述的阵列基板，还包括薄膜晶体管，其中，
    所述薄膜晶体管包括有源层、栅极、源漏极；
    所述第一电极与所述有源层、所述栅极、所述源漏极中的任意一个同层设置；
    所述第二电极与所述有源层、所述栅极、所述源漏极中的另两个中的一个同层设置。
  10. 如权利要求1-8任一项所述的阵列基板，还包括薄膜晶体管和发光元件，其中，所述薄膜晶体管包括漏极，所述发光元件包括像素电极，所述像素电极与所述漏极电连接。
  11. 一种显示面板，包括如权利要求1-10任一项所述的阵列基板。
  12. 一种电子装置，包括如权利要求1-10任一项所述的阵列基板。
  13. 一种阵列基板的制造方法，包括：
    提供衬底基板；
    在所述衬底基板上形成第一电极；
    在所述第一电极上形成第二电极，所述第二电极在垂直于所述衬底基板的方向上与所述第一电极至少部分相对；其中，
    所述第一电极与所述第二电极彼此电绝缘，且所述第一电极和所述第二电极在彼此相对的区域构成电容结构，所述电容结构包括形成至少部分第一凹槽的部分。
  14. 如权利要求13所述的方法，其中，所述电容结构包括形成多个第一凹槽的部分。
  15. 如权利要求13或14所述的方法，还包括：
    在形成所述第一电极之前，在所述衬底基板上形成绝缘层薄膜，对所述绝缘层薄膜进行刻蚀以形成包括第二凹槽的绝缘层；其中，
    所述电容结构的形成所述至少部分第一凹槽的部分在垂直于所述衬底基板的方向上与所述第二凹槽至少部分重叠。
  16. 如权利要求15所述的方法，其中，所述电容结构至少形成在所述第二凹槽的侧壁上。
  17. 如权利要求13-16任一项所述的方法，还包括：
    在形成所述第一电极的第一次构图工艺中同时形成薄膜晶体管的栅极；
    在形成所述第二电极的第二次构图工艺中同时形成所述薄膜晶体管的源 极和漏极。
  18. 一种阵列基板，包括：
    衬底基板；
    绝缘层，位于所述衬底基板上，包括凹槽，所述凹槽从所述绝缘层背离所述衬底基板的一侧贯穿至少部分所述绝缘层；
    电容结构，至少位于所述凹槽的侧壁上，所述电容结构包括第一电极、第二电极和位于所述第一电极和所述第二电极之间的介电层。
  19. 如权利要求18所述的阵列基板，所述电容结构还位于所述凹槽的底壁上。
  20. 一种阵列基板的制造方法，包括：
    在衬底基板上形成绝缘层；
    在所述绝缘层中形成凹槽，所述凹槽从所述绝缘层背离所述衬底基板的一侧贯穿至少部分所述绝缘层；
    至少在所述凹槽的侧壁上共形地形成电容结构，形成所述电容结构包括形成第一电极、形成第二电极和形成位于所述第一电极和所述第二电极之间的介电层。
PCT/CN2018/115655 2018-03-22 2018-11-15 阵列基板及其制造方法、显示面板、电子装置 WO2019179137A1 (zh)

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CN110690257A (zh) * 2019-08-29 2020-01-14 福建华佳彩有限公司 一种tft阵列基板及其制造方法
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102623451A (zh) * 2011-12-29 2012-08-01 友达光电股份有限公司 像素阵列基板
US9006717B2 (en) * 2012-04-17 2015-04-14 Samsung Display Co., Ltd. Organic light-emitting display apparatus and method of manufacturing organic light-emitting display apparatus
CN104576682A (zh) * 2013-10-18 2015-04-29 昆山工研院新型平板显示技术中心有限公司 一种有机发光显示装置及其制备方法
CN106647059A (zh) * 2017-01-04 2017-05-10 京东方科技集团股份有限公司 阵列基板、显示面板及其制造方法
CN108447874A (zh) * 2018-03-22 2018-08-24 绵阳京东方光电科技有限公司 阵列基板及其制造方法、显示面板、电子装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101073565B1 (ko) * 2010-02-08 2011-10-17 삼성모바일디스플레이주식회사 유기 발광 표시장치 및 이의 제조방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102623451A (zh) * 2011-12-29 2012-08-01 友达光电股份有限公司 像素阵列基板
US9006717B2 (en) * 2012-04-17 2015-04-14 Samsung Display Co., Ltd. Organic light-emitting display apparatus and method of manufacturing organic light-emitting display apparatus
CN104576682A (zh) * 2013-10-18 2015-04-29 昆山工研院新型平板显示技术中心有限公司 一种有机发光显示装置及其制备方法
CN106647059A (zh) * 2017-01-04 2017-05-10 京东方科技集团股份有限公司 阵列基板、显示面板及其制造方法
CN108447874A (zh) * 2018-03-22 2018-08-24 绵阳京东方光电科技有限公司 阵列基板及其制造方法、显示面板、电子装置

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