WO2016000342A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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WO2016000342A1
WO2016000342A1 PCT/CN2014/088082 CN2014088082W WO2016000342A1 WO 2016000342 A1 WO2016000342 A1 WO 2016000342A1 CN 2014088082 W CN2014088082 W CN 2014088082W WO 2016000342 A1 WO2016000342 A1 WO 2016000342A1
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layer
photoresist
film layer
source
pattern
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PCT/CN2014/088082
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English (en)
French (fr)
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龙春平
梁逸南
皇甫鲁江
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京东方科技集团股份有限公司
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Priority to US14/646,925 priority Critical patent/US9761616B2/en
Publication of WO2016000342A1 publication Critical patent/WO2016000342A1/zh

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    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/772—Field effect transistors
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    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.
  • OLED organic light emitting diode
  • PMOLED Passive Matrix Driving OLED
  • AMOLED Active Matrix Driving OLED
  • an AMOLED In the framework of an AMOLED, it can be driven using amorphous silicon, polysilicon, an oxide semiconductor or an organic thin film transistor.
  • a patterning process multiple times, for example, an 8- to 9-mask exposure process. In this way, not only the process is complicated, the cost is high, but the cumbersome process steps also lead to the continuous superposition of production errors, making the quality of the AMOLED display device difficult to ensure.
  • a method for fabricating an array substrate including:
  • an array substrate including:
  • a gate electrode a gate electrode, a gate insulating layer, and a polysilicon active layer formed on the base substrate;
  • a passivation layer formed on a surface of the polysilicon active layer, and first via holes and second via holes on a surface of the passivation layer;
  • a pixel electrode electrically connected to the drain.
  • a display device comprising any of the array substrates as described above.
  • 1 is a schematic structural view of a known array substrate
  • FIG. 2 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention
  • 3a-3e are schematic structural diagrams of steps in another process of fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a flow chart of another method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of another method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 6 is a flowchart of still another method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of each step in the process of fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 8 is a flowchart of still another method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of each step in the process of preparing an array substrate according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 11 is a flowchart of still another method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 12 is a schematic structural diagram of each step in the process of fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 13 is a schematic structural diagram of another array substrate according to an embodiment of the present invention.
  • a polysilicon active layer 102 made of polysilicon is located on a surface of the buffer layer 200; the surface of the polysilicon active layer 102 has a gate insulating layer 101 and a gate in this order.
  • an interlayer insulating layer 201; a source 106 and a drain 107 are electrically connected to the polysilicon active layer 102 through via holes on the surface of the interlayer insulating layer 201, and the pixel electrode 108 passes through a via located on the surface of the passivation layer 103.
  • the drain 107 is electrically connected; the pixel electrode 108 and the surface of the passivation layer 103 are provided with a pixel defining layer 109.
  • An embodiment of the present invention provides a method for fabricating an array substrate, as shown in FIG. 2, including:
  • a pattern including the gate electrode 100, the gate insulating layer 101, and the polysilicon active layer 102 may be formed by one patterning process.
  • a passivation layer 103 may be formed on the surface of the substrate on which the above pattern is formed, and a pattern of the first via hole 104 and the second via hole 105 may be formed on the surface of the passivation layer 103 by one patterning process. .
  • a pattern of the source 106, the drain 107, and the pixel electrode 108 may be formed by a patterning process on the surface of the substrate on which the pattern is formed; wherein the source 106 passes through the first via 104 and the polysilicon
  • the active layer 102 is electrically connected, and the drain 106 is electrically connected to the polysilicon active layer 102 through the second via 105.
  • the pattern of the pixel defining layer 109 can be formed by one patterning process.
  • the patterning process refers to a photolithography process, or includes a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, etc.;
  • the process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, etc., including a film forming, exposure, and developing process.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
  • Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device.
  • a gate electrode, a gate insulating layer, and a polysilicon active layer may be formed on the substrate by one patterning process; and the first via located on the surface of the passivation layer is formed by one patterning process.
  • a pixel defining layer is formed by one patterning process. In this way, only four patterning processes are used in the process of the AMOLED array substrate, which effectively reduces the number of patterning processes, simplifies the process steps, reduces production errors, and improves production efficiency and quality.
  • step S101 includes:
  • the buffer layer 200 is covered on the base substrate 10.
  • the buffer layer 200 is located between the gate electrode 100 and the base substrate 01, and includes a second material layer 221 near the surface of the gate 100 side and a surface near the surface of the substrate substrate 01. A material layer 220.
  • the first material layer 220 is made of silicon nitride (SiN) and has a thickness of 50 to 100 nm; and the second material layer 221 is made of silicon dioxide (SiO2) and has a thickness of 100 to 400 nm.
  • the first material layer 220 composed of silicon nitride (SiN) has a strong diffusion barrier property, can suppress the influence of metal ions on the polysilicon active layer 102, and has a function of waterproof dust.
  • the second material layer 221 composed of silicon oxide (SiO2) has an excellent interface with the polysilicon active layer 102, and can prevent the self-defect of the first material layer 220 composed of silicon nitride (SiN) from the polysilicon active layer 102. The quality caused damage.
  • a gate metal thin film layer 300, a gate insulating film layer 301, and a polysilicon thin film layer 302 are sequentially formed on the surface of the buffer layer 200.
  • a gate metal thin film layer 300 having a thickness of 200 to 500 nm may be deposited on the surface of the buffer layer 200 by magnetron sputtering.
  • the gate metal thin film layer 300 may be made of at least one of aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), and aluminum-niobium alloy (AlNd), or may be made of molybdenum/aluminum.
  • Multilayer metal composite film such as molybdenum (Mo/Al/Mo) or titanium/aluminum/titanium (Ti/Al/Ti).
  • a gate insulating film layer 301 is deposited on the surface of the gate metal thin film layer 300 by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.
  • the gate insulating layer 101 formed of the gate insulating film layer 301 may be located between the gate electrode 100 and the polysilicon active layer 102, including the first material layer 220 near the surface of the gate 100 side. And a second material layer 221 near a surface of one side of the polysilicon active layer 102.
  • the first material layer 220 is made of silicon nitride (SiN) and has a thickness of 20 to 100 nm; and the second material layer 221 is made of silicon dioxide (SiO2) and has a thickness of 30 to 400 nm.
  • the first material layer 220 composed of silicon nitride (SiN) has a strong diffusion barrier property, and the influence of the metal ions on the polysilicon active layer 102 can be suppressed.
  • the second material layer 221 composed of silicon oxide (SiO2) has an excellent interface with the polysilicon active layer 102, and can prevent the self-defect of the first material layer 220 composed of silicon nitride (SiN) from the polysilicon active layer 102. The quality caused damage.
  • the step of forming the polysilicon film layer 302 on the surface of the gate insulating film layer 301, as shown in FIG. 5, may include:
  • an amorphous silicon (a-Si) thin film is formed on the surface of the gate insulating film layer 301.
  • a-Si amorphous silicon
  • PECVD method chemical vapor deposition method
  • an amorphous silicon (a-Si) film may be formed on the surface of the second material layer 221 composed of silicon oxide (SiO2).
  • Amorphous silicon (a-Si) film subjected to the above dehydrogenation process is subjected to a crystallization process to form a polysilicon film layer 302.
  • a method such as laser annealing crystallization, metal induced crystallization, solid phase crystallization, or the like can be used.
  • amorphous silicon (a-Si) film is subjected to a dehydrogenation process before the crystallization process, it is possible to prevent the hydrogen ion from overflowing due to laser irradiation or the like during the crystallization process, resulting in hydrogen explosion.
  • the surface of the polysilicon film layer 302 is not flat, which seriously affects the quality of the product.
  • a photoresist 400 is coated on the surface of the polysilicon film layer 302, and is exposed by a two-tone reticle to form a first photoresist completely remaining region A (photoresist 401).
  • the thickness is 1 to 3 ⁇ m
  • the first photoresist portion is reserved (not shown in the drawing, the photoresist of the region is 0.5 to 1 ⁇ m thick)
  • the first photoresist is completely removed from the region B.
  • the first photoresist completely remaining region A corresponds to a pattern of the gate electrode 100, the gate insulating layer 101, and the polysilicon active layer 102 to be formed.
  • the first photoresist partially reserved region corresponds to a pattern of gate lines (not shown) connected to the gate 100; the first photoresist completely removed region B corresponds to the remaining region of the surface of the polysilicon film layer 302, the first The photoresist completely removed region B is not covered by the photoresist 400.
  • the gate 100 and the gate finally formed by the patterning process are illustrated.
  • the patterns of the insulating layer 101 and the polysilicon active layer 102 are identical. Therefore, a region other than the gate electrode 100 (or the gate insulating layer 101 or the polysilicon active layer 102) and the gate line on the surface of the polysilicon film layer 302 may be the first photoresist completely removed region B.
  • the polysilicon film layer 302 may be cleaned by the diluted hydrofluoric acid to reduce the surface roughness of the polysilicon film layer 302.
  • the two-tone reticle is a semi-transparent reticle, and two different thicknesses of photoresist 400 can be formed on the surface of the polysilicon film layer 302 (the first photoresist completely retains the area A).
  • the two-tone reticle may include a gray-tone mask and a half-tone mask.
  • a mixed gas such as carbon tetrafluoride/oxygen (CF4/O2), trifluoromethane/oxygen (CHF3/O2) or sulfur hexafluoride/oxygen (SF6/O2) may be used, by plasma or inductively coupled plasma method.
  • CF4/O2 carbon tetrafluoride/oxygen
  • CHF3/O2 trifluoromethane/oxygen
  • SF6/O2 sulfur hexafluoride/oxygen
  • etching or etching is performed by plasma or inductively coupled plasma method.
  • a gas such as carbon tetrafluoride (CF4), carbon tetrafluoride/oxygen (CF4/O2), or trifluoromethane/oxygen (CHF3/O2)
  • etching or etching is performed by plasma or inductively coupled plasma method.
  • wet etching or dry etching such as inductively coupled plasma using a mixed gas of carbon tetrachloride/boron trichloride (CCl2/BCl3) and carbon tetrafluoride/oxygen (CF4/O2), may be employed.
  • the gate etch process etches the gate metal film layer 300 to form a gate 100 and a gate line electrically connected to the gate 100.
  • the gate metal film layer 300 can be etched by a dry etching process when manufacturing a high resolution display panel; for a low resolution display panel
  • the gate metal thin film layer 300 may be etched by a wet etching process.
  • a thinner photoresist is removed using a plasma ashing process
  • a thicker photoresist 401 is retained as an etch barrier
  • a thinner photoresist is removed during ashing
  • a thicker photoresist is used.
  • the thickness of 401 is reduced.
  • the polysilicon film layer 302 is then etched by a plasma or inductively coupled plasma method to remove the polysilicon film layer 302 overlying the array gate lines.
  • step S206 as shown in FIG. 3e, the photoresist 401 of the first photoresist completely remaining region A is peeled off, and finally the pattern of the gate electrode 100, the gate insulating layer 101, and the gate line is formed.
  • the surface of the polysilicon film layer 302 which is preliminarily prepared as the polysilicon active layer 102 can be exposed.
  • the region other than the above polysilicon island may be performed through the mask. Protection to avoid adverse effects on the above areas during ion doping.
  • step S102 may include:
  • a passivation layer 103 is formed on the surface of the polysilicon active layer 102; for example, the passivation layer 103 is composed of a silicon nitride (SiN) film containing a hydrogen element. Its thickness is 200 to 500 nm.
  • annealing the passivation layer 103 by using an annealing process includes rapid thermal annealing or annealing using a heat treatment furnace.
  • both the passivation layer 103 and the gate insulating layer 101 contain silicon nitride (SiN), and the passivation layer 103 contains a hydrogen element. Therefore, hydrogenation treatment of the inside of the polysilicon active layer 102 and the interface of the polysilicon active layer 102 can be realized by silicon nitride (SiN). The dangling bonds in the polysilicon active layer 102 can be removed by the above hydrogenation treatment, thereby improving the mobility and reducing the drift of the threshold voltage.
  • a pattern of the first via hole 104 and the second via hole 105 is formed by one patterning process (for example, one mask exposure process).
  • step S103 includes:
  • a source/drain metal thin film layer 303 and a transparent conductive thin film layer 304 are sequentially formed on the surface of the passivation layer 103.
  • a source/drain metal thin film layer 303 having a thickness of 200 to 500 nm may be deposited on the surface of the passivation layer 103 by magnetron sputtering.
  • the source/drain metal thin film layer 303 may be made of at least one of aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), and aluminum-niobium alloy (AlNd), or may be used.
  • a multilayer metal film such as molybdenum/aluminum/molybdenum (Mo/Al/Mo) or titanium/aluminum/titanium (Ti/Al/Ti).
  • the metallic materials such as copper (Cu), molybdenum (Mo) or molybdenum/aluminum/molybdenum (Mo/Al/Mo) are relatively common in production processes due to their mature manufacturing process.
  • a transparent conductive film layer 304 is deposited on the surface of the source/drain metal film layer 303 by magnetron sputtering, and indium tin oxide/silver/indium tin oxide (ITO/Ag/ITO), indium zinc oxide/silver may be used.
  • Composite film (IZO/Ag) For example, the ITO has a thickness of 10 to 50 nm, and the Ag metal film has a thickness of 20 to 100 nm.
  • a photoresist 400 is formed on the surface of the transparent conductive film layer 304, and a second photoresist corresponding to the pattern of the source 106 and the drain 107 to be formed is completely retained by a single exposure and development process.
  • the region G, and the second photoresist corresponding to the remaining region of the surface of the transparent conductive film layer 304 completely removes the region F.
  • the second photoresist completely removed region F includes a source to be formed on the surface of the transparent conductive film layer 304.
  • the pixel defining layer 109 is formed on the surface of the substrate on which the above structure is formed by the step S104, and the array substrate as shown in FIG. 10 is produced.
  • the array substrate can be used to form a low temperature polysilicon display panel of a top emission type AMOLED.
  • the light of the display panel can be emitted upward (in a direction away from the surface of the base substrate 01). Since the source 106 and the drain 107 formed of the source/drain metal thin film layer 303 can reflect the emitted light, the aperture ratio of the display panel can be increased. Therefore, the top emission type AMOLED display panel can be applied to a high resolution display device.
  • step S103 may include:
  • a transparent conductive film layer 304 and a source/drain metal film layer 303 are sequentially formed on the surface of the passivation layer 103.
  • a transparent conductive film layer 304 is deposited on the surface of the passivation layer 103 by magnetron sputtering, and indium tin oxide/silver/indium tin oxide (ITO/Ag/ITO), indium zinc oxide/silver (IZO/) may be used.
  • Composite film such as Ag). The thickness is 20 to 100 nm.
  • a source/drain metal film layer 303 is deposited on the surface of the transparent conductive film layer 304 by magnetron sputtering to a thickness of 200 to 500 nm.
  • a photoresist 400 is formed on the surface of the source/drain metal film layer 303, and can be exposed once by the above-mentioned two-color reticle to form a third photoresist completely reserved region after development.
  • the domain C (the thickness of the photoresist 401 is 1 to 3 ⁇ m)
  • the second photoresist portion retaining region D (the thickness of the photoresist 402 is 0.5 to 1.5 ⁇ m)
  • the third photoresist completely removed region E is the third photoresist completely removed region E.
  • the third photoresist completely remaining region C corresponds to the source 106 and the drain 107 to be formed and the pattern of the data line (not shown) connected to the source 106; the second photoresist portion retains the region D Corresponding to the pattern of the pixel electrode 108; the third photoresist completely removed region E corresponds to the remaining region of the surface of the source/drain metal film layer 303.
  • the third photoresist completely removed region E includes a source to be formed on the surface of the transparent conductive film layer 304.
  • the photoresist 402 of the second photoresist portion remaining region D is removed by an ashing process, and the source/drain metal film layer 303 of the second photoresist portion remaining region D is etched.
  • the thickness of the photoresist 401 of the third photoresist completely remaining region C is thinned.
  • the photoresist 401 of the third photoresist completely remaining region C is peeled off, and finally the source conductive layer 1061, the source 106 located on the surface of the source conductive layer 1061, the pixel electrode 108, and A pattern of drain electrodes 107 to which pixel electrodes 108 are connected.
  • the pixel defining layer 109 is formed on the surface of the substrate on which the above structure is formed by the step S104, and the array substrate as shown in FIG. 13 is produced.
  • the array substrate can be used to form a low temperature polysilicon display panel of a bottom emission AMOLED.
  • the light of the display panel can be emitted downward (in the direction close to the surface of the base substrate 01). In this way, since the thin film transistor blocks a part of the light, the aperture ratio of the display panel is small. Therefore, the top emission type AMOLED display panel can be applied to a low resolution display device.
  • An embodiment of the present invention provides an array substrate, as shown in FIG. 10 or 13, including:
  • a source 106 electrically connected to the polysilicon active layer 102 through the first via 104;
  • a pixel electrode 108 electrically connected to the drain 107.
  • Embodiments of the present invention provide an array substrate.
  • the array substrate includes a base substrate, a gate formed on the base substrate, a gate insulating layer, a polysilicon active layer, a passivation layer formed on a surface of the polysilicon active layer, and a first via located on a surface of the passivation layer And a second via, a source electrically connected to the polysilicon active layer through the first via, a drain electrically connected to the polysilicon active layer through the second via, and a pixel electrode electrically connected to the drain.
  • only four patterning processes can be used in the process of fabricating the above-mentioned AMOLED array substrate, which effectively reduces the number of patterning processes, simplifies the process steps, reduces production errors, and improves production efficiency and quality.
  • the gate 100, the gate insulating layer 101, and the polysilicon active layer 102 may be sequentially located on the surface of the base substrate 01; and the patterns of the gate 100, the gate insulating layer 101, and the polysilicon active layer 102 are uniform. . In this way, the gate electrode 100, the gate insulating layer 101, and the polysilicon active layer 102 on the surface of the base substrate 01 can be fabricated by one patterning process, thereby simplifying the fabrication process, improving productivity, and product quality.
  • the embodiment of the present invention provides a display device, including any of the array substrates described above, having the same advantageous effects as the array substrate provided by the foregoing embodiments of the present invention, since the detailed structure of the array substrate has been made in the foregoing embodiment. A detailed description will not be repeated here.
  • the display device may be any product or component having a display function, such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
  • a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
  • Embodiments of the present invention provide a display device including an array substrate.
  • the array substrate includes a base substrate, a gate formed on the base substrate, a gate insulating layer, a polysilicon active layer, a passivation layer formed on a surface of the polysilicon active layer, and a first pass on the surface of the passivation layer Hole and second via.
  • the source is electrically connected to the polysilicon active layer through the first via
  • the drain is electrically connected to the polysilicon active layer through the second via.

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Abstract

一种阵列基板及其制作方法、显示装置。在衬底基板（10）上通过一次构图工艺形成包括栅极（100）、栅极绝缘层（101）、多晶硅有源层（102）的图案；在形成有上述图案的基板表面，形成钝化层（103），并在所述钝化层的表面通过一次构图工艺形成第一过孔（104）和第二过孔（105）的图案；在形成有上述图案的基板表面，通过一次构图工艺形成源极（106）、漏极（107）以及像素电极（108）的图案；其中，所述源极（106）通过所述第一过孔（104）与所述多晶硅有源层（102）电连接，所述漏极（107）通过所述第二过孔（105）与所述多晶硅有源层（102）电连接；形成有上述图案的基板表面通过一次构图工艺形成像素界定层（109）的图案。该方法减少了低温多晶硅AMOLED阵列基板制作过程中的掩模曝光工艺的次数。

Description

阵列基板及其制作方法、显示装置 技术领域
本发明实施例涉及阵列基板及其制作方法、显示装置。
背景技术
随着显示技术的急速进步，作为显示装置核心的半导体元件技术也随之得到了飞跃性的进步。对于现有的显示装置而言，有机发光二极管(Organic Light Emitting Diode，OLED)作为一种电流型发光器件，因其所具有的自发光、快速响应、宽视角和可制作在柔性衬底上等特点而越来越多地被应用于高性能显示领域当中。OLED按驱动方式可分为PMOLED(Passive Matrix Driving OLED，无源矩阵驱动有机发光二极管)和AMOLED(Active Matrix Driving OLED，有源矩阵驱动有机发光二极管)两种。
在AMOLED的构架中，可使用非晶硅、多晶硅、氧化物半导体或有机薄膜晶体管驱动。然而，采用现有技术在制作上述AMOLED阵列基板的过程中，通常需要多次应用构图工艺，例如8～9道掩模曝光工艺。这样一来，不仅工艺过程复杂，成本较高，而且繁琐的工艺步骤还会导致生产误差的不断叠加，使得AMOLED显示装置的质量难以保证。
发明内容
根据本发明的第一方面，提供一种阵列基板的制作方法，包括：
在衬底基板上通过一次构图工艺形成包括栅极、栅极绝缘层、多晶硅有源层的图案；
在形成有上述图案的基板表面，形成钝化层，并在所述钝化层的表面通过一次构图工艺形成第一过孔和第二过孔的图案；
在形成有上述图案的基板表面，通过一次构图工艺形成源极、漏极以及像素电极的图案；其中，所述源极通过所述第一过孔与所述多晶硅有源层电连接，所述漏极通过所述第二过孔与所述多晶硅有源层电连接；
在形成有上述图案的基板表面通过一次构图工艺形成像素界定层的图 案。
本发明实施例的另一方面，提供一种阵列基板，包括：
衬底基板；
形成于所述衬底基板上的栅极、栅极绝缘层、多晶硅有源层；
形成于所述多晶硅有源层表面的钝化层，以及位于所述钝化层表面的第一过孔和第二过孔；
通过所述第一过孔与所述多晶硅有源层电连接的源极；
通过所述第二过孔与所述多晶硅有源层电连接的漏极；
与所述漏极电连接的像素电极。
根据本发明的又一方面，提供一种显示装置，包括如上所述的任意一种阵列基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为已知阵列基板的结构示意图；
图2为本发明实施例提供的一种阵列基板的制作方法流程图；
图3a-图3e为本发明实施例提供的另一种阵列基板制备过程中的各步骤的结构示意图；
图4为本发明实施例提供的另一种阵列基板的制作方法流程图；
图5为本发明实施例提供的另一种阵列基板的制作方法流程图；
图6为本发明实施例提供的又一种阵列基板的制作方法流程图；
图7a-图7b为本发明实施例提供的又一种阵列基板制备过程中的各步骤的结构示意图；
图8为本发明实施例提供的又一种阵列基板的制作方法流程图；
图9a-图9c为本发明实施例提供的又一种阵列基板制备过程中的各步骤的结构示意图；
图10为本发明实施例提供的一种阵列基板的结构示意图；
图11为本发明实施例提供的又一种阵列基板的制作方法流程图；
图12a-图12d为本发明实施例提供的又一种阵列基板制备过程中的各步骤的结构示意图；
图13本发明实施例提供的另一种阵列基板的结构示意图。
具体实施方式
如图1所示，在采用多晶硅的AMOLED阵列基板中，由多晶硅制成的多晶硅有源层102位于缓冲层200的表面；上述多晶硅有源层102的表面依次具有栅极绝缘层101、栅极100、层间绝缘层201；源极106和漏极107通过位于层间绝缘层201表面的过孔与该多晶硅有源层102电连接，像素电极108通过位于钝化层103表面的过孔与漏极107电连接；像素电极108以及钝化层103的表面设置有像素界定层109。
然而，采用在制作上述AMOLED阵列基板的过程中，通常需要多次应用构图工艺，例如8～9道掩模曝光工艺。不仅工艺过程复杂，成本较高，而且繁琐的工艺步骤还会导致生产误差的不断叠加，使得AMOLED显示装置的质量难以保证。
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置 改变后，则该相对位置关系也可能相应地改变。
本发明实施例提供一种阵列基板的制作方法，如图2所示，包括：
S101、在如图3d所示的衬底基板10上，可以采用一次构图工艺形成包括栅极100、栅极绝缘层101、多晶硅有源层102的图案。
S102、如图7b所示，在形成有上述图案的基板表面，可以形成钝化层103，并在钝化层103的表面通过一次构图工艺形成第一过孔104和第二过孔105的图案。
S103、如图9c所示，在形成有上述图案的基板表面，可以通过一次构图工艺形成源极106、漏极107以及像素电极108的图案；其中，源极106通过第一过孔104与多晶硅有源层102电连接，漏极106通过第二过孔105与多晶硅有源层102电连接。
S104、如图10或图13所示，在形成有上述图案的基板表面，可以通过一次构图工艺形成像素界定层109的图案。
需要说明的是，在本发明中，构图工艺，指包括光刻工艺，或，包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明中所形成的结构选择相应的构图工艺。
本发明实施例提供一种阵列基板及其制作方法、显示装置。在制备上述阵列基板的过程中，可以通过一次构图工艺在衬底基板上形成包括栅极、栅极绝缘层、多晶硅有源层；再通过一次构图工艺形成位于钝化层表面的第一过孔和第二过孔的图案；又通过一次构图工艺形成源极、漏极以及像素电极；其中，源极、漏极分别通过第一过孔和第二过孔与多晶硅有源层电连接。最后，通过一次构图工艺形成像素界定层。这样一来，在AMOLED阵列基板的过程中只采用了四次构图工艺，有效减少了构图工艺的使用数量，简化工艺步骤，减小生产误差，提高了生产效率和质量。
在一个示例中，如图4所示，步骤S101包括：
S201、如图3a所示，在衬底基板10上覆盖缓冲层200。
例如，如图10所示，缓冲层200位于栅极100与衬底基板01之间，包括靠近栅极100一侧表面的第二材料层221和靠近衬底基板01一侧表面的第 一材料层220。
例如，第一材料层220由氮化硅(SiN)构成，厚度为50～100nm；第二材料层221由二氧化硅(SiO2)构成，厚度为100～400nm。这样一来，由氮化硅(SiN)构成的第一材料层220具有很强的扩散阻挡特性，可以抑制金属离子对于多晶硅有源层102的影响，并具有防水隔尘的作用。由二氧化硅(SiO2)构成的第二材料层221与多晶硅有源层102具有优良的界面，可以防止由氮化硅(SiN)构成的第一材料层220的自身缺陷对多晶硅有源层102的质量造成损害。
S202、如图3b所示，在缓冲层200的表面依次形成栅极金属薄膜层300、栅极绝缘薄膜层301以及多晶硅薄膜层302。
例如，首先，可以采用磁控溅射的方法在缓冲层200的表面沉积一层厚度为200～500nm的栅极金属薄膜层300。该栅极金属薄膜层300可以采用铝(Al)、铜(Cu)、钼(Mo)、钛(Ti)、铝钕合金(AlNd)中的至少一种金属材料构成，也可以采用钼/铝/钼(Mo/Al/Mo)或钛/铝/钛(Ti/Al/Ti)等多层金属复合薄膜。其中，金属材料铜(Cu)、钼(Mo)或者钼/铝/钼(Mo/Al/Mo)，由于其制作工艺成熟、简单在生产加工中比较常用。
然后，可采用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气象沉积)法，在栅极金属薄膜层300的表面上沉积一层栅极绝缘薄膜层301。例如，如图10所示，由栅极绝缘薄膜层301形成的栅极绝缘层101可以位于栅极100与多晶硅有源层102之间，包括靠近栅极100一侧表面的第一材料层220和靠近多晶硅有源层102一侧表面的第二材料层221。
例如，第一材料层220由氮化硅(SiN)构成，厚度为20～100nm；第二材料层221由二氧化硅(SiO2)构成，厚度为30～400nm。这样一来，由氮化硅(SiN)构成的第一材料层220具有很强的扩散阻挡特性，可以抑制金属离子对于多晶硅有源层102的影响。由二氧化硅(SiO2)构成的第二材料层221与多晶硅有源层102具有优良的界面，可以防止由氮化硅(SiN)构成的第一材料层220的自身缺陷对多晶硅有源层102的质量造成损害。
在一个示例中，在栅极绝缘薄膜层301的表面形成多晶硅薄膜层302的步骤，如图5所示，可以包括：
S301、在栅极绝缘薄膜层301的表面形成非晶硅(a-Si)薄膜，例如，可以通过化学气象沉积的方法(PECVD法)形成非晶硅(a-Si)薄膜。
例如，可以在由二氧化硅(SiO2)构成的第二材料层221表面形成非晶硅(a-Si)薄膜。
S302、对上述非晶硅(a-Si)薄膜进行脱氢工艺。
S303、对经过上述脱氢工艺的非晶硅(a-Si)薄膜采用结晶工艺，以形成多晶硅薄膜层302。例如，可以使用激光退火结晶、金属诱导结晶、固相结晶等方法。
这样一来，由于在结晶工艺之前对非晶硅(a-Si)薄膜进行脱氢工艺，从而可以防止结晶过程中，由于激光照射等原因，使得氢离子溢出而出现氢爆现象，造成形成后的多晶硅薄膜层302薄膜表面不平整，严重影响产品的质量。
S203、如图3c所示，在多晶硅薄膜层302的表面涂覆一层光刻胶400，通过双色调掩模版进行一次曝光，显影后形成第一光刻胶完全保留区域A(光刻胶401的厚度为1～3微米)，第一光刻胶部分保留区域(图中未示出，该区域的光刻胶的厚度为0.5～1微米)以及第一光刻胶完全去除区域B。第一光刻胶完全保留区域A对应待形成的栅极100、栅极绝缘层101以及多晶硅有源层102的图案。第一光刻胶部分保留区域对应与栅极100相连的栅线(图中未示出)的图案；上述第一光刻胶完全去除区域B对应多晶硅薄膜层302表面的其余区域，该第一光刻胶完全去除区域B未被光刻胶400覆盖。
需要说明的是，由于第一光刻胶完全保留区域A对应待形成的栅极100、栅极绝缘层101以及多晶硅有源层102的图案，因此通过构图工艺最终形成的栅极100、栅极绝缘层101以及多晶硅有源层102的图案一致。所以在多晶硅薄膜层302表面的对应除栅极100(或栅极绝缘层101或多晶硅有源层102)、栅线以外的区域可以为第一光刻胶完全去除区域B。
例如，在多晶硅薄膜层302的表面涂覆一层光刻胶400之前，可以采用稀释处理的氢氟酸对多晶硅薄膜层302进行清洗，降低多晶硅薄膜层302表面粗糙度。
需要说明的是，双色调掩模版为一种半透式掩模版，可以在多晶硅薄膜层302表面形成两种不同厚度的光刻胶400(第一光刻胶完全保留区域A的 光刻胶401、第一光刻胶部分保留区域的光刻胶)。该双色调掩模版可以包括：灰色调掩模版(Gray-tone mask)和半色调掩模版(Half-tone mask)。
S204、如图3d所示，刻蚀对应第一光刻胶完全去除区域B的多晶硅薄膜层302、栅极绝缘薄膜层301以及栅极金属薄膜层300。
例如，可以采用四氟化碳/氧气(CF4/O2)、三氟甲烷/氧气(CHF3/O2)或者六氟化硫/氧气(SF6/O2)等混合气体，通过等离子体或者电感耦合等离子方法对多晶硅薄膜层302进行刻蚀。
然后，采用四氟化碳(CF4)、四氟化碳/氧气(CF4/O2)、或者三氟甲烷/氧气(CHF3/O2)等气体，通过等离子体或者电感耦合等离子方法，刻蚀去除暴露的栅极绝缘薄膜层301，其中，由于栅极绝缘薄膜层301具有由二氧化硅(SiO2)构成的第二材料层221。因此，上述刻蚀气体的中可以不需要通入氧气(O2)或者可以通入含有较低流量的氧气(O2)。
最后，可以采用湿法刻蚀，或者干法刻蚀，如采用二氯化碳/三氯化硼(CCl2/BCl3)和四氟化碳/氧气(CF4/O2)等混合气体的电感耦合等离子体刻蚀工艺，对栅极金属薄膜层300进行刻蚀，以形成栅极100以及与该栅极100电连接的栅线。其中，由于干法刻蚀的精度较高，因此在制作高分辨率的显示面板时可以采用干法刻蚀工艺完成对栅极金属薄膜层300进行刻蚀；对于低分辨率的显示面板而言可以采用湿法刻蚀工艺完成对栅极金属薄膜层300进行刻蚀。
S205、去除第一光刻胶部分保留区域的光刻胶，并对第一光刻胶部分保留区域对应的多晶硅薄膜层302进行刻蚀。从而形成薄膜晶体管的多晶硅孤岛。
例如，使用等离子体灰化工艺去除较薄的光刻胶时，保留较厚的光刻胶401作为刻蚀阻挡层，在灰化过程中较薄的光刻胶去除，较厚的光刻胶401的厚度减薄。然后通过等离子体或者电感耦合等离子方法进行多晶硅薄膜层302的刻蚀，去除阵列栅线上覆盖的多晶硅薄膜层302。
S206、如图3e所示，对第一光刻胶完全保留区域A的光刻胶401进行剥离，最终形成栅极100、栅极绝缘层101以及栅线的图案。通过上述步骤S206，可以而使得预被制备成多晶硅有源层102的多晶硅薄膜层302的表面露出。
S207、对对应第一光刻胶完全保留区域A的多晶硅薄膜层302进行离子掺杂工艺，以形成多晶硅有源层102。这样一来，可以形成低阻抗的源漏电极接触区，以提高薄膜晶体管的导通性能。
需要说明的是，在对对应第一光刻胶完全保留区域A的多晶硅薄膜层302(即薄膜晶体管的多晶硅孤岛)进行离子掺杂的过程中，可以通过掩模板对除了上述多晶硅孤岛以外区域进行保护，以避免离子掺杂过程中对上述区域造成不利的影响。
在一个示例中，上述步骤S102，如图6所示，可以包括：
S401、如图7a所示，在多晶硅有源层102的表面形成钝化层103；例如，钝化层103由含氢元素的氮化硅(SiN)薄膜构成。其厚度为200～500nm。
S402、采用退火工艺对钝化层103进行退火处理。上述退火工艺包括快速热退火或采用热处理炉进行退火。
这样一来，由于钝化层103以及栅极绝缘层101均含有氮化硅(SiN)，并且钝化层103中含氢元素。因此可以利用氮化硅(SiN)实现多晶硅有源层102内部以及多晶硅有源层102界面的氢化处理。通过上述氢化处理可以去除多晶硅有源层102中的悬挂键，从而提升迁移率，降低阈值电压的漂移。
S403、如图7b所示，在经过上述退火处理的钝化层103表面，通过一次构图工艺(例如，一次掩模曝光工艺)形成第一过孔104和第二过孔105的图案。
在一个示例中，上述步骤S103，如图8所示，包括：
S501、如图9a所示，在钝化层103的表面，依次形成源漏金属薄膜层303、透明导电薄膜层304。
例如，首先，可以采用磁控溅射的方法在钝化层103的表面沉积一层厚度为200～500nm的源漏金属薄膜层303。优选的，该源漏金属薄膜层303可以采用铝(Al)、铜(Cu)、钼(Mo)、钛(Ti)、铝钕合金(AlNd)中的至少一种金属材料构成，也可以采用钼/铝/钼(Mo/Al/Mo)或钛/铝/钛(Ti/Al/Ti)等多层金属薄膜。例如，金属材料铜(Cu)、钼(Mo)或者钼/铝/钼(Mo/Al/Mo)，由于其制作工艺成熟、简单在生产加工中比较常用。
然后，采用磁控溅射在源漏金属薄膜层303的表面沉积一层透明导电薄膜层304，可以采用氧化铟锡/银/氧化铟锡(ITO/Ag/ITO)、氧化铟锌/银 (IZO/Ag)等复合薄膜。例如，ITO厚度为10～50nm，Ag金属薄膜厚度为20～100nm。
S502、如图9b所示，在透明导电薄膜层304的表面形成光刻胶400，通过一次曝光、显影工艺，形成对应待形成的源极106和漏极107图案的第二光刻胶完全保留区域G，以及对应透明导电薄膜层304表面其余区域的第二光刻胶完全去除区域F。
例如，源极和漏极之间存在间隙，为形成源极和漏极之间的间隙，因此上述第二光刻胶完全去除区域F包括在透明导电薄膜层304的表面对应待形成的源极106与漏极107之间的间隙区域。
S503、如图9c所示，对对应第二光刻胶完全去除区域F的透明导电薄膜层304、源漏金属薄膜层303进行刻蚀。
S504、将第二光刻胶完全保留区域G的光刻胶剥离，以形成源极106、漏极107以及位于源极106表面的源极导电层1061、位于漏极107表面的像素电极108。需要说明的是，上述源极导电层1061可以去除。
这样一来，在形成上述结构的基板表面通过步骤S104形成像素界定层109，制作出如图10所述的阵列基板。该阵列基板可以用于形成顶发射式AMOLED的低温多晶硅显示面板。该显示面板的光线能够向上(远离衬底基板01表面的方向)发射出。因为，由源漏金属薄膜层303形成的源极106和漏极107可以对出射光进行反射，从而能够增加显示面板的开口率。所以顶发射式AMOLED显示面板可以应用于高分辨率的显示装置中。
在一个示例中，上述步骤S103，如图11所示，可以包括：
S601、如图12a所示，在钝化层103的表面，依次形成透明导电薄膜层304、源漏金属薄膜层303。
首先，采用磁控溅射在钝化层103的表面沉积一层透明导电薄膜层304，可以采用氧化铟锡/银/氧化铟锡(ITO/Ag/ITO)、氧化铟锌/银(IZO/Ag)等复合薄膜。厚度为20～100nm。
然后，采用磁控溅射的方法在透明导电薄膜层304的表面沉积一层源漏金属薄膜层303，厚度为200～500nm。
S602、如图12b所示，在源漏金属薄膜层303的表面形成光刻胶400，可以通过上述双色掩模版进行一次曝光，显影后形成第三光刻胶完全保留区 域C(光刻胶401的厚度为1～3微米)，第二光刻胶部分保留区域D(光刻胶402的厚度为0.5～1.5微米)以及第三光刻胶完全去除区域E。第三光刻胶完全保留区域C对应待形成的源极106和漏极107以及与该源极106相连接的数据线(图中未示出)的图案；第二光刻胶部分保留区域D对应像素电极108的图案；第三光刻胶完全去除区域E对应源漏金属薄膜层303表面的其余区域。
例如，源极和漏极之间存在间隙，为形成源极和漏极之间的间隙，因此上述第三光刻胶完全去除区域E包括在透明导电薄膜层304的表面对应待形成的源极106与漏极107之间的间隙区域。
S603、如图12c所示，刻蚀对应第三光刻胶完全去除区域E的透明导电薄膜层304、源漏金属薄膜层303。
S604、如图12c所示，通过灰化工艺去除第二光刻胶部分保留区域D的光刻胶402，并对第二光刻胶部分保留区域D的源漏金属薄膜层303进行刻蚀。例如，在灰化的过程中，第三光刻胶完全保留区域C的光刻胶401的厚度减薄。
S605、如图12d所示，将第三光刻胶完全保留区域C的光刻胶401剥离，最终形成源极导电层1061、位于源极导电层1061表面的源极106、像素电极108以及与像素电极108相连接的漏极107的图案。
这样一来，在形成上述结构的基板表面通过步骤S104形成像素界定层109，制作出如图13所述的阵列基板。该阵列基板可以用于形成底发射式AMOLED的低温多晶硅显示面板。该显示面板的光线能够向下(靠近衬底基板01表面的方向)发射出。这样一来，由于薄膜晶体管将一部分光线遮挡住，所以显示面板的开口率较小。因此顶发射式AMOLED显示面板可以应用于低分辨率的显示装置中。
本发明实施例提供一种阵列基板，如图10或13所示，包括：
衬底基板10；
形成于衬底基板10上的栅极100、栅极绝缘层101、多晶硅有源层102；
形成于多晶硅有源层102表面的钝化层103，以及位于钝化层103表面的第一过孔104和第二过孔105。
通过第一过孔104与多晶硅有源层102电连接的源极106；
通过第二过孔105与多晶硅有源层102电连接的漏极107。
与漏极107电连接的像素电极108。
本发明实施例提供一种阵列基板。该阵列基板包括衬底基板、形成于衬底基板上的栅极、栅极绝缘层、多晶硅有源层、形成于多晶硅有源层表面的钝化层，位于钝化层表面的第一过孔和第二过孔、通过第一过孔与多晶硅有源层电连接的源极、通过第二过孔与多晶硅有源层电连接的漏极以及与漏极电连接的像素电极。这样一来，在制作上述AMOLED阵列基板的过程中可以只采用了四次构图工艺，有效减少了构图工艺的使用数量，简化工艺步骤，减小生产误差，提高了生产效率和质量。
在一个示例中，栅极100、栅极绝缘层101、多晶硅有源层102可以依次位于衬底基板01的表面；并且，栅极100、栅极绝缘层101以及多晶硅有源层102的图案一致。这样一来，在可以通过一次构图工艺制作出位于衬底基板01的表面的栅极100、栅极绝缘层101以及多晶硅有源层102，从而能够简化制作工艺，提高生产率和产品质量。
本发明实施例提供一种显示装置，包括如上所述的任意一种阵列基板，具有与本发明前述实施例提供的阵列基板相同的有益效果，由于阵列基板的详细结构已在前述实施例中做了详细的描述，此处不再赘述。
在本发明实施例中，显示装置，例如可以为液晶显示器、液晶电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。
本发明实施例提供一种显示装置，包括阵列基板。该阵列基板包括衬底基板、形成于衬底基板上的栅极、栅极绝缘层、多晶硅有源层、形成于多晶硅有源层表面的钝化层，以及位于钝化层表面的第一过孔和第二过孔。其中，源极通过第一过孔与多晶硅有源层电连接，漏极通过第二过孔与多晶硅有源层电连接。这样一来，在制作上述AMOLED阵列基板的过程中可以只采用了四次构图工艺，有效减少了构图工艺的使用数量，简化工艺步骤，减小生产误差，提高了生产效率和质量。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请基于并且要求于2014年6月30日递交的中国专利申请第201410308003.1号的优先权，在此全文引用上述中国专利申请公开的内容。

Claims (13)

  1. 一种阵列基板的制作方法，包括：
    在衬底基板上通过一次构图工艺形成包括栅极、栅极绝缘层、多晶硅有源层的图案；
    在形成有上述图案的基板表面，形成钝化层，并在所述钝化层的表面通过一次构图工艺形成第一过孔和第二过孔的图案；
    在形成有上述图案的基板表面，通过一次构图工艺形成源极、漏极以及像素电极的图案；其中，所述源极通过所述第一过孔与所述多晶硅有源层电连接，所述漏极通过所述第二过孔与所述多晶硅有源层电连接；
    在形成有上述图案的基板表面通过一次构图工艺形成像素界定层的图案。
  2. 根据权利要求1所述的阵列基板的制作方法，其中所述在衬底基板上形成栅极、栅极绝缘层、多晶硅有源层的图案的步骤包括：
    在所述衬底基板上覆盖缓冲层；
    在所述缓冲层的表面依次形成栅极金属薄膜层、栅极绝缘薄膜层以及多晶硅薄膜层；
    在所述多晶硅薄膜层的表面涂覆一层光刻胶，通过一次曝光显影工艺后形成第一光刻胶完全保留区域、第一光刻胶部分保留区域和第一光刻胶完全去除区域，所述第一光刻胶完全保留区域对应待形成的所述栅极、所述栅极绝缘层以及所述多晶硅有源层的图案，所述第一光刻胶部分保留区域对应与所述栅极相连的栅线的图案，所述第一光刻胶完全去除区域对应所述多晶硅薄膜层表面的其余区域；
    刻蚀对应所述第一光刻胶完全去除区域的所述多晶硅薄膜层、所述栅极绝缘薄膜层以及所述栅极金属薄膜层；
    去除所述第一光刻胶部分保留区域的光刻胶，并对所述第一光刻胶部分保留区域对应的所述多晶硅薄膜层进行刻蚀；
    对所述第一光刻胶完全保留区域的光刻胶进行剥离，最终形成所述栅极、所述栅极绝缘层以及所述栅线的图案；
    对对应所述第一光刻胶完全保留区域的所述多晶硅薄膜层进行离子掺杂 工艺，以形成所述多晶硅有源层的图案。
  3. 根据权利要求2所述的阵列基板的制作方法，其中
    所述栅极绝缘层位于所述栅极与所述多晶硅有源层之间，包括靠近所述栅极一侧表面的第二材料层和靠近所述多晶硅有源层一侧表面的第一材料层；
    所述缓冲层位于所述栅极与所述衬底基板之间，包括靠近所述栅极一侧表面的所述第一材料层和靠近所述衬底基板一侧表面的所述第二材料层。
  4. 根据权利要求3所述的阵列基板的制作方法，其中所述第一材料层由氮化硅构成；所述第二材料层由二氧化硅构成。
  5. 根据权利要求2所述的阵列基板的制作方法，其中在所述栅极绝缘薄膜层的表面形成所述多晶硅薄膜层的步骤包括：
    在所述栅极绝缘薄膜层的表面形成非晶硅薄膜；
    对所述非晶硅薄膜进行脱氢工艺；
    对经过所述脱氢工艺的所述非晶硅薄膜采用结晶工艺，以形成所述多晶硅薄膜层。
  6. 根据权利要求2所述的阵列基板的制作方法，其中所述在形成有上述图案的基板表面，形成钝化层，并在所述钝化层的表面形成第一过孔和第二过孔的步骤包括：
    在所述多晶硅有源层的表面形成所述钝化层；其中，所述钝化层由含氢元素的氮化硅薄膜构成；
    采用退火工艺对所述钝化层进行退火处理；
    在经过所述退火处理的所述钝化层表面，通过一次构图工艺形成所述第一过孔和所述第二过孔的图案。
  7. 根据权利要求6所述的阵列基板的制作方法，其中所述在形成有上述图案的基板表面形成源极、漏极以及像素电极的图案的步骤包括：
    在所述钝化层的表面，依次形成源漏金属薄膜层、透明导电薄膜层；
    在所述透明导电薄膜层的表面形成所述光刻胶，通过一次曝光显影工艺，在所述透明导电薄膜层的表面形成对应待形成的所述源极和所述漏极图案的第二光刻胶完全保留区域，以及对应所述透明导电薄膜层表面其余区域的第二光刻胶完全去除区域；
    对对应所述第二光刻胶完全去除区域的所述透明导电薄膜层、所述源漏金属薄膜层进行刻蚀；
    将所述第二光刻胶完全保留区域的光刻胶剥离，最终形成所述源极、所述漏极以及位于所述源极表面的源极导电层、位于所述漏极表面的所述像素电极。
  8. 根据权利要求6所述的阵列基板的制作方法，其中所述在形成有上述图案的基板表面形成源极、漏极以及像素电极的图案的步骤包括：
    在所述钝化层的表面，依次形成所述透明导电薄膜层、所述源漏金属薄膜层；
    在所述源漏金属薄膜层的表面形成所述光刻胶，通过一次曝光，显影工艺形成第三光刻胶完全保留区域、第二光刻胶部分保留区域以及第三光刻胶完全去除区域，所述第三光刻胶完全保留区域对应待形成的所述源极和所述漏极的图案；所述第二光刻胶部分保留区域对应所述像素电极的图案；所述第三光刻胶完全去除区域对应所述源漏金属薄膜层表面的其余区域；
    刻蚀对应所述第三光刻胶完全去除区域的所述透明导电薄膜层、所述源漏金属薄膜层；
    去除所述第二光刻胶部分保留区域的光刻胶，并对所述第二光刻胶部分保留区域的所述源漏金属薄膜层进行刻蚀；
    将所述第三光刻胶完全保留区域的所述光刻胶剥离，最终形成所述源极导电层、位于所述源极导电层表面的源极、像素电极以及与所述像素电极相连接的所述漏极的图案。
  9. 根据权利要求1-8任一项所述的阵列基板的制作方法，其中所述栅极金属薄膜层和所述源漏金属薄膜层均由铝、钼、铜、钛中的一种或多种构成。
  10. 根据权利要求2所述的阵列基板的制作方法，其中所述在所述多晶硅薄膜层的表面涂覆一层光刻胶的步骤之前，所述方法还包括：
    采用稀释处理的氢氟酸对多晶硅薄膜层的表面进行清洗。
  11. 一种阵列基板，包括：
    衬底基板；
    形成于所述衬底基板上的栅极、栅极绝缘层、多晶硅有源层；
    形成于所述多晶硅有源层表面的钝化层，以及位于所述钝化层表面的第 一过孔和第二过孔；
    通过所述第一过孔与所述多晶硅有源层电连接的源极；
    通过所述第二过孔与所述多晶硅有源层电连接的漏极；和
    与所述漏极电连接的像素电极。
  12. 根据权利要求11所述的阵列基板，其中所述栅极、所述栅极绝缘层、所述多晶硅有源层依次位于所述衬底基板的表面；并且，所述栅极、所述栅极绝缘层以及所述多晶硅有源层的图案一致。
  13. 一种显示装置，包括权利要求11或12所述的阵列基板。
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