WO2019169820A1 - 高精度时间同步方法 - Google Patents

高精度时间同步方法 Download PDF

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WO2019169820A1
WO2019169820A1 PCT/CN2018/095822 CN2018095822W WO2019169820A1 WO 2019169820 A1 WO2019169820 A1 WO 2019169820A1 CN 2018095822 W CN2018095822 W CN 2018095822W WO 2019169820 A1 WO2019169820 A1 WO 2019169820A1
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time
node
time synchronization
disturbance
nodes
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PCT/CN2018/095822
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French (fr)
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华楠
罗瑞杰
郑小平
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清华大学
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0673—Clock or time synchronisation among packet nodes using intermediate nodes, e.g. modification of a received timestamp before further transmission to the next packet node, e.g. including internal delay time or residence time into the packet
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/004—Synchronisation arrangements compensating for timing error of reception due to propagation delay
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0697—Synchronisation in a packet node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/001—Synchronization between nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/0055—Synchronisation arrangements determining timing error of reception due to propagation delay
    • H04W56/0065—Synchronisation arrangements determining timing error of reception due to propagation delay using measurement of signal travel time
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W24/00—Supervisory, monitoring or testing arrangements
    • H04W24/04—Arrangements for maintaining operational condition

Definitions

  • the present invention relates to the field of network communication technologies, and in particular, to a high-precision time synchronization method.
  • the nanosecond time synchronization accuracy is basically based on accurate phase discrimination or similar technology.
  • the hardware implementation is complicated, the cost is high, the synchronization distance is short, the network is difficult, and it is difficult to implement the large-scale network time synchronization system in a short time. Due to the digital logic, the existing network time synchronization technology cannot exceed the clock resolution, resulting in an overall network time synchronization accuracy of sub-microsecond or lower.
  • the existing network time synchronization is based on the IEEE 1588 synchronization protocol, and the master-slave synchronization structure is less robust, and the failure of the upstream node or link in the synchronization path will affect the synchronization accuracy of the downstream node. Once the clock source node fails or is attacked, the time synchronization network will be paralyzed and the network is invulnerable.
  • the present invention aims to solve at least one of the above technical problems.
  • the first object of the present invention is to provide a high-precision time synchronization method which can eliminate the correlation of multiple synchronization result errors, and further compensate the introduced disturbance amount by statistical average method, and reduce the clock resolution by the synchronization node.
  • the synchronization error caused by insufficient rate can achieve nanosecond-level time synchronization accuracy.
  • a second object of the present invention is to provide an apparatus.
  • a third object of the present invention is to provide a nonvolatile computer storage medium.
  • an embodiment of the first aspect of the present invention provides a high-precision time synchronization method, including the following steps: S1: Introducing a periodic transmission time disturbance between any two nodes in a time synchronization network, defining a node i to a node
  • the periodic transmission time perturbation introduced between j is a function f i,j (t) of time t, and the maximum value of the disturbance is greater than or equal to the clock period T j of the receiving node j , wherein the perturbation period is P i , j , the mean of the disturbance during the disturbance period
  • the message reception time is recorded as t 1 , t 2 , t 3 , t 4
  • the high-precision time synchronization method according to the above embodiment of the present invention may further have the following additional technical features:
  • the periodic transmission time perturbation size is an arithmetic progression
  • the time synchronization node transmits pulses to synchronize with other nodes
  • the transmit and receive clock cycles of node 1 are denoted as T s1 and T r1 , respectively
  • the transmit and receive clock cycles of node 2 are denoted as T s2 and T, respectively.
  • R2 is equivalent to introducing the periodic transmission time disturbance between nodes, and the variation period of the two-way transmission of the disturbance is the least common multiple of T s1 and T r2 and the least common multiple of T s2 and T r1 respectively, and the mean value of the disturbance is calculated. Then, the time correction amount calculation is performed in accordance with the method of the step S1 to the step S2.
  • the method further includes: defining a time synchronization error upper limit requirement as Error max , and then selecting, by frequency selection, the following inequality T r /2n r ⁇ Error max .
  • the method further includes: defining a fault waiting time threshold F th , when the communication failure time between the node i and its neighboring node j is greater than F th , determining that the node i is no longer adjacent to the node j, and the node j is from the Removed from the adjacent node set ⁇ N i ⁇ .
  • the method further includes: the time synchronization node sends a data packet with a timestamp to synchronize with other nodes, and the receiving end divides the received data packet signal into two paths, respectively, by using a data packet parsing module and a timestamp generating module.
  • Receiving wherein a fixed length delay line is added before the timestamp generating module to ensure that the data packet parsing module can complete data packet parsing within a delay time; the data packet parsing module adopts the same frequency as when the data packet is sent.
  • the clock C1 parses the packet header, and its period is denoted as T s .
  • an enable control signal is generated and sent to the time stamp generation module; the time stamp generation module Using a clock C2 different from the C1 frequency, the period is denoted as T r .
  • the enable control signal sent by the packet parsing module is received, time stamping is performed on the data packet to arrive at the time stamp generating module.
  • the correlation of the multiple synchronization result errors can be eliminated, and the introduced disturbance amount is compensated by the statistical average method, and the synchronization error caused by the insufficient clock resolution of the synchronization node is reduced.
  • the method has obvious advantages over the traditional IEEE 1588 and other traditional time synchronization methods, and can achieve nanosecond level time synchronization accuracy.
  • an embodiment of the second aspect of the present invention further provides an apparatus comprising: one or more processors; a memory; one or more programs, the one or more programs being stored in the memory
  • the high-precision time synchronization method of the above-described embodiment of the present invention is executed when executed by the one or more processors.
  • an embodiment of a third aspect of the present invention further provides a nonvolatile computer storage medium storing one or more programs when the one or more programs are used by a device When executed, the apparatus is caused to perform the high-precision time synchronization method of the above-described embodiment of the present invention.
  • FIG. 1 is a flow chart showing a high precision time synchronization method according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a high-precision time synchronization network fault processing state machine according to an embodiment of the present invention
  • FIG. 3 is a graph showing experimental results of time synchronization accuracy according to an embodiment of the present invention.
  • FIG. 4 is a block diagram showing the structure of a time synchronization by a data packet according to an embodiment of the present invention.
  • connection In the description of the present invention, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise explicitly defined and defined. Connected, or integrally connected; can be mechanical or electrical; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of the two components.
  • Connected, or integrally connected can be mechanical or electrical; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of the two components.
  • the specific meaning of the above terms in the present invention can be understood in a specific case by those skilled in the art.
  • Step S1 Introducing a periodic transmission time disturbance between any two nodes in the time synchronization network, and defining a periodic transmission time disturbance size introduced between the node i and the node j as a function f i,j (t) of the time t, and the perturbed
  • the maximum value is greater than or equal to the clock period T j of the receiving node j, wherein the disturbance period is P i,j , and the mean of the disturbance in the disturbance period
  • Step S2 When the nodes i, j are performing time synchronization, the two nodes send a time-stamped message to each other, and the message sending time of the node i, the message receiving time of the node j, the message sending time of the node j, and the message of the node i
  • the receiving times are recorded as t 1 , t 2 , t 3 , t 4 , respectively, and the mean values of the recorded times t 1 , t 2 , t 3 , t 4 are calculated in a perturbation period. Then the time correction of node j relative to node i is
  • f i,j (t) d ⁇ t,t ⁇ [0, P i,j ).
  • d 1ns/s
  • P i,j 10s
  • f i,j (t) is an arithmetic progression of 0ns to 9ns
  • the perturbation mean E i,j 4.5ns
  • the method further includes: the time synchronization node sends a pulse to synchronize with other nodes, and the transmit and receive clock cycles of the node 1 are respectively recorded as T s1 and T r1 , and the transmit and receive clocks of the node 2
  • the periods are denoted as T s2 and T r2 respectively , which is equivalent to introducing the periodic transmission time disturbance between nodes, and the variation period of the two-way transmission of the disturbance is the least common multiple of T s1 and T r2 and T s2 and T r1 respectively .
  • the least common multiple is calculated, and the time correction amount is calculated according to the method of the step S1 to the step S2 after calculating the mean value of the disturbance.
  • the method further includes: in a time synchronization network, setting a pulse transmission clock period of all the time synchronization nodes to T s and setting a reception clock period to T r , the time correction amount calculation is further simplified.
  • the method further includes: defining a time synchronization error upper limit requirement as Error max , and then selecting, by frequency selection, satisfying the following inequality T r /2n r ⁇ Error max .
  • Error max 0.1 ns
  • the method further includes: defining a neighboring node set ⁇ N i ⁇ of the node i , where a total of n nodes are included in the ⁇ N i ⁇ ; calculating the node i relative to the node j in each ⁇ N i ⁇ The time correction amount is Offset i,j ,j ⁇ N i ⁇ , then the final time correction amount of node i is
  • the method further includes: defining a fault waiting time threshold F th , and determining that the node i and the node j are no longer adjacent when the communication failure time between the node i and the neighboring node j is greater than F th j is removed from the set of adjacent nodes ⁇ N i ⁇ .
  • the method further includes: the time synchronization node sends a data packet with a time stamp to synchronize with other nodes, and the receiving end divides the received data packet signal into two paths, respectively, using the data packet parsing module and time.
  • the stamp generating module receives the fixed length delay line before the time stamp generating module to ensure that the data packet parsing module can complete the data packet parsing within the delay time; the data packet parsing module adopts the data packet
  • the clock C1 with the same frequency is used to parse the packet header, and the period is recorded as T s .
  • the timestamp generating module uses a clock C2 different from the C1 frequency, and its period is denoted as T r .
  • T r the period of the module and sends it to the node time data processor for data processing; the timestamp generated by the timestamp generation module After the calculated arrival time of the data packet, it changes the disturbance period T s and T r is the least common multiple calculated average disturbance correction amount of time.
  • FIG. 1 is a schematic flow chart of a high-precision space-time synchronization method according to an embodiment of the present invention, in which a pulse is transmitted between two nodes for synchronization.
  • the transmission pulse and the reception pulse use different clock frequencies such that the reception time recording error (the time difference between the reception time true value and the recorded value) in each synchronization process is different.
  • This approach is equivalent to introducing a perturbation in the transmission time, the perturbation period being the least common multiple of the two clock cycles of transmission and reception, and the mean of the perturbation amount over a perturbation period can be calculated.
  • a time correction amount that exceeds the resolution of the clock resolution can be obtained by simultaneously measuring the average value and compensating the disturbance amount in a disturbance period.
  • Figure 2 shows a high precision time synchronization network fault handling state machine.
  • a time synchronization node does not receive the synchronization pulse sent by the neighboring node at the expected time, its state machine transitions from the normal time synchronization state to the neighbor node monitoring state. If a synchronization pulse is received within the set fault waiting time threshold, it is determined that the fault has recovered and the state machine returns to the normal time synchronization state. If the synchronization pulse is not received within the set fault waiting time threshold, it is determined that the neighbor node is faulty, the state machine enters the state of changing the neighbor node, and the neighbor node database is updated. The network administrator actively deletes the neighbor node and also enables the state machine to enter the state of changing the neighbor node. After the neighbor node database update is completed, the state machine enters the time synchronization initialization state, and after the initialization is completed, it returns to the normal time synchronization state, and the node completes a fault processing.
  • Fig. 3 shows experimental results of a high precision time synchronization method of an embodiment of the present invention.
  • the experiment is based on a 4-node ring topology and is synchronized using the method of the present invention.
  • the pulse transmission and reception frequencies are 50 MHz and 52 MHz, respectively.
  • the clock signal of each node is input to the integrated frequency meter for picosecond time error measurement.
  • the results of the synchronization experiment show that the synchronization error of the proposed dual-frequency high-precision synchronization method is reduced from 9.58 ns to 0.17 ns and the synchronization accuracy is improved by more than 56 times compared with the conventional IEEE 1588 method, realizing nanosecond time synchronization.
  • FIG. 4 shows a node structure for time synchronization by data packets in the embodiment of the present invention.
  • the crystal oscillator signal is input to the clock phase locked loop together with the frequency synchronization signal from other nodes to complete the frequency synchronization of the node.
  • the clock phase-locked loop generates C1 and C2 clocks respectively for the packet parsing module and the timestamp generating module.
  • the data packet signal received by the node is divided into two paths, which are respectively received by using the data packet parsing module and the timestamp generating module, wherein a fixed length delay line is added before the timestamp generating module to ensure that the data packet is within the delay time.
  • the parsing module can complete packet parsing.
  • the packet parsing module parses the packet header by using the same clock C1 as the data packet transmission frequency, and its period is recorded as T s .
  • an enable control signal is sent to the time. Stamp generation module.
  • the timestamp generation module uses a clock C2 different from the C1 frequency, and its period is denoted as T r .
  • T r the period of time
  • the node data processor to the time stamp generating module After the node data processor to the time stamp generating module generates a time stamp packet arrival time, changes in the disturbance period T s and T r is the least common multiple calculated average disturbance according to the steps S1 to step S2 The method performs time correction calculations and completes the time synchronization of the node.
  • the system manager completes the system flow such as node initialization and fault handling.
  • the frequency synchronization signal output module outputs a frequency synchronization signal to achieve frequency synchronization with other nodes.
  • the synchronous packet output module uses the C1 clock frequency to output synchronous packets for time synchronization with other nodes.
  • the correlation of the multiple synchronization result errors can be eliminated, and the introduced disturbance amount is compensated by the statistical average method, and the synchronization caused by the insufficient clock resolution of the synchronization node is reduced.
  • this method has obvious advantages over the traditional IEEE 1588 and other traditional time synchronization methods, and can achieve nanosecond-level time synchronization accuracy.
  • the logic and/or steps represented in the schematic or otherwise described herein, for example, may be considered as an ordered list of executable instructions for implementing logical functions, and may be embodied in any computer readable medium, Used by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other system that can fetch instructions and execute instructions from an instruction execution system, apparatus, or device) Used for equipment.
  • an instruction execution system, apparatus, or device such as a computer-based system, a system including a processor, or other system that can fetch instructions and execute instructions from an instruction execution system, apparatus, or device
  • portions of the invention may be implemented in hardware, software, firmware or a combination thereof.
  • multiple steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system.
  • a suitable instruction execution system For example, if implemented in hardware, it can be implemented by any one or combination of the following techniques well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, with suitable combinational logic Gate circuit ASIC, Programmable Gate Array (PGA), Field Programmable Gate Array (FPGA), etc.
  • each functional unit in each embodiment of the present invention may be integrated into one processing module, or each unit may exist physically separately, or two or more units may be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or in the form of software functional modules.
  • the integrated modules, if implemented in the form of software functional modules and sold or used as stand-alone products, may also be stored in a computer readable storage medium.
  • the above mentioned storage medium may be a read only memory, a magnetic disk or an optical disk or the like.

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Abstract

本发明提出一种高精度时间同步方法，该方法对传统 IEEE 1588 网络时间同步协议进行改进，在时间同步网络中任意两节点间引入周期性传输时间扰动，该扰动可以通过改变传输路径或收发端使用不同频率的时钟引入时钟相位扰动来实现。该方法可以消除多次同步结果误差的相关性，并进而通过统计平均的方法补偿引入的扰动量，降低由同步节点时钟分辨率不足导致的同步误差。本发明较现有 IEEE 1588 等传统时间同步方法有明显优势，能够实现纳秒级的时间同步精度。

Description

高精度时间同步方法
相关申请的交叉引用
本申请要求清华大学于2018年3月8日提交的、发明名称为“高精度时间同步方法”的、中国专利申请号为“201810191208.4”的优先权。
技术领域
本发明涉及网络通信技术领域，特别涉及一种高精度时间同步方法。
背景技术
目前，实现纳秒级时间同步精度基本采用精确鉴相或类似技术，其硬件实现复杂，成本高昂，同步距离短，网络化难度大，短时间内难以实用于大规模网络时间同步***。现有网络时间同步技术由于基于数字逻辑，其同步精度无法突破时钟分辨率，导致整体网络时间同步精度在亚微秒级或更低。
此外，现有网络时间同步基于IEEE 1588同步协议，其主从式的同步结构鲁棒性较低，同步路径中的上游节点或链路发生故障将影响下游节点的同步精度。一旦时钟源节点出现故障或被攻击，时间同步网将陷于瘫痪，网络抗毁性低。
发明内容
本发明旨在至少解决上述技术问题之一。
为此，本发明的第一个目的在于提出一种高精度时间同步方法，可以消除多次同步结果误差的相关性，并进而通过统计平均的方法补偿引入的扰动量，降低由同步节点时钟分辨率不足导致的同步误差，能够实现纳秒级的时间同步精度。
本发明的第二个目的在于提供一种设备。
本发明的第三个目的在于提供一种非易失性计算机存储介质。
为了实现上述目的，本发明第一方面的实施例提出了一种高精度时间同步方法，包括以下步骤：S1：在时间同步网络中任意两节点间引入周期性传输时间扰动，定义节点i到节点j间引入的所述周期性传输时间扰动大小为时间t的函数f i,j(t)，且扰动的最大值大于或等于接收节点j的时钟周期T j，其中，扰动周期为P i,j，扰动在所述扰动周期内的均值为
Figure PCTCN2018095822-appb-000001
S2：所述节点i,j在进行时间同步时，两节点互相发送带有时间戳的 消息，将节点i的消息发送时间、节点j的消息接收时间、节点j的消息发送时间和节点i的消息接收时间分别记录为t 1,t 2,t 3,t 4，并在一个所述扰动周期内，计算出记录的时间t 1,t 2,t 3,t 4的均值
Figure PCTCN2018095822-appb-000002
则节点j相对于节点i的时间修正量为
Figure PCTCN2018095822-appb-000003
另外，根据本发明上述实施例的高精度时间同步方法还可以具有如下附加的技术特征：
在一些示例中，所述周期性传输时间扰动大小为等差数列，扰动差值为d，表示为：f i,j(t)＝d·t,t∈[0,P i,j)。
在一些示例中，所述周期性传输时间扰动大小为随机数列，表示为：f i,j(t)＝random(t),t∈[0,P i,j)。
在一些示例中，所述时间同步节点发送脉冲与其它节点进行同步，节点1的发送和接收时钟周期分别记为T s1和T r1，节点2的发送和接收时钟周期分别记为T s2和T r2，等效于在节点间引入所述周期性传输时间扰动，双向传输所述扰动的变化周期分别为T s1和T r2的最小公倍数及T s2和T r1的最小公倍数，计算出扰动的均值后按照所述步骤S1至步骤S2的方法进行时间修正量计算。
在一些示例中，还包括：定义n s1,n s2,n r1,n r2为T s1,T s2和T r1,T r2之间的最简整数比，即n s1:n r2＝T s1:T r2,n s2:n r1＝T s2:T r1；定义i节点发出的第k个脉冲到达j节点的时刻与j节点接收时钟下一个上升沿间的时间间隔为
Figure PCTCN2018095822-appb-000004
则计算得到的时间修正量为：
Figure PCTCN2018095822-appb-000005
在一些示例中，进一步包括：通过选取T s1,T s2,T r1,T r2使得n r1>>1,n r2>>1时，所述时间修正量计算可以简化为
Figure PCTCN2018095822-appb-000006
在一些示例中，进一步包括：在时间同步网络中，将所有所述时间同步节点的脉冲发送时钟周期设为T s，接收时钟周期设为T r，则时间修正量计算进一步简化为
Figure PCTCN2018095822-appb-000007
在一些示例中，还包括：定义时间同步误差上限要求为Error max，则需要通过频率选取 满足如下不等式T r/2n r<Error max。
在一些示例中，还包括：定义节点i的相邻节点集合{N i}，{N i}中共包含n个节点；计算节点i相对于每一个{N i}中的节点j的时间修正量为Offset i,j,j∈{N i}，则节点i最终的时间修正量为
Figure PCTCN2018095822-appb-000008
在一些示例中，还包括：定义故障等待时间阈值F th，当节点i与其相邻节点j间通讯失效时间大于F th时，认定节点i与节点j不再相邻，将节点j从所述相邻节点集合{N i}中移除。
在一些示例中，还包括：所述时间同步节点发送含有时间戳的数据包与其它节点进行同步，接收端将收到的数据包信号分成两路分别使用数据包解析模块及时间戳生成模块进行接收，其中在所述时间戳生成模块之前加入定长延时线，保证在延时时间内所述数据包解析模块能够完成数据包解析；所述数据包解析模块采用与数据包发送时频率相同的时钟C1对包头进行解析，其周期记为T s，当解析出所收到的数据包为时间同步包时，生成一个使能控制信号发送给所述时间戳生成模块；所述时间戳生成模块使用与C1频率不同的时钟C2，其周期记为T r，当收到所述数据包解析模块发送的使能控制信号时，对该数据包打时间戳记录下其到达所述时间戳生成模块的时间，并发送给节点时间数据处理器进行数据处理；将所述时间戳生成模块生成的时间戳作为数据包到达时间，所述扰动的变化周期为T s和T r的最小公倍数，计算出扰动的均值后按照所述步骤S1至步骤S2的方法进行时间修正量计算。
根据本发明实施例的高精度时间同步方法，可以消除多次同步结果误差的相关性，并进而通过统计平均的方法补偿引入的扰动量，降低由同步节点时钟分辨率不足导致的同步误差，该方法较现有IEEE 1588等传统时间同步方法有明显优势，能够实现纳秒级的时间同步精度。
为了实现上述目的，本发明第二方面的实施例还提供了一种设备，包括：一个或者多个处理器；存储器；一个或者多个程序，所述一个或者多个程序存储在所述存储器中，当被所述一个或者多个处理器执行时，执行本发明上述实施例的高精度时间同步方法。
为了实现上述目的，本发明第三方面的实施例的还提供一种非易失性计算机存储介质，所述计算机存储介质存储有一个或者多个程序，当所述一个或者多个程序被一个设备执行时，使得所述设备执行本发明上述实施例的高精度时间同步方法。
本发明的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
附图说明
本发明的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：
图1是根据本发明一个实施例的高精度时间同步方法的流程示意图；
图2是根据本发明一个实施例的高精度时间同步网故障处理状态机示意图；
图3是根据本发明一个具体实施例的时间同步精度实验结果图；
图4是根据本发明一个具体实施例的通过数据包进行时间同步的节点结构示意图。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
以下结合附图描述根据本发明实施例的高精度时间同步方法。
根据本发明实施例的高精度时间同步方法，包括以下步骤：
步骤S1：在时间同步网络中任意两节点间引入周期性传输时间扰动，定义节点i到节点j间引入的周期性传输时间扰动大小为时间t的函数f i,j(t)，且扰动的最大值大于或等于接收节点j的时钟周期T j，其中，扰动周期为P i,j，扰动在扰动周期内的均值为
Figure PCTCN2018095822-appb-000009
步骤S2：节点i,j在进行时间同步时，两节点互相发送带有时间戳的消息，将节点i的消息发送时间、节点j的消息接收时间、节点j的消息发送时间和节点i的消息接收时间分别记录为t 1,t 2,t 3,t 4，并在一个扰动周期内，计算出记录的时间t 1,t 2,t 3,t 4的均值
Figure PCTCN2018095822-appb-000010
则节点j相对于节点i的时间修正量为
Figure PCTCN2018095822-appb-000011
在本发明的一个实施例中，上述的周期性传输时间扰动大小例如可以为等差数列，扰动差值为d，表示为：f i,j(t)＝d·t,t∈[0,P i,j)。例如，当d＝1ns/s,P i,j＝10s,每秒进行1次同步时，则f i,j(t)为0ns到9ns的等差数列，扰动均值E i,j＝4.5ns，代入时间修正量公式后即可得到精准的同步结果。
在本发明的另一个实施例中，上述的周期性传输时间扰动大小例如也可以为随机数列，表示为：f i,j(t)＝random(t),t∈[0,P i,j)。例如，当P i,j＝4s,每秒进行1次同步时，则随机生成的f i,j(t)可以为f i,j(0)＝0,f i,j(1)＝6,f i,j(2)＝4,f i,j(3)＝2，扰动均值E i,j＝3ns，代入时间修正量公式后即可得到精准的同步结果。
进一步地，在本发明的一个实施例中，还包括：时间同步节点发送脉冲与其它节点进行同步，节点1的发送和接收时钟周期分别记为T s1和T r1，节点2的发送和接收时钟周期分别记为T s2和T r2，等效于在节点间引入所述周期性传输时间扰动，双向传输所述扰动的变化周期分别为T s1和T r2的最小公倍数及T s2和T r1的最小公倍数，计算出扰动的均值后按照所述步骤S1至步骤S2的方法进行时间修正量计算。
进一步地，在本发明的一个实施例中，还包括：定义n s1,n s2,n r1,n r2为T s1,T s2和T r1,T r2之间的最简整数比，即n s1:n r2＝T s1:T r2,n s2:n r1＝T s2:T r1；定义i节点发出的第k个脉冲到达j节点的时刻与j节点接收时钟下一个上升沿间的时间间隔为
Figure PCTCN2018095822-appb-000012
则计算得到的时间修正量为：
Figure PCTCN2018095822-appb-000013
在本发明的一个实施例中，还包括：通过选取T s1,T s2,T r1,T r2使得n r1>>1,n r2>>1时，所述时间修正量计算可以简化为
Figure PCTCN2018095822-appb-000014
例如，T r1＝10ns， T r2＝9.9ns，则n r1＝100>>1,n r2＝99>>1，即可采用简化后的时间修正量公式。
在本发明的一个实施例中，还包括：在时间同步网络中，将所有所述时间同步节点的脉冲发送时钟周期设为T s，接收时钟周期设为T r，则时间修正量计算进一步简化为
Figure PCTCN2018095822-appb-000015
在本发明的一个实施例中，还包括：定义时间同步误差上限要求为Error max，则需要通过频率选取满足如下不等式T r/2n r<Error max。例如，Error max＝0.1ns，在发送时钟周期确定为T s＝10ns时，可以设置接收时钟T r＝9.9ns，则n s＝100,n r＝99，T r/2n r＝0.05ns<Error max＝0.1ns。
在本发明的一个实施例中，还包括：定义节点i的相邻节点集合{N i}，{N i}中共包含n个节点；计算节点i相对于每一个{N i}中的节点j的时间修正量为Offset i,j,j∈{N i}，则节点i最终的时间修正量为
Figure PCTCN2018095822-appb-000016
例如，节点1与节点2,3,4相邻(n＝3)，节点1相对于节点2,3,4的时间修正量分别为Offset 1,2＝3ns,Offset 1,3＝2ns,Offset 1,4＝3ns，则节点1的时间修正量为Offset 1＝2ns。
在本发明的一个实施例中，还包括：定义故障等待时间阈值F th，当节点i与其相邻节点j间通讯失效时间大于F th时，认定节点i与节点j不再相邻，将节点j从所述相邻节点集合{N i}中移除。
在本发明的一个实施例中，还包括：所述时间同步节点发送含有时间戳的数据包与其它节点进行同步，接收端将收到的数据包信号分成两路分别使用数据包解析模块及时间戳生成模块进行接收，其中在所述时间戳生成模块之前加入定长延时线，保证在延时时间内所述数据包解析模块能够完成数据包解析；所述数据包解析模块采用与数据包发送时频率相同的时钟C1对包头进行解析，其周期记为T s，当解析出所收到的数据包为时间同步包时，生成一个使能控制信号发送给所述时间戳生成模块；所述时间戳生成模块使用与C1频率不同的时钟C2，其周期记为T r，当收到所述数据包解析模块发送的使能控制信号时，对该数据包打时间戳记录下其到达所述时间戳生成模块的时间，并发送给节点时间数据处理器进行数据处理；将所述时间戳生成模块生成的时间戳作为数据包到达时间，所述扰动的变化 周期为T s和T r的最小公倍数，计算出扰动的均值后按照所述步骤S1至步骤S2的方法进行时间修正量计算。
为使本领域技术人员更好地理解本发明，下面结合图1至图4对本发明实施例的方法作进一步说明。
图1示出了本发明实施例的高精度时空同步方法的流程示意图，两个节点间发送脉冲进行同步。发送脉冲和接收脉冲使用不同的时钟频率，使得每一次同步过程中的接收时间记录误差(接收时间真值与记录值之间的时间差)不同。这种方式等效于在传输时间上引入一个扰动，扰动周期为发送和接收两个时钟周期的最小公倍数，可以计算出扰动量在一个扰动周期内的均值。通过在一个扰动周期内多次同步测量取均值再补偿扰动量的方式可以得到超越时钟分辨率精度的时间修正量。
图2示出了一种高精度时间同步网故障处理状态机。当一个时间同步节点未在预计的时间收到相邻节点发送的同步脉冲时，其状态机由正常时间同步状态转入邻居节点监测状态。若在设定的故障等待时间阈值内又收到了同步脉冲，判定故障已恢复，状态机回到正常时间同步态。若在设定的故障等待时间阈值内没收到同步脉冲，判定邻居节点发生故障，状态机进入更改邻居节点状态，更新邻居节点数据库。网管主动删除邻居节点也可以使状态机进入更改邻居节点状态。邻居节点数据库更新完成后状态机进入时间同步初始化状态，初始化完成后就回到正常时间同步状态，至此该节点完成了一次故障处理。
图3示出了本发明实施例的高精度时间同步方法的实验结果。该实验基于4个节点环形拓扑，采用本发明所提到的方法进行同步，脉冲发射与接收频率分别为50MHz和52MHz。每个节点的时钟信号输入到综合频率计中进行皮秒级的时间误差测量。同步实验结果显示，本发明所提出的双频高精度同步方法相比传统IEEE 1588方法同步误差由9.58ns降低到0.17ns，同步精度提高56倍以上，实现了纳秒级时间同步。
图4示出了本发明实施例中的通过数据包进行时间同步的节点结构。晶振信号与来自其它节点的频率同步信号共同输入到时钟锁相环中完成该节点的频率同步。时钟锁相环生成C1与C2时钟分别提供给数据包解析模块及时间戳生成模块。
节点收到的数据包信号分成两路分别使用数据包解析模块及时间戳生成模块进行接收，其中在所述时间戳生成模块之前加入定长延时线，保证在延时时间内所述数据包解析模块能够完成数据包解析。
数据包解析模块采用与数据包发送时频率相同的时钟C1对包头进行解析，其周期记为T s，当解析出所收到的数据包为时间同步包时，生成一个使能控制信号发送给时间戳生成模块。
时间戳生成模块使用与C1频率不同的时钟C2，其周期记为T r，当收到数据包解析模块发送的使能控制信号时，对该数据包打时间戳记录下其到达所述时间戳生成模块的时间，并发送给节点时间数据处理器进行数据处理。
节点时间数据处理器将时间戳生成模块生成的时间戳作为数据包到达时间，所述扰动的变化周期为T s和T r的最小公倍数，计算出扰动的均值后按照所述步骤S1至步骤S2的方法进行时间修正量计算，并完成该节点的时间同步。
***管理器完成节点初始化及故障处理等***流程。
频率同步信号输出模块输出一个频率同步信号实现与其它节点的频率同步。
同步数据包输出模块利用C1时钟频率输出同步数据包实现与其它节点的时间同步。
综上，根据本发明实施例的高精度时间同步方法，可以消除多次同步结果误差的相关性，并进而通过统计平均的方法补偿引入的扰动量，降低由同步节点时钟分辨率不足导致的同步误差，该方法较现有IEEE 1588等传统时间同步方法有明显优势，能够实现纳秒级的时间同步精度。
示意图中或在此以其他方式描述的任何过程或方法描述可以被理解为，表示包括一个或更多个用于实现特定逻辑功能或过程的步骤的可执行指令的代码的模块、片段或部分，并且本发明的优选实施方式的范围包括另外的实现，其中可以不按所示出或讨论的顺序，包括根据所涉及的功能按基本同时的方式或按相反的顺序，来执行功能，这应被本发明的实施例所属技术领域的技术人员所理解。
在示意图中表示或在此以其他方式描述的逻辑和/或步骤，例如，可以被认为是用于实现逻辑功能的可执行指令的定序列表，可以具体实现在任何计算机可读介质中，以供指令执行***、装置或设备(如基于计算机的***、包括处理器的***或其他可以从指令执行***、装置或设备取指令并执行指令的***)使用，或结合这些指令执行***、装置或设备而使用。
应当理解，本发明的各部分可以用硬件、软件、固件或它们的组合来实现。在上述实施方式中，多个步骤或方法可以用存储在存储器中且由合适的指令执行***执行的软件或固件来实现。例如，如果用硬件来实现，可用本领域公知的下列技术中的任一项或他们的组合来实现：具有用于对数据信号实现逻辑功能的逻辑门电路的离散逻辑电路，具有合适的组合逻辑门电路的专用集成电路，可编程门阵列(PGA)，现场可编程门阵列(FPGA)等。
本技术领域的普通技术人员可以理解实现上述实施例方法携带的全部或部分步骤是可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，该程序在执行时，包括方法实施例的步骤之一或其组合。
此外，在本发明各个实施例中的各功能单元可以集成在一个处理模块中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。所述集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。
上述提到的存储介质可以是只读存储器，磁盘或光盘等。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，本领域的技术人员可以将本说明书中描述的不同实施例或示例进行结合和组合。
尽管上面已经示出和描述了本发明的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (13)

  1. 一种高精度时间同步方法，其特征在于，包括以下步骤：
    S1：在时间同步网络中任意两节点间引入周期性传输时间扰动，定义节点i到节点j间引入的所述周期性传输时间扰动大小为时间t的函数f i,j(t)，且扰动的最大值大于或等于接收节点j的时钟周期T j，其中，扰动周期为P i,j，扰动在所述扰动周期内的均值为
    Figure PCTCN2018095822-appb-100001
    S2：所述节点i,j在进行时间同步时，两节点互相发送带有时间戳的消息，将节点i的消息发送时间、节点j的消息接收时间、节点j的消息发送时间和节点i的消息接收时间分别记录为t 1,t 2,t 3,t 4，并在一个所述扰动周期内，计算出记录的时间t 1,t 2,t 3,t 4的均值
    Figure PCTCN2018095822-appb-100002
    则节点j相对于节点i的时间修正量为
    Figure PCTCN2018095822-appb-100003
  2. 根据权利要求1所述的高精度时间同步方法，其特征在于，其中，所述周期性传输时间扰动大小为等差数列，扰动差值为d，表示为：f i,j(t)＝d·t,t∈[0,P i,j)。
  3. 根据权利要求1所述的高精度时间同步方法，其特征在于，其中，所述周期性传输时间扰动大小为随机数列，表示为：f i,j(t)＝random(t),t∈[0,P i,j)。
  4. 根据权利要求1所述的高精度时间同步方法，其特征在于，其中，所述时间同步节点发送脉冲与其它节点进行同步，节点1的发送和接收时钟周期分别记为T s1和T r1，节点2的发送和接收时钟周期分别记为T s2和T r2，等效于在节点间引入所述周期性传输时间扰动，双向传输所述扰动的变化周期分别为T s1和T r2的最小公倍数及T s2和T r1的最小公倍数，计算出扰动的均值后按照所述步骤S1至步骤S2的方法进行时间修正量计算。
  5. 根据权利要求4所述的高精度时间同步方法，其特征在于，还包括：
    定义n s1,n s2,n r1,n r2为T s1,T s2和T r1,T r2之间的最简整数比，即n s1:n r2＝T s1:T r2,n s2:n r1＝T s2:T r1；
    定义i节点发出的第k个脉冲到达j节点的时刻与j节点接收时钟下一个上升沿间的时间间隔为
    Figure PCTCN2018095822-appb-100004
    则计算得到的时间修正量为：
    Figure PCTCN2018095822-appb-100005
  6. 根据权利要求5所述的高精度时间同步方法，其特征在于，进一步包括：
    通过选取T s1,T s2,T r1,T r2使得n r1>>1,n r2>>1时，所述时间修正量计算可以简化为
    Figure PCTCN2018095822-appb-100006
  7. 根据权利要求6所述的高精度时间同步方法，其特征在于，还包括：
    在时间同步网络中，将所有所述时间同步节点的脉冲发送时钟周期设为T s，接收时钟 周期设为T r，则时间修正量计算进一步简化为
    Figure PCTCN2018095822-appb-100007
  8. 根据权利要求7所述的高精度时间同步方法，其特征在于，还包括：
    定义时间同步误差上限要求为Error max，则需要通过频率选取满足如下不等式T r/2n r<Error max。
  9. 根据权利要求1所述的高精度时间同步方法，其特征在于，还包括：
    定义节点i的相邻节点集合{N i}，{N i}中共包含n个节点；
    计算节点i相对于每一个{N i}中的节点j的时间修正量为Offset i,j,j∈{N i}，则节点i最终的时间修正量为
    Figure PCTCN2018095822-appb-100008
  10. 根据权利要求9所述的高精度时间同步方法，其特征在于，还包括：
    定义故障等待时间阈值F th，当节点i与其相邻节点j间通讯失效时间大于F th时，认定节点i与节点j不再相邻，将节点j从所述相邻节点集合{N i}中移除。
  11. 根据权利要求1所述的高精度时间同步方法，其特征在于，还包括：
    所述时间同步节点发送含有时间戳的数据包与其它节点进行同步，接收端将收到的数据包信号分成两路分别使用数据包解析模块及时间戳生成模块进行接收，其中在所述时间戳生成模块之前加入定长延时线，保证在延时时间内所述数据包解析模块能够完成数据包解析；
    所述数据包解析模块采用与数据包发送时频率相同的时钟C1对包头进行解析，其周期记为T s，当解析出所收到的数据包为时间同步包时，生成一个使能控制信号发送给所述时间戳生成模块；
    所述时间戳生成模块使用与C1频率不同的时钟C2，其周期记为T r，当收到所述数据包解析模块发送的使能控制信号时，对该数据包打时间戳记录下其到达所述时间戳生成模块的时间，并发送给节点时间数据处理器进行数据处理；
    将所述时间戳生成模块生成的时间戳作为数据包到达时间，所述扰动的变化周期为T s和T r的最小公倍数，计算出扰动的均值后按照所述步骤S1至步骤S2的方法进行时间修正量计算。
  12. 一种设备，其特征在于，包括：
    一个或者多个处理器；
    存储器；
    一个或者多个程序，所述一个或者多个程序存储在所述存储器中，当被所述一个或者多个处理器执行时，执行如权利要求1-11任一项所述的高精度时间同步方法。
  13. 一种非易失性计算机存储介质，其特征在于，所述计算机存储介质存储有一个或者多个程序，当所述一个或者多个程序被一个设备执行时，使得所述设备执行如权利要求 1-11任一项所述的高精度时间同步方法。
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