WO2019136873A1 - 一种阵列基板及其制作方法、显示装置 - Google Patents

一种阵列基板及其制作方法、显示装置 Download PDF

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WO2019136873A1
WO2019136873A1 PCT/CN2018/083357 CN2018083357W WO2019136873A1 WO 2019136873 A1 WO2019136873 A1 WO 2019136873A1 CN 2018083357 W CN2018083357 W CN 2018083357W WO 2019136873 A1 WO2019136873 A1 WO 2019136873A1
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layer
amorphous silicon
silicon layer
insulating layer
array substrate
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PCT/CN2018/083357
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English (en)
French (fr)
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喻蕾
李松杉
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武汉华星光电半导体显示技术有限公司
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Priority to US16/034,390 priority Critical patent/US11069724B2/en
Publication of WO2019136873A1 publication Critical patent/WO2019136873A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • LTPS Low Temperature Poly-silicon thin film transistor display
  • excimer laser As a heat source in the packaging process. After the laser light passes through the projection system, a laser beam with uniform energy distribution is generated, which is projected onto the amorphous silicon structure. On the glass substrate, when the amorphous silicon structure glass substrate absorbs the energy of the excimer laser, it is converted into a polysilicon structure.
  • a-Si amorphous silicon
  • p-Si polysilicon
  • ELA excimer laser anneal
  • the technical problem to be solved by the present application is to provide an array substrate, a manufacturing method thereof, and a display device, which can solve the problem that the surface of the polysilicon is oxidized to affect the carrier concentration therein, and the working performance of the array substrate is improved.
  • a technical solution adopted by the present application is to provide a display device including an array substrate, the array substrate includes a stacked polysilicon layer and an insulating layer, and the polysilicon layer and the insulating layer are fabricated by the following method. : introducing a first mixed gas to deposit an amorphous silicon layer; introducing a second mixed gas to deposit an insulating layer on the amorphous silicon layer; dehydrogenating the amorphous silicon layer; and removing the amorphous silicon layer after dehydrogenation An excimer laser annealing treatment is performed to change the amorphous silicon layer into a polysilicon layer.
  • another technical solution adopted by the present application is to provide a method for fabricating an array substrate, which comprises: forming an amorphous silicon layer and an insulating layer covering the amorphous silicon layer in a single deposition process; The amorphous silicon layer is processed to change the amorphous silicon layer into a polysilicon layer.
  • an array substrate which is fabricated by forming an amorphous silicon layer and covering an amorphous silicon layer in a single deposition process.
  • An insulating layer; the amorphous silicon layer is treated to change the amorphous silicon layer into a polysilicon layer.
  • the method for fabricating the array substrate provided by the present application includes: forming an amorphous silicon layer and an insulating layer covering the amorphous silicon layer in one deposition process; The layer is processed to change the amorphous silicon layer into a polysilicon layer.
  • the amorphous silicon is converted into polycrystalline silicon, the polycrystalline silicon is exposed to the air to be oxidized, and the surface oxidation of the polycrystalline silicon is affected to affect the carrier concentration, thereby improving the working performance of the array substrate.
  • the formation of amorphous silicon and an insulating layer in the same process reduces a process and saves production time and cost.
  • FIG. 1 is a schematic structural view of an array substrate in the prior art
  • FIG. 2 is a schematic flow chart of an embodiment of a method for fabricating an array substrate provided by the present application
  • step 22 is a schematic structural view of step 22 in an embodiment of a method for fabricating an array substrate provided by the present application
  • FIG. 4 is a schematic flow chart of another embodiment of a method for fabricating an array substrate provided by the present application.
  • FIG. 5 is a schematic flow chart of still another embodiment of a method for fabricating an array substrate provided by the present application.
  • FIG. 6 is a schematic structural diagram of steps 51 to 53 in still another embodiment of the method for fabricating an array substrate provided by the present application;
  • FIG. 7 is a schematic structural view of a step 54 in still another embodiment of the method for fabricating an array substrate provided by the present application.
  • FIG. 8 is a schematic structural view of steps 55 to 57 in still another embodiment of the method for fabricating the array substrate provided by the present application;
  • step 58 is a schematic structural diagram of step 58 in still another embodiment of the method for fabricating the array substrate provided by the present application.
  • FIG. 10 is a schematic structural view of an embodiment of an array substrate provided by the present application.
  • FIG. 11 is a schematic structural diagram of an embodiment of a display device provided by the present application.
  • references to "an embodiment” herein mean that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least one embodiment of the present application.
  • the appearances of the phrases in various places in the specification are not necessarily referring to the same embodiments, and are not exclusive or alternative embodiments that are mutually exclusive. Those skilled in the art will understand and implicitly understand that the embodiments described herein can be combined with other embodiments.
  • FIG. 1 is a schematic structural view of an array substrate in the prior art.
  • the top gate type array substrate includes a polysilicon layer 13, a insulating layer 14, and a gate electrode 15 which are stacked.
  • the polysilicon layer 13 is formed. Before the insulating layer 14 is formed, the polysilicon layer 13 is exposed to the air, and the surface of the polysilicon layer 13 is oxidized in the air to form a very thin (about 5 nm) impurity layer 13a.
  • the impurity layer 13a generally includes SiO x .
  • SiO x contains many defects, which are interposed between the polysilicon layer 13 and the insulating layer 14. When the TFT is operated, carriers are trapped, and then the carrier concentration thereof is changed, which seriously affects the working performance of the TFT.
  • FIG. 2 is a schematic flowchart of an embodiment of a method for fabricating an array substrate provided by the present application, where the method includes:
  • Step 21 forming an amorphous silicon layer and an insulating layer covering the amorphous silicon layer in one deposition process.
  • amorphous silicon is also called amorphous silicon, a form of elemental silicon. Brownish black or grayish black microcrystals. Silicon does not have a complete diamond unit cell and is not of high purity. The melting point, density and hardness are also significantly lower than crystalline silicon. Chemical properties are more active than crystalline silicon.
  • the silicon tetrahalide can be reduced by heating with a reactive metal (such as sodium, potassium, etc.) or reduced by a reducing agent such as carbon.
  • An amorphous silicon film containing hydrogen is obtained by glow discharge vapor deposition.
  • the insulating layer may be SiO x , SiN x or a mixture of SiO x and SiN x .
  • the above deposition process may adopt a method such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), for example, gas evaporation.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • Step 22 The amorphous silicon layer is treated to change the amorphous silicon layer into a polysilicon layer.
  • the amorphous silicon is mainly converted into polycrystalline silicon by using an excimer laser annealing (ELA) technology.
  • ELA excimer laser annealing
  • the temperature at which the ELA is used to prepare the p-Si material is usually lower than 450 ° C, and ordinary TFT glass can be used.
  • the characteristics of the p-Si material obtained by this method fully satisfy the requirements of the performance of the TFT switching device for pixel and the TFT device for peripheral driving. Since the XeCl (cerium chloride) excimer laser has good gas stability and an a-Si film having a high absorption coefficient (about 106 cm-1) at a wavelength of 308 nm, it is generally produced by using a XeCl excimer laser.
  • a dot-shaped laser beam was used to anneal the a-Si film at a very slow rate, and the resulting p-Si material had many defects. If the laser beam is changed to a line shape, the laser scanning process can be made simple.
  • an amorphous silicon layer 12 and an insulating layer 14 covering the amorphous silicon layer are first formed in a deposition process, and then the amorphous silicon layer 12 is subjected to an excimer laser annealing treatment to change the amorphous silicon layer 12.
  • a polysilicon layer 13 is formed.
  • the method for fabricating the array substrate of the embodiment includes: forming an amorphous silicon layer and an insulating layer covering the amorphous silicon layer in a single deposition process; and processing the amorphous silicon layer to make the amorphous silicon The layer becomes a polysilicon layer.
  • the amorphous silicon is converted into polycrystalline silicon, the polycrystalline silicon is exposed to the air to be oxidized, and the surface oxidation of the polycrystalline silicon is affected to affect the carrier concentration, thereby improving the working performance of the array substrate.
  • the formation of amorphous silicon and an insulating layer in the same process reduces a process and saves production time and cost.
  • FIG. 4 is a schematic flowchart diagram of another embodiment of a method for fabricating an array substrate provided by the present application, where the method includes:
  • Step 41 A first mixed gas is introduced to deposit an amorphous silicon layer.
  • Step 42 Passing a second mixed gas to deposit an insulating layer on the amorphous silicon layer.
  • the insulating layer may be SiN x .
  • the first mixed gas may be a mixed gas of SiH 4 and H 2
  • the second mixed gas may be a mixed gas of SiH 4 and NH 3 .
  • a-Si and SiNx can be deposited at one time by CVD technology, that is, two steps are used in the CVD process, the first step gas is SiH 4 +H 2 , and the second step is to replace the gas with SiH 4 +NH 3 .
  • a-Si and SiN x can be formed using a single CVD process.
  • Step 43 Dehydrogenating the amorphous silicon layer.
  • Step 44 performing an excimer laser annealing treatment on the de-hydrogenated amorphous silicon layer to change the amorphous silicon layer into a polysilicon layer.
  • ELA excimer laser annealing
  • SiN x has been formed unaffected
  • a method of CVD is used to form p -Si polysilicon layer and gate insulating layer SiN x .
  • FIG. 5 is a schematic flowchart diagram of still another embodiment of a method for fabricating an array substrate provided by the present application.
  • the manufacturing method includes:
  • Step 51 Provide a substrate.
  • the substrate may be a glass substrate or a plastic substrate. It is understood that the substrate is used as a substrate only during the fabrication process, and the substrate is peeled off after the array substrate is fabricated.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • gas evaporation can be used in the fabrication of each of the functional layers described below. If the functional layer to be formed needs to be subjected to corresponding patterning, a photolithography, development, etching, stripping, etc. process may be employed, which will not be described below.
  • Step 52 Form an insulating layer on the substrate.
  • the insulating layer may be SiO x , SiN x or a mixture of SiO x and SiN x .
  • Step 53 forming an amorphous silicon layer and an insulating layer covering the amorphous silicon layer on the insulating layer in one deposition process.
  • a substrate 10 is provided on which a buffer layer 11 is formed, and an amorphous silicon layer 12 and an insulating layer 14 covering the amorphous silicon layer are formed on the buffer layer 11 in a single deposition process.
  • a-Si and SiNx can be deposited at one time by CVD technology, that is, two steps are used in the CVD process, the first step gas is SiH 4 +H 2 , and the second step is to replace the gas with SiH 4 +NH 3 .
  • a-Si and SiN x can be formed using a single CVD process.
  • Step 54 The amorphous silicon layer is treated to change the amorphous silicon layer into a polysilicon layer.
  • the amorphous silicon layer 12 is processed to change the amorphous silicon layer 12 into the polysilicon layer 13.
  • ELA excimer laser annealing
  • SiN x has been formed unaffected
  • a method of CVD is used to form p -Si polysilicon layer and gate insulating layer SiN x .
  • Step 55 Forming a gate on the insulating layer.
  • Step 56 Forming a dielectric layer on the insulating layer and the gate.
  • Step 57 Form a via hole on the dielectric layer and the insulating layer to partially expose the polysilicon layer.
  • a gate electrode 15 is formed on the insulating layer 14
  • a dielectric layer 16 is formed on the insulating layer 14 and the gate electrode 15, and via holes are formed on the dielectric layer 16 and the insulating layer 14, so that the polysilicon layer 13 is formed. Partially bare.
  • the gate 15 can be formed by first depositing a conductive layer and then forming a gate 15 by a patterning process. Therefore, the gate 15 is not completely covered on the insulating layer 14. Therefore, when a via hole is formed in the dielectric layer 16 and the insulating layer 14, it is formed at a position where the gate electrode 15 is not covered, so that the via hole does not come into contact with the gate electrode 15.
  • the gate is metal Mo
  • the dielectric layer 16 is SiO x , SiN x or a mixture of SiO x and SiN x .
  • Step 58 forming a source and a drain on the dielectric layer, and the source and the drain respectively connect the polysilicon layer through the via.
  • a source electrode 171 and a drain electrode 172 are formed on the dielectric layer 16, and the source electrode 171 and the drain electrode 172 are connected to the polysilicon layer 13 through via holes, respectively.
  • the source 171 and the drain 172 are metal Ti, metal Al, and metal Ti which are stacked.
  • the array substrate in this embodiment may also be a bottom gate type array substrate, that is, the substrate 10 is sequentially stacked in the following order: buffer layer 11, gate electrode 15, gate insulating layer 14, polysilicon layer 13, and dielectric.
  • the layer 16, the source 171 and the drain 172 are connected to the polysilicon layer 13 through via holes formed on the dielectric layer 16 and the insulating layer 14, respectively.
  • FIG. 10 is a schematic structural diagram of an embodiment of an array substrate according to the present application.
  • the array substrate includes a substrate 10, a buffer layer 11, a polysilicon layer 13, an insulating layer 14, a gate 15, and a dielectric layer 16 which are stacked. And a source 171 and a drain 172.
  • the source 171 and the drain 172 are connected to the polysilicon layer 13 through via holes formed on the dielectric layer 16 and the insulating layer 14, respectively.
  • the polysilicon layer 13 and the insulating layer 14 are formed by forming an amorphous silicon layer and an insulating layer covering the amorphous silicon layer on the insulating layer in a single deposition process, and processing the amorphous silicon layer to make the amorphous layer
  • the silicon layer becomes a polysilicon layer.
  • CVD can be used to deposit a-Si and SiN x at a time , that is, two steps are used in the CVD process, the first step gas is SiH 4 +H 2 , and the second step is to replace the gas with SiH 4 +NH 3 , so that a-Si and SiN x can be formed using a single CVD process.
  • ELA excimer laser annealing
  • the array substrate of this embodiment can be fabricated by using the manufacturing method provided in the above embodiments, and details are not described herein again.
  • FIG. 11 is a schematic structural diagram of an embodiment of a display device provided by the present application.
  • the display device 110 includes a display panel 111 , and the display panel 111 includes an array substrate.
  • the display panel 111 can be a liquid crystal panel or an OLED panel, that is, the array substrate provided in the above embodiments can be applied to the liquid crystal panel or the OLED panel.
  • a flat layer may be further disposed on the source electrode 171, the drain electrode 172, and the dielectric layer 16.
  • the common electrode is disposed on the flat layer, and the common electrode passes through the via hole on the flat layer.
  • the source 171 or the drain 172 is connected.
  • the liquid crystal panel further includes a color filter substrate disposed opposite to the array substrate, wherein the color filter and the pixel electrode may be included, and the liquid crystal panel is formed after the array substrate and the color filter substrate are paired with the liquid crystal.
  • a flat layer may be further disposed on the source electrode 171, the drain electrode 172, and the dielectric layer 16.
  • the anode, the OLED luminescent material, the cathode, and the encapsulation layer are sequentially stacked on the flat layer.
  • the anode is connected to the source 171 or the drain 172 through a via hole on the flat layer.
  • the amorphous silicon layer is then processed to change the amorphous silicon layer into a polysilicon layer.
  • the polycrystalline silicon is exposed to air and oxidized, solving the problem of oxidation of the surface of the polycrystalline silicon and affecting the carrier concentration therein, thereby improving the working performance of the array substrate.
  • the formation of amorphous silicon and an insulating layer in the same process reduces a process, saves production time, and is advantageous in reducing the manufacturing cost of the display device.

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Abstract

一种阵列基板及其制作方法、显示装置，该阵列基板的制作方法包括：在一次沉积工艺中形成非晶硅层和覆盖非晶硅层的绝缘层（21）；对非晶硅层进行处理，以使非晶硅层变成多晶硅层（22）。通过上述方式，能够解决多晶硅表面氧化而影响其中载流子浓度的问题，提高了阵列基板的工作性能。

Description

一种阵列基板及其制作方法、显示装置 技术领域
本申请涉及显示技术领域，特别是涉及一种阵列基板及其制作方法、显示装置。
背景技术
LTPS(Low Temperature Poly-silicon，低温多晶硅)薄膜晶体管显示器是在封装过程中，利用准分子镭射作为热源，镭射光经过投射***后，会产生能量均匀分布的镭射光束，投射于非晶硅结构的玻璃基板上，当非晶硅结构玻璃基板吸收准分子镭射的能量后，会转变成为多晶硅结构。
传统的LTPS制作过程中，先形成a-Si(非晶硅)，再使用ELA(excimer laser anneal，准分子镭射退火)将a-Si转变成p-Si(多晶硅)并图形化。在p-Si形成后，p-Si表面在空气中会被氧化，严重影响LTPS-TFT的工作性能。
技术问题
本申请主要解决的技术问题是提供一种阵列基板及其制作方法、显示装置，能够解决多晶硅表面氧化而影响其中载流子浓度的问题，提高了阵列基板的工作性能。
技术解决方案
为解决上述技术问题，本申请采用的一个技术方案是：提供一种显示装置，显示装置包括阵列基板，阵列基板包括层叠设置的多晶硅层和绝缘层，多晶硅层和绝缘层是采用以下方法制作的：通入第一混合气体，沉积非晶硅层；通入第二混合气体，在非晶硅层上沉积绝缘层；对非晶硅层进行去氢处理；对去氢后的非晶硅层进行准分子镭射退火处理，以将非晶硅层变成多晶硅层。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种阵列基 板的制作方法，该方法包括：在一次沉积工艺中形成非晶硅层和覆盖非晶硅层的绝缘层；对非晶硅层进行处理，以使非晶硅层变成多晶硅层。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种阵列基板，该阵列基板是采用如下方法制作得到的：在一次沉积工艺中形成非晶硅层和覆盖非晶硅层的绝缘层；对非晶硅层进行处理，以使非晶硅层变成多晶硅层。
有益效果
本申请的有益效果是：区别于现有技术的情况，本申请提供的阵列基板的制作方法包括：在一次沉积工艺中形成非晶硅层和覆盖非晶硅层的绝缘层；对非晶硅层进行处理，以使非晶硅层变成多晶硅层。通过上述方式，一方面，避免先对非晶硅转化为多晶硅后，多晶硅暴露在空气中而氧化，解决多晶硅表面氧化而影响其中载流子浓度的问题，提高了阵列基板的工作性能。另一方面，在同一制程中形成非晶硅和绝缘层，减少了一道工序，节省了制作时间和成本。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是现有技术中阵列基板的结构示意图；
图2是本申请提供的阵列基板的制作方法一实施例的流程示意图；
图3是本申请提供的阵列基板的制作方法一实施例中步骤22的结构示意图；
图4是本申请提供的阵列基板的制作方法另一实施例的流程示意图；
图5是本申请提供的阵列基板的制作方法又一实施例的流程示意图；
图6是本申请提供的阵列基板的制作方法又一实施例中步骤51-步骤53的 结构示意图；
图7是本申请提供的阵列基板的制作方法又一实施例中步骤54的结构示意图；
图8是本申请提供的阵列基板的制作方法又一实施例中步骤55-步骤57的结构示意图；
图9是本申请提供的阵列基板的制作方法又一实施例中步骤58的结构示意图；
图10是本申请提供的阵列基板一实施例的结构示意图；
图11是本申请提供的显示装置一实施例的结构示意图。
本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、***、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与 其它实施例相结合。
参阅图1，图1是现有技术中阵列基板的结构示意图。
以现有技术中的顶栅型为例，该顶栅型阵列基板包括层叠设置的多晶硅层13、绝缘层14以及栅极15。
由于在制作多晶硅层13的过程中，一般是先沉积一层非晶硅，然后对非晶硅进行处理后，再形成多晶硅层13。在制作绝缘层14之前，多晶硅层13暴露在空气中，多晶硅层13表面在空气中会被氧化形成一层很薄(大概5nm左右)的杂质层13a，该杂质层13a一般包括SiO x，此SiO x含有的缺陷较多，介于多晶硅层13和绝缘层14之间，在TFT工作时会捕获载流子，继而改变其中的载流子浓度，严重影响TFT的工作性能。
参阅图2，图2是本申请提供的阵列基板的制作方法一实施例的流程示意图，该方法包括：
步骤21：在一次沉积工艺中形成非晶硅层和覆盖非晶硅层的绝缘层。
其中，非晶硅又称无定形硅，单质硅的一种形态。棕黑色或灰黑色的微晶体。硅不具有完整的金刚石晶胞，纯度不高。熔点、密度和硬度也明显低于晶体硅。化学性质比晶体硅活泼。可由活泼金属(如钠、钾等)在加热下还原四卤化硅，或用碳等还原剂还原二氧化硅制得。采用辉光放电气相沉积法就得含氢的非晶硅薄膜。
其中，绝缘层可以采用SiO x、SiN x或者SiO x和SiN x的混合物。
可以理解的，上述的沉积工艺可以采用物理气相沉积(PVD)或化学气相沉积(CVD)等方式，例如，气体蒸镀。
步骤22：对非晶硅层进行处理，以使非晶硅层变成多晶硅层。
可选的，在本实施例中，主要采用准分子镭射退火(ELA)技术，将非晶硅转化为多晶硅。
ELA制备p-Si材料的温度通常低于450℃，用普通TFT玻璃即可。这种方法获得的p-Si材料的特性完全满足像素用TFT开关器件及周边驱动用TFT器件 性能的要求。因为XeCl(氯化氙)准分子激光器具有较好的气体稳定性和在波长308nm处a-Si薄膜具有高吸收系数(约为106cm-1)的优点，所以一般采用XeCl准分子激光器进行生产。最初采用点状的激光束退火a-Si薄膜，速度很慢，且得到的p-Si材料缺陷很多。如果将激光束改变为线状，则可以使雷射扫描过程变得简单。
具体参阅图3，先在一次沉积工艺中形成非晶硅层12和覆盖非晶硅层的绝缘层14，然后对非晶硅层12进行准分子镭射退火处理，以使非晶硅层12变成多晶硅层13。
区别于现有技术，本实施例的阵列基板的制作方法包括：在一次沉积工艺中形成非晶硅层和覆盖非晶硅层的绝缘层；对非晶硅层进行处理，以使非晶硅层变成多晶硅层。通过上述方式，一方面，避免先对非晶硅转化为多晶硅后，多晶硅暴露在空气中而氧化，解决多晶硅表面氧化而影响其中载流子浓度的问题，提高了阵列基板的工作性能。另一方面，在同一制程中形成非晶硅和绝缘层，减少了一道工序，节省了制作时间和成本。
参阅图4，图4是本申请提供的阵列基板的制作方法另一实施例的流程示意图，该方法包括：
步骤41：通入第一混合气体，沉积非晶硅层。
步骤42：通入第二混合气体，在非晶硅层上沉积绝缘层。
其中，绝缘层可以是SiN x，具体地，第一混合气体可以是SiH 4和H 2的混合气体，第二混合气体可以是SiH 4和NH 3的混合气体。
具体地，可以利用CVD技术一次性沉积a-Si和SiNx，即在CVD过程中采用两步，第一步的气体为SiH 4+H 2，第二步将气体置换为SiH 4+NH 3，这样使用一次CVD工艺即可以形成a-Si和SiN x。
步骤43：对非晶硅层进行去氢处理。
步骤44：对去氢后的非晶硅层进行准分子镭射退火处理，以将非晶硅层变成多晶硅层。
具体地，在对a-Si进行去氢制程后再使用ELA(准分子镭射退火)将a-Si转变成p-Si多晶硅，同时SiN x已经形成不受影响；利用一次CVD的方法即形成p-Si多晶硅层和栅极绝缘层SiN x。
下面以顶栅型TFT为例对其制作方式进行详细说明。
参阅图5，图5是本申请提供的阵列基板的制作方法又一实施例的流程示意图，该制作方法包括：
步骤51：提供一基板。
其中，该基板可以是玻璃基板或者塑料基板，可以理解的，该基板只是在制作过程中作为衬底使用，在阵列基板制作完成之后，会将该基板进行剥离。
可以理解的，在下述的各个功能层的制作时，均可以采用物理气相沉积(PVD)或化学气相沉积(CVD)等方式，例如，气体蒸镀。若在形成的功能层需要进行相应的图案化处理时，可以采用光刻、显影、蚀刻、剥离等工艺制程，下面不在赘述。
步骤52：在基板上形成绝缘层。
其中，该绝缘层可以是SiO x、SiN x或者SiO x和SiN x的混合物。
步骤53：在一次沉积工艺中在绝缘层上形成非晶硅层和覆盖非晶硅层的绝缘层。
如图6所示，提供一基板10，在基板10上形成缓冲层11，在一次沉积工艺中在缓冲层11上形成非晶硅层12和覆盖非晶硅层的绝缘层14。
具体地，可以利用CVD技术一次性沉积a-Si和SiNx，即在CVD过程中采用两步，第一步的气体为SiH 4+H 2，第二步将气体置换为SiH 4+NH 3，这样使用一次CVD工艺即可以形成a-Si和SiN x。
步骤54：对非晶硅层进行处理，以使非晶硅层变成多晶硅层。
同时参阅图6和图7，对非晶硅层12进行处理，以使非晶硅层12变成多晶硅层13。
具体地，在对a-Si进行去氢制程后再使用ELA(准分子镭射退火)将a-Si 转变成p-Si多晶硅，同时SiN x已经形成不受影响；利用一次CVD的方法即形成p-Si多晶硅层和栅极绝缘层SiN x。
步骤55：在绝缘层上形成栅极。
步骤56：在绝缘层和栅极上形成介电层。
步骤57：在介电层和绝缘层上形成过孔，以使多晶硅层部分裸露。
如图8所示，在绝缘层14上形成栅极15，在绝缘层14和栅极15上形成介电层16，在介电层16和绝缘层14上形成过孔，以使多晶硅层13部分裸露。
可以理解的，栅极15的形成可以是先沉积一层导电层，然后通过图案化处理形成栅极15，因此，栅极15并没有完全覆盖在绝缘层14上。所以，在介电层16和绝缘层14上形成过孔时，是在没有栅极15覆盖的位置形成的，所以过孔不会与栅极15接触。
其中，栅极为金属Mo，介电层16为SiO x、SiN x或者SiO x和SiN x的混合物。
步骤58：在介电层上形成源极和漏极，源极和漏极分别通过过孔连接多晶硅层。
如图9所示，在介电层16上形成源极171和漏极172，源极171和漏极172分别通过过孔连接多晶硅层13。
其中，源极171和漏极172为层叠设置的金属Ti、金属Al和金属Ti。
可以理解的，本实施例中的阵列基板还可以是底栅型的阵列基板，即基板10上依次层叠顺序为：缓冲层11、栅极15、栅极绝缘层14、多晶硅层13以及介电层16，源极171和漏极172分别通过介电层16和绝缘层14上形成的过孔连接多晶硅层13。
参阅图10，图10是本申请提供的阵列基板一实施例的结构示意图，该阵列基板包括层叠设置的基板10、缓冲层11、多晶硅层13、绝缘层14、栅极15、介电层16以及源极171和漏极172。其中，源极171和漏极172分别通过介电层16和绝缘层14上形成的过孔连接多晶硅层13。
其中，多晶硅层13和绝缘层14的制作方法如下：在一次沉积工艺中在绝 缘层上形成非晶硅层和覆盖非晶硅层的绝缘层，对非晶硅层进行处理，以使非晶硅层变成多晶硅层。
具体地，具体地，可以利用CVD技术一次性沉积a-Si和SiN x，即在CVD过程中采用两步，第一步的气体为SiH 4+H 2，第二步将气体置换为SiH 4+NH 3，这样使用一次CVD工艺即可以形成a-Si和SiN x。在对a-Si进行去氢制程后再使用ELA(准分子镭射退火)将a-Si转变成p-Si多晶硅，同时SiN x已经形成不受影响；利用一次CVD的方法即形成p-Si多晶硅层和栅极绝缘层SiN x。
可以理解的，本实施例的阵列基板可以采用如上述的实施例中提供的制作方法制作，这里不再赘述。
参阅图11，图11是本申请提供的显示装置一实施例的结构示意图，该显示装置110包括显示面板111，该显示面板111包括阵列基板。
其中，该显示面板111可以是液晶面板，也可以是OLED面板，即上述实施例提供的阵列基板，既可以应用在液晶面板中，也可以应用在OLED面板。
结合图10，如果应用于液晶面板中，可以在源极171、漏极172以及介电层16上再设置一层平坦层，平坦层上设置公共电极，公共电极通过平坦层上的过孔与源极171或者漏极172连接。另外，该液晶面板还包括与阵列基板相对设置的彩膜基板，其中可以包括彩色滤光片和像素电极，阵列基板和彩膜基板液晶对盒后形成液晶面板。
结合图10，如果应用于OLED面板中，可以在源极171、漏极172以及介电层16上再设置一层平坦层，平坦层上依次层叠设置阳极、OLED发光材料、阴极以及封装层。其中，阳极通过平坦层上的过孔与源极171或者漏极172连接。
区别于现有技术，本实施例提供的阵列基板以及采用该阵列基板的显示装置，其中的多晶硅层在制作时，在一次沉积工艺中形成非晶硅层和覆盖非晶硅层的绝缘层；再对非晶硅层进行处理，以使非晶硅层变成多晶硅层。一方面，避免先对非晶硅转化为多晶硅后，多晶硅暴露在空气中而氧化，解决多晶硅表 面氧化而影响其中载流子浓度的问题，提高了阵列基板的工作性能。另一方面，在同一制程中形成非晶硅和绝缘层，减少了一道工序，节省了制作时间，有利于降低显示装置的制作成本。
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种显示装置，其中，所述显示装置包括阵列基板，所述阵列基板包括层叠设置的多晶硅层和绝缘层，所述多晶硅层和所述绝缘层是采用以下方法制作的：
    通入第一混合气体，沉积非晶硅层；
    通入第二混合气体，在所述非晶硅层上沉积所述绝缘层；
    对所述非晶硅层进行去氢处理；
    对去氢后的所述非晶硅层进行准分子镭射退火处理，以将所述非晶硅层变成多晶硅层。
  2. 根据权利要求1所述的显示装置，其中，
    所述第一混合气体为SiH 4和H 2的混合气体。
  3. 根据权利要求1所述的显示装置，其中，
    所述第二混合气体为SiH 4和NH 3的混合气体。
  4. 根据权利要求1所述的显示装置，其中，
    所述阵列基板还包括层叠设置的基板和缓冲层，所述多晶硅层设置在所述缓冲层上。
  5. 根据权利要求4所述的显示装置，其中，
    所述绝缘层上还包括形成于所述绝缘层上的栅极、形成于所述绝缘层和所述栅极上的介电层、以及形成于所述介电层上的源极和漏极，其中，所述源极和所述漏极分别通过所述介电层和所述绝缘层上形成的过孔连接所述多晶硅层。
  6. 根据权利要求5所述的显示装置，其中，
    所述栅极为金属Mo；或
    所述源极和所述漏极为层叠设置的金属Ti、金属Al和金属Ti。
  7. 一种阵列基板的制作方法，其中，包括：
    在一次沉积工艺中形成非晶硅层和覆盖所述非晶硅层的绝缘层；
    对所述非晶硅层进行处理，以使所述非晶硅层变成多晶硅层。
  8. 根据权利要求7所述的制作方法，其中，
    所述在一次沉积工艺中形成非晶硅层和覆盖所述非晶硅层的绝缘层的步骤，包括：
    通入第一混合气体，沉积所述非晶硅层；
    通入第二混合气体，在所述非晶硅层上沉积所述绝缘层。
  9. 根据权利要求8所述的制作方法，其中，
    所述第一混合气体为SiH 4和H 2的混合气体。
  10. 根据权利要求8所述的制作方法，其中，
    所述第二混合气体为SiH 4和NH 3的混合气体。
  11. 根据权利要求7所述的制作方法，其中，
    所述对所述非晶硅层进行处理，以使所述非晶硅层变成多晶硅层的步骤，包括：
    对所述非晶硅层进行去氢处理；
    对去氢后的所述非晶硅层进行准分子镭射退火处理，以将所述非晶硅层变成多晶硅层。
  12. 根据权利要求7所述的制作方法，其中，
    所述在一次沉积工艺中形成非晶硅层和覆盖所述非晶硅层的绝缘层的步骤之前，还包括：
    提供一基板；
    在所述基板上形成缓冲层；
    所述在一次沉积工艺中形成非晶硅层和覆盖所述非晶硅层的绝缘层的步骤，具体为：
    在一次沉积工艺中在所述缓冲层上形成非晶硅层和覆盖所述非晶硅层的绝缘层。
  13. 根据权利要求12所述的制作方法，其中，
    所述对所述非晶硅层进行处理，以使所述非晶硅层变成多晶硅层的步骤之后，还包括：
    在所述绝缘层上形成栅极；
    在所述绝缘层和所述栅极上形成介电层；
    在所述介电层和所述绝缘层上形成过孔，以使所述多晶硅层部分裸露；
    在所述介电层上形成源极和漏极，所述源极和所述漏极分别通过所述过孔连接所述多晶硅层。
  14. 根据权利要求13所述的制作方法，其中，
    所述栅极为金属Mo；或
    所述源极和所述漏极为层叠设置的金属Ti、金属Al和金属Ti。
  15. 一种阵列基板，其中，所述阵列基板包括层叠设置的多晶硅层和绝缘层，所述多晶硅层和所述绝缘层是采用以下方法制作的：
    在一次沉积工艺中形成非晶硅层和覆盖所述非晶硅层的绝缘层；
    对所述非晶硅层进行处理，以使所述非晶硅层变成多晶硅层。
  16. 根据权利要求15所述的阵列基板，其中，
    所述在一次沉积工艺中形成非晶硅层和覆盖所述非晶硅层的绝缘层的步骤，包括：
    通入第一混合气体，沉积所述非晶硅层；
    通入第二混合气体，在所述非晶硅层上沉积所述绝缘层。
  17. 根据权利要求16所述的阵列基板，其中，
    所述第一混合气体为SiH 4和H 2的混合气体。
  18. 根据权利要求16所述的阵列基板，其中，
    所述第二混合气体为SiH 4和NH 3的混合气体。
  19. 根据权利要求15所述的阵列基板，其中，
    所述阵列基板还包括层叠设置的基板和缓冲层，所述多晶硅层设置在所述 缓冲层上。
  20. 根据权利要求15所述的阵列基板，其中，
    所述绝缘层上还包括形成于所述绝缘层上的栅极、形成于所述绝缘层和所述栅极上的介电层、以及形成于所述介电层上的源极和漏极，其中，所述源极和所述漏极分别通过所述介电层和所述绝缘层上形成的过孔连接所述多晶硅层。
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