WO2019000508A1 - 薄膜晶体管阵列基板及其制备方法、显示装置 - Google Patents

薄膜晶体管阵列基板及其制备方法、显示装置 Download PDF

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WO2019000508A1
WO2019000508A1 PCT/CN2017/093424 CN2017093424W WO2019000508A1 WO 2019000508 A1 WO2019000508 A1 WO 2019000508A1 CN 2017093424 W CN2017093424 W CN 2017093424W WO 2019000508 A1 WO2019000508 A1 WO 2019000508A1
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layer
thin film
region
active
electrode
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PCT/CN2017/093424
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English (en)
French (fr)
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周星宇
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/741,132 priority Critical patent/US10693011B2/en
Publication of WO2019000508A1 publication Critical patent/WO2019000508A1/zh

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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor array substrate and a method for fabricating the same, and to a display device including the thin film transistor array substrate.
  • the flat panel display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the conventional flat panel display device mainly includes a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • Thin Film Transistors (TFTs) are an important part of flat panel display devices and can be formed on glass substrates or plastic substrates, and are commonly used as light-emitting devices and driving devices such as LCDs and OLEDs.
  • Poly-Si films are composed of many small grains with different sizes and different crystal plane orientations.
  • the grain size is generally between tens and hundreds of nanometers, and the large grain size can reach several micrometers.
  • the large-grain polycrystalline silicon film has a high mobility and is close to the mobility of the bulk material, so the polycrystalline silicon film has been widely used in the fabrication of semiconductor devices. For example, in thin film transistors in LCD or OLED products, a polysilicon film is mostly used as an active layer.
  • a method for preparing a polycrystalline silicon film is mainly to prepare an amorphous silicon (a-Si) film, and then crystallizing the amorphous silicon film to obtain a polycrystalline silicon film.
  • the crystallization of amorphous silicon films mainly includes: Excimer Laser Anneal (ELA), Metal Induced Crystallization (MIC), Metal Induced Lateral Crystallization (MILC). And solid-phase crystallization (SPC).
  • ELA Excimer Laser Anneal
  • MIC Metal Induced Crystallization
  • MILC Metal Induced Lateral Crystallization
  • SPC solid-phase crystallization
  • the poly-Si obtained by the ELA crystallization method has a low gap density and is difficult to produce a large-area poly-Si film, and the apparatus used in this method is expensive and costly.
  • the metal residue is large, resulting in deterioration of TFT characteristics.
  • the SPC crystallization method can be used to prepare a poly-Si film having a large grain size.
  • the method is applied to a thin film transistor array substrate, since the substrate is easily deformed at a high temperature, it is required to be crystallized. The temperature is set lower, and the decrease in the crystallization temperature results in a large increase in the crystallization time and a reduction in production efficiency.
  • the present invention provides a method for preparing a thin film transistor array substrate, which uses a solid phase crystallization method to prepare a polysilicon film as an active layer, which can reduce the crystallization temperature and avoid deformation of the substrate, and the method It can shorten the crystallization time and increase the production efficiency.
  • a method of fabricating a thin film transistor array substrate comprising the steps of: preparing a patterned active layer on a substrate, comprising:
  • the amorphous silicon film layer and the boron-doped amorphous silicon germanium film layer are crystallized by a thermal annealing process, and the amorphous silicon film layer is converted into a polysilicon film layer, and the boron doped non- Converting the crystalline silicon germanium film layer into a boron-doped polysilicon germanium film layer;
  • the active layer including an active region, the active region including a channel region and respectively located a source region and a drain region on both sides of the channel region; wherein the active region is formed by etching the polysilicon film layer, and a polysilicon germanium film layer above the source region is retained to form a first A contact layer, a polysilicon germanium film layer over the drain region is retained to form a second contact layer.
  • the method specifically includes the steps of:
  • the temperature of the thermal annealing process is 500 to 1000 ° C, and the time is 5 to 60 min.
  • the active layer further includes a storage capacitor region.
  • the storage capacitor region simultaneously retains the polysilicon film layer and the polysilicon germanium film layer.
  • the boron-doped amorphous silicon germanium thin film layer has a thickness of 20 to 200 nm.
  • the present invention also provides a thin film transistor array substrate comprising an active layer, a source electrode and a drain electrode disposed on a base substrate, wherein the active layer includes an active region, and the active region includes a channel And a source region and a drain region respectively located on opposite sides of the channel region, wherein the source region is provided with a first contact layer, and the source electrode is electrically connected to the first contact layer a source region, the drain region is provided with a second contact layer, the drain electrode is electrically connected to the drain region through the second contact layer; the material of the active layer is polysilicon, The material of the first contact layer and the second contact layer is boron-doped polysilicon germanium.
  • the thin film transistor array substrate includes: a base substrate; the active layer patternedly formed on the base substrate; a gate insulating layer covering the active layer; and patternedly formed in the substrate a first metal layer on the gate insulating layer, the first metal layer including a gate electrode and a scan line; an interlayer dielectric layer covering the gate electrode and the scan line; and patternedly formed on the interlayer dielectric layer a second metal layer, the second metal layer including the source electrode, the drain electrode, and a data line, the source electrode being disposed through the interlayer dielectric layer and the gate insulating layer a via is connected to the first contact layer, the drain electrode being connected to the second contact layer through a second via provided in the interlayer dielectric layer and the gate insulating layer; covering the a planarization layer of the source electrode, the drain electrode, and the data line; a transparent conductive layer patternedly formed on the planarization layer, the transparent conductive layer including a pixel electrode, the pixel electrode being disposed on the planarization layer a third
  • the active layer further includes a storage capacitor region, and the storage capacitor region includes a polysilicon layer and a boron-doped polysilicon layer disposed on the substrate substrate in sequence.
  • the thickness of the first contact layer and the second contact layer are respectively 20 to 200 nm.
  • Another aspect of the present invention is to provide a display device including the thin film transistor array substrate as described above.
  • a polycrystalline silicon film is prepared by using a solid phase crystallization method as an active layer, wherein a boron-doped amorphous silicon germanium thin film layer is prepared on the amorphous silicon thin film layer.
  • the boron-doped amorphous silicon germanium film can induce the conversion of the amorphous silicon film layer into a polysilicon film, thereby reducing the crystallization temperature of the amorphous silicon film and shortening the crystallization time, thereby avoiding lining
  • the base substrate is deformed by high temperature, which also improves production efficiency.
  • 1a-1k are exemplary illustrations of device structures obtained in various steps in a method of fabricating a thin film transistor array substrate according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a thin film transistor array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a display device according to an embodiment of the present invention.
  • This embodiment first provides a method for fabricating a thin film transistor array substrate. Referring to FIGS. 1a-1k, the method includes the steps of:
  • a patterned active layer 20 is formed on the base substrate 10. This step may specifically include:
  • an amorphous silicon (a-Si) thin film layer 21a and a boron-doped amorphous silicon germanium (a-SiGe) thin film layer 22a are sequentially deposited on the base substrate 10.
  • a buffer layer 11 may be first prepared on the base substrate 10 before depositing the amorphous silicon (a-Si) thin film layer 21a and the boron-doped amorphous silicon germanium (a-SiGe) thin film layer 22a.
  • the buffer layer 11 may be a silicon oxide (SiO x ) layer or a silicon nitride (SiN x ) layer or a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
  • the main raw material is a material for forming an amorphous silicon thin film, and at the same time, GeH 4 and BH 3 gases are also introduced, thereby obtaining boron-doped amorphous silicon. ⁇ film layer 22a.
  • the boron-doped amorphous silicon germanium thin film layer 22a may have a thickness of 20 to 200 nm.
  • S12 is subjected to a crystallization treatment by a solid phase crystallization method.
  • the amorphous silicon thin film layer 21a and the boron-doped amorphous silicon germanium thin film layer 22a are placed in an annealing furnace, and the amorphous silicon thin film layer 21a and boron doped are subjected to a rapid thermal annealing process.
  • the amorphous silicon germanium thin film layer 22a is subjected to crystallization treatment, and the amorphous silicon thin film layer 21a is converted into a polycrystalline silicon (poly-Si) thin film layer 21, and the boron-doped amorphous silicon germanium thin film layer 22a is converted into a blend.
  • the temperature of the thermal annealing process is 500 to 1000 ° C, and the time is 5 to 60 min.
  • the polysilicon thin film layer 21 and the polysilicon germanium thin film layer 22 are etched to form a patterned active layer 20 by using a photolithography process, and the active layer 20 includes an active region 20a.
  • the active region 20a includes a channel region 211 and a source region 212 and a drain region 213 respectively located on both sides of the channel region.
  • the active region 20a is etched by the polysilicon film layer 21, and the polysilicon germanium film layer 22 above the source region 212 is left to form a first contact layer 221, above the drain region 213.
  • the polysilicon germanium film layer 22 is retained to form a second contact layer 222, and the polysilicon germanium film layer 22 above the channel region 211 is completely etched away.
  • the active layer 20 further includes a storage capacitor region 20b disposed in the same layer as the active region 20a, and the storage capacitor region 20b includes a stacked polysilicon layer 214 and A boron doped polysilicon layer 223.
  • the polysilicon film layer 21 and the polysilicon germanium film layer 22 are subjected to a patterning process (lithography process)
  • the polysilicon film layer 21 and the portion are retained corresponding to the position of the storage capacitor region 20b.
  • the polysilicon germanium film layer 22 is formed by etching the polysilicon film layer 21, and the polysilicon germanium layer 223 is formed by etching the polysilicon germanium film layer 22.
  • a gate insulating layer 30 is formed on the active layer 20.
  • the gate insulating layer 30 may be a silicon oxide (SiO x ) layer or a silicon nitride (SiN x ) layer or a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
  • a patterned first metal layer 40 is formed on the gate insulating layer 30 by using a photolithography process.
  • the first metal layer 40 includes a gate electrode 41 and a scan line 42.
  • the gate electrode 41 is located directly above the channel region 211, and one of the scan lines 42 is located directly above the storage capacitor region 20b.
  • the material of the first metal layer 40 is selected from, but not limited to, Cr, One or more of Mo, Al, and Cu may be stacked in one or more layers.
  • an interlayer dielectric layer 50 is formed on the gate electrode 41 and the scan line 42.
  • the interlayer dielectric layer 50 may be a silicon oxide (SiO x ) layer or a silicon nitride (SiN x ) layer or a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
  • the second metal layer 60 includes the source electrode 61 and the leakage current. a pole 62 and a data line 63, the source electrode 61 being connected to the first contact layer 221 through the first via 51, and the drain electrode 62 being connected to the second contact through the second via 52 Layer 222.
  • the material of the second metal layer 60 is selected from one or more of Cr, Mo, Al, and Cu, and may be one or more layers.
  • One of the data lines 63 is located directly above the storage capacitor region 20b.
  • a planarization layer 70 is formed on the source electrode 61, the drain electrode 62, and the data line 63.
  • the planarization layer 70 may be a silicon oxide (SiO x ) layer or a silicon nitride (SiN x ) layer or a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
  • a third via 71 exposing the drain electrode 62 is etched in the planarization layer 70 by a photolithography process.
  • a patterned transparent conductive layer 80 is formed on the planarization layer 70 by using a photolithography process, the transparent conductive layer 80 includes a pixel electrode 81, and the pixel electrode 81 passes through the The third via 71 is connected to the drain electrode 62.
  • the third via 71 may be disposed to correspond to the position of the source electrode 61.
  • the pixel electrode 81 passes through the third via. 71 is connected to the source electrode 61.
  • a photolithography process (patterning process) is employed in a plurality of steps.
  • Each of the photolithography processes includes masking, exposure, development, etching, and stripping processes, respectively, wherein the etching process includes dry etching and wet etching.
  • the lithography process has been a relatively mature process technology in the art and will not be described in detail herein.
  • a polycrystalline silicon film is prepared by using a solid phase crystallization method as an active layer, wherein a boron-doped amorphous silicon germanium thin film layer is prepared on the amorphous silicon thin film layer.
  • the solid phase crystallization treatment is performed, the crystallization process starts from the boron-doped amorphous silicon germanium thin film layer, and the boron-doped amorphous silicon germanium thin film layer has a lower crystallization temperature, which can be faster at a lower temperature.
  • the ground is transformed into a boron-doped polysilicon germanium film layer, thereby inducing the conversion of the amorphous silicon film layer into a polysilicon film, thereby reducing the crystallization temperature of the amorphous silicon film and shortening the crystallization time, thereby avoiding deformation of the substrate substrate due to high temperature. It also improves production efficiency.
  • the boron-doped amorphous silicon germanium thin film layer is formed by a deposition process, and the amorphous silicon thin film material is deposited while introducing GeH 4 and BH 3 gas, thereby obtaining boron-doped amorphous.
  • the silicon germanium film layer is less expensive to produce than the ion implantation method.
  • the present embodiment further provides a thin film transistor array substrate obtained by the above preparation method.
  • the thin film transistor array substrate includes an active layer 20 and a gate insulating layer which are sequentially disposed on the base substrate 10. 30.
  • a buffer layer 11 is further disposed between the active layer 20 and the base substrate 10.
  • the active layer 20 includes an active region 20a including a channel region 211 and a source region 212 and a drain region 213 respectively located on opposite sides of the channel region 211, the source region
  • the first contact layer 221 is disposed on the 212
  • the material of the active layer 20a is polysilicon
  • the material of the first contact layer 221 and the second contact layer 222 is boron doped polysilicon.
  • the active layer 20 further includes a storage capacitor region 20b disposed in the same layer as the active region 20a, and the storage capacitor region 20b includes a stacked polysilicon layer 214 and a boron-doped polysilicon layer. 223.
  • the thickness of the first contact layer 221 and the second contact layer 222 is preferably set to 20 to 200 nm.
  • the first metal layer 40 includes a gate electrode 41 and a scan line 42.
  • the gate electrode 41 is located directly above the channel region 211, and one scan line 42 is opposite to the storage capacitor region 20b. Directly above.
  • the second metal layer 60 includes the source electrode 61, the drain electrode 62, and the data line 63.
  • the source electrode 61 is connected to the first contact layer 221 through a first via 51 provided in the interlayer dielectric layer 50 and the gate insulating layer 30, and the drain electrode 62 is disposed through the The interlayer dielectric layer 50 and the second via 52 in the gate insulating layer 30 are connected to the second contact layer 222, and one of the data lines 63 is located directly above the storage capacitor region 20b.
  • the transparent conductive layer 80 includes a pixel electrode 81 connected to the drain electrode 62 through a third via 71 provided in the planarization layer 70.
  • the pixel electrode 81 may also be connected to the source electrode 61 through the third via 71.
  • the source electrode 61 and the drain electrode 62 are connected to the corresponding source region through the first contact layer 221 and the second contact layer 222 of a material doped with boron-doped polysilicon.
  • 212 and the drain region 213 reduce the contact resistance between the source electrode 61 and the source region 212, between the drain electrode 62 and the drain region 213, and improve the electrical performance of the thin film transistor.
  • the embodiment further provides a display device in which the thin film transistor array substrate provided by the embodiment of the present invention is used.
  • the display device can be a thin film transistor liquid crystal display device (TFT-LCD) or an organic electroluminescence display device (OLED), and the thin film transistor array substrate provided by the embodiment of the invention can be used to make the display device compare with the prior art. It has superior performance while reducing costs.
  • the thin film transistor liquid crystal display device is taken as an example.
  • the liquid crystal display device includes a liquid crystal panel 1 and a backlight module 2 .
  • the liquid crystal panel 1 is opposite to the backlight module 2 , and the backlight module is disposed.
  • the liquid crystal panel 1 includes an array substrate 101 and a filter substrate 102 disposed opposite to each other, and further includes a liquid crystal layer 103 between the array substrate 101 and the filter substrate 102.
  • the array substrate 101 adopts the thin film transistor array substrate provided by the embodiment of the invention.

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Abstract

提供一种薄膜晶体管阵列基板的制备方法、薄膜晶体管阵列基板以及包含该阵列基板的显示装置，包括在衬底基板（10）上制备形成图案化的有源层（20）的步骤，该步骤包括：在衬底基板（10）上依次制备形成非晶硅薄膜层（21a）和掺杂硼的非晶硅锗薄膜层（22a）；采用热退火工艺对所述非晶硅薄膜层（21a）和掺杂硼的非晶硅锗薄膜层（22a）进行晶化处理，获得多晶硅薄膜层（21）和掺杂硼的多晶硅锗薄膜层（22）；应用光刻工艺，将所述多晶硅薄膜层（21）和所述多晶硅锗薄膜层（22）刻蚀形成图案化的有源层（20），所述有源层（20）包括有源区（20a），所述有源区（20a）包括沟道区（211）和分别位于所述沟道区（211）两侧的源极区（212）和漏极区（213）。

Description

薄膜晶体管阵列基板及其制备方法、显示装置 技术领域
本发明涉及显示器技术领域，尤其涉及一种薄膜晶体管阵列基板及其制备方法，还涉及包含该薄膜晶体管阵列基板的显示装置。
背景技术
平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平板显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机电致发光显示装置(Organic Light Emitting Display，OLED)。薄膜晶体管(Thin Film Transistor，TFT)是平板显示装置的重要组成部分，可形成在玻璃基板或塑料基板上，通常作为开光装置和驱动装置用在诸如LCD、OLED。
多晶硅(Poly-Si)薄膜是由许多大小不等和晶面取向不同的小晶粒组成，晶粒尺寸一般在几十到几百纳米之间，大晶粒尺寸可达数微米。大晶粒的多晶硅薄膜有较高的迁移率，接近块状材料的迁移率，因此多晶硅薄膜其已被广泛应用于半导体器件的制作中。例如在LCD或OLED产品中薄膜晶体管，大多采用多晶硅薄膜作为有源层。
目前多晶硅薄膜的制备方法，主要是先制备非晶硅(a-Si)薄膜，然后对非晶硅薄膜进行晶化处理获得多晶硅薄膜。对非晶硅薄膜进行晶化处理主要有：准分子激光退火法(Excimer LaserAnneal，ELA)、金属诱导晶化法(Metal Induced Crystallized，MIC)、金属横向诱导晶化法(Metal Induced Lateral Crystallization，MILC)和固相晶化法(Solid-phase Crystallization，SPC)等。采用ELA晶化法制得的poly-Si，其缺隙态密度低且难以制作大面积poly-Si薄膜，另外该方法使用的设备昂贵，成本高。采用MIC、MILC晶化法制得的poly-Si薄膜中，金属残留大，导致TFT特性变差。采用SPC晶化法，可以制备得到晶粒尺寸较大的poly-Si薄膜，但是若将方法应用于制备薄膜晶体管阵列基板中时，由于衬底基板在高温时极易变形，需要将晶化的温度设置为较低，晶化温度的降低导致晶化的时间需要大幅度增加，降低生产效率。
发明内容
有鉴于此，本发明提供了一种薄膜晶体管阵列基板的制备方法，采用固相晶化法制备多晶硅薄膜作为有源层，该方法可以降低结晶温度，避免衬底基板发生变形，同时该方法又可以缩短结晶时间，提高生产效率。
为了实现上述目的，本发明采用了如下的技术方案：
一种薄膜晶体管阵列基板的制备方法，包括在衬底基板上制备形成图案化的有源层的步骤，其包括：
在衬底基板上依次制备形成非晶硅薄膜层和掺杂硼的非晶硅锗薄膜层；
采用热退火工艺对所述非晶硅薄膜层和掺杂硼的非晶硅锗薄膜层进行晶化处理，将所述非晶硅薄膜层转化为多晶硅薄膜层，将所述掺杂硼的非晶硅锗薄膜层转化为掺杂硼的多晶硅锗薄膜层；
应用光刻工艺，将所述多晶硅薄膜层和所述多晶硅锗薄膜层刻蚀形成图案化的有源层，所述有源层包括有源区，所述有源区包括沟道区和分别位于所述沟道区两侧的源极区和漏极区；其中，所述有源区由所述多晶硅薄膜层刻蚀形成，所述源极区上方的多晶硅锗薄膜层被保留以形成第一接触层，所述漏极区上方的多晶硅锗薄膜层被保留以形成第二接触层。
其中，该方法具体包括步骤：
S1、在衬底基板上制备形成图案化的有源层；
S2、在所述有源层上制备形成栅极绝缘层；
S3、应用光刻工艺，在所述栅极绝缘层上制备形成图案化的第一金属层，所述第一金属层包括栅电极和扫描线；
S4、在所述栅电极和扫描线上制备形成层间介质层；
S5、应用光刻工艺，在所述层间介质层和所述栅极绝缘层中刻蚀形成暴露出所述第一接触层的第一过孔、暴露出所述第二接触层的第二过孔；
S6、应用光刻工艺，在所述层间介质层上制备形成图案化的第二金属层，所述第二金属层包括源电极、漏电极和数据线，所述源电极通过所述第一过孔连接到所述第一接触层，所述漏电极通过所述第二过孔连接到所述第二接触层；
S7、在所述源电极、漏电极和数据线上制备形成平坦化层；
S8、应用光刻工艺，在所述平坦化层中刻蚀形成暴露出所述源电极或所述漏电极的第三过孔；
S9、应用光刻工艺，在所述平坦化层上制备形成图案化的透明导电层，所述透明导电层包括像素电极，所述像素电极通过所述第三过孔连接到所述源电极或所述漏电极。
其中，进行热退火工艺的温度为500～1000℃，时间为5～60min。
其中，所述有源层还包括存储电容区，进行图案化处理时，所述存储电容区同时保留所述多晶硅薄膜层和所述多晶硅锗薄膜层。
其中，所述掺杂硼的非晶硅锗薄膜层的厚度为20～200nm。
本发明还提供了一种薄膜晶体管阵列基板，包括设置在衬底基板上的有源层、源电极和漏电极，其中，所述有源层包括有源区，所述有源区包括沟道区和分别位于所述沟道区两侧的源极区和漏极区，所述源极区上设置有第一接触层，所述源电极通过所述第一接触层电性连接到所述源极区，所述漏极区上设置有第二接触层，所述漏电极通过所述第二接触层电性连接到所述漏极区；所述有源层的材料为多晶硅，所述第一接触层和所述第二接触层的材料为掺杂硼的多晶硅锗。
其中，所述薄膜晶体管阵列基板包括：衬底基板；图案化地形成于所述衬底基板上的所述有源层；覆盖所述有源层的栅极绝缘层；图案化地形成于所述栅极绝缘层上的第一金属层，所述第一金属层包括栅电极和扫描线；覆盖所述栅电极和扫描线的层间介质层；图案化地形成于所述层间介质层上的第二金属层，所述第二金属层包括所述源电极、所述漏电极和数据线，所述源电极通过设置在所述层间介质层和所述栅极绝缘层中的第一过孔连接到所述第一接触层，所述漏电极通过设置在所述层间介质层和所述栅极绝缘层中的第二过孔连接到所述第二接触层；覆盖所述源电极、漏电极和数据线的平坦化层；图案化地形成于所述平坦化层上的透明导电层，所述透明导电层包括像素电极，所述像素电极通过设置在所述平坦化层中的第三过孔连接到所述源电极或所述漏电极。
其中，所述有源层还包括存储电容区，所述存储电容区包括依次设置在所述衬底基板上多晶硅层和掺杂硼的多晶硅锗层。
其中，所述第一接触层和所述第二接触层的厚度分别为20～200nm。
本发明的另一方面是提供一种显示装置，其包括如上所述的薄膜晶体管阵列基板。
本发明实施例中提供的薄膜晶体管阵列基板的制备方法，采用固相晶化法制备多晶硅薄膜作为有源层，其中，在非晶硅薄膜层上制备掺杂硼的非晶硅锗薄膜层，在进行固相晶化处理时，掺杂硼的非晶硅锗薄膜可以诱导非晶硅薄膜层转化为多晶硅薄膜，由此降低了非晶硅薄膜的结晶温度并缩短结晶时间，不仅可以避免衬底基板因高温发生变形，还提高了生产效率。
附图说明
图1a-图1k是本发明实施例的薄膜晶体管阵列基板的制备方法中，各个步骤得到的器件结构的示例性图示；
图2是本发明实施例提供的薄膜晶体管阵列基板的结构示意图；
图3是本发明实施例提供的显示装置的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明的具体实施方式进行详细说明。这些优选实施方式的示例在附图中进行了例示。附图中所示和根据附图描述的本发明的实施方式仅仅是示例性的，并且本发明并不限于这些实施方式。
在此，还需要说明的是，为了避免因不必要的细节而模糊了本发明，在附图中仅仅示出了与根据本发明的方案密切相关的结构和/或处理步骤，而省略了与本发明关系不大的其他细节。
本实施例首先提供了一种薄膜晶体管阵列基板的制备方法，参阅图1a-图1k，该方法包括步骤：
S1、在衬底基板10上制备形成图案化的有源层20。该步骤可以具体包括：
S11、如图1a所示，在衬底基板10上依次沉积形成非晶硅(a-Si)薄膜层21a和掺杂硼的非晶硅锗(a-SiGe)薄膜层22a。优选的是，在沉积非晶硅(a-Si)薄膜层21a和掺杂硼的非晶硅锗(a-SiGe)薄膜层22a之前，还可以在衬底基板10上首先制备一缓冲层11，所述缓冲层11可以是氧化硅(SiOx)层或氮化硅 (SiNx)层或者是氧化硅层与氮化硅层叠加的复合结构层。其中，在沉积掺杂硼的非晶硅锗薄膜层22a时，主要的原料还是形成非晶硅薄膜的材料，同时还通入GeH4和BH3气体，由此获得掺杂硼的非晶硅锗薄膜层22a。优选的方案中，所述掺杂硼的非晶硅锗薄膜层22a的厚度可以选择为20～200nm。
S12、如图1b所示，应用固相晶化法进行晶化处理。具体地，将沉积了非晶硅薄膜层21a和掺杂硼的非晶硅锗薄膜层22a放入到退火炉中，采用快速热退火工艺对所述非晶硅薄膜层21a和掺杂硼的非晶硅锗薄膜层22a进行晶化处理，将所述非晶硅薄膜层21a转化为多晶硅(poly-Si)薄膜层21，将所述掺杂硼的非晶硅锗薄膜层22a转化为掺杂硼的多晶硅锗(poly-SiGe)薄膜层22。其中，进行热退火工艺的温度为500～1000℃，时间为5～60min。
S13、如图1c所示，应用光刻工艺，将所述多晶硅薄膜层21和所述多晶硅锗薄膜层22刻蚀形成图案化的有源层20，所述有源层20包括有源区20a，所述有源区20a包括沟道区211和分别位于所述沟道区两侧的源极区212和漏极区213。其中，所述有源区20a由所述多晶硅薄膜层21刻蚀形成，所述源极区212上方的多晶硅锗薄膜层22被保留以形成第一接触层221，所述漏极区213上方的多晶硅锗薄膜层22被保留以形成第二接触层222，所述沟道区211上方的多晶硅锗薄膜层22则完全刻蚀去除。
在本实施例中，如图1c所示，所述有源层20还包括与所述有源区20a同层设置的存储电容区20b，所述存储电容区20b包括叠层的多晶硅层214和掺杂硼的多晶硅锗层223。具体地，在对所述多晶硅薄膜层21和所述多晶硅锗薄膜层22进行图案化处理(光刻工艺)时，对应于所述存储电容区20b的位置同时保留所述多晶硅薄膜层21和所述多晶硅锗薄膜层22，所述多晶硅层214由所述多晶硅薄膜层21刻蚀形成，所述多晶硅锗层223则是由所述多晶硅锗薄膜层22刻蚀形成。
S2、如图1d所示，在所述有源层20上制备形成栅极绝缘层30。具体地，所述栅极绝缘层30可以是氧化硅(SiOx)层或氮化硅(SiNx)层或者是氧化硅层与氮化硅层叠加的复合结构层。
S3、如图1e所示，应用光刻工艺，在所述栅极绝缘层30上制备形成图案化的第一金属层40，所述第一金属层40包括栅电极41和扫描线42。具体地，所述栅电极41相对位于所述沟道区211的正上方，其中的一个扫描线42相对位于所述存储电容区20b的正上方。所述第一金属层40的材料选自但不限于Cr、 Mo、Al、Cu中的一种或多种，可为一层或多层堆叠。
S4、如图1f所示，在所述栅电极41和扫描线42上制备形成层间介质层50。具体地，所述层间介质层50可以是氧化硅(SiOx)层或氮化硅(SiNx)层或者是氧化硅层与氮化硅层叠加的复合结构层。
S5、如图1g所示，应用光刻工艺，在所述层间介质层50和所述栅极绝缘层30中刻蚀形成暴露出所述第一接触层221的第一过孔51以及暴露出所述第二接触层222的第二过孔52。
S6、如图1h所示，应用光刻工艺，在所述层间介质层50上制备形成图案化的第二金属层60，所述第二金属层60包括所述源电极61、所述漏电极62和数据线63，所述源电极61通过所述第一过孔51连接到所述第一接触层221，所述漏电极62通过所述第二过孔52连接到所述第二接触层222。其中，所述第二金属层60的材料选自但不限于Cr、Mo、Al、Cu中的一种或多种，可为一层或多层堆叠。其中的一个数据线63相对位于所述存储电容区20b的正上方。
S7、如图1i所示，在所述源电极61、漏电极62和数据线63上制备形成平坦化层70。具体地，所述平坦化层70可以是氧化硅(SiOx)层或氮化硅(SiNx)层或者是氧化硅层与氮化硅层叠加的复合结构层。
S8、如图1j所示，应用光刻工艺，在所述平坦化层70中刻蚀形成暴露出所述漏电极62的第三过孔71。
S9、如图1k所示，应用光刻工艺，在所述平坦化层70上制备形成图案化的透明导电层80，所述透明导电层80包括像素电极81，所述像素电极81通过所述第三过孔71连接到所述漏电极62。
需要说明的是，步骤S8中，所述第三过孔71也可以是设置为对应于所述源电极61的位置，此时，步骤S9中，所述像素电极81通过所述第三过孔71连接到所述源电极61。
以上的工艺过程中，在多个步骤中采用了光刻工艺(构图工艺)。其中，每一次光刻工艺中又分别包括掩膜、曝光、显影、刻蚀和剥离等工艺，其中刻蚀工艺包括干法刻蚀和湿法刻蚀。光刻工艺已经是本领域中的比较成熟的工艺技术，在此不再展开详细说明。
以上实施例中提供的薄膜晶体管阵列基板的制备方法，采用固相晶化法制 备多晶硅薄膜作为有源层，其中，在非晶硅薄膜层上制备掺杂硼的非晶硅锗薄膜层，在进行固相晶化处理时，晶化过程从掺杂硼的非晶硅锗薄膜层开始，掺杂硼的非晶硅锗薄膜层的晶化温度较低，其可以在较低温度下较快地转化为掺杂硼的多晶硅锗薄膜层，进而诱导非晶硅薄膜层转化为多晶硅薄膜，由此降低了非晶硅薄膜的结晶温度并缩短结晶时间，不仅可以避免衬底基板因高温发生变形，还提高了生产效率。本发明实施例中，掺杂硼的非晶硅锗薄膜层是通过沉积工艺制备形成，在沉积非晶硅薄膜材料的同时通入GeH4和BH3气体，由此获得掺杂硼的非晶硅锗薄膜层，相比于离子植入的方式，其生产成本更低。
本实施例还提供了按照如上的制备方法制备获得的薄膜晶体管阵列基板，如图2所示，所述薄膜晶体管阵列基板包括依次设置在衬底基板10上的有源层20、栅极绝缘层30、第一金属层40、层间介质层50、第二金属层60、平坦化层70和透明导电层80。
其中，所述有源层20和所述衬底基板10之间还设置有缓冲层11。所述有源层20包括有源区20a，所述有源区20a包括沟道区211和分别位于所述沟道区211两侧的源极区212和漏极区213，所述源极区212上设置有第一接触层221，所述有源层20a的材料为多晶硅，所述第一接触层221和所述第二接触层222的材料为掺杂硼的多晶硅锗。本实施例中，所述有源层20还包括与所述有源区20a同层设置的存储电容区20b，所述存储电容区20b包括叠层的多晶硅层214和掺杂硼的多晶硅锗层223。优选的方案中，所述第一接触层221和所述第二接触层222的厚度优选设置为20～200nm。
其中，所述第一金属层40包括栅电极41和扫描线42，所述栅电极41相对位于所述沟道区211的正上方，其中的一个扫描线42相对位于所述存储电容区20b的正上方。
其中，所述第二金属层60包括所述源电极61、所述漏电极62和数据线63。所述源电极61通过设置在所述层间介质层50和所述栅极绝缘层30中的第一过孔51连接到所述第一接触层221，所述漏电极62通过设置在所述层间介质层50和所述栅极绝缘层30中的第二过孔52连接到所述第二接触层222，其中的一个数据线63相对位于所述存储电容区20b的正上方。
其中，所述透明导电层80包括像素电极81，所述像素电极81通过设置在所述平坦化层70中的第三过孔71连接到所述漏电极62。在另外的一些实施例中，所述像素电极81也可以是通过所述第三过孔71连接到所述源电极61。
如上实施例提供的薄膜晶体管阵列基板中，所述源电极61和所述漏电极62通过材料为掺杂硼的多晶硅锗的第一接触层221和第二接触层222连接到对应的源极区212和漏极区213，降低源电极61与源极区212之间、漏电极62与漏极区213之间的接触电阻，提升薄膜晶体管的电性能。
本实施例还提供了一种显示装置，其中采用了本发明实施例提供的薄膜晶体管阵列基板。该显示装置例如可以是薄膜晶体管液晶显示装置(TFT-LCD)或有机电致发光显示装置(OLED)，采用了本发明实施例提供的薄膜晶体管阵列基板，可以使得显示装置相比于现有技术具有更优越的性能，同时还降低了成本。具体地，以薄膜晶体管液晶显示装置为例，参阅图3，该液晶显示装置包括液晶面板1及背光模组2，所述液晶面板1与所述背光模组2相对设置，所述背光模组2提供显示光源给所述液晶面板1，以使所述液晶面板1显示影像。其中，液晶面板1包括相对设置的阵列基板101和滤光基板102，还包括位于阵列基板101和滤光基板102之间的液晶层103。其中，阵列基板101即采用了本发明实施例提供的薄膜晶体管阵列基板。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个......”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (18)

  1. 一种薄膜晶体管阵列基板的制备方法，包括在衬底基板上制备形成图案化的有源层的步骤，其中，包括：
    在衬底基板上依次制备形成非晶硅薄膜层和掺杂硼的非晶硅锗薄膜层；
    采用热退火工艺对所述非晶硅薄膜层和掺杂硼的非晶硅锗薄膜层进行晶化处理，将所述非晶硅薄膜层转化为多晶硅薄膜层，将所述掺杂硼的非晶硅锗薄膜层转化为掺杂硼的多晶硅锗薄膜层；
    应用光刻工艺，将所述多晶硅薄膜层和所述多晶硅锗薄膜层刻蚀形成图案化的有源层，所述有源层包括有源区，所述有源区包括沟道区和分别位于所述沟道区两侧的源极区和漏极区；其中，所述有源区由所述多晶硅薄膜层刻蚀形成，所述源极区上方的多晶硅锗薄膜层被保留以形成第一接触层，所述漏极区上方的多晶硅锗薄膜层被保留以形成第二接触层。
  2. 根据权利要求1所述的薄膜晶体管阵列基板的制备方法，其中，该方法具体包括步骤：
    S1、在衬底基板上制备形成图案化的有源层；
    S2、在所述有源层上制备形成栅极绝缘层；
    S3、应用光刻工艺，在所述栅极绝缘层上制备形成图案化的第一金属层，所述第一金属层包括栅电极和扫描线；
    S4、在所述栅电极和扫描线上制备形成层间介质层；
    S5、应用光刻工艺，在所述层间介质层和所述栅极绝缘层中刻蚀形成暴露出所述第一接触层的第一过孔、暴露出所述第二接触层的第二过孔；
    S6、应用光刻工艺，在所述层间介质层上制备形成图案化的第二金属层，所述第二金属层包括源电极、漏电极和数据线，所述源电极通过所述第一过孔连接到所述第一接触层，所述漏电极通过所述第二过孔连接到所述第二接触层；
    S7、在所述源电极、漏电极和数据线上制备形成平坦化层；
    S8、应用光刻工艺，在所述平坦化层中刻蚀形成暴露出所述源电极或所述漏电极的第三过孔；
    S9、应用光刻工艺，在所述平坦化层上制备形成图案化的透明导电层，所述透明导电层包括像素电极，所述像素电极通过所述第三过孔连接到所述源电极或所述漏电极。
  3. 根据权利要求1所述的薄膜晶体管阵列基板的制备方法，其中，进行热退火工艺的温度为500～1000℃，时间为5～60min。
  4. 根据权利要求1所述的薄膜晶体管阵列基板的制备方法，其中，所述有源层还包括存储电容区，进行图案化处理时，所述存储电容区同时保留所述多晶硅薄膜层和所述多晶硅锗薄膜层。
  5. 根据权利要求1所述的薄膜晶体管阵列基板的制备方法，其中，所述掺杂硼的非晶硅锗薄膜层的厚度为20～200nm。
  6. 根据权利要求1所述的薄膜晶体管阵列基板的制备方法，其中，所述掺杂硼的非晶硅锗薄膜层是通过沉积工艺制备形成，在沉积非晶硅薄膜材料的同时通入GeH4和BH3气体，由此获得所述掺杂硼的非晶硅锗薄膜层。
  7. 一种薄膜晶体管阵列基板，包括设置在衬底基板上的有源层、源电极和漏电极，其中，所述有源层包括有源区，所述有源区包括沟道区和分别位于所述沟道区两侧的源极区和漏极区，所述源极区上设置有第一接触层，所述源电极通过所述第一接触层电性连接到所述源极区，所述漏极区上设置有第二接触层，所述漏电极通过所述第二接触层电性连接到所述漏极区；所述有源层的材料为多晶硅，所述第一接触层和所述第二接触层的材料为掺杂硼的多晶硅锗。
  8. 根据权利要求7所述的薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括：
    衬底基板；
    图案化地形成于所述衬底基板上的所述有源层；
    覆盖所述有源层的栅极绝缘层；
    图案化地形成于所述栅极绝缘层上的第一金属层，所述第一金属层包括栅电极和扫描线；
    覆盖所述栅电极和扫描线的层间介质层；
    图案化地形成于所述层间介质层上的第二金属层，所述第二金属层包括所 述源电极、所述漏电极和数据线，所述源电极通过设置在所述层间介质层和所述栅极绝缘层中的第一过孔连接到所述第一接触层，所述漏电极通过设置在所述层间介质层和所述栅极绝缘层中的第二过孔连接到所述第二接触层；
    覆盖所述源电极、漏电极和数据线的平坦化层；
    图案化地形成于所述平坦化层上的透明导电层，所述透明导电层包括像素电极，所述像素电极通过设置在所述平坦化层中的第三过孔连接到所述源电极或所述漏电极。
  9. 根据权利要求8所述的薄膜晶体管阵列基板，其中，所述有源层还包括存储电容区，所述存储电容区包括依次设置在所述衬底基板上多晶硅层和掺杂硼的多晶硅锗层。
  10. 根据权利要求8所述的薄膜晶体管阵列基板，其中，所述第一接触层和所述第二接触层的厚度分别为20～200nm。
  11. 根据权利要求8所述的薄膜晶体管阵列基板，其中，所述第一金属层为一层或多层堆叠，其材料选自Cr、Mo、Al、Cu中的一种或多种；所述第二金属层为一层或多层堆叠，其材料选自Cr、Mo、Al、Cu中的一种或多种。
  12. 根据权利要求8所述的薄膜晶体管阵列基板，其中，所述栅极绝缘层为氧化硅层或氮化硅层或者是氧化硅层与氮化硅层叠加的复合结构层；所述层间介质层为氧化硅层或氮化硅层或者是氧化硅层与氮化硅层叠加的复合结构层；所述平坦化层为氧化硅层或氮化硅层或者是氧化硅层与氮化硅层叠加的复合结构层。
  13. 一种显示装置，包括薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括设置在衬底基板上的有源层、源电极和漏电极，其中，所述有源层包括有源区，所述有源区包括沟道区和分别位于所述沟道区两侧的源极区和漏极区，所述源极区上设置有第一接触层，所述源电极通过所述第一接触层电性连接到所述源极区，所述漏极区上设置有第二接触层，所述漏电极通过所述第二接触层电性连接到所述漏极区；所述有源层的材料为多晶硅，所述第一接触层和所述第二接触层的材料为掺杂硼的多晶硅锗。
  14. 根据权利要求13所述的显示装置，其中，所述薄膜晶体管阵列基板包括：
    衬底基板；
    图案化地形成于所述衬底基板上的所述有源层；
    覆盖所述有源层的栅极绝缘层；
    图案化地形成于所述栅极绝缘层上的第一金属层，所述第一金属层包括栅电极和扫描线；
    覆盖所述栅电极和扫描线的层间介质层；
    图案化地形成于所述层间介质层上的第二金属层，所述第二金属层包括所述源电极、所述漏电极和数据线，所述源电极通过设置在所述层间介质层和所述栅极绝缘层中的第一过孔连接到所述第一接触层，所述漏电极通过设置在所述层间介质层和所述栅极绝缘层中的第二过孔连接到所述第二接触层；
    覆盖所述源电极、漏电极和数据线的平坦化层；
    图案化地形成于所述平坦化层上的透明导电层，所述透明导电层包括像素电极，所述像素电极通过设置在所述平坦化层中的第三过孔连接到所述源电极或所述漏电极。
  15. 根据权利要求14所述的显示装置，其中，所述有源层还包括存储电容区，所述存储电容区包括依次设置在所述衬底基板上多晶硅层和掺杂硼的多晶硅锗层。
  16. 根据权利要求14所述的显示装置，其中，所述第一接触层和所述第二接触层的厚度分别为20～200nm。
  17. 根据权利要求14所述的显示装置，其中，所述第一金属层为一层或多层堆叠，其材料选自Cr、Mo、Al、Cu中的一种或多种；所述第二金属层为一层或多层堆叠，其材料选自Cr、Mo、Al、Cu中的一种或多种。
  18. 根据权利要求14所述的显示装置，其中，所述栅极绝缘层为氧化硅层或氮化硅层或者是氧化硅层与氮化硅层叠加的复合结构层；所述层间介质层为氧化硅层或氮化硅层或者是氧化硅层与氮化硅层叠加的复合结构层；所述平坦化层为氧化硅层或氮化硅层或者是氧化硅层与氮化硅层叠加的复合结构层。
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