WO2019105012A1 - 阵列基板及其制造方法及显示屏 - Google Patents

阵列基板及其制造方法及显示屏 Download PDF

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Publication number
WO2019105012A1
WO2019105012A1 PCT/CN2018/091860 CN2018091860W WO2019105012A1 WO 2019105012 A1 WO2019105012 A1 WO 2019105012A1 CN 2018091860 W CN2018091860 W CN 2018091860W WO 2019105012 A1 WO2019105012 A1 WO 2019105012A1
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Prior art keywords
flexible substrate
array substrate
peripheral metal
display area
layer
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PCT/CN2018/091860
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English (en)
French (fr)
Inventor
刘明星
张德强
吕东芸
王徐亮
甘帅燕
高峰
Original Assignee
昆山国显光电有限公司
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Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Publication of WO2019105012A1 publication Critical patent/WO2019105012A1/zh
Priority to US16/513,734 priority Critical patent/US10985195B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Definitions

  • the present application relates to the field of display technologies, and in particular to an array substrate, a method of manufacturing the same, and a display screen.
  • the display includes a display area (AA area) and a non-display area (non-AA area).
  • the non-display area may be required to be bent.
  • the non-display area is bent to the back of the screen to reduce the width of the frame.
  • An array substrate includes a display area and a non-display area, the non-display area being located outside the display area; the non-display area comprising:
  • a peripheral metal trace the peripheral metal trace being located in the recess.
  • the flexible substrate surface is provided with a groove, and the peripheral metal trace is located in the groove, so that the thickness of the flexible substrate at the peripheral metal trace is reduced, and the flexible substrate to the peripheral metal trace is reduced during the bending process.
  • the arrangement of the grooves during bending can also effectively release the stress of the flexible substrate; thereby effectively preventing the breakage of the peripheral metal traces and improving the reliability of the array substrate.
  • the depths of the plurality of grooves are not completely the same.
  • the non-display area further includes an encapsulation layer formed on a surface of the flexible substrate proximate the peripheral metal trace.
  • the non-display area further includes a stress buffer layer formed between the bottom wall of the recess and the peripheral metal trace.
  • the stress buffer layer is provided with a plurality of through holes or blind holes.
  • the width of the peripheral metal trace is smaller than the width of the recess, and the peripheral metal trace is located at an intermediate position of the recess, and the non-display area further includes a buffer strip in the recess, the buffer strip filling the space on both sides of the peripheral metal traces in the recess.
  • the flexible substrate comprises a flexible substrate body layer, and a flexible substrate skin layer formed on a surface of the flexible substrate body layer proximate the peripheral metal trace.
  • the flexible substrate body layer comprises at least one layer of flexible substrate, the flexible substrate skin layer comprising at least one layer of flexible substrate.
  • the flexible substrate skin layer is a patterned flexible substrate skin layer, the hollow region of the flexible substrate skin layer and the flexible substrate body layer forming the groove.
  • the thickness of the flexible substrate skin is equal to the depth of the groove.
  • the plurality of grooves are arranged in a grid shape.
  • the application also provides a display screen.
  • a display screen comprising the array substrate provided by the present application.
  • the display screen includes the array substrate provided by the present application.
  • the structure of the non-display area of the array substrate can effectively prevent the breakage of the peripheral metal traces, thereby better ensuring the transmission of signals and prolonging the service life of the display.
  • the application also provides a method of manufacturing an array substrate.
  • a method of manufacturing an array substrate, the array substrate comprising a display area and a non-display area comprising: manufacturing a non-display area of the array substrate, wherein the non-display area for fabricating the array substrate comprises:
  • a peripheral metal trace is formed in the recess.
  • the forming a plurality of grooves on the surface of the flexible substrate comprises:
  • a patterned flexible substrate skin layer is formed on the flexible substrate body layer such that the hollow region of the flexible substrate skin layer and the flexible substrate body layer constitute the groove.
  • forming a patterned flexible substrate skin layer on the flexible substrate body layer comprises forming the patterned flexible substrate skin layer on the flexible substrate body layer by reticle.
  • the method before the operation of forming a plurality of grooves on the surface of the flexible substrate and forming a peripheral metal trace in the groove, the method further comprises:
  • a stress buffer layer is formed on the bottom wall of the groove.
  • the method further includes:
  • a buffer strip is formed on both sides of the peripheral metal traces in the recess.
  • the groove reduces the thickness of the flexible substrate at the peripheral metal trace, and reduces the extrusion of the peripheral metal trace by the flexible substrate during the bending process;
  • the arrangement of the grooves when bending can also effectively release the stress of the flexible substrate; thereby effectively preventing the breakage of the peripheral metal traces.
  • FIG. 1 is a schematic cross-sectional view of an array substrate according to Embodiment 1 of the present application.
  • FIG. 2 is a schematic cross-sectional view showing a non-display area of the array substrate shown in FIG. 1;
  • FIG. 3 is a top plan view of the non-display area of the array substrate shown in FIG. 1;
  • FIG. 4 is a schematic cross-sectional view showing a non-display area of an array substrate according to Embodiment 2 of the present application;
  • FIG. 5 is a schematic cross-sectional view showing a non-display area of an array substrate according to Embodiment 3 of the present application.
  • the array substrate 100 provided in the first embodiment of the present application includes a display area 110 and a non-display area 120 located outside the display area.
  • the display area 110 (ie, the AA area) is an area corresponding to the pixel unit in the array substrate 100, and the display area 110 is provided with an electronic component for driving the pixel unit such as a thin film transistor and a capacitor.
  • the specific structure of the display area 110 is not particularly limited, and various structures that are suitable for those skilled in the art may be employed, and details are not described herein again.
  • the non-display area 120 (i.e., the non-AA area) surrounds the display area 110.
  • the non-display area 120 may also exist only outside the one or more sides of the display area 110.
  • the non-display area 120 includes a flexible substrate 121 and peripheral metal traces 123. Specifically, the surface of the flexible substrate 121 is provided with a plurality of grooves 1211, and the peripheral metal traces 123 are located in the grooves 1211.
  • the flexible substrate 121 includes a flexible substrate.
  • the flexible substrate 121 may also include a stacked multilayer flexible substrate.
  • the groove 1211 has a rectangular cross section. It should be noted that the cross section of the groove 1211 is not limited to a rectangle, and may also have other regular or irregular shapes, such as a trapezoid or the like.
  • the recess 1211 reduces the thickness of the flexible substrate 121 at the peripheral metal trace 123, reducing the pressing of the peripheral metal trace 123 by the flexible substrate 121 during the bending process; in addition, the setting of the recess 1211 is effective when bent. The stress of the flexible substrate 121 is released; thereby effectively preventing the breakage of the peripheral metal traces 123.
  • the position of the groove 1211 is set according to the position of the peripheral metal trace 123.
  • a plurality of grooves 1211 are criss-crossed and arranged in a grid shape.
  • the plurality of grooves 1211 have the same depth, and are suitable for the case where the bending degree of each position of the non-display area 120 is substantially the same.
  • the peripheral metal trace 123 may be broken even if the degree of bending is the same, and the depth of the groove 1211 may be changed to adapt. Different bending conditions prevent the breakage of the peripheral metal traces 123. That is, the depths of the plurality of grooves 1211 may not be completely the same.
  • the non-display area 120 may further include an encapsulation layer formed on the surface of the flexible substrate 131 near the peripheral metal traces to prevent oxidation of the peripheral metal traces 133 by water oxygen or the like.
  • the non-display area 130 further includes a bottom surface formed between the bottom surface of the recess 1311 and the peripheral metal trace 133.
  • Stress buffer layer 135. The stress buffer layer 135 further effectively slows the extrusion of the peripheral metal traces 133 by the flexible substrate 131, and more effectively prevents the breakage of the peripheral metal traces 133.
  • the stress buffer layer 135 may be an organic layer or other layer of material that can act as a stress buffer.
  • a plurality of through holes 1351 are disposed on the stress buffer layer 135.
  • the through hole 1351 can release the stress on the stress buffer layer 135, thereby further reducing the pressing of the peripheral metal trace 133.
  • the non-display area 130 further includes a buffer strip 137 formed in the recess 1311 for filling the space on both sides of the peripheral metal trace 133 in the recess 1311.
  • the arrangement of the buffer strips 137 envelops both sides of the peripheral metal traces 133, effectively slowing the extrusion of the flexible substrate 131 on both sides of the peripheral metal traces 133 during the bending process.
  • the buffer strip 137 may be composed of an organic material or other material that can act as a stress buffer.
  • only the stress buffer layer 135 or only the buffer strip 137 may be provided according to the bending condition of the non-display area 130.
  • FIG. 5 is a schematic cross-sectional view showing a non-display area of an array substrate according to Embodiment 3 of the present application.
  • the flexible substrate 141 of the non-display area 140 includes a flexible substrate body layer 1413 and a flexible substrate skin layer 1415 formed on the surface of the flexible substrate body layer 1413 near the peripheral metal traces 143.
  • the flexible substrate body layer 1413 includes at least one flexible substrate; the flexible substrate skin layer 1415 includes at least one flexible substrate.
  • the thickness of the flexible substrate skin 1415 is equal to the depth of the groove 1411.
  • a patterned flexible substrate skin 1415 may be formed on the surface of the flexible substrate body layer 1413 by a reticle or the like, and the hollow region of the flexible substrate skin 1415 and the flexible substrate body layer 1413 constitute a groove 1411.
  • a stress buffer layer may be formed between the bottom wall of the recess 1411 and the peripheral metal trace 143, which further effectively slows the extrusion of the peripheral metal trace 143 by the flexible substrate 141, and is more effective.
  • the breakage of the peripheral metal traces 143 is prevented.
  • a plurality of through holes or blind holes may also be disposed on the stress buffer layer. When bent, the through holes or the blind holes may release the stress on the stress buffer layer, thereby further reducing the extrusion of the peripheral metal traces 143. The breakage of the peripheral metal trace 143 is more effectively prevented.
  • a buffer strip may be formed in the recess 1411 to fill the space on both sides of the peripheral metal trace 143 in the recess 1411.
  • the application provides a display screen comprising the array substrate provided by the present application.
  • the display screen includes other devices in addition to the array substrate, and the specific structures of other devices and the connection relationship between the devices may adopt structures well known to those skilled in the art, and details are not described herein again.
  • the structure of the non-display area of the array substrate provided by the present application can effectively prevent the breakage of the peripheral metal traces, thereby better ensuring the transmission of signals and prolonging the service life of the display.
  • the present application provides a method of fabricating an array substrate.
  • the manufacturing method of the non-display area of the array substrate specifically includes the following steps:
  • a plurality of grooves are formed on the surface of the flexible substrate.
  • the groove can be formed directly on the surface of the flexible substrate by etching or the like.
  • the flexible substrate comprises a flexible substrate body layer and a flexible substrate skin layer.
  • the flexible substrate body layer includes at least one layer of flexible substrate;
  • the flexible substrate skin layer includes at least one layer of flexible substrate.
  • the operation of forming a plurality of grooves on the surface of the flexible substrate is:
  • a patterned flexible substrate skin layer is formed on the flexible substrate body layer such that the hollow regions of the flexible substrate skin layer and the flexible substrate body layer form grooves.
  • a patterned flexible substrate skin layer may be formed on the flexible substrate body layer by a reticle or the like.
  • the inorganic film layer or the planarization layer on the flexible substrate may be removed by etching or the like before the step S1. .
  • the array substrate includes a display area and a non-display area.
  • the manufacturing method of the display area may be a manufacturing method known to those skilled in the art, and details are not described herein again.
  • the groove reduces the thickness of the flexible substrate at the peripheral metal trace, and reduces the extrusion of the peripheral metal trace by the flexible substrate during the bending process;
  • the arrangement of the grooves when bending can also effectively release the stress of the flexible substrate; thereby effectively preventing the breakage of the peripheral metal traces.
  • the manufacturing method of the non-display area of the array substrate further includes step SX, forming a stress on the bottom wall of the recess. buffer layer. Step SX is performed after step S1 and before step S2.
  • the manufacturing method of the non-display area of the array substrate further includes the step SY, in the concave A buffer zone is formed on both sides of the peripheral metal traces in the slot. Step SY is performed after step S2.
  • the inorganic film layer is etched away from the non-display region, the break of the peripheral metal trace due to the breakage of the inorganic film layer during bending is avoided; and the groove is provided on the surface of the flexible substrate, and the peripheral metal trace is located In the groove, the thickness of the flexible substrate at the peripheral metal trace is reduced, which reduces the extrusion of the flexible metal substrate to the peripheral metal trace during the bending process; in addition, the arrangement of the groove during bending can effectively release the flexible substrate The stress; thereby effectively preventing the breakage of the peripheral metal traces and improving the reliability of the array substrate.

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Abstract

一种阵列基板（100），其包括显示区（110）、以及位于所述显示区（110）外侧的非显示区（120，130，140）；所述非显示区（120，130，140）包括：柔性衬底（121，131，141），表面设有若干个凹槽（1211，1311，1411）；以及***金属走线（123，133，143），位于所述凹槽（1211，1311，1411）内。上述阵列基板（100），柔性衬底（121，131，141）表面设有凹槽（1211，1311，1411），***金属走线（123，133，143）位于凹槽（1211，1311，1411）内，使得***金属走线（123，133，143）处的柔性衬底（121，131，141）的厚度减小，减少了弯曲过程柔性衬底（121，131，141）对***金属走线（123，133，143）的挤压；另外，弯曲时凹槽（1211，1311，1411）的设置还能有效释放柔性衬底（121，131，141）的应力；从而有效防止***金属走线（123，133，143）的断裂，提高阵列基板（100）的可靠性。还提供一种显示屏和一种阵列基板（100）的制造方法。

Description

阵列基板及其制造方法及显示屏 技术领域
本申请涉及显示技术领域，特别是一种阵列基板及其制造方法及显示屏。
背景技术
显示屏包括显示区(AA区)以及非显示区(非AA区)，为了达到某些功能，会要求非显示区能够弯折。例如为了实现窄边框化，将非显示区弯折到屏体的背面，从而减少边框宽度。
但是，目前的显示屏，在非显示区的弯折过程中，非显示区中的***金属走线易断裂，从而造成屏体不良。
发明内容
基于此，有必要提供一种能够有效防止***金属走线断裂的阵列基板。
一种阵列基板，包括显示区、以及非显示区，该非显示区位于所述显示区外侧；所述非显示区包括：
柔性衬底，该柔性衬底表面设有若干凹槽；以及
***金属走线，该***金属走线位于所述凹槽内。
上述阵列基板，柔性衬底表面设有凹槽，***金属走线位于凹槽内，使得***金属走线处的柔性衬底的厚度减小，减少了弯曲过程柔性衬底对***金属走线的挤压；另外，弯曲时凹槽的设置还能有效地释放柔性衬底的应力；从而有效防止***金属走线的断裂，提高阵列基板的可靠性。
在其中一个实施例中，若干个所述凹槽的深度不完全相同。
在其中一个实施例中，所述非显示区还包括形成于所述柔性衬底的靠近所述***金属走线的表面的封装层。
在其中一个实施例中，所述非显示区还包括形成于所述凹槽底壁与所述***金属走线之间的应力缓冲层。
在其中一个实施例中，所述应力缓冲层上布设有若干个通孔或盲孔。
在其中一个实施例中，所述***金属走线的宽度小于所述凹槽的宽度，且所述***金属走线位于所述凹槽的中间位置，所述非显示区还包括形成于所述凹槽内的缓冲带，所述缓冲带填满所述凹槽内***金属走线两侧的空间。
在其中一个实施例中，所述柔性衬底包括柔性衬底主体层，以及形成于所述柔性衬底主体层的靠近所述***金属走线的表面的柔性衬底表层。
在其中一个实施例中，所述柔性衬底主体层包括至少一层柔性基板，所述柔性衬底表层包括至少一层柔性基板。
在其中一个实施例中，所述柔性衬底表层为图案化的柔性衬底表层，所述柔性衬底表层的镂空区域与所述柔性衬底主体层构成所述凹槽。
在其中一个实施例中，所述柔性衬底表层的厚度等于所述凹槽的深度。
在其中一个实施例中，若干凹槽呈格栅状排列。
本申请还提供一种显示屏。
一种显示屏，包括本申请提供的阵列基板。
上述显示屏包括本申请提供的阵列基板，阵列基板的非显示区的结构可以有效防止***金属走线的断裂，从而能够更好的保证讯号的传递，延长显示屏的使用寿命。
本申请还提供一种阵列基板的制造方法。
一种阵列基板的制造方法，所述阵列基板包括显示区及非显示区，所述方法包括制造所述阵列基板的非显示区，所述制造所述阵列基板的非显示区包括：
提供柔性衬底；
在柔性衬底的表面形成若干凹槽；
在所述凹槽内形成***金属走线。
在其中一个实施例中，所述在柔性衬底的表面形成若干凹槽包括：
提供柔性衬底主体层；
在所述柔性衬底主体层上形成图案化的柔性衬底表层，以使柔性衬底表层的镂空区域与所述柔性衬底主体层构成所述凹槽。
在其中一个实施例中，在所述柔性衬底主体层上形成图案化的柔性衬底表层，包括通过掩模版方式在所述柔性衬底主体层上形成所述图案化的柔性衬底 表层。
在其中一个实施例中，在所述柔性衬底的表面形成若干凹槽之后、在所述凹槽内形成***金属走线的操作之前，该方法还包括：
在所述凹槽的底壁形成应力缓冲层。
在其中一个实施例中，在所述凹槽内形成***金属走线的操作之后，该方法还包括：
在所述凹槽内的***金属走线的两侧形成缓冲带。
通过上述阵列基板的制造方法制得的阵列基板，一方面，凹槽使得***金属走线处的柔性衬底的厚度减小，减少了弯曲过程柔性衬底对***金属走线的挤压；另外，弯曲时凹槽的设置还能有效释放柔性衬底的应力；从而有效防止***金属走线的断裂。
附图说明
图1为本申请实施例一的阵列基板的截面示意图；
图2为图1所示阵列基板的非显示区的截面示意图；
图3为图1所示阵列基板的非显示区的俯视图；
图4为本申请实施例二的阵列基板的非显示区的截面示意图；
图5为本申请实施例三的阵列基板的非显示区的截面示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。
如图1至图3所示，本申请实施例一提供的阵列基板100，包括显示区110、以及位于显示区外侧的非显示区120。
其中，显示区110(即AA区)为阵列基板100中与像素单元对应的区域，在显示区110中设有薄膜晶体管以及电容器等用于驱动像素单元的电子元件。本申请对于显示区110的具体结构没有特殊限制，可以采用本领域技术人员认为合适的各种结构，在此不再赘述。
非显示区120(即非AA区)围绕在显示区110周围。当然，非显示区120也可以仅存在于显示区110的一个或多个侧边的外侧。
非显示区120包括柔性衬底121以及***金属走线123。具体地，柔性衬底121表面设有若干个凹槽1211，***金属走线123位于凹槽1211内。
本实施例中，柔性衬底121包括一层柔性基板。当然，柔性衬底121还可以包括叠加的多层柔性基板。
本实施例中，凹槽1211的截面呈矩形。需要说明的是，凹槽1211的截面不限于矩形，还可以呈其他规则或不规则的形状，如梯形等。
凹槽1211使得***金属走线123处的柔性衬底121的厚度减小，减少了弯曲过程柔性衬底121对***金属走线123的挤压；另外，弯曲时凹槽1211的设置还能有效释放柔性衬底121的应力；从而有效防止***金属走线123的断裂。
需要说明的是，凹槽1211的位置根据***金属走线123的位置进行设置。本实施例中，若干个凹槽1211纵横交错，呈格栅状排列。
本实施例中，若干个所述凹槽1211的深度相同，适用于非显示区120的各个位置弯曲程度基本相同的情况。
当然，若非显示区120的各个位置的弯曲程度不同，或者因金属走线的角度等原因造成即使弯曲程度相同也可能导致***金属走线123断裂的情况，可以通过改变凹槽1211的深度以适应不同的弯曲状况，从而避免***金属走线123的断裂。即若干个凹槽1211的深度也可以不完全相同。
另外一个实施例中，非显示区120还可以包括形成于柔性衬底131的靠近***金属走线的表面的封装层，用以防止水氧等氧化***金属走线133。
图4是本申请实施例二提供的阵列基板的非显示区的截面示意图，与阵列基板100不同的是，非显示区130还包括形成于凹槽1311底壁与***金属走线133之间的应力缓冲层135。应力缓冲层135进一步有效的减缓柔性衬底131对***金属走线133的挤压，更有效的防止***金属走线133的断裂。所述应力缓冲层135可以是有机物层或其他可以起应力缓冲作用的材料层。
本实施例中，应力缓冲层135上布设若干个通孔1351。弯曲时，通孔1351可释放应力缓冲层135上的应力，从而更进一步地减缓对***金属走线133的 挤压。当然，也可以在应力缓冲层135上设置若干个盲孔，同样能在弯曲时起到释放应力缓冲层135上的应力的作用。
进一步地，***金属走线133的宽度小于凹槽1311的宽度，且***金属走线133位于凹槽1311的中间位置。非显示区130还包括形成于凹槽1311内的缓冲带137，用来填满凹槽1311内***金属走线133两侧的空间。缓冲带137的设置，包裹***金属走线133两侧，有效减缓了弯曲过程柔性衬底131对***金属走线133两侧的挤压。所述缓冲带137可以由有机物或其他可以起应力缓冲作用的材料构成。
需要说明的是，可以根据非显示区130的弯曲情况，仅设置应力缓冲层135，或仅设置缓冲带137。
图5是本申请实施例三提供的阵列基板的非显示区的截面示意图。与阵列基板100不同的是，非显示区140的柔性衬底141包括柔性衬底主体层1413以及形成于柔性衬底主体层1413的、靠近***金属走线143的表面的柔性衬底表层1415。
具体的，柔性衬底主体层1413包括至少一层柔性基板；柔性衬底表层1415包括至少一层柔性基板。
本实施例中，柔性衬底表层1415的厚度等于凹槽1411的深度。具体地，可以通过掩模版等方式在柔性衬底主体层1413的表面形成图案化的柔性衬底表层1415，柔性衬底表层1415的镂空区域与柔性衬底主体层1413构成凹槽1411。
当然，本实施例中，也可以在凹槽1411的底壁与***金属走线143之间形成应力缓冲层，进一步有效地减缓柔性衬底141对***金属走线143的挤压，更有效的防止***金属走线143的断裂。当然，也可以在应力缓冲层上设置若干个通孔或盲孔，弯曲时，通孔或盲孔都可释放应力缓冲层上的应力，从而更进一步地减缓对***金属走线143的挤压，更有效地防止***金属走线143的断裂。
同样地，也可以在凹槽1411内形成缓冲带，用以填满凹槽1411内***金属走线143两侧的空间。缓冲带的设置，包裹***金属走线143两侧，有效地减缓了弯曲过程柔性衬底141对***金属走线143两侧的挤压。
本申请提供一种显示屏，包括本申请提供的阵列基板。
需要说明的是，显示屏除了阵列基板，还包括其它器件，其它器件的具体结构以及器件之间的连接关系均可以采用本领域技术人员所公知的结构，此处不再赘述。
本申请提供的阵列基板的非显示区的结构可以有效防止***金属走线的断裂，从而能够更好地保证讯号的传递，延长显示屏的使用寿命。
本申请提供了一种阵列基板的制造方法。阵列基板的非显示区的制造方法具体的包括如下步骤：
S1，在柔性衬底的表面形成若干个凹槽。
具体地，可以通过刻蚀等方式直接在柔性衬底的表面形成凹槽。
在另外一个实施例中，柔性衬底包括柔性衬底主体层和柔性衬底表层。柔性衬底主体层包括至少一层柔性基板；柔性衬底表层包括至少一层柔性基板。在柔性衬底的表面形成若干个凹槽的操作为：
提供柔性衬底主体层；
在柔性衬底主体层上形成图案化的柔性衬底表层，以使柔性衬底表层的镂空区域与柔性衬底主体层构成凹槽。
具体地，可以通过掩模版等方式在柔性衬底主体层上形成图案化的柔性衬底表层。
需要说明的是，若在柔性衬底上形成有无机膜层或平坦化层等，可以在步骤S1前，通过刻蚀等方式将柔性衬底上的无机膜层或平坦化层等膜层去掉。
S2，在凹槽内形成***金属走线。
需要说明的是，阵列基板包括显示区和非显示区，显示区的制造方法可采用本领域技术人员所公知的制造方法，此处不再赘述。
通过上述阵列基板的制造方法制得的阵列基板，一方面，凹槽使得***金属走线处的柔性衬底的厚度减小，减少了弯曲过程柔性衬底对***金属走线的挤压；另外，弯曲时凹槽的设置还能有效释放柔性衬底的应力；从而有效防止***金属走线的断裂。
需要说明的是，若非显示区包括形成于凹槽底壁与***金属走线之间的应 力缓冲层，则阵列基板的非显示区的制造方法还包括步骤SX，在凹槽的底壁形成应力缓冲层。步骤SX在步骤S1之后，且在步骤S2之前进行。
同样地，若非显示区包括形成于凹槽内的、用于填满凹槽内***金属走线两侧的空间的缓冲带，则阵列基板的非显示区的制造方法还包括步骤SY，在凹槽内的***金属走线的两侧形成缓冲带。步骤SY在步骤S2之后进行。
上述阵列基板，由于非显示区域刻蚀掉了无机膜层，避免了弯曲时由于无机膜层的断裂导致***金属走线的断裂；并且在柔性衬底表面设有凹槽，***金属走线位于凹槽内，使得***金属走线处的柔性衬底的厚度减小，减少了弯曲过程柔性衬底对***金属走线的挤压；另外，弯曲时凹槽的设置还能有效释放柔性衬底的应力；从而有效防止***金属走线的断裂，提高阵列基板的可靠性。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。

Claims (17)

  1. 一种阵列基板，包括：
    显示区；以及
    非显示区，所述非显示区位于所述显示区外侧，所述非显示区包括：
    柔性衬底，所述柔性衬底表面设有若干凹槽；以及
    ***金属走线，所述***金属走线位于所述凹槽内。
  2. 根据权利要求1所述的阵列基板，其中，若干个所述凹槽的深度不完全相同。
  3. 根据权利要求1所述的阵列基板，其中，所述非显示区还包括形成于所述柔性衬底的靠近所述***金属走线的表面的封装层。
  4. 根据权利要求1所述的阵列基板，其中，所述非显示区还包括形成于所述凹槽底壁与所述***金属走线之间的应力缓冲层。
  5. 根据权利要求4所述的阵列基板，其中，所述应力缓冲层上布设有若干个通孔或盲孔。
  6. 根据权利要求1所述的阵列基板，其中，所述***金属走线的宽度小于所述凹槽的宽度，且所述***金属走线位于所述凹槽的中间位置，所述非显示区还包括形成于所述凹槽内的缓冲带，所述缓冲带填满所述凹槽内***金属走线两侧的空间。
  7. 根据权利要求1所述的阵列基板，其中，所述柔性衬底包括柔性衬底主体层，以及形成于所述柔性衬底主体层的靠近所述***金属走线的表面的柔性衬底表层。
  8. 根据权利要求7所述的阵列基板，其中，所述柔性衬底主体层包括至少一层柔性基板，所述柔性衬底表层包括至少一层柔性基板。
  9. 根据权利要求7所述的阵列基板，其中，所述柔性衬底表层为图案化的柔性衬底表层，所述柔性衬底表层的镂空区域与所述柔性衬底主体层构成所述凹槽。
  10. 根据权利要求7至9任一项所述的阵列基板，其中，所述柔性衬底表层的厚度等于所述凹槽的深度。
  11. 根据权利要求1所述的阵列基板，其中，所述若干凹槽呈格栅状排列。
  12. 一种显示屏，包括权利要求1至11任一项所述的阵列基板。
  13. 一种阵列基板的制造方法，所述阵列基板包括显示区及非显示区，所述方法包括制造所述阵列基板的非显示区，所述制造所述阵列基板的非显示区，包括：
    提供柔性衬底；
    在柔性衬底的表面形成若干凹槽；
    在所述凹槽内形成***金属走线。
  14. 根据权利要求13所述的阵列基板的制造方法，其中，所述在柔性衬底的表面形成若干凹槽，包括：
    提供柔性衬底主体层；
    在所述柔性衬底主体层上形成图案化的柔性衬底表层，以使柔性衬底表层的镂空区域与所述柔性衬底主体层构成所述凹槽。
  15. 根据权利要求14所述的阵列基板的制造方法，其中，
    在所述柔性衬底主体层上形成图案化的柔性衬底表层，包括：
    通过掩模版方式在所述柔性衬底主体层上形成所述图案化的柔性衬底表层。
  16. 根据权利要求13所述的阵列基板的制造方法，其中，所述在柔性衬底的表面形成若干凹槽之后、所述在所述凹槽内形成***金属走线之前，所述方法还包括：
    在所述凹槽的底壁形成应力缓冲层。
  17. 根据权利要求13所述的阵列基板的制造方法，其中，在所述凹槽内形成***金属走线的操作之后，所述方法还包括：
    在所述凹槽内的***金属走线的两侧形成缓冲带。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10818702B2 (en) 2017-11-30 2020-10-27 Yungu (Gu' An) Technology Co., Ltd. Array substrates and display screens

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107910336B (zh) * 2017-11-30 2019-07-02 昆山国显光电有限公司 阵列基板及其制造方法及显示屏
CN108682391B (zh) * 2018-05-03 2020-10-20 昆山国显光电有限公司 显示面板、显示装置及制备方法
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CN109830503A (zh) * 2019-01-08 2019-05-31 云谷（固安）科技有限公司 柔性显示面板
CN109920332B (zh) 2019-02-28 2020-08-11 武汉华星光电半导体显示技术有限公司 柔性阵列基板、其制备方法及显示面板
CN110109299B (zh) * 2019-04-09 2020-11-10 深圳市华星光电技术有限公司 一种显示面板的线路结构及其制造方法
CN112309836B (zh) 2019-08-01 2022-10-28 京东方科技集团股份有限公司 一种背板及其制备方法、背光模组和显示装置
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CN111276495B (zh) * 2020-02-12 2022-06-07 武汉华星光电半导体显示技术有限公司 阵列基板及其制备方法
CN111540757B (zh) * 2020-05-07 2024-03-05 武汉华星光电技术有限公司 显示面板及其制备方法、显示装置
CN111524465B (zh) * 2020-06-11 2022-06-21 厦门通富微电子有限公司 一种显示装置的制备方法
CN111524466B (zh) * 2020-06-11 2022-06-21 厦门通富微电子有限公司 一种显示装置的制备方法
CN111524464B (zh) * 2020-06-11 2022-10-28 厦门通富微电子有限公司 一种显示装置
CN111564107B (zh) * 2020-06-11 2022-06-21 厦门通富微电子有限公司 一种显示装置的制备方法
CN111640881B (zh) * 2020-06-17 2023-05-12 昆山国显光电有限公司 阵列基板及其制备方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101078826A (zh) * 2007-07-23 2007-11-28 友达光电股份有限公司 具有边框信号线路的显示基板、显示面板及其制造方法
US20120291275A1 (en) * 2011-05-19 2012-11-22 Korea Institute Of Machinery & Materials Method of forming metal interconnection line on flexible substrate
CN105144418A (zh) * 2013-02-01 2015-12-09 乐金显示有限公司 柔性显示基板、柔性有机发光显示装置及其制造方法
CN105612589A (zh) * 2013-12-27 2016-05-25 Lg化学株式会社 导电膜及其制造方法
CN106252380A (zh) * 2016-08-31 2016-12-21 上海天马有机发光显示技术有限公司 柔性显示面板及装置
CN206685061U (zh) * 2017-04-27 2017-11-28 昆山国显光电有限公司 一种柔性基板及显示装置
CN107910336A (zh) * 2017-11-30 2018-04-13 昆山国显光电有限公司 阵列基板及其制造方法及显示屏
CN207517287U (zh) * 2017-11-30 2018-06-19 云谷（固安）科技有限公司 阵列基板及显示屏

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100846711B1 (ko) * 2007-03-13 2008-07-16 삼성에스디아이 주식회사 유기 발광 표시 장치 및 그 제조 방법
KR20130013515A (ko) * 2011-07-28 2013-02-06 삼성디스플레이 주식회사 유기 발광 표시 장치
CN104376899B (zh) * 2014-10-14 2017-01-11 业成光电（深圳）有限公司 电子装置、触控屏、透明导电膜及透明导电膜的制备方法
WO2016088394A1 (ja) * 2014-12-04 2016-06-09 株式会社Ｊｏｌｅｄ 表示装置および電子機器
CN204302629U (zh) * 2014-12-31 2015-04-29 京东方科技集团股份有限公司 一种显示基板及显示装置
US9412692B2 (en) * 2015-01-13 2016-08-09 Winbond Electronics Corp. Flexible microsystem structure
KR102385233B1 (ko) * 2015-08-06 2022-04-12 삼성디스플레이 주식회사 디스플레이 장치 및 그 제조방법
CN106876259B (zh) 2015-12-11 2019-12-13 昆山工研院新型平板显示技术中心有限公司 一种柔性导电线及设置有所述柔性导电性的柔性背板
KR102409200B1 (ko) * 2017-06-01 2022-06-15 엘지디스플레이 주식회사 터치전극을 포함하는 표시장치 및 그의 제조방법
CN109859624B (zh) * 2017-11-30 2021-04-20 昆山国显光电有限公司 阵列基板及其制备方法及显示屏

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101078826A (zh) * 2007-07-23 2007-11-28 友达光电股份有限公司 具有边框信号线路的显示基板、显示面板及其制造方法
US20120291275A1 (en) * 2011-05-19 2012-11-22 Korea Institute Of Machinery & Materials Method of forming metal interconnection line on flexible substrate
CN105144418A (zh) * 2013-02-01 2015-12-09 乐金显示有限公司 柔性显示基板、柔性有机发光显示装置及其制造方法
CN105612589A (zh) * 2013-12-27 2016-05-25 Lg化学株式会社 导电膜及其制造方法
CN106252380A (zh) * 2016-08-31 2016-12-21 上海天马有机发光显示技术有限公司 柔性显示面板及装置
CN206685061U (zh) * 2017-04-27 2017-11-28 昆山国显光电有限公司 一种柔性基板及显示装置
CN107910336A (zh) * 2017-11-30 2018-04-13 昆山国显光电有限公司 阵列基板及其制造方法及显示屏
CN207517287U (zh) * 2017-11-30 2018-06-19 云谷（固安）科技有限公司 阵列基板及显示屏

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10818702B2 (en) 2017-11-30 2020-10-27 Yungu (Gu' An) Technology Co., Ltd. Array substrates and display screens

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