WO2019061926A1 - Carbon nano-material composite structure-based three-dimensional silicon through-hole vertical interconnection method - Google Patents

Carbon nano-material composite structure-based three-dimensional silicon through-hole vertical interconnection method Download PDF

Info

Publication number
WO2019061926A1
WO2019061926A1 PCT/CN2018/000016 CN2018000016W WO2019061926A1 WO 2019061926 A1 WO2019061926 A1 WO 2019061926A1 CN 2018000016 W CN2018000016 W CN 2018000016W WO 2019061926 A1 WO2019061926 A1 WO 2019061926A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
silicon
composite structure
depositing
dry film
Prior art date
Application number
PCT/CN2018/000016
Other languages
French (fr)
Chinese (zh)
Inventor
陆向宁
何贞志
韩继光
宿磊
樊梦莹
刘凡
Original Assignee
江苏师范大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 江苏师范大学 filed Critical 江苏师范大学
Publication of WO2019061926A1 publication Critical patent/WO2019061926A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures

Definitions

  • the invention relates to a method for vertical interconnection of through-silicon vias, in particular to a three-dimensional through-silicon via vertical interconnection method based on a composite structure of carbon nano materials, belonging to the technical field of microelectronic packaging.
  • Microelectronic packaging technology faces new challenges as integrated circuit (IC) integrated circuit functions, size reduction, energy consumption and cost reduction.
  • IC integrated circuit
  • three-dimensional packaging technology came into being.
  • TSV Through Silicon Via
  • TSV technology directly bonds two or more layers of device die or the entire silicon wafer through a number of vertically through electrodes to achieve the shortest and most abundant z-directional interconnection. This not only improves device integration, but also reduces interconnect latency, increases device speed and reduces power consumption. Therefore, TSV technology is regarded as one of the mainstream processes for the development of future packaging technologies.
  • the TSV interconnect channel will become a highly dense and very complex three-dimensional microstructure group.
  • the increase in package density causes the power density of the stacked chip to rise sharply due to the significant difference between the thermal expansion coefficients of the package material.
  • the 3D TSV structure faces serious heat dissipation problems, and the silicon/copper thermal stress mismatch problem is also more prominent. This results in a large thermal stress in the TSV structure at both process and service temperatures.
  • the stress migration occurring under the residual stress of the process causes the vacancies in the metal to move and accumulate in the direction of the stress gradient to form voids, which eventually leads to the disconnection of the interconnect; the residual stress accumulated in the process and the thermal stress in the TSV structure at the service temperature are superimposed, The stress situation in the TSV structure is more complicated, and severe thermal stress mismatch will lead to the failure of the TSV interconnect structure.
  • the present invention provides a three-dimensional through-silicon via vertical interconnection method based on a carbon nanomaterial composite structure, which solves the heat dissipation problem of the TSV package structure caused by the increase in power density and the thermal stress loss between the package materials. Match the problem.
  • the technical solution adopted by the present invention is: a three-dimensional through-silicon via vertical interconnection method based on a carbon nano material composite structure, comprising the following steps:
  • the catalytic metal layer is formed by ion beam sputtering or physical vapor deposition, and the catalytic metal layer material is cobalt or iron.
  • the nano catalytic particles are formed by plasma etching, and the etching gas is hydrogen or argon.
  • the carbon nanomaterial composite structure layer in the step e is prepared by a thermal chemical vapor deposition method, the carbon source gas is methane, and hydrogen is used as a shielding gas, and the total gas pressure is stabilized at 1 kPa.
  • the structure of the carbon nanomaterial composite structure layer in the step e is divided into two layers, the upper layer is a horizontal multilayer graphene, and the lower layer is a vertical carbon nanotube array.
  • the diameter of the dry film layer is smaller than the diameter of the silicon hole and the hole of the dry film layer is coaxial with the silicon hole.
  • the silicon hole is plated with a conductive material by using the seed layer as a guide.
  • the present invention opens a hole in a silicon substrate and then deposits an insulating layer, a barrier layer, a carbon nano material composite structure layer, a dry film, a seed layer and a conductive material, and a good thermal energy using the carbon nanotube bundle.
  • mechanical properties to solve the heat dissipation problem of the TSV package structure caused by the increase in power density and the thermal stress mismatch between the package materials, improve the thermal conductivity and package reliability of the 3D-TSV structure.
  • FIG. 1 is a schematic view showing the structure of a silicon hole according to the present invention.
  • FIG. 2 is a schematic view showing the structure of depositing an insulating layer, a barrier layer and a catalytic metal layer in this invention
  • FIG. 3 is a schematic view showing the structure of etching a catalytic metal layer of the present invention to form nano catalytic metal particles;
  • FIG. 4 is a schematic structural view of a composite carbon nanomaterial composite structure layer of the present invention.
  • FIG. 5 is a schematic structural view of a carbon nanomaterial composite structural layer
  • Figure 6 is a schematic view showing the structure of the dry film layer of the present invention.
  • FIG. 7 is a schematic structural view of depositing a seed layer and filling a conductive material according to the present invention.
  • FIG. 8 is a schematic diagram of thermal stress buffering of a carbon nanomaterial composite structure layer of the present invention.
  • silicon substrate 2, insulating layer, 3, barrier layer, 4, catalytic metal layer, 5, carbon nano material composite structural layer, 6, dry film layer, 7, seed layer, 8, conductive material, 9, silicon holes.
  • the present invention includes the following steps:
  • a silicon hole 9 is formed on the silicon substrate 1;
  • the surface of the carbon nanomaterial composite structure layer 5 on the silicon substrate 1 is coated with a dry film, exposed and developed to form a dry film layer 6;
  • the conductive material 8 is filled in the silicon hole 9.
  • a silicon hole 9 is formed on the silicon substrate 1 by deep reaction etching, laser etching or wet etching; the diameter of the silicon hole 9 is 1-100 ⁇ m, and the silicon hole 9 is The cross section is generally circular, and the aspect ratio of the silicon holes 9 is generally from 1 to 30.
  • an insulating layer 2 is grown on the surface of the silicon substrate 1 and the inner walls (circumferential surface and bottom surface) of the silicon via 9, and the deposition of the insulating layer 2 is performed by thermal oxidation, chemical vapor deposition or physical vapor deposition, and the insulating layer is formed.
  • the material of 2 may be selected from inorganic materials such as silicon dioxide, aluminum oxide or silicon nitride, the thickness of the insulating layer 2 is 0.5-1 micrometer; the barrier layer 3 is deposited on the insulating layer 2, and the deposition of the barrier layer 3 is performed by physical vapor deposition or
  • the material of the barrier layer 3 may be selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, etc., and the thickness of the barrier layer 3 is 50-100 nm; the catalytic metal layer 4 is deposited on the barrier layer 3, and the catalytic metal is The layer 4 is formed by ion beam sputtering or physical vapor deposition.
  • the material is generally cobalt or iron, and the thickness of the catalytic metal layer 4 is 2-5 nm.
  • the catalytic metal layer 4 is etched by plasma etching to form nano-catalytic particles; the etching gas is hydrogen or argon, and the plasma power density is 0.1-0.5 (W/cm2), time 0.5- 3 minutes.
  • a carbon nanomaterial composite structure layer 5 is grown on the surface of the catalytic metal layer 4; the growth process is performed by a thermal chemical vapor deposition method, the carbon source gas is methane, and hydrogen gas is used as a shielding gas, and the total gas pressure is stabilized at 1 kPa.
  • the growth temperature is 450-600 ° C; the growth of the carbon nanomaterial composite structure layer 5 firstly precipitates the graphene layer from the catalytic metal cobalt, and then synthesizes the carbon nano material composite structural layer 5 from the cobalt nanoparticles according to the tip growth mode, as shown in FIG. 5 . It is shown that the structure of the carbon nanomaterial composite structure layer 5 after growth is that the upper layer is a graphene layer and the lower layer is a carbon nanotube bundle array.
  • the surface of the carbon nanomaterial composite structure layer 5 on the silicon substrate 1 is coated with a dry film, and the structure of the silicon hole 9 is exposed by exposure and development, and then the multilayer dry film is attached to the silicon substrate by hot pressing.
  • the surface of the sheet 1 is exposed by a photolithography machine, and the exposed silicon substrate 1 is placed in a developing solution to remove a part of the dry film to form a dry film layer 6 requiring a pattern.
  • the diameter of the dry film layer 6 is smaller than that of the silicon hole 9.
  • the diameter of the dry film layer 6 is coaxial with the silicon hole 9.
  • a seed layer 7 is deposited on the bottom surface of the silicon hole 9 and the surface of the dry film layer 6.
  • the seed layer 7 is deposited on the silicon hole by electron beam evaporation or magnetron sputtering using the dry film layer 6 as a mask.
  • the material of the seed layer 7 is generally selected from gold or copper; the conductive material 8 is filled by electroplating in the silicon hole 9 with the seed layer 7 as a guide, and the conductive material 8 is filled by electroplating, and the conductive material is used.
  • 8 is generally copper; an inhibitor and an accelerator are added to the plating solution to achieve high-speed, high-quality filling of the conductive material 8 "bottom up".
  • the bottom of the TSV channel is removed by chemical mechanical polishing techniques and planarization is achieved.
  • the heat in the TSV channel can be rapidly transferred up and down and left and right through the carbon nanomaterial composite structure layer 5 to accelerate thermal diffusion, regardless of process conditions or service conditions. Meanwhile, the thermal stress of the carbon nanomaterial composite structural layer 5 as the filling material 8
  • the release and buffer layers avoid severe thermal stress mismatch between the fill material 8 and the insulating layer 2/silicon substrate 1 causing TSV interconnect defects or even failure.

Abstract

Disclosed by the present invention is a carbon nano-material composite structure-based three-dimensional silicon through-hole vertical interconnection method: fabricating silicon holes on a silicon substrate; depositing an insulating layer on a surface of the silicon substrate and an inner wall of the silicon holes; depositing a blocking layer on the insulating layer, and depositing a catalytic metal layer on the blocking layer; etching the catalytic metal layer to form catalytic nano-particles; using the catalytic nano-particles to grow a carbon nano-material composite layer; attaching a dry film on a surface of the carbon nano-material composite layer on the silicon substrate, exposing and developing to form a dry film layer; depositing a seed layer on a bottom surface of the silicon holes and a surface of the dry film layer; filling a conductive material into the silicon holes. The present invention uses the excellent thermal and mechanical performance of a carbon nano-material to solve the heat dissipation problem of a through silicon via (TSV) encapsulation structure that is caused by increased power density as well as the problem of thermal stress mismatch among encapsulation materials, thus improving the thermal conductivity and encapsulation reliability of a 3D-TSV structure.

Description

一种基于碳纳米材料复合结构的三维硅通孔垂直互联方法Three-dimensional through-silicon via vertical interconnection method based on carbon nano material composite structure 技术领域Technical field
本发明涉及一种硅通孔垂直互联方法，具体涉及一种基于碳纳米材料复合结构的三维硅通孔垂直互联方法，属于微电子封装技术领域。The invention relates to a method for vertical interconnection of through-silicon vias, in particular to a three-dimensional through-silicon via vertical interconnection method based on a composite structure of carbon nano materials, belonging to the technical field of microelectronic packaging.
背景技术Background technique
随着集成电路(IC，Integrated Circuit)芯片功能增强、尺寸缩小、能耗与成本降低等，微电子封装技术面临新的挑战。为了满足IC产品的要求，三维封装技术应运而生。硅通孔垂直互联(TSV，Through Silicon Via)技术将两层和更多层器件裸片或者整个硅圆片通过许多垂直贯通的电极直接键合在一起，实现最短、最丰富的z向互联。这样不仅可提高器件集成度，而且可减少互连延时，提高器件运行速度和降低功耗。因此TSV技术被视为未来封装技术发展的主流工艺之一。Microelectronic packaging technology faces new challenges as integrated circuit (IC) integrated circuit functions, size reduction, energy consumption and cost reduction. In order to meet the requirements of IC products, three-dimensional packaging technology came into being. TSV (Through Silicon Via) technology directly bonds two or more layers of device die or the entire silicon wafer through a number of vertically through electrodes to achieve the shortest and most abundant z-directional interconnection. This not only improves device integration, but also reduces interconnect latency, increases device speed and reduces power consumption. Therefore, TSV technology is regarded as one of the mainstream processes for the development of future packaging technologies.
在22/16nm技术节点下，TSV互连通道将变为高度密集且十分复杂的三维微结构群，封装密度的提高使堆叠芯片的功率密度急剧上升，由于封装材料的热膨胀系数间的显著差异，3D TSV结构面临着严重的散热问题，硅/铜热应力失配问题也更加突出。导致TSV结构在工艺温度和服役温度下均存在较大的热应力。工艺残余应力下发生的应力迁移，促使金属中产生空位，并沿应力梯度方向移动、聚集形成空洞，最终导致互连断路；工艺过程累积的残余应力和服役温度下TSV结构中的热应力叠加，使得TSV结构中应力情况更为复杂，严重的热应力失配将导致TSV互连结构失效。Under the 22/16nm technology node, the TSV interconnect channel will become a highly dense and very complex three-dimensional microstructure group. The increase in package density causes the power density of the stacked chip to rise sharply due to the significant difference between the thermal expansion coefficients of the package material. The 3D TSV structure faces serious heat dissipation problems, and the silicon/copper thermal stress mismatch problem is also more prominent. This results in a large thermal stress in the TSV structure at both process and service temperatures. The stress migration occurring under the residual stress of the process causes the vacancies in the metal to move and accumulate in the direction of the stress gradient to form voids, which eventually leads to the disconnection of the interconnect; the residual stress accumulated in the process and the thermal stress in the TSV structure at the service temperature are superimposed, The stress situation in the TSV structure is more complicated, and severe thermal stress mismatch will lead to the failure of the TSV interconnect structure.
发明内容Summary of the invention
针对上述现有技术存在的问题，本发明提供一种基于碳纳米材料复合结构的三维硅通孔垂直互联方法，解决由功率密度增加导致的TSV封装结构的散热问题和封装材料间的热应力失配问题。In view of the above problems in the prior art, the present invention provides a three-dimensional through-silicon via vertical interconnection method based on a carbon nanomaterial composite structure, which solves the heat dissipation problem of the TSV package structure caused by the increase in power density and the thermal stress loss between the package materials. Match the problem.
为了实现上述目的，本发明采用的技术方案是：一种基于碳纳米材料复合结构的三维硅通孔垂直互联方法，包括以下步骤：In order to achieve the above object, the technical solution adopted by the present invention is: a three-dimensional through-silicon via vertical interconnection method based on a carbon nano material composite structure, comprising the following steps:
a.在硅基片上制作硅孔；a. making a silicon hole on the silicon substrate;
b.在硅基片表面及硅孔内壁沉积绝缘层；b. depositing an insulating layer on the surface of the silicon substrate and the inner wall of the silicon hole;
c.在绝缘层上沉积阻挡层，在阻挡层上沉积催化金属层；c. depositing a barrier layer on the insulating layer, depositing a catalytic metal layer on the barrier layer;
d.刻蚀催化金属层，形成纳米催化金属颗粒；d. etching the catalytic metal layer to form nano catalytic metal particles;
e.利用纳米催化金属颗粒生长碳纳米材料复合结构层；e. growing a carbon nanomaterial composite structural layer by using nanocatalytic metal particles;
f.在硅基片上的碳纳米材料复合结构层表面贴干膜，曝光、显影形成干膜层；f. sticking a dry film on the surface of the carbon nanomaterial composite structural layer on the silicon substrate, exposing and developing to form a dry film layer;
g.在硅孔底面和干膜层表面上沉积种子层；g. depositing a seed layer on the bottom surface of the silicon hole and the surface of the dry film layer;
h.在硅孔内填充导电材料。h. Fill the silicon hole with a conductive material.
进一步的，所述步骤c中催化金属层采用离子束溅射法或者物理气相沉积法制作，催化金属层材料为钴或者铁。Further, in the step c, the catalytic metal layer is formed by ion beam sputtering or physical vapor deposition, and the catalytic metal layer material is cobalt or iron.
进一步的，所述步骤d中纳米催化颗粒采用等离子体刻蚀法制作，刻蚀气体采用氢气或者氩气。Further, in the step d, the nano catalytic particles are formed by plasma etching, and the etching gas is hydrogen or argon.
进一步的，所述步骤e中生长碳纳米材料复合结构层采用热化学气相沉积法制作，碳源气体采用甲烷，采用氢气作为保护气体，总气体压力稳定在1kPa。Further, the carbon nanomaterial composite structure layer in the step e is prepared by a thermal chemical vapor deposition method, the carbon source gas is methane, and hydrogen is used as a shielding gas, and the total gas pressure is stabilized at 1 kPa.
进一步的，所述步骤e中生长碳纳米材料复合结构层结构分为两层，上层为水平的多层石墨烯，下层为垂直的碳纳米管阵列。Further, the structure of the carbon nanomaterial composite structure layer in the step e is divided into two layers, the upper layer is a horizontal multilayer graphene, and the lower layer is a vertical carbon nanotube array.
进一步的，所述步骤f中干膜层的孔直径小于硅孔直径且干膜层的孔与硅孔同轴。Further, in the step f, the diameter of the dry film layer is smaller than the diameter of the silicon hole and the hole of the dry film layer is coaxial with the silicon hole.
进一步的，所述步骤h中以种子层为引导对硅孔内进行电镀填充导电材料。Further, in the step h, the silicon hole is plated with a conductive material by using the seed layer as a guide.
与现有技术相比本发明在硅基片上开孔然后先后沉积绝缘层、阻挡层、生长碳纳米材料复合结构层，贴干膜，沉积种子层后填充导电材料，利用碳纳米管束良好的热学和机械性能，解决由功率密度增加导致的TSV封装结构的散热问题和封装材料间的热应力失配问题，提高3D-TSV结构的导热性及封装可靠性。Compared with the prior art, the present invention opens a hole in a silicon substrate and then deposits an insulating layer, a barrier layer, a carbon nano material composite structure layer, a dry film, a seed layer and a conductive material, and a good thermal energy using the carbon nanotube bundle. And mechanical properties, to solve the heat dissipation problem of the TSV package structure caused by the increase in power density and the thermal stress mismatch between the package materials, improve the thermal conductivity and package reliability of the 3D-TSV structure.
附图说明DRAWINGS
图1是本发明制作硅孔的结构示意图；1 is a schematic view showing the structure of a silicon hole according to the present invention;
图2是本发明先后沉积绝缘层、阻挡层和催化金属层的结构示意图；2 is a schematic view showing the structure of depositing an insulating layer, a barrier layer and a catalytic metal layer in this invention;
图3是本发明刻蚀催化金属层，形成纳米催化金属颗粒的结构示意图；3 is a schematic view showing the structure of etching a catalytic metal layer of the present invention to form nano catalytic metal particles;
图4是本发明生长碳纳米材料复合结构层的结构示意图；4 is a schematic structural view of a composite carbon nanomaterial composite structure layer of the present invention;
图5是碳纳米材料复合结构层的结构示意图；5 is a schematic structural view of a carbon nanomaterial composite structural layer;
图6是本发明贴干膜层的结构示意图；Figure 6 is a schematic view showing the structure of the dry film layer of the present invention;
图7是本发明沉积种子层并填充导电材料的结构示意图；7 is a schematic structural view of depositing a seed layer and filling a conductive material according to the present invention;
图8是本发明碳纳米材料复合结构层热应力缓冲示意图。FIG. 8 is a schematic diagram of thermal stress buffering of a carbon nanomaterial composite structure layer of the present invention.
图中：1、硅基片，2、绝缘层，3、阻挡层，4、催化金属层，5、碳纳米材料复合结构层，6、干膜层，7、种子层，8、导电材料，9、硅孔。In the figure: 1, silicon substrate, 2, insulating layer, 3, barrier layer, 4, catalytic metal layer, 5, carbon nano material composite structural layer, 6, dry film layer, 7, seed layer, 8, conductive material, 9, silicon holes.
具体实施方式Detailed ways
下面结合附图对本发明作进一步说明。The invention will now be further described with reference to the accompanying drawings.
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.
如图7所示，本发明包括以下步骤：As shown in Figure 7, the present invention includes the following steps:
a.在硅基片1上制作硅孔9；a silicon hole 9 is formed on the silicon substrate 1;
b.在硅基片1表面及硅孔9内壁沉积绝缘层2；b. depositing an insulating layer 2 on the surface of the silicon substrate 1 and the inner wall of the silicon hole 9;
c.在绝缘层2上沉积阻挡层3，在阻挡层3上沉积催化金属层4；c. Depositing a barrier layer 3 on the insulating layer 2, depositing a catalytic metal layer 4 on the barrier layer 3;
d.刻蚀催化金属层4，形成纳米催化颗粒；d. etching the catalytic metal layer 4 to form nano catalytic particles;
e.利用纳米催化金属颗粒生长碳纳米材料复合结构层5；e. using nano-catalytic metal particles to grow carbon nano-material composite structural layer 5;
f.在硅基片1上的碳纳米材料复合结构层5表面贴干膜，曝光、显影形成干膜层6；f. The surface of the carbon nanomaterial composite structure layer 5 on the silicon substrate 1 is coated with a dry film, exposed and developed to form a dry film layer 6;
g.在硅孔9底面和干膜层6表面上沉积种子层7；g. depositing a seed layer 7 on the bottom surface of the silicon hole 9 and the surface of the dry film layer 6;
h.在硅孔9内填充导电材料8。h. The conductive material 8 is filled in the silicon hole 9.
实施例：Example:
如图1所示，在硅基片1上采用深反应刻蚀法、激光刻蚀法或湿法腐蚀法刻蚀制作硅孔9；硅孔9的直径为1-100微米，硅孔9的横截面一般为圆形，硅孔9的深宽比一般为1～30。As shown in FIG. 1, a silicon hole 9 is formed on the silicon substrate 1 by deep reaction etching, laser etching or wet etching; the diameter of the silicon hole 9 is 1-100 μm, and the silicon hole 9 is The cross section is generally circular, and the aspect ratio of the silicon holes 9 is generally from 1 to 30.
如图2所示，在硅基片1表面上及硅孔9内壁(圆周面及底面)生长绝缘层2，绝缘层2的沉积采用热氧化、化学气相沉积或者物理气相沉积方法制作，绝缘层2的材料可以选用二氧化硅、氧化铝或者氮化硅等无机物，绝缘层2的厚度为0.5-1微米；在绝缘层2上沉积阻挡层3，阻挡层3的沉积采用物理气相沉积或者化学气相沉积法制作，阻挡层3的材料可以选择钛、氮化钛、钽、氮化钽等，阻挡层3的厚度为50-100纳米；在阻挡层3上沉积催化金属层4，催化金属层4采用离子束溅射法或者物理气相沉积法制作，材料一般选用钴或者铁，催化金属层4的厚度为2-5纳米。As shown in FIG. 2, an insulating layer 2 is grown on the surface of the silicon substrate 1 and the inner walls (circumferential surface and bottom surface) of the silicon via 9, and the deposition of the insulating layer 2 is performed by thermal oxidation, chemical vapor deposition or physical vapor deposition, and the insulating layer is formed. The material of 2 may be selected from inorganic materials such as silicon dioxide, aluminum oxide or silicon nitride, the thickness of the insulating layer 2 is 0.5-1 micrometer; the barrier layer 3 is deposited on the insulating layer 2, and the deposition of the barrier layer 3 is performed by physical vapor deposition or The material of the barrier layer 3 may be selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, etc., and the thickness of the barrier layer 3 is 50-100 nm; the catalytic metal layer 4 is deposited on the barrier layer 3, and the catalytic metal is The layer 4 is formed by ion beam sputtering or physical vapor deposition. The material is generally cobalt or iron, and the thickness of the catalytic metal layer 4 is 2-5 nm.
如图3所示，采用等离子体刻蚀法刻蚀催化金属层4，形成纳米催化颗粒；刻蚀气体采用氢气或者氩气，等离子体功率密度为0.1-0.5(W/cm2)，时间0.5-3分钟。As shown in FIG. 3, the catalytic metal layer 4 is etched by plasma etching to form nano-catalytic particles; the etching gas is hydrogen or argon, and the plasma power density is 0.1-0.5 (W/cm2), time 0.5- 3 minutes.
如图4所示，在催化金属层4表面生长碳纳米材料复合结构层5；生长工艺采用热化学气相沉积方法制作，碳源气体采用甲烷，采用氢气作为保护气体，总气体压力稳定在1kPa，生长温度为450-600℃；碳纳米材料复合结构层5的生长首先从催化金属钴上析出石墨烯层，然后根据尖端生长模式从钴纳米颗粒合成碳纳米材料复合结构层5，如图5所示，生长后的碳纳米材料复合结构层5的结构为上层是石墨烯层，下层是碳纳米管束阵列。As shown in FIG. 4, a carbon nanomaterial composite structure layer 5 is grown on the surface of the catalytic metal layer 4; the growth process is performed by a thermal chemical vapor deposition method, the carbon source gas is methane, and hydrogen gas is used as a shielding gas, and the total gas pressure is stabilized at 1 kPa. The growth temperature is 450-600 ° C; the growth of the carbon nanomaterial composite structure layer 5 firstly precipitates the graphene layer from the catalytic metal cobalt, and then synthesizes the carbon nano material composite structural layer 5 from the cobalt nanoparticles according to the tip growth mode, as shown in FIG. 5 . It is shown that the structure of the carbon nanomaterial composite structure layer 5 after growth is that the upper layer is a graphene layer and the lower layer is a carbon nanotube bundle array.
如图6所示，在硅基片1上的碳纳米材料复合结构层5表面贴干膜，通过曝光、显影暴露出硅孔9结构，然后采用热压方法将多层干膜贴于硅基片1表面，使用光刻机进行曝光，将曝光后的硅基片1放置于显影液中，去除部分干膜，形成需要图案的干膜层6，干膜层6的孔直径小于硅孔9直径且干膜层6的孔与硅孔9同轴。As shown in FIG. 6, the surface of the carbon nanomaterial composite structure layer 5 on the silicon substrate 1 is coated with a dry film, and the structure of the silicon hole 9 is exposed by exposure and development, and then the multilayer dry film is attached to the silicon substrate by hot pressing. The surface of the sheet 1 is exposed by a photolithography machine, and the exposed silicon substrate 1 is placed in a developing solution to remove a part of the dry film to form a dry film layer 6 requiring a pattern. The diameter of the dry film layer 6 is smaller than that of the silicon hole 9. The diameter of the dry film layer 6 is coaxial with the silicon hole 9.
如图7所示，在硅孔9底面和干膜层6表面上沉积种子层7，种子层7是以干膜层6为掩膜，采用电子束蒸发或者磁控溅射方法沉积于硅孔9底面和干膜层6表面上，种子层7的材料一般选用金或者铜；以种子层7为引导对硅孔9内进行电镀填充导电材料8，导电材料8采用电镀方法进行填充，导电材料8一般是铜；在电镀液中添加抑制剂和加速剂，实现导电材料8“自底而上”的高速、高质量填充。As shown in FIG. 7, a seed layer 7 is deposited on the bottom surface of the silicon hole 9 and the surface of the dry film layer 6. The seed layer 7 is deposited on the silicon hole by electron beam evaporation or magnetron sputtering using the dry film layer 6 as a mask. 9 On the surface of the bottom surface and the dry film layer 6, the material of the seed layer 7 is generally selected from gold or copper; the conductive material 8 is filled by electroplating in the silicon hole 9 with the seed layer 7 as a guide, and the conductive material 8 is filled by electroplating, and the conductive material is used. 8 is generally copper; an inhibitor and an accelerator are added to the plating solution to achieve high-speed, high-quality filling of the conductive material 8 "bottom up".
如图8所示，填充完成后通过化学机械研磨技术除去TSV通道底部并实现平坦化。无 论在工艺条件或服役情况下，TSV通道中的热量可通过碳纳米材料复合结构层5迅速向上下和左右传输，加速热扩散；同时，碳纳米材料复合结构层5作为填充材料8的热应力释放和缓冲层，避免填充材料8与绝缘层2/硅基片1之间严重的热应力失配而引起TSV互联缺陷甚至失效的情况。As shown in FIG. 8, after the filling is completed, the bottom of the TSV channel is removed by chemical mechanical polishing techniques and planarization is achieved. The heat in the TSV channel can be rapidly transferred up and down and left and right through the carbon nanomaterial composite structure layer 5 to accelerate thermal diffusion, regardless of process conditions or service conditions. Meanwhile, the thermal stress of the carbon nanomaterial composite structural layer 5 as the filling material 8 The release and buffer layers avoid severe thermal stress mismatch between the fill material 8 and the insulating layer 2/silicon substrate 1 causing TSV interconnect defects or even failure.
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其它的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。It is obvious to those skilled in the art that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the present embodiments are to be considered as illustrative and not restrictive, and the scope of the invention is defined by the appended claims instead All changes in the meaning and scope of equivalent elements are included in the present invention. Any reference signs in the claims should not be construed as limiting the claim.
以上所述，仅为本发明的较佳实施例，并不用以限制本发明，凡是依据本发明的技术实质对以上实施例所作的任何细微修改、等同替换和改进，均应包含在本发明技术方案的保护范围之内。The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any minor modifications, equivalent substitutions and improvements made to the above embodiments in accordance with the technical spirit of the present invention should be included in the present technology. Within the scope of protection of the program.

Claims (7)

  1. 一种基于碳纳米材料复合结构的三维硅通孔垂直互联方法，其特征在于，包括以下步骤：A three-dimensional through-silicon via vertical interconnection method based on carbon nano material composite structure, characterized in that the method comprises the following steps:
    a.在硅基片(1)上制作硅孔(9)；a. making a silicon hole (9) on the silicon substrate (1);
    b.在硅基片(1)表面及硅孔(9)内壁沉积绝缘层(2)；b. depositing an insulating layer (2) on the surface of the silicon substrate (1) and the inner wall of the silicon hole (9);
    c.在绝缘层(2)上沉积阻挡层(3)，在阻挡层(3)上沉积催化金属层(4)；c. depositing a barrier layer (3) on the insulating layer (2), depositing a catalytic metal layer (4) on the barrier layer (3);
    d.刻蚀催化金属层(4)，形成纳米催化金属颗粒；d. etching the catalytic metal layer (4) to form nano catalytic metal particles;
    e.利用纳米催化金属颗粒生长碳纳米材料复合结构层(5)；e. using nano-catalyzed metal particles to grow a carbon nano-material composite structural layer (5);
    f.在硅基片(1)上的碳纳米材料复合结构层(5)表面贴干膜，曝光、显影形成干膜层(6)；f. The surface of the carbon nanomaterial composite structure layer (5) on the silicon substrate (1) is coated with a dry film, exposed and developed to form a dry film layer (6);
    g.在硅孔(9)底面和干膜层(6)表面上沉积种子层(7)；g. depositing a seed layer (7) on the bottom surface of the silicon hole (9) and the surface of the dry film layer (6);
    h.在硅孔(9)内填充导电材料(8)。h. Fill the silicon hole (9) with a conductive material (8).
  2. 根据权利要求1所述的一种基于碳纳米材料复合结构的三维硅通孔垂直互联方法，其特征在于，所述步骤c中催化金属层(4)采用离子束溅射法或者物理气相沉积法制作，催化金属层(4)材料为钴或者铁。The three-dimensional through-silicon via vertical interconnection method based on carbon nanomaterial composite structure according to claim 1, wherein the catalytic metal layer (4) in the step c is ion beam sputtering or physical vapor deposition The material of the catalytic metal layer (4) is made of cobalt or iron.
  3. 根据权利要求1所述的一种基于碳纳米材料复合结构的三维硅通孔垂直互联方法，其特征在于，所述步骤d中纳米催化颗粒采用等离子体刻蚀法制作，刻蚀气体采用氢气或者氩气。The three-dimensional through-silicon via vertical interconnection method based on a carbon nanomaterial composite structure according to claim 1, wherein the nano catalytic particles in the step d are formed by plasma etching, and the etching gas is hydrogen or Argon.
  4. 根据权利要求1所述的一种基于碳纳米材料复合结构的三维硅通孔垂直互联方法，其特征在于，所述步骤e中生长碳纳米材料复合结构层(5)采用热化学气相沉积法制作，碳源气体采用甲烷，采用氢气作为保护气体，总气体压力稳定在1kPa。The three-dimensional through-silicon via vertical interconnection method based on carbon nanomaterial composite structure according to claim 1, wherein the carbon nanomaterial composite structural layer (5) in the step e is fabricated by thermal chemical vapor deposition The carbon source gas is methane, and hydrogen is used as a shielding gas, and the total gas pressure is stabilized at 1 kPa.
  5. 根据权利要求1所述的一种基于碳纳米材料复合结构的三维硅通孔垂直互联方法，其特征在于，所述步骤e中生长碳纳米材料复合结构层(5)结构分为两层，上层为水平的多层石墨烯，下层为垂直的碳纳米管阵列。The three-dimensional through-silicon via vertical interconnection method based on carbon nanomaterial composite structure according to claim 1, wherein the carbon nanomaterial composite structure layer (5) in the step e is divided into two layers, the upper layer For horizontal multilayer graphene, the lower layer is a vertical array of carbon nanotubes.
  6. 根据权利要求1所述的一种基于碳纳米材料复合结构的三维硅通孔垂直互联方法， 其特征在于，所述步骤f中干膜层(6)的孔直径小于硅孔(9)直径。The three-dimensional through-silicon via vertical interconnection method based on a carbon nanomaterial composite structure according to claim 1, wherein the diameter of the dry film layer (6) in the step f is smaller than the diameter of the silicon hole (9).
  7. 根据权利要求1所述的一种基于碳纳米材料复合结构的三维硅通孔垂直互联方法，其特征在于，所述步骤h中以种子层(7)为引导对硅孔(9)内进行电镀填充导电材料(8)。The three-dimensional through-silicon via vertical interconnection method based on carbon nanomaterial composite structure according to claim 1, wherein in the step h, the silicon hole (9) is plated by using the seed layer (7) as a guide. Fill the conductive material (8).
PCT/CN2018/000016 2017-09-28 2018-01-15 Carbon nano-material composite structure-based three-dimensional silicon through-hole vertical interconnection method WO2019061926A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710900247.2A CN107658263B (en) 2017-09-28 2017-09-28 Three-dimensional through silicon via vertical interconnection method based on carbon nano material composite structure
CN201710900247.2 2017-09-28

Publications (1)

Publication Number Publication Date
WO2019061926A1 true WO2019061926A1 (en) 2019-04-04

Family

ID=61115941

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/000016 WO2019061926A1 (en) 2017-09-28 2018-01-15 Carbon nano-material composite structure-based three-dimensional silicon through-hole vertical interconnection method

Country Status (2)

Country Link
CN (1) CN107658263B (en)
WO (1) WO2019061926A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109524513A (en) * 2018-11-23 2019-03-26 江苏新广联半导体有限公司 A kind of silicon substrate flip LED chips and preparation method thereof
CN116435290B (en) * 2023-06-13 2023-08-22 中诚华隆计算机技术有限公司 Three-dimensional stacking structure and stacking method of chips

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010025962A1 (en) * 2000-03-31 2001-10-04 Masayuki Nakamoto Field emmision type cold cathode device, manufacturing method thereof and vacuum micro device
US20020163079A1 (en) * 2001-05-02 2002-11-07 Fujitsu Limited Integrated circuit device and method of producing the same
CN102569181A (en) * 2011-12-15 2012-07-11 中国科学院微电子研究所 Method for manufacturing vertically interconnecting carbon nanotube bundle
CN103258789A (en) * 2013-04-17 2013-08-21 华中科技大学 Manufacturing method of through hole interconnection structure and product of through hole interconnection structure

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102530931B (en) * 2011-12-14 2014-04-02 天津大学 Graphene-based nano composite material and preparation method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010025962A1 (en) * 2000-03-31 2001-10-04 Masayuki Nakamoto Field emmision type cold cathode device, manufacturing method thereof and vacuum micro device
US20020163079A1 (en) * 2001-05-02 2002-11-07 Fujitsu Limited Integrated circuit device and method of producing the same
CN102569181A (en) * 2011-12-15 2012-07-11 中国科学院微电子研究所 Method for manufacturing vertically interconnecting carbon nanotube bundle
CN103258789A (en) * 2013-04-17 2013-08-21 华中科技大学 Manufacturing method of through hole interconnection structure and product of through hole interconnection structure

Also Published As

Publication number Publication date
CN107658263A (en) 2018-02-02
CN107658263B (en) 2021-01-22

Similar Documents

Publication Publication Date Title
TWI269404B (en) Interconnect structure for semiconductor devices
KR20100108503A (en) Electronic device and method of manufacturing the same
JP4899703B2 (en) Carbon wiring structure, manufacturing method thereof, and semiconductor device
TW201417647A (en) Circuit board with twinned Cu circuit layer and method for manufacturing the same
US20120202347A1 (en) Through silicon vias using carbon nanotubes
US20140061916A1 (en) Semiconductor device with low resistance wiring and manufacturing method for the device
WO2019061926A1 (en) Carbon nano-material composite structure-based three-dimensional silicon through-hole vertical interconnection method
CN104952786B (en) Electric interconnection structure and forming method thereof
CN102881651B (en) A kind of method improving electrical interconnection characteristic of carbon nano tube
JP5694272B2 (en) Semiconductor device and manufacturing method thereof
JP2013535820A (en) Method and structure for improving the conductivity of narrow copper filled vias
JP2008251701A (en) Wiring structure and its forming method
JP2008258184A (en) Electronic device and its manufacturing method
JP5699164B2 (en) Interconnect structure made of redirected carbon nanotubes
JP5953701B2 (en) Connection board, semiconductor device, and manufacturing method of connection board
JP2010135631A (en) Interconnect structure and method of forming same, and semiconductor device
CN111180387A (en) Silicon through hole interconnection structure and preparation method thereof
Ghosh et al. Integration of CNT in TSV (≤ 5 μm) for 3D IC application and its process challenges
JP5708762B2 (en) Method for manufacturing through electrode substrate
JP2012530362A (en) Reduction of cracks at the metal / organic dielectric interface
CN107658262B (en) Three-dimensional through silicon via vertical interconnection method based on graphene composite structure
CN102683265A (en) Method for filling carbon nano tube bundles in TSV (through silicon vias) of silicon interposer
CN104576509B (en) Semiconductor structure and forming method thereof
JP2011258803A (en) Silicon substrate with plating layer having through holes
CN104517894B (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18860429

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18860429

Country of ref document: EP

Kind code of ref document: A1