CN107658263B - Three-dimensional through silicon via vertical interconnection method based on carbon nano material composite structure - Google Patents
Three-dimensional through silicon via vertical interconnection method based on carbon nano material composite structure Download PDFInfo
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- CN107658263B CN107658263B CN201710900247.2A CN201710900247A CN107658263B CN 107658263 B CN107658263 B CN 107658263B CN 201710900247 A CN201710900247 A CN 201710900247A CN 107658263 B CN107658263 B CN 107658263B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
Abstract
The invention discloses a three-dimensional through silicon via vertical interconnection method based on a carbon nano material composite structure, which comprises the steps of manufacturing a silicon via on a silicon substrate; depositing an insulating layer on the surface of the silicon substrate and the inner wall of the silicon hole; depositing a barrier layer on the insulating layer, and depositing a catalytic metal layer on the barrier layer; etching the catalytic metal layer to form nano catalytic particles; growing a carbon nano material composite layer by utilizing the nano catalytic particles; pasting a dry film on the surface of the carbon nano material composite structure layer on the silicon substrate, exposing and developing to form a dry film layer; depositing a seed layer on the bottom surface of the silicon hole and the surface of the dry film layer; and filling the silicon hole with a conductive material. According to the invention, the good thermal and mechanical properties of the carbon nano material are utilized, the heat dissipation problem of the TSV packaging structure and the thermal stress mismatch problem among packaging materials caused by the increase of power density are solved, and the thermal conductivity and the packaging reliability of the 3D-TSV structure are improved.
Description
Technical Field
The invention relates to a vertical interconnection method of through silicon vias, in particular to a three-dimensional vertical interconnection method of through silicon vias based on a carbon nano material composite structure, and belongs to the technical field of microelectronic packaging.
Background
With the increased functionality, size reduction, power consumption and cost reduction of Integrated Circuit (IC) chips, microelectronic packaging technology faces new challenges. In order to meet the requirements of IC products, three-dimensional packaging techniques have been developed. Through-Silicon Via (TSV) technology directly bonds two or more device dies or the entire Silicon wafer together Through a plurality of vertically Through electrodes, thereby realizing the shortest and most abundant z-direction interconnection. Therefore, the integration level of the device can be improved, the interconnection delay can be reduced, the operation speed of the device can be improved, and the power consumption can be reduced. The TSV technology is therefore considered as one of the mainstream processes for future packaging technology development.
Under the 22/16nm technology node, the TSV interconnection channel becomes a highly dense and very complex three-dimensional microstructure group, the power density of the stacked chip is increased sharply due to the improvement of the packaging density, the 3D TSV structure faces a serious heat dissipation problem due to the obvious difference between the thermal expansion coefficients of the packaging materials, and the problem of silicon/copper thermal stress mismatch is more prominent. The TSV structure is subjected to large thermal stress at both the process temperature and the service temperature. Stress migration generated under the process residual stress promotes the generation of vacancies in the metal, and the vacancies are formed by movement and aggregation along the stress gradient direction, and finally lead to interconnection open circuit; residual stress accumulated in the process is superposed with thermal stress in the TSV structure at the service temperature, so that the stress condition in the TSV structure is more complicated, and the TSV interconnection structure fails due to severe thermal stress mismatch.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a three-dimensional through silicon via vertical interconnection method based on a carbon nano material composite structure, which solves the problems of heat dissipation of a TSV packaging structure and thermal stress mismatch between packaging materials caused by power density increase.
In order to achieve the purpose, the invention adopts the technical scheme that: a three-dimensional through silicon via vertical interconnection method based on a carbon nano material composite structure comprises the following steps:
a. manufacturing a silicon hole on a silicon substrate;
b. depositing an insulating layer on the surface of the silicon substrate and the inner wall of the silicon hole;
c. depositing a barrier layer on the insulating layer, and depositing a catalytic metal layer on the barrier layer;
d. etching the catalytic metal layer to form nano catalytic metal particles;
e. growing a carbon nano material composite structure layer by utilizing nano catalytic metal particles;
f. pasting a dry film on the surface of the carbon nano material composite structure layer on the silicon substrate, exposing and developing to form a dry film layer;
g. depositing a seed layer on the bottom surface of the silicon hole and the surface of the dry film layer;
h. and filling the silicon hole with a conductive material.
Furthermore, the catalytic metal layer in the step c is made by an ion beam sputtering method or a physical vapor deposition method, and the catalytic metal layer is made of cobalt or iron.
Furthermore, the nano catalytic particles in the step d are manufactured by a plasma etching method, and the etching gas is hydrogen or argon.
Furthermore, the carbon nano-material composite structure layer grown in the step e is manufactured by a thermal chemical vapor deposition method, the carbon source gas adopts methane, hydrogen is adopted as a protective gas, and the total gas pressure is stabilized at 1 kPa.
Furthermore, the structure of the composite structure layer of the carbon nano-material grown in the step e is divided into two layers, the upper layer is horizontal multi-layer graphene, and the lower layer is a vertical carbon nano-tube array.
Furthermore, in the step f, the diameter of the hole of the dry film layer is smaller than that of the silicon hole, and the hole of the dry film layer is coaxial with the silicon hole.
Furthermore, in the step h, the seed layer is used as a guide to perform electroplating filling on the conductive material in the silicon hole.
Compared with the prior art, the method has the advantages that the silicon substrate is provided with the holes, the insulating layer, the barrier layer and the carbon nano material composite structure layer are sequentially deposited, the dry film is pasted, the seed layer is deposited, and then the conductive material is filled, so that the good thermal and mechanical properties of the carbon nano tube bundle are utilized, the problems of heat dissipation of the TSV packaging structure and thermal stress mismatch between the packaging materials caused by power density increase are solved, and the thermal conductivity and packaging reliability of the 3D-TSV structure are improved.
Drawings
FIG. 1 is a schematic diagram of a structure for forming a silicon via according to the present invention;
FIG. 2 is a schematic structural view of an insulating layer, a barrier layer and a catalytic metal layer deposited successively in accordance with the present invention;
FIG. 3 is a schematic structural diagram of the present invention for etching a catalytic metal layer to form nano-catalytic metal particles;
FIG. 4 is a schematic structural diagram of a composite structural layer of the grown carbon nanomaterial of the present invention;
FIG. 5 is a schematic structural view of a carbon nanomaterial composite structure layer;
FIG. 6 is a schematic view of the structure of the dry film layer of the present invention;
FIG. 7 is a schematic diagram of a structure of the present invention for depositing a seed layer and filling with a conductive material;
fig. 8 is a schematic view of the thermal stress buffering of the carbon nanomaterial composite structure layer of the present invention.
In the figure: 1. the device comprises a silicon substrate, 2, an insulating layer, 3, a barrier layer, 4, a catalytic metal layer, 5, a carbon nano material composite structure layer, 6, a dry film layer, 7, a seed layer, 8, a conductive material, 9 and a silicon hole.
Detailed Description
The invention will be further explained with reference to the drawings.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 7, the present invention includes the steps of:
a. manufacturing a silicon hole 9 on a silicon substrate 1;
b. depositing an insulating layer 2 on the surface of the silicon substrate 1 and the inner wall of the silicon hole 9;
c. depositing a barrier layer 3 on the insulating layer 2, and depositing a catalytic metal layer 4 on the barrier layer 3;
d. etching the catalytic metal layer 4 to form nano catalytic particles;
e. growing a carbon nano material composite structure layer 5 by using nano catalytic metal particles;
f. sticking a dry film on the surface of the carbon nano material composite structure layer 5 on the silicon substrate 1, exposing and developing to form a dry film layer 6;
g. depositing a seed layer 7 on the bottom surface of the silicon hole 9 and the surface of the dry film layer 6;
h. the silicon holes 9 are filled with a conductive material 8.
Example (b):
as shown in fig. 1, a silicon substrate 1 is etched and manufactured with a deep reactive etching method, a laser etching method or a wet etching method to form a silicon hole 9; the diameter of the silicon hole 9 is 1-100 microns, the cross section of the silicon hole 9 is generally circular, and the depth-to-width ratio of the silicon hole 9 is generally 1-30.
As shown in fig. 2, an insulating layer 2 is grown on the surface of a silicon substrate 1 and on the inner walls (circumferential surface and bottom surface) of a silicon hole 9, the insulating layer 2 is deposited by thermal oxidation, chemical vapor deposition or physical vapor deposition, the insulating layer 2 can be made of inorganic substances such as silicon dioxide, aluminum oxide or silicon nitride, and the thickness of the insulating layer 2 is 0.5-1 micron; depositing a barrier layer 3 on the insulating layer 2, wherein the barrier layer 3 is deposited by adopting a physical vapor deposition or chemical vapor deposition method, the barrier layer 3 can be made of titanium, titanium nitride, tantalum nitride and the like, and the thickness of the barrier layer 3 is 50-100 nanometers; depositing a catalytic metal layer 4 on the barrier layer 3, wherein the catalytic metal layer 4 is made by an ion beam sputtering method or a physical vapor deposition method, cobalt or iron is generally selected as a material, and the thickness of the catalytic metal layer 4 is 2-5 nanometers.
As shown in fig. 3, the catalytic metal layer 4 is etched by plasma etching to form nano catalytic particles; the etching gas adopts hydrogen or argon, the plasma power density is 0.1-0.5(W/cm2), and the time is 0.5-3 minutes.
As shown in fig. 4, a carbon nano-material composite structure layer 5 is grown on the surface of the catalytic metal layer 4; the growth process is manufactured by a thermal chemical vapor deposition method, the carbon source gas adopts methane, the hydrogen is adopted as a protective gas, the total gas pressure is stabilized at 1kPa, and the growth temperature is 450-600 ℃; the growth of the carbon nanomaterial composite structure layer 5 firstly separates out the graphene layer from the catalytic metal cobalt, and then synthesizes the carbon nanomaterial composite structure layer 5 from the cobalt nanoparticles according to a tip growth mode, as shown in fig. 5, the upper layer of the grown carbon nanomaterial composite structure layer 5 is the graphene layer, and the lower layer is the carbon nanotube bundle array.
As shown in fig. 6, a dry film is attached to the surface of the carbon nanomaterial composite structure layer 5 on the silicon substrate 1, a silicon hole 9 structure is exposed through exposure and development, then a plurality of dry films are attached to the surface of the silicon substrate 1 by a hot pressing method, a photoetching machine is used for exposure, the exposed silicon substrate 1 is placed in a developing solution, a part of the dry film is removed, a dry film layer 6 with a required pattern is formed, the hole diameter of the dry film layer 6 is smaller than that of the silicon hole 9, and the hole of the dry film layer 6 is coaxial with the silicon hole 9.
As shown in fig. 7, a seed layer 7 is deposited on the bottom surface of the silicon via 9 and the surface of the dry film layer 6, the seed layer 7 is deposited on the bottom surface of the silicon via 9 and the surface of the dry film layer 6 by using the dry film layer 6 as a mask and adopting an electron beam evaporation or magnetron sputtering method, and the seed layer 7 is generally made of gold or copper; the seed layer 7 is used as a guide to carry out electroplating filling on the conductive material 8 in the silicon hole 9, the conductive material 8 is filled by adopting an electroplating method, and the conductive material 8 is generally copper; the inhibitor and accelerator are added to the plating solution to realize high-speed and high-quality filling of the conductive material 8 from bottom to top.
As shown in fig. 8, after filling, the bottom of the TSV channel is removed by chemical mechanical polishing and planarization is achieved. Under the process condition or service condition, the heat in the TSV channel can be rapidly transmitted up and down, left and right through the carbon nano material composite structure layer 5, and the heat diffusion is accelerated; meanwhile, the carbon nano material composite structure layer 5 is used as a thermal stress release and buffer layer of the filling material 8, so that the condition that TSV interconnection defects and even failure are caused by serious thermal stress mismatch between the filling material 8 and the insulating layer 2/silicon substrate 1 is avoided.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and any minor modifications, equivalent replacements and improvements made to the above embodiment according to the technical spirit of the present invention should be included in the protection scope of the technical solution of the present invention.
Claims (6)
1. A three-dimensional through silicon via vertical interconnection method based on a carbon nano material composite structure is characterized by comprising the following steps:
a. manufacturing a silicon hole (9) on a silicon substrate (1);
b. depositing an insulating layer (2) on the surface of the silicon substrate (1) and the inner wall of the silicon hole (9);
c. depositing a barrier layer (3) on the insulating layer (2), depositing a catalytic metal layer (4) on the barrier layer (3);
d. etching the catalytic metal layer (4) to form nano catalytic metal particles;
e. growing a carbon nano material composite structure layer (5) by utilizing nano catalytic metal particles, wherein the structure of the carbon nano material composite structure layer (5) is divided into two layers, the upper layer is horizontal multi-layer graphene, and the lower layer is a vertical carbon nano tube array;
f. sticking a dry film on the surface of the carbon nano material composite structure layer (5) on the silicon substrate (1), exposing and developing to form a dry film layer (6);
g. depositing a seed layer (7) on the bottom surface of the silicon hole (9) and the surface of the dry film layer (6);
h. and filling the silicon hole (9) with a conductive material (8).
2. The method for vertically interconnecting three-dimensional through silicon vias based on carbon nanomaterial composite structures of claim 1, wherein the catalytic metal layer (4) in the step c is made by ion beam sputtering or physical vapor deposition, and the material of the catalytic metal layer (4) is cobalt or iron.
3. The method for vertically interconnecting three-dimensional through silicon vias based on carbon nanomaterial composite structures of claim 1, wherein the nano catalytic particles in the step d are manufactured by a plasma etching method, and etching gas is hydrogen or argon.
4. The method for vertically interconnecting three-dimensional through silicon vias based on carbon nanomaterial composite structure according to claim 1, wherein the carbon nanomaterial composite structure layer (5) grown in step e is fabricated by thermal chemical vapor deposition, the carbon source gas is methane, hydrogen is used as protective gas, and the total gas pressure is stabilized at 1 kPa.
5. The method for vertically interconnecting three-dimensional through silicon vias based on carbon nanomaterial composite structure of claim 1, wherein the hole diameter of the dry film layer (6) in step f is smaller than the diameter of the silicon hole (9).
6. The method for vertically interconnecting through silicon vias based on carbon nanomaterial composite structures according to claim 1, wherein the step h is to fill the conductive material (8) into the silicon vias (9) by electroplating with the seed layer (7) as a guide.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710900247.2A CN107658263B (en) | 2017-09-28 | 2017-09-28 | Three-dimensional through silicon via vertical interconnection method based on carbon nano material composite structure |
| PCT/CN2018/000016 WO2019061926A1 (en) | 2017-09-28 | 2018-01-15 | Carbon nano-material composite structure-based three-dimensional silicon through-hole vertical interconnection method |
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| CN201710900247.2A CN107658263B (en) | 2017-09-28 | 2017-09-28 | Three-dimensional through silicon via vertical interconnection method based on carbon nano material composite structure |
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| CN107658263B true CN107658263B (en) | 2021-01-22 |
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| CN109524513A (en) * | 2018-11-23 | 2019-03-26 | 江苏新广联半导体有限公司 | A kind of silicon substrate flip LED chips and preparation method thereof |
| CN116435290B (en) * | 2023-06-13 | 2023-08-22 | 中诚华隆计算机技术有限公司 | Three-dimensional stacking structure and stacking method of chips |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102530931A (en) * | 2011-12-14 | 2012-07-04 | 天津大学 | Graphene-based nano composite material and preparation method thereof |
| CN102569181A (en) * | 2011-12-15 | 2012-07-11 | 中国科学院微电子研究所 | Method for manufacturing vertically interconnecting carbon nanotube bundle |
| CN103258789A (en) * | 2013-04-17 | 2013-08-21 | 华中科技大学 | Manufacturing method of through hole interconnection structure and product of through hole interconnection structure |
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| JP3730476B2 (en) * | 2000-03-31 | 2006-01-05 | 株式会社東芝 | Field emission cold cathode and manufacturing method thereof |
| US7084507B2 (en) * | 2001-05-02 | 2006-08-01 | Fujitsu Limited | Integrated circuit device and method of producing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102530931A (en) * | 2011-12-14 | 2012-07-04 | 天津大学 | Graphene-based nano composite material and preparation method thereof |
| CN102569181A (en) * | 2011-12-15 | 2012-07-11 | 中国科学院微电子研究所 | Method for manufacturing vertically interconnecting carbon nanotube bundle |
| CN103258789A (en) * | 2013-04-17 | 2013-08-21 | 华中科技大学 | Manufacturing method of through hole interconnection structure and product of through hole interconnection structure |
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| WO2019061926A1 (en) | 2019-04-04 |
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