WO2019042011A1 - 阵列基板及其制备方法、驱动方法、显示装置 - Google Patents

阵列基板及其制备方法、驱动方法、显示装置 Download PDF

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Publication number
WO2019042011A1
WO2019042011A1 PCT/CN2018/094614 CN2018094614W WO2019042011A1 WO 2019042011 A1 WO2019042011 A1 WO 2019042011A1 CN 2018094614 W CN2018094614 W CN 2018094614W WO 2019042011 A1 WO2019042011 A1 WO 2019042011A1
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Prior art keywords
transistor
line
gate
pixel
lines
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PCT/CN2018/094614
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English (en)
French (fr)
Inventor
陈虞龙
王念念
熊永
张祥
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京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Priority to US16/333,163 priority Critical patent/US10629135B2/en
Publication of WO2019042011A1 publication Critical patent/WO2019042011A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
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    • H10K59/131—Interconnections, e.g. wiring lines or terminals
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    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a preparation method thereof, a driving method, and a display device.
  • a typical display device includes an array substrate.
  • a plurality of gate lines and a plurality of data lines are arranged on the array substrate, and the plurality of gate lines and the plurality of data lines are vertically arranged to define a plurality of pixel regions (also referred to as sub-pixel regions).
  • a thin film transistor (TFT) that controls pixel display is disposed at an intersection of the gate line and the data line.
  • An aspect of the present disclosure provides an array substrate including a plurality of gate lines and a plurality of data lines extending in a mutual direction, a plurality of pixel units defined by the plurality of gate lines and the plurality of data lines, and a plurality of auxiliary electrode lines alternately arranged with the gate lines.
  • Each of the pixel units includes a first transistor, a second transistor, and a pixel electrode.
  • a control electrode of the first transistor is electrically connected to a gate line of a row of pixel cells in which the pixel unit is driven, a first pole of the first transistor is electrically connected to a data line, and the first a second pole of a transistor is electrically connected to the pixel electrode; a control pole of the second transistor is electrically connected to an auxiliary electrode line driving a row of the pixel unit in which the pixel unit is located, and a first pole of the second transistor and data The wires are electrically connected, and the second pole of the second transistor is electrically connected to the pixel electrode.
  • the array substrate further includes a third transistor disposed between each of the gate lines and an auxiliary electrode line adjacent thereto, the control electrode of the third transistor being electrically connected to the data line, and the first of the third transistor The pole is electrically connected to the gate line, and the second pole of the third transistor is electrically connected to the auxiliary electrode line.
  • the third transistor is disposed at an intersection of each of the gate lines and each of the data lines.
  • a first pole of the third transistor is electrically connected to the auxiliary electrode line that drives a row of pixel cells in which the pixel unit is located, and a second pole and a driving of the third transistor
  • the gate lines of adjacent row pixel units are electrically connected.
  • a first pole of the third transistor is electrically connected to the auxiliary electrode line that drives a row of pixel cells in which the pixel unit is located, and a second pole and a driving of the third transistor
  • the gate lines of the pixel unit row in which the pixel unit is located are electrically connected.
  • the semiconductor layer of at least one of the first transistor, the second transistor, and the third transistor includes an amorphous silicon layer and a doped layer.
  • the auxiliary electrode lines are multiplexed into a common electrode line.
  • Another aspect of the present disclosure provides a display device including any of the above array substrates.
  • Yet another aspect of the present disclosure provides a method of fabricating an array substrate, comprising: forming a first conductive layer and a second semiconductor layer on a base substrate, the first conductive layer including a plurality of gate lines and a plurality of alternately arranged lines An auxiliary semiconductor line, the second semiconductor layer including a third semiconductor pattern disposed between each of the gate lines and one of the auxiliary electrode lines adjacent thereto, the third semiconductor pattern and the gate line
  • the auxiliary electrode lines are all electrically contacted; a first semiconductor layer and a second conductive layer are formed.
  • the first semiconductor layer includes a plurality of first semiconductor patterns and a plurality of second semiconductor patterns, an orthogonal projection of the first semiconductor patterns and the gate lines on the base substrate, the second semiconductor The pattern and the orthographic projection of the auxiliary electrode lines on the base substrate overlap.
  • the second conductive layer includes a first source, a first drain, a second source, a second drain, and a plurality of data lines crossing the extending direction of the gate line, the first source and the The first drain is in electrical contact with the first semiconductor pattern, and the second source and the second drain are both in electrical contact with the second semiconductor pattern, the data line and the third semiconductor
  • the orthographic projection of the pattern on the substrate substrate overlaps.
  • the manufacturing method before the forming the first conductive layer and the second semiconductor layer on the base substrate, the manufacturing method further includes: forming a third conductive layer on the base substrate, the The three conductive layers include a plurality of pixel electrodes, each of which is electrically connected to a corresponding first drain and second drain to be formed.
  • the manufacturing method further includes: forming a third conductive layer, the third conductive layer including a plurality of pixels And an electrode, each of the pixel electrodes being electrically connected to the corresponding first drain and the second drain.
  • the third semiconductor pattern is formed by forming the third semiconductor pattern at an intersection position of each of the gate lines and each of the data lines.
  • a further aspect of the present disclosure provides a driving method of the above array substrate, comprising inputting a data signal to a pixel electrode connected to the first transistor and the second transistor through at least one of a first transistor and a second transistor.
  • a first pole of the third transistor is electrically connected to the auxiliary electrode line that drives a row of pixel cells in which the pixel unit is located, and a second pole and a driving of the third transistor
  • the gate lines of adjacent row pixel units are electrically connected.
  • a gate scan signal is input to a gate line row by row, and a pixel connected to the first transistor and the second transistor is connected to at least one of the first transistor and the second transistor
  • the electrode input data signal includes: inputting a data signal to a pixel electrode connected to the first transistor and the second transistor through the first transistor or the second transistor.
  • a gate scan signal is simultaneously input to each of the gate lines and another gate line adjacent to the gate lines.
  • Inputting the data signal to the pixel electrode connected to the first transistor and the second transistor through at least one of the first transistor and the second transistor includes: passing the first transistor and the second transistor in response to the first transistor being undamaged Both input a data signal to a pixel electrode connected to the first transistor and the second transistor, and are connected to the first transistor and the second transistor through a second transistor in response to damage of the first transistor The pixel electrode inputs a data signal.
  • an absolute value of a voltage of a gate scan signal input to the gate line is greater than a voltage absolute value of a gate scan signal input to the other gate line, and is configured to a first transistor connected to the gate line is turned on, and an absolute value of a voltage of the gate scan signal input to the other gate line is configured to turn on the second transistor through the third transistor and connect the other gate line
  • the first transistor is not conducting.
  • a first pole of the third transistor is electrically connected to the auxiliary electrode line that drives a row of pixel cells in which the pixel unit is located, and a second pole and a driving of the third transistor
  • the gate lines of the pixel unit row in which the pixel unit is located are electrically connected.
  • a gate scan signal is input to a gate line row by row, and a pixel connected to the first transistor and the second transistor is connected to at least one of the first transistor and the second transistor
  • the electrode input data signal includes: inputting a data signal to a pixel electrode connected to the first transistor and the second transistor through both the first transistor and the second transistor in response to the first transistor being undamaged, and responsive to the first The transistor is damaged and a data signal is input to the pixel electrode connected to the first transistor and the second transistor through the second transistor.
  • FIG. 1 is a schematic structural view of a typical array substrate
  • FIG. 2(a) is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • FIG. 2(b) is a second schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 3( a ) is a third structural diagram of an array substrate according to an embodiment of the present disclosure.
  • 3(b) is a schematic structural view 4 of an array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic flow chart of a method for preparing an array substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of forming a first conductive layer and a second semiconductor layer on a base substrate according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of forming a first conductive layer, a second semiconductor layer, a first semiconductor layer, and a second conductive layer on a base substrate according to an embodiment of the present disclosure
  • Figure 7 (a) is a cross-sectional view taken along line AA of Figure 6;
  • Figure 7 (b) is a cross-sectional view taken along line BB of Figure 6;
  • FIG. 8 is a schematic structural diagram of forming a first conductive layer, a second semiconductor layer, and a first semiconductor layer on a base substrate according to an embodiment of the present disclosure.
  • a typical TFT array substrate includes a plurality of gate lines G1, G2 and a plurality of data lines D1, D2, D3 crossing each other, a plurality of gate lines G1, G2, and a plurality of data lines D1, D2.
  • a plurality of pixel regions (also referred to as sub-pixel regions) defined by D3.
  • Each pixel region includes a transistor 20 and a pixel electrode 10. The transistor 20 is for controlling the input of a signal to the pixel electrode 10 to illuminate the pixel.
  • the inventors have found that in the case where the transistor 20 is damaged, the pixel electrode 10 connected to the transistor 20 is out of control, so that the pixel controlled by the transistor 20 is in a normally dark or steady state, thereby becoming a dark spot visible to the naked eye. This seriously affects product quality.
  • an embodiment of the present disclosure provides an array substrate, as shown in FIG. 2(a), FIG. 2(b), FIG. 3(a), and FIG. 3(b), including a plurality of gate lines G1 crossing each other. , G2, G3, ... and a plurality of data lines D1, D2, D3, ..., a plurality of pixel units defined by a plurality of gate lines and a plurality of data lines, and a gate line G1 G2, G3, ... a plurality of auxiliary electrode lines C1, C2, ... arranged alternately.
  • Each of the pixel units includes a first transistor T1, a second transistor T2, and a pixel electrode 10.
  • the control electrode of the first transistor T1 is electrically connected to the gate line of the pixel unit row in which the driving pixel unit is located, the first electrode of the first transistor T1 is electrically connected to the data line, and the second electrode of the first transistor T1 is electrically connected to the pixel electrode 10.
  • the control electrode of the second transistor T2 is electrically connected to the auxiliary electrode line of the row of the pixel unit, the first electrode of the second transistor T2 is electrically connected to the data line, and the second electrode of the second transistor T2 is electrically connected to the pixel electrode.
  • a third transistor T3 is disposed between the gate line and an auxiliary electrode line adjacent thereto, and a control electrode of the third transistor T3 is electrically connected to the data line, and a first electrode of the third transistor T3 is electrically connected to the gate line, and The second pole of the three transistor T3 is electrically connected to the auxiliary electrode line.
  • each of the gate lines has two adjacent auxiliary electrode lines, and each auxiliary electrode The line has two adjacent grid lines.
  • the auxiliary electrode line C1 and the auxiliary electrode line C2 are adjacent to the gate line G2, respectively, and the gate line G1.
  • the gate line G2 are adjacent to the auxiliary electrode line C1, respectively.
  • a third transistor T3 is disposed between the gate line and an auxiliary electrode line adjacent thereto, meaning that a third crystal T3 is disposed between the auxiliary electrode line C1 and the gate line G2, or the auxiliary electrode line C2 and the gate electrode G2 are provided.
  • a third transistor T3 is provided between.
  • third transistors T3 disposed between the gate lines and one of the auxiliary electrode lines adjacent thereto is not limited.
  • only one third transistor T3 is provided between the gate line and an auxiliary electrode line adjacent thereto.
  • two or more third transistors T3 may be disposed between the gate lines and one of the auxiliary electrode lines adjacent thereto as shown in FIGS. 2(b) and 3(b).
  • the auxiliary electrode line may be a signal line provided in the array substrate itself, or may be an additional signal line, which is not limited thereto.
  • a voltage may be input in advance on the auxiliary electrode line, but the voltage is smaller than the minimum driving voltage of the control electrode of the second transistor T2, that is, smaller than the minimum conduction voltage of the second transistor T2 (when the second transistor T2 When the gate voltage is greater than the minimum driving voltage of the gate, the second transistor T2 can be turned on.
  • a voltage may not be input in advance on the auxiliary electrode line.
  • the gate of the first transistor T1 is electrically connected to the gate line of the row of the pixel unit in which the pixel unit is driven, and thus the first transistor T1 is in an on state when the gate line inputs a scan signal.
  • the control electrode of the second transistor T2 is electrically connected to the auxiliary electrode line of the row of pixel cells in which the driving pixel unit is located. Since the voltage signal input to the auxiliary electrode line is low, the second transistor T2 cannot be turned on, and the second transistor T2 is turned off. The second transistor T2 can be turned on only when the third transistor T3 is turned on under the control of the connected data line, and the voltage on the gate line is input to the auxiliary electrode line through the third transistor T3.
  • the magnitude of the minimum driving voltage for driving the second transistor T2 to be turned on can be adjusted by adjusting the material of the semiconductor layer of the second transistor T2.
  • the maximum voltage allowed to pass by the third transistor T3 can be adjusted by adjusting the material of the semiconductor layer of the third transistor T3.
  • the pixel electrode 10 of each pixel unit of the array substrate is connected to both the first transistor T1 and the second transistor T2, respectively, in the first transistor T1 and the second transistor T2
  • the pixel can be lit by another transistor, thereby avoiding the problem that the pixel unit is in a normally dark or always bright state, thereby effectively reducing the defect of the display panel and improving the product quality.
  • the signal on the gate line can also be input to the auxiliary electrode line connected to the third transistor T3 through the third transistor T3. If only one third transistor T3 or a small number of third transistors T3 is disposed between the gate line and an auxiliary electrode line adjacent thereto, on the one hand, the signal on the gate line cannot be quickly input to the auxiliary electrode line through the third transistor T3. On the other hand, due to the inherent loss of the auxiliary electrode line, the signal at the position farther from the third transistor T3 in the auxiliary electrode line is weaker, which may cause the voltage input to the pixel electrode 10 on the array substrate to be uneven, thereby affecting display effect.
  • the third transistor T3 is disposed at the intersection of each of the gate lines and each of the data lines.
  • each gate line and each data line does not refer to a specific intersection, but refers to a certain area around the intersection.
  • the third transistor T3 is disposed at the intersection of each of the gate lines and each of the data lines, that is, a plurality of third portions are disposed between the adjacent gate lines and the auxiliary electrode lines Transistor T3, thus when a signal is input to the gate line, a signal on the gate line can be input to the auxiliary electrode line connected to the third transistor T3 through the plurality of third transistors T3.
  • the first electrode of the third transistor T3 is electrically connected to the auxiliary electrode line of the row of pixel cells in which the driving pixel unit is located, and the third transistor The second pole of T3 is electrically coupled to the gate line that drives the adjacent row of pixel cells.
  • gate drive signals are input to the gate lines G1, G2, ..., Gn row by row.
  • the gate driving signal is input to the gate line G1
  • the first transistor T1 connected to the gate line G1 is not damaged, the first transistor T1 is turned on, and the data signal on the data line D1 is input to the pixel through the first transistor T1.
  • Electrode 102 At this time, the voltage on the auxiliary electrode line C1 is smaller than the minimum on voltage of the second transistor T2, and thus the second transistor T2 is in an off state.
  • the gate driving signal When the gate driving signal is input to the gate line G2, if the first transistor T1 connected to the gate line G2 is not damaged, the first transistor T1 is turned on, and the data signal on the data line is input to the pixel through the first transistor T1. Electrode 101. At the same time, the gate driving signal on the gate line G2 is also input to the auxiliary electrode line C1 through the third transistor T3, so that the voltage on the auxiliary electrode line C1 is increased to be larger than the minimum on-voltage of the second transistor T2.
  • the voltage on the auxiliary electrode line C1 is increased but smaller than the pixel voltage of the pixel electrode 102, that is, the gate voltage of the second transistor T2 is smaller than a second pole voltage of the second transistor T2 (the control electrode of the second transistor T2 is connected to the auxiliary electrode line C1, and the second electrode of the second transistor T2 is connected to the pixel electrode 102), so according to the nature of the transistor, on the data line D1 The voltage cannot be input to the pixel electrode 102 through the second transistor T2.
  • the gate drive signals are input to the gate lines G1, G2, ..., Gn row by row.
  • the gate driving signal is input to the gate line G1
  • the first transistor T1 connected to the gate line G1 is damaged, the first transistor T1 is turned off, and the data signal on the data line cannot be input to the pixel electrode 102 through the first transistor T1.
  • the voltage signal on the auxiliary electrode line C1 is smaller than the minimum on-voltage of the second transistor T2, and therefore the second transistor T2 is also in an off state.
  • the gate driving signal is input to the gate line G2 if the first transistor T1 connected to the gate line G2 is not damaged, the first transistor T1 is turned on.
  • the data signal on the data line is input to the pixel electrode 101 through the first transistor T1.
  • the signal on the gate line G2 is also input to the auxiliary electrode line C1 through the third transistor T3, so that the voltage on the auxiliary electrode line C1 is increased to be larger than the minimum on-voltage of the second transistor T2, so the second transistor T2 leads through. Since the voltage on the data line is not input to the pixel electrode 102 when the gate line G1 is turned on, at this time, the voltage on the data line can be input to the pixel electrode 102 through the second transistor T2, so that the pixel electrode 101 and the pixel electrode 102 Input the signal at the same time.
  • the pre-input voltage on the auxiliary electrode line is 5V
  • the data voltage on the data line D1 is 10V
  • the gate driving voltage on the gate line G1 is 25V.
  • the gate driving voltage is input to the gate line G1
  • the first transistor T1 is not damaged
  • the data voltage is input to the pixel electrode 102 through the first transistor T1.
  • the gate voltage of the second transistor T2 is 5 V, which is lower than the minimum on voltage of the second transistor T2 (for example, 6 V)
  • the second transistor T2 is turned off.
  • the pre-input voltage on the auxiliary electrode line is 5V
  • the data voltage on the data line D1 is 10V
  • the gate driving voltage on the gate line G2 is 25V
  • the pixel voltage of the pixel electrode 102 is 8V.
  • the auxiliary electrode line C1 is electrically connected to the control electrode of the second transistor T2.
  • the gate voltage of the second transistor T2 is boosted by the gate line G2 to 7V, but at this time, the gate voltage (7V) of the second transistor T2 is lower than the pixel voltage (8V) of the pixel electrode 102, so the second transistor T2 is turned off. .
  • the purpose of automatically shielding the second transistor T2 when the first transistor T1 is normal is realized.
  • the pre-input voltage on the auxiliary electrode line is 5V
  • the data voltage on the data line D1 is 10V
  • the gate driving voltage on the gate line G1 is 25V
  • the first transistor T1 is damaged.
  • the data voltage is not loaded on the pixel electrode 102.
  • the gate voltage of the second transistor T2 is 5V, which is lower than the minimum on voltage of the second transistor T2, the second transistor T2 is turned off.
  • the auxiliary electrode line C1 is electrically connected to the control electrode of the second transistor T2.
  • the gate voltage of the second transistor T2 is boosted by the auxiliary electrode line to 7V.
  • the gate voltage (7V) of the second transistor T2 is higher than the data voltage (3V) of the pixel electrode 102 and higher than the minimum turn-on voltage (6V) of the second transistor T2, so that the second transistor T2 is turned on, thereby The purpose of automatically turning on the second transistor T2 when the first transistor T1 is damaged is realized.
  • the gate lines G1, G2, ..., Gn are simultaneously scanned every two rows, and all the gate lines are scanned one by two in each frame and are gated to the gate line Gn.
  • the input gate drive voltage is smaller than the gate drive voltage input to the gate line Gn.
  • the gate driving signal is simultaneously input to the gate line G1 and the gate line G2, and the gate driving voltage input to the gate line G1 is greater than the gate driving voltage input to the gate line G2; at the second clock In the period, the gate driving signal is simultaneously input to the gate line G2 and the gate line G3, and the gate driving voltage input to the gate line G2 is greater than the gate driving voltage input to the gate line G3; in the third clock period, the gate is turned on The line G3 and the gate line G4 simultaneously input a gate driving signal, and the gate driving voltage input to the gate line G3 is larger than the gate driving voltage input to the gate line G4, and so on.
  • the gate driving voltage input to the gate line G1 is larger than the gate driving voltage input to the gate line G2.
  • the voltage signal on the gate line G1 can turn on the first transistor T1 connected to the gate line G1, and the voltage signal on the gate line G2 can turn on the second transistor T2 connected to the auxiliary electrode line C1 through the third transistor T3.
  • the first transistor T1 connected to the gate line G2 cannot be turned on. If the first transistor T1 connected to the pixel electrode 102 is not damaged, when the gate driving voltage is simultaneously input to the gate line G1 and the gate line G2, the first transistor T1 is turned on, and the data signal on the data line passes through the first transistor T1.
  • the voltage on the gate line G2 is input to the auxiliary electrode line C1 through the third transistor T3, so that the voltage on the auxiliary electrode line C1 is increased to be larger than the minimum on-voltage of the second transistor T2, and the auxiliary electrode line C1
  • the connected second transistor T2 is turned on, so the voltage on the data line is input to the pixel electrode 102 through the second transistor T2. That is, the voltage on the data line is simultaneously input to the pixel electrode 102 through the first transistor T1 and the second transistor T2.
  • the first transistor T1 connected to the pixel electrode 102 is damaged, when the gate driving voltage is simultaneously input to the gate line G1 and the gate line G2, the data signal on the data line cannot be input to the pixel electrode 102 through the first transistor T1.
  • the voltage on the gate line G2 is input to the auxiliary electrode line C1 through the third transistor T3, so that the voltage on the auxiliary electrode line C1 is increased to be larger than the minimum on-voltage of the second transistor T2, and thus is connected to the auxiliary electrode line C1.
  • the second transistor T2 is turned on, so that the data voltage on the data line is input to the pixel electrode 102 through the second transistor T2, and the pixel unit corresponding to the pixel electrode 102 is lit.
  • the first electrode of the third transistor T3 is electrically connected to the auxiliary electrode line of the pixel unit row in which the driving pixel unit is located, and the third transistor The second pole of T3 is electrically connected to the gate line of the row of pixel cells in which the driving pixel unit is located.
  • gate drive signals are input to the gate lines G1, G2, ..., Gn row by row.
  • the gate driving signal is input to the gate line G1
  • the first transistor T1 connected to the gate line G1 is not damaged, the first transistor T1 is turned on, and the data signal on the data line is input to the pixel electrode 10 through the first transistor T1.
  • the signal on the gate line is input to the auxiliary electrode line through the third transistor T3, the voltage on the auxiliary electrode line rises to be greater than the driving voltage of the second transistor T2, and the second transistor T2 is turned on, and the data on the data line
  • the signal is also input to the pixel electrode 10 through the second transistor T2.
  • the data signal on the data line will be input to the pixel electrode 10 only through the second transistor T2.
  • the semiconductor layers of the first transistor T1, the second transistor T2, and the third transistor T3 may include an amorphous silicon ( ⁇ -Si) layer and an N-type doped layer. That is, the first transistor T1, the second transistor T2, and the third transistor T3 may be N-type transistors.
  • the operation of the array substrate is described by taking the first transistor T1, the second transistor T2, and the third transistor T3 as N-type transistors as an example in the above description, the first transistor T1 and the second transistor T2 are described.
  • One or more of the third transistor T3 and the third transistor T3 may also be P-type transistors, and details are not described herein again.
  • the maximum allowable voltage that the transistor is allowed to pass without damaging the transistor and the minimum turn-on voltage that causes the transistor to conduct can be adjusted.
  • the auxiliary electrode lines may be multiplexed into a common electrode line.
  • a voltage is previously input to the common electrode line, but the voltage is smaller than the minimum on-voltage of the second transistor T2, and thus although the gate electrode of the second transistor T2 is connected to the common electrode line, The second transistor T2 cannot be turned on.
  • an embodiment of the present disclosure provides a display device including any of the above array substrates.
  • the display device may be a liquid crystal display device (LCD) or an organic light-emitting diode display device (OLED).
  • the display device is a liquid crystal display device
  • the liquid crystal display device includes an array substrate, a counter substrate, and a liquid crystal layer disposed between the array substrate and the counter substrate.
  • the organic electroluminescent diode display device includes an array substrate and a package cover.
  • the display device can be any device that displays whether motion (eg, video) or fixed (eg, still image) and whether text or image. More specifically, it is contemplated that the above-described embodiments can be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs), Handheld or portable computer, GPS receiver/navigator, camera, MP4 video player, camera, game console, watch, clock, calculator, TV monitor, flat panel display, computer monitor, car display (eg mileage Table display, etc.), navigator, cockpit controller and/or display, camera view display (eg, rear view camera display in a vehicle), electronic photo, electronic billboard or signage, projector, building structure, packaging and Aesthetic structure (for example, a display for an image of a piece of jewelry), etc. Further, the display device may also be a display panel.
  • PDAs personal data assistants
  • Handheld or portable computer GPS receiver/navigator, camera, MP4 video player, camera, game console, watch,
  • Embodiments of the present disclosure provide a display device including the above array substrate. Since the pixel electrode 10 of each pixel unit of the array substrate is connected to the first transistor T1 and the second transistor T2, respectively, when one of the first transistor T1 and the second transistor T2 is in a damaged state, another transistor can be passed. The pixel is lit, thus avoiding the problem that the pixel is in a dark or steady state, thereby effectively reducing the defect of the point and improving the product quality.
  • Embodiments of the present disclosure also provide a method of fabricating an array substrate.
  • Fig. 4 is a flow chart showing the preparation method.
  • a first conductive layer and a second semiconductor layer are formed on a base substrate 110 (for example, may be a glass substrate).
  • the first conductive layer includes a plurality of gate lines 30 and a plurality of auxiliary electrode lines 40 alternately arranged.
  • the second semiconductor layer includes a plurality of third semiconductor patterns 50.
  • the third semiconductor pattern 50 is formed between the gate line 30 and one of the auxiliary electrode lines 40 adjacent thereto, and is in electrical contact with the gate line 30 and the auxiliary electrode line 40.
  • the first conductive layer may be formed first, and then the second semiconductor layer may be formed.
  • the second semiconductor layer may be formed first, and then the first conductive layer may be formed, which is not limited thereto.
  • the auxiliary electrode lines 40 in the first conductor layer may be provided by the array substrate itself (for example, a common electrode line), or may be additionally provided.
  • the material of the third semiconductor pattern 50 is not limited.
  • the third semiconductor pattern 50 may be composed of an amorphous silicon layer and a doped layer.
  • the forming process of the third semiconductor pattern 50 may be: first depositing an amorphous silicon film and a doped film on the substrate, and then forming the third semiconductor pattern 50 by a patterning process.
  • each gate line has two adjacent auxiliary electrode lines except for the outermost gate line and the auxiliary electrode line, and each auxiliary line The electrode lines have two adjacent gate lines.
  • a third semiconductor pattern 50 is formed between the gate line 30 and an auxiliary electrode line 40 adjacent thereto, and may be the gate line 30 in the row of the pixel unit in which the pixel unit is driven and the auxiliary electrode line 40 in the row of the pixel unit in which the driving pixel unit is located The third semiconductor pattern 50 is disposed therebetween, and the third semiconductor pattern 50 may be disposed between the auxiliary electrode line 40 that drives the pixel unit row in which the pixel unit is located and the gate line 30 that drives the adjacent row pixel unit.
  • a gate insulating layer (Gate Insulator, GI for short) 120 is formed on the base substrate 110.
  • the material of the gate insulating layer 120 is not limited, and may be, for example, at least one of silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy).
  • the first semiconductor layer includes a plurality of first semiconductor patterns 60 and a plurality of second semiconductor patterns 70.
  • the orthographic projection of the first semiconductor pattern 60 and the gate line 30 on the base substrate 110 overlaps, and the orthographic projection of the second semiconductor pattern 70 and the auxiliary electrode line 40 on the base substrate 110 overlaps.
  • the second conductive layer includes a first source 801, a first drain 802, a second source 901, a second drain 902, and a plurality of data lines 100 crossing the extending direction of the gate lines 30.
  • the first source 801 and the first drain 802 are both in electrical contact with the first semiconductor pattern 60, and the second source 901 and the second drain 902 are both in electrical contact with the second semiconductor pattern 70.
  • the orthographic projection of the data line 100 and the third semiconductor pattern 50 on the base substrate 110 overlaps.
  • 7(a) and 7(b) are respectively a cross-sectional view taken along line AA of FIG. 6 and a cross-sectional view taken along line BB to show the structure of the array substrate in detail.
  • a first semiconductor layer is formed first, and a second conductive layer is formed.
  • the second conductive layer may be formed first to form the first semiconductor layer, which is not limited thereto.
  • the first source 801, the first drain 802, and the first semiconductor pattern 60 constitute a first transistor T1
  • the second source 901, the second drain 902, and the second semiconductor pattern 70 constitute a second transistor.
  • T2 and the third semiconductor pattern 50 and the portions of the gate line 30 and the auxiliary electrode line 40 in electrical contact with the third semiconductor pattern 50 constitute the third transistor T3 as shown in Fig. 7(a).
  • the forming process of the second conductive layer may be performed by depositing a second conductive layer film on the substrate, and then forming a first source 801, a first drain 802, and a second by a patterning process.
  • the materials of the first semiconductor pattern 60 and the second semiconductor pattern 70 are not limited.
  • the first semiconductor pattern 60 and the second semiconductor pattern 70 may be composed of an amorphous silicon layer and a doped layer. Specifically, an amorphous silicon film and a doped film may be first deposited on the substrate. The first semiconductor pattern 60 and the second semiconductor pattern 70 are then formed by a patterning process.
  • the above method may further include forming a passivation layer (PVX) and a common electrode.
  • PVX passivation layer
  • Embodiments of the present disclosure provide a method of fabricating an array substrate.
  • the first transistor T1 and the second transistor T2 are both electrically connected to the pixel electrode 10, thus being the first
  • the pixel can be lit by another transistor, thereby avoiding the problem that the pixel is in a normally dark or steady state, thereby effectively reducing the defect of the point and improving the product quality.
  • the above preparation method may further include forming a third conductive layer on the base substrate, the third conductive layer including Piezoelectric electrodes 10.
  • the pixel electrode 10 is electrically connected to both the first drain 802 and the second drain 902 to be formed.
  • the above-described preparation method may further include forming a third conductive layer, and the third conductive layer includes a plurality of pixel electrodes 10.
  • the pixel electrodes 10 are each electrically connected to the first drain 802 and the second drain 902.
  • the material of the pixel electrode 10 may include at least one of ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).
  • the forming process of the third conductive layer may specifically include first forming a third conductive film on the base substrate, and then forming a pixel electrode by a patterning process.
  • forming the third semiconductor pattern 50 between the gate line 30 and one of the auxiliary electrode lines 40 adjacent thereto includes: driving the auxiliary electrode line 40 and driving adjacent line pixels in the row of the pixel unit in which the pixel unit is driven A plurality of third semiconductor patterns 50 are formed between the gate lines 30 of the cells.
  • each of the third semiconductor patterns 50 and the data lines 100 on the base substrate 110 overlaps.
  • the third transistor including the third semiconductor pattern 50 is turned on.
  • the plurality of third semiconductor patterns 50 are formed between the auxiliary electrode lines 40 of the pixel unit rows in which the pixel unit is driven and the gate lines 30 driving the adjacent row pixel units, and the third semiconductor patterns 50 and the gates are formed. Both the line 30 and the auxiliary electrode line 40 are in electrical contact, so that when the third transistor including the third semiconductor pattern 50 is turned on, the signal on the gate line 30 can be input to the auxiliary electrode line 40 through the plurality of third semiconductor patterns 50.
  • the first electrode of the third transistor T3 of the array substrate is electrically connected to the auxiliary electrode line 40 of the pixel unit row where the driving pixel unit is located, and the third transistor T3 of the array substrate is electrically connected.
  • the embodiment of the present disclosure further provides a method for driving the array substrate, including: through the first transistor T1 and/or the second transistor T2 A pixel electrode 10 connected to a transistor T1 and a second transistor T2 inputs a data signal.
  • the data signal may be simultaneously input to the pixel electrode 10 connected to the first transistor T1 and the second transistor T2 through the first transistor T1 and the second transistor T2, or may be passed through the first transistor T1 or the second transistor.
  • T2 inputs a data signal to the pixel electrode 10 connected to the first transistor T1 and the second transistor T2.
  • the pixel electrode 10 of each pixel unit of the array substrate is respectively connected to the first transistor T1 and the second transistor T2, the first transistor T1 and the second transistor are When one of the transistors T2 is in a damaged state, the pixel can be lit by another transistor, thereby avoiding the problem that the pixel is in a normally dark or always bright state, thereby effectively reducing the defect of the point and improving the product quality.
  • the gate lines are progressively scanned, and inputting the data signals to the pixel electrodes 10 connected to the first transistor T1 and the second transistor T2 through the first transistor T1 and/or the second transistor T2 includes: A transistor T1 or a second transistor T2 inputs a data signal to the pixel electrode 10 connected to the first transistor T1 and the second transistor T2.
  • gate drive signals are input to the gate lines G1, G2, ..., Gn row by row.
  • the gate driving signal is input to the gate line G1
  • the first transistor T1 connected to the gate line G1 is not damaged, the first transistor T1 is turned on, and the data signal on the data line is input to the pixel electrode through the first transistor T1.
  • the voltage on the auxiliary electrode line C1 is smaller than the minimum on voltage of the second transistor T2, and thus the second transistor T2 is in an off state.
  • the gate driving signal When the gate driving signal is input to the gate line G2, if the first transistor T1 connected to the gate line G2 is not damaged, the first transistor T1 is turned on, and the data signal on the data line is input to the pixel through the first transistor T1. Electrode 101. At the same time, the gate driving signal on the gate line G2 is also input to the auxiliary electrode line C1 through the third transistor T3, so that the voltage on the auxiliary electrode line C1 is increased to be larger than the minimum on-voltage of the second transistor T2.
  • the voltage on the auxiliary electrode line C1 is increased but smaller than the pixel voltage of the pixel electrode 102, that is, the gate voltage of the second transistor T2 is smaller than a second pole voltage of the second transistor T2 (the control electrode of the second transistor T2 is connected to the auxiliary electrode line C1, and the second electrode of the second transistor T2 is connected to the pixel electrode 102), so the voltage on the data line according to the nature of the transistor It cannot be input to the pixel electrode 102 through the second transistor T2.
  • the first transistor T1 connected to the gate line G1 is damaged, the first transistor T1 is turned off, and the data signal on the data line cannot be input to the pixel electrode 102 through the first transistor T1.
  • the voltage signal on the auxiliary electrode line C1 is smaller than the minimum on-voltage of the second transistor T2, and therefore the second transistor T2 is also in an off state.
  • the gate driving signal is input to the gate line G2 if the first transistor T1 connected to the gate line G2 is not damaged, the first transistor T1 is turned on. At this time, the data signal on the data line is input to the pixel electrode 101 through the first transistor T1.
  • the signal on the gate line G2 is also input to the auxiliary electrode line C1 through the third transistor T3, so that the voltage on the auxiliary electrode line C1 is increased to be larger than the minimum on-voltage of the second transistor T2, so the second transistor T2 leads through. Since the voltage on the data line is not input to the pixel electrode 102 when the gate line G1 is turned on, at this time, the voltage on the data line can be input to the pixel electrode 102 through the second transistor T2, so that the pixel electrode 101 and the pixel electrode 102 Input the signal at the same time.
  • the first transistor T1 when the first transistor T1 is not damaged, a signal is input to the pixel electrode 101 through the first transistor T1 connected to the pixel electrode 101; when the first transistor T1 is damaged, through the pixel electrode
  • the second transistor T2 connected to 101 inputs a signal to the pixel electrode 101.
  • the gate driving signal is simultaneously input to the gate line and another gate line adjacent to the gate line, and then the first transistor T1 and/or the second transistor T2 are passed to the first transistor T1.
  • the pixel electrode input data signal connected to the second transistor T2 includes inputting a data signal to the same pixel electrode 10 connected to the first transistor T1 and the second transistor T2 through the first transistor T1 and the second transistor T2.
  • the voltage of the gate driving signal input to the gate line is greater than the voltage of the gate driving signal input to the other gate line adjacent to the gate line.
  • the voltage signal on the gate line is configured to turn on the first transistor T1 connected to the gate line, and the voltage signal on the other gate line adjacent to the gate line is configured to be second through the third transistor T3 Transistor T2 is turned on.
  • the gate scan signal is input to the gate line and the other gate line adjacent to the gate line, only the pixel electrode 10 in the pixel unit row driven by the gate line is connected to the pixel electrode 10.
  • the first transistor T1 and the second transistor T2 input data signals, and the pixel electrodes 10 of the other pixel unit rows cannot input the data signal because the voltage of the gate driving signal input to the other gate line adjacent to the gate line It is lower than the minimum on-voltage of the first transistor T1 connected to the other gate line.
  • the input of the data signal to the same pixel electrode 10 connected to the first transistor T1 and the second transistor T2 through the first transistor T1 and the second transistor T2 means that neither the first transistor T1 nor the second transistor T2 is present.
  • the data signal can be input to the pixel electrode 10 only by another transistor that is not damaged.
  • the voltage signal on the gate line G1 is larger than the voltage signal on the gate line G2, and the voltage signal on the gate line G1 can be connected to the gate line G1.
  • a transistor T1 is turned on, and the voltage signal on the gate line G2 can turn on the second transistor T2 connected to the auxiliary electrode line C1 through the third transistor T3, but the first transistor T1 connected to the gate line G2 cannot be turned on. If the first transistor T1 connected to the pixel electrode 102 is not damaged, when the gate scan signal is simultaneously input to the gate line G1 and the gate line G2, the first transistor T1 is turned on, and the data signal on the data line passes through the first transistor T1.
  • the voltage signal on the gate line G2 is input to the auxiliary electrode line C1 through the third transistor T3, so that the voltage on the auxiliary electrode line C1 is increased to be larger than the minimum on-voltage of the second transistor T2, thereby being connected to the auxiliary electrode line C1.
  • the second transistor T2 is turned on, so the voltage on the data line is input to the pixel electrode 102 through the second transistor T2. That is, the voltage on the data line is simultaneously input to the pixel electrode 102 through the first transistor T1 and the second transistor T2.
  • the first transistor T1 connected to the pixel electrode 102 is damaged, when the gate scan signal is simultaneously input to the gate line G1 and the gate line G2, the data signal on the data line cannot be input to the pixel electrode 102 through the first transistor T1.
  • the voltage on the gate line G2 is input to the auxiliary electrode line C1 through the third transistor T3, so that the voltage on the auxiliary electrode line C1 is increased to be larger than the minimum on-voltage of the second transistor T2, and thus is connected to the auxiliary electrode line C1.
  • the second transistor T2 is turned on, and the data voltage on the data line is input to the pixel electrode 102 through the second transistor T2, thereby lighting the pixel unit where the pixel electrode 102 is located.
  • the first transistor T1 and/or the second transistor T2 may be passed to the first transistor T1.
  • the pixel electrode 10 connected to the second transistor T2 inputs a data signal, thereby preventing the pixel from being in a normally dark or normally bright state when the first transistor T1 connected to the pixel electrode 10 is damaged.
  • One or more of the first transistor, the second transistor, and the third transistor may be P-type transistors. Since the conduction condition of the P-type transistor is opposite to that of the N-type transistor, when the voltage signal on the gate line G1 is larger than the voltage signal on the gate line G2, in the case of using the P-type transistor, it means the gate line G1. The absolute value of the voltage signal on the upper side is greater than the absolute value of the voltage signal on the gate line G2.

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Abstract

本公开实施例提供一种阵列基板及其制备方法、驱动方法、显示装置。该阵列基板包括延伸方向相互交叉的多条栅线和多条数据线、由所述多条栅线和所述多条数据线限定的多个像素单元，以及与所述栅线交替排列的多条辅助电极线。每个像素单元包括第一晶体管、第二晶体管和像素电极。所述阵列基板还包括设置在每一条栅线和与其相邻的一条辅助电极线之间的第三晶体管，所述第三晶体管的控制极与数据线电连接，所述第三晶体管的第一极与所述栅线电连接，并且所述第三晶体管的第二极与所述辅助电极线电连接。

Description

阵列基板及其制备方法、驱动方法、显示装置
相关申请
本申请要求享有2017年8月30日提交的中国专利申请No.201710765829.4的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、驱动方法、显示装置。
背景技术
典型的显示装置包括阵列基板。在阵列基板上布置多条栅线和多条数据线，多条栅线与多条数据线垂直交叉排列限定多个像素区域(也可以称为亚像素区域)。在栅线和数据线的交叉位置设置有控制像素显示的薄膜晶体管(TFT)。
发明内容
本公开的一方面提供了一种阵列基板，包括延伸方向相互交叉的多条栅线和多条数据线、由所述多条栅线和所述多条数据线限定的多个像素单元，以及与所述栅线交替排列的多条辅助电极线。每个像素单元包括第一晶体管、第二晶体管和像素电极。在每一个像素单元中，所述第一晶体管的控制极与驱动所述像素单元所在像素单元行的栅线电连接，所述第一晶体管的第一极与数据线电连接，并且所述第一晶体管的第二极与所述像素电极电连接；所述第二晶体管的控制极与驱动所述像素单元所在像素单元行的辅助电极线电连接，所述第二晶体管的第一极与数据线电连接，并且所述第二晶体管的第二极与所述像素电极电连接。所述阵列基板还包括设置在每一条栅线和与其相邻的一条辅助电极线之间的第三晶体管，所述第三晶体管的控制极与数据线电连接，所述第三晶体管的第一极与所述栅线电连接，并且所述第三晶体管的第二极与所述辅助电极线电连接。
根据本公开的一些示例性实施例，在每条所述栅线和每条所述数据线的交叉位置处均设置有所述第三晶体管。
根据本公开的一些示例性实施例，所述第三晶体管的第一极与驱动所述像素单元所在像素单元行的所述辅助电极线电连接，并且所述第三晶体管的第二极与驱动相邻行像素单元的所述栅线电连接。
根据本公开的一些示例性实施例，所述第三晶体管的第一极与驱动所述像素单元所在像素单元行的所述辅助电极线电连接，并且所述第三晶体管的第二极与驱动所述像素单元所在像素单元行的所述栅线电连接。
根据本公开的一些示例性实施例，所述第一晶体管、第二晶体管和第三晶体管中的至少一个的半导体层包括非晶硅层和掺杂层。
根据本公开的一些示例性实施例，所述辅助电极线被复用为公共电极线。
本公开的另一方面提供了一种显示装置，包括上述任一种阵列基板。
本公开的又一方面提供了一种阵列基板的制备方法，包括：在衬底基板上形成第一导电层和第二半导体层，所述第一导电层包括交替排列的多条栅线和多条辅助电极线，所述第二半导体层包括设置在每一条栅线和与其相邻的一条所述辅助电极线之间的第三半导体图案，所述第三半导体图案与所述栅线和所述辅助电极线均电接触；形成第一半导体层和第二导电层。所述第一半导体层包括多个第一半导体图案和多个第二半导体图案，所述第一半导体图案和所述栅线在所述衬底基板上的正投影交叠，所述第二半导体图案和所述辅助电极线在所述衬底基板上的正投影交叠。所述第二导电层包括第一源极、第一漏极、第二源极、第二漏极以及与所述栅线的延伸方向交叉的多条数据线，所述第一源极和所述第一漏极均与所述第一半导体图案电接触，所述第二源极和所述第二漏极均与所述第二半导体图案电接触，所述数据线和所述第三半导体图案在所述衬底基板上的正投影交叠。
根据本公开的一些示例性实施例，在衬底基板上形成第一导电层和第二半导体层之前，所述制备方法还包括：在所述衬底基板上形成第三导电层，所述第三导电层包括多个像素电极，每一个像素电极与待形成的对应的第一漏极和第二漏极均电连接。
根据本公开的一些示例性实施例，在衬底基板上形成第一半导体层和第二导电层之后，所述制备方法还包括：形成第三导电层，所述 第三导电层包括多个像素电极，每一个像素电极均与对应的所述第一漏极和所述第二漏极电连接。
根据本公开的一些示例性实施例，所述第三半导体图案通过以下步骤形成：在每条所述栅线和每条所述数据线的交叉位置处均形成所述第三半导体图案。
本公开另外的方面提供了一种上述阵列基板的驱动方法，包括通过第一晶体管和第二晶体管中的至少一个向与所述第一晶体管和所述第二晶体管相连的像素电极输入数据信号。
根据本公开的一些示例性实施例，所述第三晶体管的第一极与驱动所述像素单元所在像素单元行的所述辅助电极线电连接，并且所述第三晶体管的第二极与驱动相邻行像素单元的所述栅线电连接。
根据本公开的一些示例性实施例，向栅线逐行输入栅极扫描信号，并且通过第一晶体管和第二晶体管中的至少一个向与所述第一晶体管和所述第二晶体管相连的像素电极输入数据信号包括：通过所述第一晶体管或所述第二晶体管向与所述第一晶体管和所述第二晶体管相连的像素电极输入数据信号。
根据本公开的一些示例性实施例，同时向每一条栅线和与所述栅线相邻的另一栅线输入栅极扫描信号。通过第一晶体管和第二晶体管中的至少一个向与所述第一晶体管和所述第二晶体管相连的像素电极输入数据信号包括：响应于第一晶体管未损坏而通过第一晶体管和第二晶体管二者向与所述第一晶体管和所述第二晶体管相连的像素电极输入数据信号，并且响应于第一晶体管损坏而通过第二晶体管向与所述第一晶体管和所述第二晶体管相连的像素电极输入数据信号。
根据本公开的一些示例性实施例，向所述栅线输入的栅极扫描信号的电压绝对值大于向所述另一栅线输入的栅极扫描信号的电压绝对值，并且配置成使与该栅线相连的第一晶体管导通，向所述另一栅线输入的栅极扫描信号的电压绝对值配置成通过第三晶体管使第二晶体管导通，并且使与所述另一栅线相连的第一晶体管不导通。
根据本公开的一些示例性实施例，所述第三晶体管的第一极与驱动所述像素单元所在像素单元行的所述辅助电极线电连接，并且所述第三晶体管的第二极与驱动所述像素单元所在像素单元行的所述栅线电连接。
根据本公开的一些示例性实施例，向栅线逐行输入栅极扫描信号，并且通过第一晶体管和第二晶体管中的至少一个向与所述第一晶体管和所述第二晶体管相连的像素电极输入数据信号包括：响应于第一晶体管未损坏而通过第一晶体管和第二晶体管二者向与所述第一晶体管和所述第二晶体管相连的像素电极输入数据信号，并且响应于第一晶体管损坏而通过第二晶体管向与所述第一晶体管和所述第二晶体管相连的像素电极输入数据信号。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种典型的阵列基板的结构示意图；
图2(a)为本公开实施例提供的一种阵列基板的结构示意图；
图2(b)为本公开实施例提供的一种阵列基板的结构示意图二；
图3(a)为本公开实施例提供的一种阵列基板的结构示意图三；
图3(b)为本公开实施例提供的一种阵列基板的结构示意图四；
图4为本公开实施例提供的一种阵列基板的制备方法的流程示意图；
图5为本公开实施例提供的一种在衬底基板上形成第一导电层和第二半导体层的结构示意图；
图6为本公开实施例提供的一种在衬底基板上形成第一导电层、第二半导体层、第一半导体层和第二导电层的结构示意图；
图7(a)为图6中AA向剖视示意图；
图7(b)为图6中BB向剖视示意图；
图8为本公开实施例提供的一种在衬底基板上形成第一导电层、第二半导体层和第一半导体层的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方 案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
典型的TFT阵列基板如图1所示，包括相互交叉的多条栅线G1、G2和多条数据线D1、D2、D3、由多条栅线G1、G2和多条数据线D1、D2、D3限定的多个像素区域(也可以称为亚像素区域)。每个像素区域包括一个晶体管20和一个像素电极10。晶体管20用于控制向像素电极10输入信号，以将像素点亮。
本发明人发现，在晶体管20损坏的情况下，与该晶体管20相连的像素电极10就会失去控制，使该晶体管20控制的像素处于常暗或常亮状态，进而成为肉眼可见的暗点，从而严重影响产品品质。
有鉴于此，本公开实施例提供一种阵列基板，如图2(a)、图2(b)、图3(a)和图3(b)所示，包括相互交叉的多条栅线G1、G2、G3......和多条数据线D1、D2、D3......、由多条栅线和多条数据线限定的多个像素单元，以及与栅线G1、G2、G3......交替排列的多条辅助电极线C1、C2......。
每个像素单元包括：第一晶体管T1、第二晶体管T2和像素电极10。第一晶体管T1的控制极与驱动像素单元所在像素单元行的栅线电连接，第一晶体管T1的第一极与数据线电连接，并且第一晶体管T1的第二极与像素电极10电连接。第二晶体管T2的控制极与该像素单元所在行的辅助电极线电连接，第二晶体管T2的第一极与数据线电连接，并且第二晶体管T2的第二极与像素电极电连接。在栅线和与其相邻的一条辅助电极线之间设置有第三晶体管T3，第三晶体管T3的控制极与数据线电连接，第三晶体管T3的第一极与栅线电连接，并且第三晶体管T3的第二极与辅助电极线电连接。
需要说明的是，栅线与辅助电极线交替排列，因此，除设置在最外侧的栅线和辅助电极线外，每条栅线都有两条相邻的辅助电极线，并且每条辅助电极线都有两条相邻的栅线。例如，如图2(a)、图2(b)、图3(a)或图3(b)所示，辅助电极线C1和辅助电极线C2分别与栅线G2相邻，并且栅线G1和栅线G2分别与辅助电极线C1相邻。在栅线和与其相邻的一条辅助电极线之间设置有第三晶体管T3， 意味着在辅助电极线C1和栅线G2之间设置第三晶体T3，或者在辅助电极线C2和控制极G2之间设置第三晶体管T3。
还需要说明的是，对于栅线和与其相邻的一条辅助电极线之间设置的第三晶体管T3的数量不进行限定。例如，可以如图2(a)和图3(a)所示，在栅线和与其相邻的一条辅助电极线之间只设置一个第三晶体管T3。可替换地，可以如图2(b)和图3(b)所示，在栅线和与其相邻的一条辅助电极线之间设置两个或两个以上第三晶体管T3。
此处，辅助电极线可以是阵列基板中本身就设置有的信号线，也可以是额外设置的信号线，对此不进行限定。在此基础上，可以在辅助电极线上预先输入有电压，但该电压小于第二晶体管T2的控制极的最小驱动电压，即小于第二晶体管T2的最小导通电压(当第二晶体管T2的控制极电压大于控制极最小驱动电压时，第二晶体管T2可被导通)。可替换地，可以不在辅助电极线上预先输入有电压。
在上述实施例中，第一晶体管T1的控制极与驱动像素单元所在像素单元行的栅线电连接，因而当栅线输入扫描信号时，第一晶体管T1处于导通状态。第二晶体管T2的控制极与驱动像素单元所在像素单元行的辅助电极线电连接。由于辅助电极线上输入的电压信号较低，因而不能使第二晶体管T2导通，第二晶体管T2处于关断状态。只有在第三晶体管T3在所连接的数据线的控制下导通时，栅线上的电压通过第三晶体管T3输入至辅助电极线，才可以使第二晶体管T2导通。
基于此，通过调整第二晶体管T2的半导体层的材料可以调整驱动第二晶体管T2导通的最小驱动电压的大小。进一步地，通过调整第三晶体管T3的半导体层的材料可以调整第三晶体管T3允许通过的最大电压。
在本公开实施例提供的上述阵列基板，由于阵列基板的每个像素单元的像素电极10分别与第一晶体管T1和第二晶体管T2均相连，因而当第一晶体管T1和第二晶体管T2中的一个处于损坏状态时，可以通过另一个晶体管将像素点亮，因而避免了像素单元处于常暗或常亮状态的问题，从而有效减少显示面板的点类不良，提升产品品质。
在本公开实施例中，在向与第三晶体管T3相连的栅线输入扫描信号时，该栅线上的信号还可以通过第三晶体管T3输入至与第三晶体管T3相连的辅助电极线。若在栅线和与其相邻的一条辅助电极线之间仅 设置一个第三晶体管T3或少量第三晶体管T3，则一方面，栅线上的信号不能快速通过第三晶体管T3输入至辅助电极线，另一方面，由于辅助电极线的固有损失，辅助电极线中距离第三晶体管T3较远的位置处的信号会较弱，从而会导致阵列基板上像素电极10输入的电压不均匀，进而影响显示效果。
因此，在示例性实施例中，如图2(b)和图3(b)所示，在每条栅线和每条数据线的交叉位置处均设置有第三晶体管T3。
应当指出的是，在每条栅线和每条数据线的交叉位置处，并不是指特定交叉点，而是指交叉点的周围的一定区域。
在本公开的上述实施例中，由于在每条栅线和每条数据线的交叉位置处均设置有第三晶体管T3，即在相邻栅线和辅助电极线之间设置有多个第三晶体管T3，因而当在栅线输入信号时，栅线上的信号可以通过多个第三晶体管T3输入至与第三晶体管T3相连的辅助电极线。
在本公开的一些实施例中，如图2(a)和2(b)所示，第三晶体管T3的第一极与驱动像素单元所在像素单元行的辅助电极线电连接，并且第三晶体管T3的第二极与驱动相邻行像素单元的栅线电连接。
基于如图2(a)和2(b)所示的阵列基板的结构，以下详细说明阵列基板的工作过程。
在上述阵列基板的一种工作过程中，参考图2(b)，向栅线G1、G2......Gn逐行输入栅极驱动信号。当向栅线G1输入栅极驱动信号时，与栅线G1相连的第一晶体管T1若没有损坏，则第一晶体管T1导通，并且数据线D1上的数据信号通过第一晶体管T1输入至像素电极102。此时，辅助电极线C1上的电压小于第二晶体管T2的最小导通电压，因此第二晶体管T2处于截止状态。当向栅线G2输入栅极驱动信号时，与栅线G2相连的第一晶体管T1若没有损坏，则第一晶体管T1导通，此时数据线上的数据信号通过第一晶体管T1输入至像素电极101。与此同时，栅线G2上的栅极驱动信号还通过第三晶体管T3输入至辅助电极线C1，使得辅助电极线C1上的电压提高至大于第二晶体管T2的最小导通电压。但是由于在栅线G1导通时像素电极102的像素电压已经提高，此时，辅助电极线C1上的电压虽然提高但是小于像素电极102的像素电压，即第二晶体管T2的控制极电压小于第二晶体管T2的第二极电压(第二晶体管T2的控制极与辅助电极线C1相连，并且第二 晶体管T2的第二极与像素电极102相连)，因此根据晶体管的性质，数据线D1上的电压不能通过第二晶体管T2输入至像素电极102。
在另一种情况下，向栅线G1、G2......Gn逐行输入栅极驱动信号。当向栅线G1输入栅极驱动信号时，若与栅线G1相连的第一晶体管T1损坏，则第一晶体管T1截止，数据线上的数据信号不能通过第一晶体管T1输入至像素电极102。此时，辅助电极线C1上虽然也有信号，但是辅助电极线C1上的电压信号小于第二晶体管T2的最小导通电压，因此第二晶体管T2也处于截止状态。当向栅线G2输入栅极驱动信号时，与栅线G2相连的第一晶体管T1若没有损坏，则第一晶体管T1导通。此时数据线上的数据信号通过第一晶体管T1输入至像素电极101。与此同时，栅线G2上的信号还通过第三晶体管T3输入至辅助电极线C1，使得辅助电极线C1上的电压提高至大于第二晶体管T2的最小导通电压，因此第二晶体管T2导通。由于在栅线G1导通时数据线上的电压并没有输入至像素电极102，因此此时，数据线上的电压可以通过第二晶体管T2输入至像素电极102，使得像素电极101和像素电极102同时输入信号。
在示例性实施例中，假设辅助电极线上的预先输入的电压为5V，数据线D1上的数据电压为10V，并且栅线G1上的栅极驱动电压为25V。当向栅线G1输入栅极驱动电压时，若第一晶体管T1未损坏，通过第一晶体管T1向像素电极102输入数据电压。另一方面，由于第二晶体管T2的控制极电压为5V，低于第二晶体管T2的最小导通电压(例如为6V)，因此第二晶体管T2截止。
在示例性实施例中，假设辅助电极线上的预先输入的电压为5V，数据线D1上的数据电压为10V，栅线G2上的栅极驱动电压为25V，并且像素电极102的像素电压为8V。辅助电极线C1与第二晶体管T2的控制极电连接。第二晶体管T2的控制极电压被栅线G2提升达到7V，但是此时第二晶体管T2的控制极电压(7V)低于像素电极102的像素电压(8V)，因此第二晶体管T2处于截止状态。在这样的情况下，实现了当第一晶体管T1正常时，自动屏蔽第二晶体管T2的目的。
假设辅助电极线上的预先输入的电压为5V，数据线D1上的数据电压为10V，栅线G1上的栅极驱动电压为25V，并且第一晶体管T1损坏。像素电极102上未加载有数据电压。而且，由于第二晶体管T2 的控制极电压为5V，低于第二晶体管T2的最小导通电压，因此第二晶体管T2截止。
假设辅助电极线上的预先输入的电压为5V，数据线D1上的数据电压为10V，栅线G2上的栅极驱动电压为25V，由于第一晶体管T1损坏而未被点亮的像素单元的像素电极102上的像素电压为3V。辅助电极线C1与第二晶体管T2的控制极电连接。当栅线G2的电压为25V时，第二晶体管T2的控制极电压会被辅助电极线提升达到7V。此时第二晶体管T2的控制极电压(7V)高于像素电极102的数据电压(3V)，且高于第二晶体管T2的最小导通电压(6V)，因此第二晶体管T2导通，从而实现了在第一晶体管T1损坏时，自动导通第二晶体管T2的目的。
在上述阵列基板的另一种工作过程中，栅线G1、G2......Gn每两行同时扫描，在每一帧中逐两行地扫描所有栅线并且向栅线Gn+1输入的栅极驱动电压小于向栅线Gn输入的栅极驱动电压。例如在第一时钟周期中，向栅线G1和栅线G2同时输入栅极驱动信号，并且向栅线G1输入的栅极驱动电压大于向栅线G2输入的栅极驱动电压；在第二时钟周期中，向栅线G2和栅线G3同时输入栅极驱动信号，并且向栅线G2输入的栅极驱动电压大于向栅线G3输入的栅极驱动电压；在第三时钟周期中，向栅线G3和栅线G4同时输入栅极驱动信号，并且向栅线G3输入的栅极驱动电压大于向栅线G4输入的栅极驱动电压，依次类推。
以向栅线G1和栅线G2同时输入栅极驱动电压为例，向栅线G1输入的栅极驱动电压大于向栅线G2输入的栅极驱动电压。栅线G1上的电压信号可以使与栅线G1相连的第一晶体管T1导通，并且栅线G2上的电压信号通过第三晶体管T3可以使与辅助电极线C1相连的第二晶体管T2导通，但是不能使与栅线G2相连的第一晶体管T1导通。若与像素电极102相连的第一晶体管T1没有损坏，则当向栅线G1和栅线G2同时输入栅极驱动电压时，第一晶体管T1导通，数据线上的数据信号通过第一晶体管T1输入至像素电极102，栅线G2上的电压通过第三晶体管T3输入至辅助电极线C1，使得辅助电极线C1上的电压提高至大于第二晶体管T2的最小导通电压，与辅助电极线C1相连的第二晶体管T2导通，因此数据线上的电压通过第二晶体管T2输入至像素电极102。也就是说，数据线上的电压同时通过第一晶体管T1 和第二晶体管T2输入至像素电极102。
若与像素电极102相连的第一晶体管T1损坏，则当向栅线G1和栅线G2同时输入栅极驱动电压时，数据线上的数据信号不能通过第一晶体管T1输入至像素电极102。但是，此时栅线G2上的电压通过第三晶体管T3输入至辅助电极线C1，使得辅助电极线C1上的电压提高至大于第二晶体管T2的最小导通电压，因此与辅助电极线C1相连的第二晶体管T2导通，使得数据线上的数据电压通过第二晶体管T2输入至像素电极102，将与像素电极102对应的像素单元点亮。
在另外的示例性实施例中，如图3(a)和图3(b)所示，第三晶体管T3的第一极与驱动像素单元所在像素单元行的辅助电极线电连接，第三晶体管T3的第二极与驱动像素单元所在像素单元行的栅线电连接。
如图3(a)和图3(b)所示，向栅线G1、G2......Gn逐行输入栅极驱动信号。当向栅线G1输入栅极驱动信号时，与栅线G1相连的第一晶体管T1若没有损坏，则第一晶体管T1导通，数据线上的数据信号通过第一晶体管T1输入至像素电极10。与此同时，栅线上的信号通过第三晶体管T3输入至辅助电极线，辅助电极线上的电压升高至大于第二晶体管T2的驱动电压，第二晶体管T2导通，数据线上的数据信号还通过第二晶体管T2输入至像素电极10。
若第一晶体管T1损坏，则数据线上的数据信号将仅通过第二晶体管T2输入至像素电极10。
在示例性实施例中，第一晶体管T1、第二晶体管T2和第三晶体管T3的半导体层可以包括非晶硅(α-Si)层和N型掺杂层。也就是说，第一晶体管T1、第二晶体管T2和第三晶体管T3可以为N型晶体管。
但是应当指出的是，尽管在以上描述中以第一晶体管T1、第二晶体管T2和第三晶体管T3为N型晶体管为例描述了阵列基板的工作过程，但是第一晶体管T1、第二晶体管T2和第三晶体管T3中的一个或多个也可以是P型晶体管，在此不再赘述。
在本公开的实施例中，通过调整晶体管的半导体层的掺杂浓度，可以调整该晶体管允许通过的，且不损坏该晶体管的最大电压和使得该晶体管导通的最小导通电压。
在示例性实施例中，辅助电极线可以被复用为公共电极线。
在这样的实施例中，向公共电极线预先输入有电压，但是该电压较小，小于第二晶体管T2的最小导通电压，因此虽然第二晶体管T2的控制极与公共电极线相连，但是并不能使第二晶体管T2导通。
在这样的实施例中，通过利用公共电极线充当辅助电极线，可以无需额外设置辅助电极线，因而简化了阵列基板的制作工艺。
在另外的方面中，本公开实施例提供了一种显示装置，包括上述任一种阵列基板。
显示装置可以是液晶显示装置(Liquid Crystal Display，简称LCD)，也可以是有机电致发光二极管显示装置(Organic Light-Emitting Diode，简称OLED)。当显示装置为液晶显示装置时，液晶显示装置包括阵列基板、对盒基板以及设置在阵列基板和对盒基板之间的液晶层。当显示装置为有机电致发光二极管显示装置时，有机电致发光二极管显示装置包括阵列基板和封装盖板。
显示装置可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图像的任何装置。更明确地说，预期上述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。此外，显示装置还可以是显示面板。
本公开实施例提供一种显示装置，该显示装置包括上述的阵列基板。由于阵列基板的每个像素单元的像素电极10分别与第一晶体管T1和第二晶体管T2均相连，因而当第一晶体管T1和第二晶体管T2中的一个处于损坏状态时，可以通过另一个晶体管将像素点亮，因而避免了像素处于常暗或常亮状态的问题，从而有效减少点类不良，提升产品品质。
本公开实施例还提供一种阵列基板的制备方法。图4图示了该制 备方法的流程示意图。
如图4所示，在步骤S100处，如图5和图7(a)所示，在衬底基板110(例如可以为玻璃基板)上形成第一导电层和第二半导体层。第一导电层包括交替排列的多条栅线30和多条辅助电极线40。第二半导体层包括多个第三半导体图案50。第三半导体图案50形成在栅线30和与其相邻的一条辅助电极线40之间，且与栅线30和该辅助电极线40电接触。
在步骤S100中，可以先形成第一导电层，再形成第二半导体层，也可以先形成第二半导体层，再形成第一导电层，对此不进行限定。此外，第一导体层中的辅助电极线40可以是阵列基板本身就设置有的(例如公共电极线)，也可以是额外设置的。
另外，对于第三半导体图案50的材料不进行限定。在示例性实施例中，第三半导体图案50可以由非晶硅层和掺杂层构成。具体地，第三半导体图案50的形成过程可以是：首先在衬底基板上沉积非晶硅薄膜和掺杂薄膜，然后通过图案化工艺形成第三半导体图案50。
需要说明的是，由于栅线30和辅助电极线40交替排列，因而除设置在最外侧的栅线和辅助电极线外，每条栅线都有两条相邻的辅助电极线，每条辅助电极线都有两条相邻的栅线。在栅线30和与其相邻的一条辅助电极线40之间形成第三半导体图案50，可以是在驱动像素单元所在像素单元行的栅线30和驱动像素单元所在像素单元行的辅助电极线40之间设置第三半导体图案50，也可以是在驱动像素单元所在像素单元行的辅助电极线40和驱动相邻行像素单元的栅线30之间设置第三半导体图案50。
在可选的步骤S101处，如图7(a)和图7(b)所示，在衬底基板110上形成栅极绝缘层(Gate Insulator，简称GI)120。
对于栅极绝缘层120的材料不进行限定，例如可以是氮化硅(SiNx)、氧化硅(SiOx)或氮氧化硅(SiOxNy)中的至少一种。
在步骤S102处，如图6所示，形成第一半导体层和第二导电层。具体地，如图8所示，第一半导体层包括多个第一半导体图案60和多个第二半导体图案70。第一半导体图案60和栅线30在衬底基板110上的正投影交叠，并且第二半导体图案70和辅助电极线40在衬底基板110上的正投影交叠。第二导电层包括第一源极801、第一漏极802、 第二源极901、第二漏极902以及与栅线30的延伸方向交叉的多条数据线100。第一源极801和第一漏极802均与第一半导体图案60电接触，并且第二源极901和第二漏极902均与第二半导体图案70电接触。数据线100和第三半导体图案50在衬底基板110上的正投影交叠。
附图7(a)和图7(b)分别为图6中AA向剖视示意图和BB向剖视示意图，以详细示意阵列基板的结构。
在示例性实施例中，如图8所示，先形成第一半导体层，再形成第二导电层。可替换地，也可以先形成第二导电层，再形成第一半导体层，对此不进行限定。
在上述实施例中，第一源极801、第一漏极802和第一半导体图案60构成第一晶体管T1，第二源极901、第二漏极902和第二半导体图案70构成第二晶体管T2，并且第三半导体图案50和与第三半导体图案50电气接触的栅线30和辅助电极线40的部分构成第三晶体管T3，如图7(a)所示。
在示例性实施例中，第二导电层的形成过程具体可以是先在衬底基板上沉积第二导电层薄膜，再通过图案化工艺形成第一源极801、第一漏极802、第二源极901、第二漏极902和数据线100。对于第一半导体图案60和第二半导体图案70的材料不进行限定。在示例性实施例中，第一半导体图案60和第二半导体图案70可以由非晶硅层和掺杂层构成，具体地，可以首先在衬底基板上沉积非晶硅薄膜和掺杂薄膜，然后通过图案化工艺形成第一半导体图案60和第二半导体图案70。
在示例性实施例中，在形成第一半导体层和第二导电层之后，上述方法还可以包括形成钝化层(Passivation，简称PVX)以及公共电极。
本公开实施例提供一种阵列基板的制备方法。在通过该方法制备的阵列基板中，由于阵列基板的每个像素单元包括第一晶体管T1和第二晶体管T2，第一晶体管T1和第二晶体管T2均与像素电极10电连接，因而当第一晶体管T1和第二晶体管T2中的一个处于损坏状态时，可以通过另一个晶体管将像素点亮，因而避免了像素处于常暗或常亮状态的问题，从而有效减少点类不良，提升产品品质。
可选地，如图5所示，在衬底基板上形成第一导电层和第二半导体层之前，上述制备方法还可以包括在衬底基板上形成第三导电层，第三导电层包括多个像素电极10。像素电极10与待形成的第一漏极 802和第二漏极902均电连接。
可替换地，在衬底基板上形成第一半导体层和第二导电层之后，上述制备方法还可以包括形成第三导电层，第三导电层包括多个像素电极10。像素电极10均与第一漏极802和第二漏极902电连接。
像素电极10的材料可以包括ITO(Indium Tin Oxide，氧化铟锡)或IZO(Indium Zinc Oxide，氧化铟锌)中的至少一种。
第三导电层的形成过程可以具体地包括首先在衬底基板上形成第三导电薄膜，然后通过图案化工艺形成像素电极。
在示例性实施例中，在栅线30和与其相邻的一条辅助电极线40之间形成第三半导体图案50包括：在驱动像素单元所在像素单元行的辅助电极线40和驱动相邻行像素单元的栅线30之间形成多个第三半导体图案50。
每个第三半导体图案50和数据线100在衬底基板110上的正投影交叠。当数据线100上有信号通过时，包括第三半导体图案50的第三晶体管导通。
在上述实施例中，由于在驱动像素单元所在像素单元行的辅助电极线40和驱动相邻行像素单元的栅线30之间形成多个第三半导体图案50，且第三半导体图案50与栅线30和辅助电极线40均电气接触，因此当包括第三半导体图案50的第三晶体管导通时，栅线30上的信号可以通过多个第三半导体图案50输入至辅助电极线40。
如图2(a)和图2(b)所示，在阵列基板的第三晶体管T3的第一极与驱动像素单元所在像素单元行的辅助电极线40电连接，阵列基板的第三晶体管T3的第二极与驱动相邻行像素单元的栅线30电连接时，本公开实施例还提供一种阵列基板的驱动方法，包括：通过第一晶体管T1和/或第二晶体管T2向与第一晶体管T1和第二晶体管T2相连的像素电极10输入数据信号。
在这样的实施例中，可以通过第一晶体管T1和第二晶体管T2同时向与第一晶体管T1和第二晶体管T2相连的像素电极10输入数据信号，也可以通过第一晶体管T1或第二晶体管T2向与第一晶体管T1和第二晶体管T2相连的像素电极10输入数据信号。
在本公开实施例提供的上述阵列基板的驱动方法中，由于阵列基板的每个像素单元的像素电极10分别与第一晶体管T1和第二晶体管 T2均相连，因而当第一晶体管T1和第二晶体管T2中的一个处于损坏状态时，可以通过另一个晶体管将像素点亮，因而避免了像素处于常暗或常亮状态的问题，从而有效减少点类不良，提升产品品质。
在示例性实施例中，栅线逐行扫描，通过第一晶体管T1和/或第二晶体管T2向与所述第一晶体管T1和第二晶体管T2相连的像素电极10输入数据信号包括：通过第一晶体管T1或第二晶体管T2向与第一晶体管T1和第二晶体管T2相连的像素电极10输入数据信号。
参考图2(a)和图2(b)所示，向栅线G1、G2......Gn逐行输入栅极驱动信号。当向栅线G1输入栅极驱动信号时，与栅线G1相连的第一晶体管T1若没有损坏，则第一晶体管T1导通，并且数据线上的数据信号通过第一晶体管T1输入至像素电极102。此时，辅助电极线C1上的电压小于第二晶体管T2的最小导通电压，因此第二晶体管T2处于截止状态。当向栅线G2输入栅极驱动信号时，与栅线G2相连的第一晶体管T1若没有损坏，则第一晶体管T1导通，此时数据线上的数据信号通过第一晶体管T1输入至像素电极101。与此同时，栅线G2上的栅极驱动信号还通过第三晶体管T3输入至辅助电极线C1，使得辅助电极线C1上的电压提高至大于第二晶体管T2的最小导通电压。但是由于在栅线G1导通时像素电极102的像素电压已经提高，此时，辅助电极线C1上的电压虽然提高但是小于像素电极102的像素电压，即第二晶体管T2的控制极电压小于第二晶体管T2的第二极电压(第二晶体管T2的控制极与辅助电极线C1相连，并且第二晶体管T2的第二极与像素电极102相连)，因此根据晶体管的性质，数据线上的电压不能通过第二晶体管T2输入至像素电极102。
另一方面，若与栅线G1相连的第一晶体管T1损坏，则第一晶体管T1截止，数据线上的数据信号不能通过第一晶体管T1输入至像素电极102。此时，辅助电极线C1上虽然也有信号，但是辅助电极线C1上的电压信号小于第二晶体管T2的最小导通电压，因此第二晶体管T2也处于截止状态。当向栅线G2输入栅极驱动信号时，与栅线G2相连的第一晶体管T1若没有损坏，则第一晶体管T1导通。此时数据线上的数据信号通过第一晶体管T1输入至像素电极101。与此同时，栅线G2上的信号还通过第三晶体管T3输入至辅助电极线C1，使得辅助电极线C1上的电压提高至大于第二晶体管T2的最小导通电压，因此 第二晶体管T2导通。由于在栅线G1导通时数据线上的电压并没有输入至像素电极102，因此此时，数据线上的电压可以通过第二晶体管T2输入至像素电极102，使得像素电极101和像素电极102同时输入信号。
在上述实施例中，对于像素电极101，在第一晶体管T1没有损坏时，通过与像素电极101相连的第一晶体管T1向像素电极101输入信号；在第一晶体管T1损坏时，通过与像素电极101相连的第二晶体管T2向像素电极101输入信号。
在另外的示例性实施例中，向栅线和与该栅线相邻的另一栅线同时输入栅极驱动信号，则通过第一晶体管T1和/或第二晶体管T2向与第一晶体管T1和第二晶体管T2相连的像素电极输入数据信号包括：通过第一晶体管T1和第二晶体管T2向与第一晶体管T1和第二晶体管T2相连的同一像素电极10输入数据信号。向该栅线输入的栅极驱动信号的电压大于向与该栅线相邻的该另一栅线输入的栅极驱动信号的电压。该栅线上的电压信号配置成使与该栅线相连的第一晶体管T1导通，并且与该栅线相邻的该另一栅线上的电压信号配置成通过第三晶体管T3使第二晶体管T2导通。
需要说明的是，尽管同时向栅线和与栅线相邻的另一栅线输入栅极扫描信号，但是只有该栅线所驱动的像素单元行中的像素电极10通过与该像素电极10相连的第一晶体管T1和第二晶体管T2输入数据信号，而其它像素单元行的像素电极10不能输入数据信号，因为向与该栅线相邻的该另一栅线输入的栅极驱动信号的电压低于与该另一栅线相连的第一晶体管T1的最小导通电压。
应当指出的是，通过第一晶体管T1和第二晶体管T2向与第一晶体管T1和第二晶体管T2相连的同一像素电极10输入数据信号，是指在第一晶体管T1和第二晶体管T2均没有损坏的情况下；当第一晶体管T1或第二晶体管T2损坏时，只能通过另一个没有损坏的晶体管向像素电极10输入数据信号。
以同时向栅线G1和栅线G2输入栅极扫描信号为例，栅线G1上的电压信号大于栅线G2上的电压信号，栅线G1上的电压信号可以使与栅线G1相连的第一晶体管T1导通，栅线G2上的电压信号通过第三晶体管T3可以使与辅助电极线C1相连的第二晶体管T2导通，但是 不能使与栅线G2相连的第一晶体管T1导通。若与像素电极102相连的第一晶体管T1没有损坏，则在同时向栅线G1和栅线G2输入栅极扫描信号时，第一晶体管T1导通，数据线上的数据信号通过第一晶体管T1输入至像素电极102。同时，栅线G2上的电压信号通过第三晶体管T3输入至辅助电极线C1，使得辅助电极线C1上的电压提高至大于第二晶体管T2的最小导通电压，因而使得与辅助电极线C1相连的第二晶体管T2导通，因此数据线上的电压通过第二晶体管T2输入至像素电极102。即，数据线上的电压同时通过第一晶体管T1和第二晶体管T2输入至像素电极102。
若与像素电极102相连的第一晶体管T1损坏，则在同时向栅线G1和栅线G2输入栅极扫描信号时，数据线上的数据信号不能通过第一晶体管T1输入至像素电极102。但是，此时栅线G2上的电压通过第三晶体管T3输入至辅助电极线C1，使得辅助电极线C1上的电压提高至大于第二晶体管T2的最小导通电压，因此与辅助电极线C1相连的第二晶体管T2导通，数据线上的数据电压通过第二晶体管T2输入至像素电极102，从而将像素电极102所在的像素单元点亮。
在本公开实施例中，当逐行扫描栅线或者同时扫描栅线和与栅线相邻的另一栅线时，可以通过第一晶体管T1和/或第二晶体管T2向与第一晶体管T1和第二晶体管T2相连的像素电极10输入数据信号，从而防止了与像素电极10相连的第一晶体管T1损坏时，像素处于常暗或常亮状态的问题。
如本领域技术人员将领会到的，尽管在以上描述中以N型晶体管为例来描述本公开的概念，但是本公开不限于此。第一晶体管、第二晶体管和第三晶体管中的一个或多个可以为P型晶体管。由于P型晶体管的导通条件与N型晶体管相反，因此当提到栅线G1上的电压信号大于栅线G2上的电压信号时，在使用P型晶体管的情况下，则意味着栅线G1上的电压信号的绝对值大于栅线G2上的电压信号的绝对值。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种阵列基板，包括延伸方向相互交叉的多条栅线和多条数据线、由所述多条栅线和所述多条数据线限定的多个像素单元，以及与所述栅线交替排列的多条辅助电极线，其中
    每个像素单元包括第一晶体管、第二晶体管和像素电极，
    在每一个像素单元中，
    所述第一晶体管的控制极与驱动所述像素单元所在像素单元行的栅线电连接，所述第一晶体管的第一极与数据线电连接，并且所述第一晶体管的第二极与所述像素电极电连接；
    所述第二晶体管的控制极与驱动所述像素单元所在像素单元行的辅助电极线电连接，所述第二晶体管的第一极与数据线电连接，并且所述第二晶体管的第二极与所述像素电极电连接；并且
    所述阵列基板还包括设置在每一条栅线和与其相邻的一条辅助电极线之间的第三晶体管，所述第三晶体管的控制极与数据线电连接，所述第三晶体管的第一极与所述栅线电连接，并且所述第三晶体管的第二极与所述辅助电极线电连接。
  2. 根据权利要求1所述的阵列基板，其中，在每条所述栅线和每条所述数据线的交叉位置处均设置有所述第三晶体管。
  3. 根据权利要求1或2所述的阵列基板，其中，所述第三晶体管的第一极与驱动所述像素单元所在像素单元行的所述辅助电极线电连接，并且所述第三晶体管的第二极与驱动相邻行像素单元的所述栅线电连接。
  4. 根据权利要求1或2所述的阵列基板，其中，所述第三晶体管的第一极与驱动所述像素单元所在像素单元行的所述辅助电极线电连接，并且所述第三晶体管的第二极与驱动所述像素单元所在像素单元行的所述栅线电连接。
  5. 根据权利要求1所述的阵列基板，其中，所述第一晶体管、第二晶体管和第三晶体管中的至少一个的半导体层包括非晶硅层和掺杂层。
  6. 根据权利要求1所述的阵列基板，其中，所述辅助电极线被复用为公共电极线。
  7. 一种显示装置，包括权利要求1-6任一项所述的阵列基板。
  8. 一种阵列基板的制备方法，包括：
    在衬底基板上形成第一导电层和第二半导体层，所述第一导电层包括交替排列的多条栅线和多条辅助电极线，所述第二半导体层包括设置在每一条栅线和与其相邻的一条所述辅助电极线之间的第三半导体图案，所述第三半导体图案与所述栅线和所述辅助电极线均电接触；
    形成第一半导体层和第二导电层，所述第一半导体层包括多个第一半导体图案和多个第二半导体图案，所述第一半导体图案和所述栅线在所述衬底基板上的正投影交叠，所述第二半导体图案和所述辅助电极线在所述衬底基板上的正投影交叠；所述第二导电层包括第一源极、第一漏极、第二源极、第二漏极以及与所述栅线的延伸方向交叉的多条数据线，所述第一源极和所述第一漏极均与所述第一半导体图案电接触，所述第二源极和所述第二漏极均与所述第二半导体图案电接触，所述数据线和所述第三半导体图案在所述衬底基板上的正投影交叠。
  9. 根据权利要求8所述的制备方法，其中，在衬底基板上形成第一导电层和第二半导体层之前，所述制备方法还包括：在所述衬底基板上形成第三导电层，所述第三导电层包括多个像素电极，每一个像素电极与待形成的对应的第一漏极和第二漏极均电连接。
  10. 根据权利要求8所述的制备方法，其中，在衬底基板上形成第一半导体层和第二导电层之后，所述制备方法还包括：形成第三导电层，所述第三导电层包括多个像素电极，每一个像素电极均与对应的所述第一漏极和所述第二漏极电连接。
  11. 根据权利要求8所述的制备方法，其中，所述第三半导体图案通过以下步骤形成：
    在每条所述栅线和每条所述数据线的交叉位置处均形成所述第三半导体图案。
  12. 一种如权利要求1所述的阵列基板的驱动方法，包括：
    通过第一晶体管和第二晶体管中的至少一个向与所述第一晶体管和所述第二晶体管相连的像素电极输入数据信号。
  13. 根据权利要求12所述的驱动方法，其中，
    所述第三晶体管的第一极与驱动所述像素单元所在像素单元行的 所述辅助电极线电连接，并且所述第三晶体管的第二极与驱动相邻行像素单元的所述栅线电连接。
  14. 根据权利要求13所述的驱动方法，其中，
    向栅线逐行输入栅极扫描信号，并且
    通过第一晶体管和第二晶体管中的至少一个向与所述第一晶体管和所述第二晶体管相连的像素电极输入数据信号包括：通过所述第一晶体管或所述第二晶体管向与所述第一晶体管和所述第二晶体管相连的像素电极输入数据信号。
  15. 根据权利要求13所述的驱动方法，其中，
    同时向每一条栅线和与所述栅线相邻的另一栅线输入栅极扫描信号，
    通过第一晶体管和第二晶体管中的至少一个向与所述第一晶体管和所述第二晶体管相连的像素电极输入数据信号包括：响应于第一晶体管未损坏而通过第一晶体管和第二晶体管二者向与所述第一晶体管和所述第二晶体管相连的像素电极输入数据信号，并且响应于第一晶体管损坏而通过第二晶体管向与所述第一晶体管和所述第二晶体管相连的像素电极输入数据信号。
  16. 根据权利要求15所述的驱动方法，其中，向所述栅线输入的栅极扫描信号的电压绝对值大于向所述另一栅线输入的栅极扫描信号的电压绝对值，并且配置成使与该栅线相连的第一晶体管导通，向所述另一栅线输入的栅极扫描信号的电压绝对值配置成通过第三晶体管使第二晶体管导通，并且使与所述另一栅线相连的第一晶体管不导通。
  17. 根据权利要求12所述的驱动方法，其中，
    所述第三晶体管的第一极与驱动所述像素单元所在像素单元行的所述辅助电极线电连接，并且所述第三晶体管的第二极与驱动所述像素单元所在像素单元行的所述栅线电连接。
  18. 根据权利要求17所述的驱动方法，其中，
    向栅线逐行输入栅极扫描信号，并且
    通过第一晶体管和第二晶体管中的至少一个向与所述第一晶体管和所述第二晶体管相连的像素电极输入数据信号包括：响应于第一晶体管未损坏而通过第一晶体管和第二晶体管二者向与所述第一晶体管和所述第二晶体管相连的像素电极输入数据信号，并且响应于第一晶 体管损坏而通过第二晶体管向与所述第一晶体管和所述第二晶体管相连的像素电极输入数据信号。
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