WO2019024760A1 - 像素电路、其制造方法及显示装置 - Google Patents

像素电路、其制造方法及显示装置 Download PDF

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Publication number
WO2019024760A1
WO2019024760A1 PCT/CN2018/097236 CN2018097236W WO2019024760A1 WO 2019024760 A1 WO2019024760 A1 WO 2019024760A1 CN 2018097236 W CN2018097236 W CN 2018097236W WO 2019024760 A1 WO2019024760 A1 WO 2019024760A1
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thin film
film transistor
layer
electrode
pixel circuit
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PCT/CN2018/097236
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English (en)
French (fr)
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宋振
王国英
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京东方科技集团股份有限公司
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Priority to US16/338,125 priority Critical patent/US11088230B2/en
Priority to EP18840972.6A priority patent/EP3664142A4/en
Publication of WO2019024760A1 publication Critical patent/WO2019024760A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • Embodiments of the present disclosure relate to a pixel circuit, a method of fabricating the same, and a display device.
  • OLED displays have many advantages such as active illumination, high contrast, fast response, and thinness, making them one of the major next-generation displays.
  • the principle of operation is to apply an appropriate voltage to the anode and cathode through the pixel circuit, so that the organic light-emitting layer located between the anode and the cathode emits light, thereby displaying an image.
  • TFTs Thin-film Transistors
  • the structure and fabrication process of the devices greatly affect the performance of thin film transistors.
  • An embodiment of the present disclosure provides a pixel circuit including a substrate and a first thin film transistor and a second thin film transistor disposed on the substrate, wherein the first thin film transistor is a top gate structure, and the second thin film transistor For the bottom gate structure, the first electrode of the first thin film transistor and the gate of the second thin film transistor are electrically connected to each other, and the same layer is disposed on the substrate.
  • An embodiment of the present disclosure further provides a method of fabricating the above pixel circuit, comprising: providing a substrate; forming a first thin film transistor and a second thin film transistor on the substrate, wherein the first thin film transistor is a top gate structure, The second thin film transistor is a bottom gate structure, and a first metal layer is formed on the substrate, and the first metal layer is patterned to form a first thin film transistor electrically connected to each other and disposed in the same layer. a pole and a gate of the second thin film transistor.
  • Embodiments of the present disclosure also provide a display device including the pixel circuit as described above.
  • FIG. 1A is a schematic diagram of a 2T1C pixel circuit
  • FIG. 1B is a schematic diagram of another 2T1C pixel circuit.
  • FIG. 2 is a cross-sectional structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 3 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic cross-sectional structural view of a modified embodiment provided by an embodiment of the present disclosure.
  • 5A, 5B, 6-8, 9A, and 9B are schematic cross-sectional views of respective steps of an exemplary method of fabricating an array substrate of a pixel circuit in accordance with an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of an organic light emitting diode display device according to an embodiment of the present disclosure.
  • the OLED display device generally includes a plurality of pixel units arranged in an array, each of the pixel units including a plurality of sub-pixels, each of the sub-pixels including a pixel driving circuit and an OLED device, the pixel driving circuit being configured to drive the OLED to emit light of a predetermined intensity based on the data signal.
  • the pixel driving circuit generally includes a 2T1C pixel circuit, that is, a basic function of driving the OLED to emit light by using two TFTs and a storage capacitor Cs, wherein one TFT is a switching transistor, mainly functions as a switch, and controls transmission of data signals; another TFT In order to drive the transistor, it mainly serves as a driving current for supplying a pixel electrode as a cathode or an anode of the OLED device.
  • 1A and 1B show schematic diagrams of two 2T1C pixel circuits, respectively.
  • a 2T1C pixel driving circuit includes a switching transistor T1, a driving transistor T2, and a storage capacitor Cs.
  • the switching transistor T1 and the driving transistor T2 are both N-type TFTs.
  • the gate of the switching transistor T1 is connected to the gate line (scanning line) to receive the scan signal (Vscan), the drain is connected to the data line to receive the data signal (Vdata), the source is connected to the gate of the driving transistor T2, and the driving transistor T2 is The drain is connected to the first power terminal (Vdd, high voltage terminal), and the source is connected to the positive terminal of the OLED; one end of the storage capacitor Cs is connected to the source of the switching transistor T1 and the gate of the driving transistor T2, and the other end is connected to the driving The drain of the transistor T2 and the first power terminal; the cathode of the OLED is connected to the second power terminal (Vss, low voltage terminal), for example, to ground.
  • the 2T1C pixel circuit is driven by controlling the brightness and darkness (gray scale) of the pixel via the two TFTs and the storage capacitor Cs.
  • the scan signal Vscan is applied through the gate line to turn on the switching transistor T1
  • the data voltage (Vdata) fed by the data driving circuit through the data line charges the storage capacitor Cs via the switching transistor T1, thereby storing the data voltage in the storage capacitor Cs.
  • the stored data voltage controls the degree of conduction of the driving transistor N1, thereby controlling the magnitude of the current flowing through the driving transistor to drive the OLED to emit light, that is, the current determines the gray scale of the pixel illumination.
  • another 2T1C pixel driving circuit includes a switching transistor T1, a driving transistor T2, and a storage capacitor Cs, but the connection manner thereof is slightly changed. More specifically, the variation of the pixel circuit of FIG. 1B with respect to FIG. 1A includes that the positive terminal of the OLED is connected to the first power terminal (Vdd, high voltage terminal) and the negative terminal is connected to the drain of the driving transistor T2, the driving transistor The source of T2 is connected to the second power supply terminal (Vss, low voltage terminal), such as ground.
  • One end of the storage capacitor Cs is connected to the source of the switching transistor T1 and the gate of the driving transistor T2, and the other end is connected to the source of the driving transistor T2 and the second power supply terminal.
  • the operation mode of the 2T1C pixel circuit is basically the same as that of the pixel circuit shown in FIG. 1A, and details are not described herein again.
  • the pixel driving circuit may further include a compensation circuit including an internal compensation circuit or an external compensation circuit, and the compensation circuit It may include a transistor, a capacitor, or the like.
  • the pixel driving circuit may further include a reset circuit, a sensing circuit, and the like as needed. I won't go into details here.
  • the performance of thin film transistors is largely dependent on their structure.
  • the basic structure of the thin film transistor includes a top gate type structure and a bottom gate type structure.
  • a thin film transistor of a top gate type structure generally has a small parasitic capacitance to have a faster turn-on speed, and a thin film transistor of a bottom gate type structure has a large on-state current and electrical stability.
  • the switching transistor and the driving transistor Limited to the process technology, for example, in the fabrication process of the above 2T1C pixel circuit, the switching transistor and the driving transistor generally adopt the same structure, and it is difficult to simultaneously fabricate the two structures on the same substrate to have both advantages.
  • At least one embodiment of the present disclosure provides a pixel circuit, a method of fabricating the same, and an organic light emitting diode display device using the pixel circuit, wherein the pixel circuit uses a switching transistor of a top gate structure and a driving transistor of a bottom gate structure,
  • the advantages of the transistor structure enable the pixel circuit to have both a faster switching speed and a larger driving current, thereby improving the display performance of the display device.
  • the switching transistor of the top gate structure of the pixel circuit and the driving transistor of the bottom gate structure can be simultaneously formed in the same process, and the process is easy to implement and cost-effective.
  • An embodiment of the present disclosure provides a pixel circuit including a substrate and a first thin film transistor and a second thin film transistor disposed on the substrate, the first thin film transistor is a top gate structure, and the second thin film transistor is a bottom gate The first pole of the first thin film transistor and the gate of the second thin film transistor are electrically connected to each other, and the same layer is disposed on the substrate.
  • Another embodiment of the present disclosure also provides a display device including the above pixel circuit.
  • a further embodiment of the present disclosure further provides a method of fabricating a pixel circuit, including: providing a substrate; forming a first thin film transistor and a second thin film transistor on the substrate, the first thin film transistor being a top gate structure, The second thin film transistor is a bottom gate structure, and a first metal layer is formed on the substrate, and the first metal layer is patterned to form a first thin film transistor electrically connected to each other and disposed in the same layer. a pole and a gate of the second thin film transistor.
  • standard layer arrangement means, for example, that two structures/patterns are formed by the same material layer through a patterning process so as to lie on the same layer, rather than defining them on the same horizontal plane.
  • FIG. 2 is a cross-sectional structural diagram of a pixel circuit 10 according to an embodiment of the present disclosure.
  • the pixel circuit 10 can be applied to an OLED display device, for example, corresponding to a 2T1C pixel driving circuit or other pixel driving circuit including a 2T1C unit.
  • the pixel circuit 10 includes a substrate 100 on which a first region and a second region are defined.
  • the first thin film transistor 11 is disposed on the substrate 100 and located in the first region, and the second thin film transistor 12 is disposed on the substrate.
  • the substrate 100 is located in the second region.
  • the first thin film transistor 11 is a top gate structure including a first electrode 211, a buffer layer 311, an active layer 410, a gate insulating layer 511, a second electrode 611, and a gate 612 which are sequentially stacked on the substrate 100.
  • the active layer 410 includes a first region 411, a second region 412, and a channel region 413 between the first region 411 and the second region 412.
  • the gate insulating layer 511 is located above the channel region 413 and covers the channel region 413; the first region 411 and the second region 412 are not covered by the gate insulating layer 511, and the first region fills the via 301 and is coupled to the first electrode 211 In contact, the second zone 412 is in contact with the second pole 611.
  • the second thin film transistor 12 is a bottom gate structure including a gate electrode 212 sequentially disposed on the substrate 100, a gate insulating layer 312, an active layer 414, an etch barrier layer 512, a first pole 613, and a second pole 614.
  • the active layer 414 includes a first region 415, a second region 416, and a channel region 417 between the first region 415 and the second region 416.
  • the etch stop layer 512 is located above the channel region 417 and covers the channel region 417; the first region 415 and the second region 416 are not covered by the etch stop layer 512, and the first region 415 and the second region 416 are respectively above
  • the first pole 613 is in contact with the second pole 614.
  • the first thin film transistor 11 and the second thin film transistor 12 are formed in the same process flow, which will be described in detail below.
  • the first pole 211 of the first thin film transistor 11 and the gate 212 of the second thin film transistor are electrically connected to each other, and the same layer is disposed on the substrate 100.
  • the buffer layer 311 of the first thin film transistor 11 and the gate insulating layer 312 of the second thin film transistor 12 are disposed in the same layer.
  • the active layer 410 of the first thin film transistor 11 is disposed in the same layer as the active layer 414 of the second thin film transistor 12.
  • the gate insulating layer 511 of the first thin film transistor 11 and the etch stop layer 512 of the second thin film transistor 12 are disposed in the same layer.
  • the second pole 611 of the first thin film transistor 11 is disposed in the same layer as the gate 612 and the first pole 613 and the second pole 614 of the second thin film transistor 12.
  • the pixel circuit 10 may further include a capacitor 13 disposed on the substrate 100.
  • the capacitor 13 includes a first electrode 131, a second electrode 132, and a dielectric layer 133 disposed between the first electrode 131 and the second electrode 132.
  • the first electrode 131 of the capacitor 13 is disposed on the substrate 100 in the same layer as the first electrode 211 of the first thin film transistor 11 and the gate 212 of the second thin film transistor 12, and is electrically connected to each other.
  • the second electrode 132 of the capacitor 13 is disposed in the same layer as the gate 612 and the second pole 611 of the first thin film transistor 11, the first pole 613 and the second pole 614 of the second thin film transistor 12, and the second electrode 132 of the capacitor 13
  • the first pole 613 of the second thin film transistor 12 is electrically connected.
  • the dielectric layer 133 of the capacitor 13 is disposed in the same layer as the buffer layer 311 of the first thin film transistor 11 and the gate insulating layer 312 of the second thin film transistor 12.
  • the pixel circuit 10 may further include a passivation layer 700 disposed on the first thin film transistor 11 and the second thin film transistor 12, and a pixel electrode 141 disposed on the passivation layer 700, the pixel electrode 141 and the second film.
  • the transistor 12 is electrically connected through the via 701.
  • an OLED device is formed on the pixel electrode 141, the OLED device including a stacked structure including a cathode, an anode, and an organic light-emitting layer between the cathode and the anode.
  • the laminated structure may further include functional layers such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer.
  • the pixel electrode 141 may be a cathode or an anode or may be electrically connected to a cathode or an anode.
  • the pixel electrode 141 can be prepared by selecting a suitable conductive material such as a transparent conductive material (indium tin oxide (ITO) or the like) or a metal material (for example, aluminum or aluminum alloy, etc.). Further, the OLED device may be a top emission type, a bottom emission type, or a double-sided emission type or the like.
  • a suitable conductive material such as a transparent conductive material (indium tin oxide (ITO) or the like) or a metal material (for example, aluminum or aluminum alloy, etc.).
  • ITO indium tin oxide
  • the OLED device may be a top emission type, a bottom emission type, or a double-sided emission type or the like.
  • the pixel electrode 141 is electrically connected to the first electrode 613 of the second thin film transistor 12.
  • the equivalent circuit is shown in FIG. 3, wherein the first thin film transistor 11, the second thin film transistor 12, and the capacitor 13 are respectively Corresponding to the first thin film transistor T1, the second thin film transistor T2, and the storage capacitor Cs in the figure.
  • the operation principle of the pixel circuit 10 will be described below with reference to FIG. 3 and taking the first thin film transistor T1 and the second thin film transistor T2 as N-type tubes, and the first extreme source and the second extreme drain as an example.
  • the gate of the first thin film transistor T1 is connected to a gate line (scanning line) to receive a scan signal (Vscan), the drain is connected to the data line to receive a data signal (Vdata), and the source is connected to the second film.
  • a gate of the transistor T2 a drain of the second thin film transistor T2 is connected to the first power terminal (Vdd, high voltage terminal), a source is connected to the pixel electrode, that is, a positive terminal of the OLED; and a first electrode of the storage capacitor Cs is connected to a source of the first thin film transistor T1 and a gate of the second thin film transistor T2, the second electrode is connected to the source of the second thin film transistor T2 and the pixel electrode; the negative end of the OLED is connected to the second power terminal (Vss, low voltage end ), such as grounding.
  • the pixel electrode may be connected to an external compensation circuit (not shown) as needed, which maintains the pixel electrode at a low potential before the storage capacitor Cs starts charging.
  • the 2T1C pixel circuit is driven by controlling the brightness and darkness (gray scale) of the pixel via the two TFTs and the storage capacitor Cs.
  • the scan signal Vscan is applied through the gate line to turn on the first thin film transistor T1
  • the data voltage (Vdata) fed by the data drive circuit through the data line charges the storage capacitor Cs via the first thin film transistor T1, thereby storing the data voltage.
  • the stored data voltage controls the conduction degree of the second thin film transistor T1, thereby controlling the magnitude of the current flowing through the second thin film transistor T1 to drive the OLED to emit light, that is, the current determines the gray of the pixel. Order.
  • the pixel electrode 141 can be electrically connected to the second pole 614 of the second thin film transistor 12, as shown in FIG. At this time, the equivalent circuit of the pixel circuit 10 is the circuit in FIG. 1A. The working principle is not repeated here.
  • the first thin film transistor 11 may be an N-type thin film transistor or a P-type thin film transistor.
  • the second thin film transistor 12 may be an N-type thin film transistor or a P-type thin film transistor.
  • the first electrode 211 of the first thin film transistor 11 may be a source or a drain, and then the second electrode 611 may be a drain or a source, and the first region 411 is a source region or a drain region, respectively.
  • Region 413 is correspondingly a drain region or a source region.
  • the first electrode 613 of the second thin film transistor 12 may be a source or a drain, and then the second electrode 614 may be a drain or a source, and the first region 415 is a source region or a drain region, respectively.
  • Region 416 is correspondingly a drain region or a source region.
  • the active layer 410 of the first thin film transistor 11 and the active layer 414 of the second thin film transistor 12 include, but are not limited to, a silicon-based material (amorphous silicon a-Si, polysilicon p-Si, etc.), a metal oxide semiconductor ( a-IGZO, ZnO, ZnON, IZTO, etc.) and organic materials (hexathiophene, polythiophene, etc.).
  • a silicon-based material amorphous silicon a-Si, polysilicon p-Si, etc.
  • a metal oxide semiconductor a-IGZO, ZnO, ZnON, IZTO, etc.
  • organic materials hexathiophene, polythiophene, etc.
  • the material of the second electrode 132 includes, but is not limited to, a commonly used electrode material such as Ag, Cu, Al, Mo, etc., or a multilayer metal such as MoNb/Cu/MoNb or the like, or an alloy of the above various materials such as AlNd, MoNb or the like.
  • the first region 411 and the second region 412 of the first thin film transistor 11 may be conductors that are subjected to a conductor treatment, and the first region 411 is in contact with the first electrode 211 to directly form an electrical connection.
  • the structure has the following advantages: The parasitic capacitance of the small first thin film transistor 11 increases the charging speed of the circuit; reduces the contact resistance of the active layer 414 with the first region 411 and the second region 412, thereby increasing the carrier mobility of the first thin film transistor 11; Save layout area and increase pixel aperture ratio.
  • first region 415 and the second region 416 of the second thin film transistor 12 may also be conductors that are conductord to reduce the contact resistance of the active layer 414 with the first region 415 and the second region 416, thereby improving the The carrier mobility of the second thin film transistor 12.
  • the gate insulating layer 511 of the first thin film transistor 11, the buffer insulating layer 311 and the gate insulating layer 312 of the second thin film transistor 12, the etch barrier layer 512, and the dielectric layer 133 of the capacitor 13 include, but are not limited to, conventional Dielectric materials, such as dielectric materials such as SiOx, SiNx, SiON, or various organic insulating materials, or High k materials such as AlOx, HfOx, TaOx, and the like.
  • the substrate 100 may be a flexible flexible substrate, for example, various plastic films such as polyethylene terephthalate (PET), polyether sulfone (PES), polycarbonate (Polycarbonate, PC). Or a substrate made of polyimide (PI) and its derivatives.
  • the substrate 100 may be a rigid substrate such as a glass substrate, a stainless steel substrate, or the like.
  • the pixel circuit provided by the embodiment of the present disclosure and the modified embodiment thereof adopts a switching transistor of a top gate structure and a driving transistor of a bottom gate structure, and combines the advantages of the two structures, so that the pixel circuit can have a faster switching speed. It can also have a large driving current, thereby improving the display performance of the display device.
  • the second thin film transistor has a bottom-gate structure and has a light-shielding effect, which can improve the display unevenness of the thin film transistor caused by illumination in the NBTIS (Negative Bias Thermal Illumination Stress) test, thereby reducing the compensation difficulty of the pixel compensation circuit.
  • NBTIS Near Bias Thermal Illumination Stress
  • An embodiment of the present disclosure provides a method of fabricating the above pixel circuit, the method comprising: providing at least a substrate; forming a first thin film transistor and a second thin film transistor on the substrate, wherein the first thin film transistor is a top gate a second thin film transistor having a bottom gate structure, the first thin film transistor being formed on the substrate and patterned by the first metal layer and electrically connected to each other and disposed in the same layer a first pole and a gate of the second thin film transistor.
  • FIGS. 5A through 9B An exemplary manufacturing method of a pixel circuit provided by an embodiment of the present disclosure will be described below with reference to FIGS. 5A through 9B.
  • the substrate 100 is provided, and the substrate 100 is washed and dried.
  • the substrate 100 may be a flexible flexible substrate, for example, various plastic films such as polyethylene terephthalate (PET), polyether sulfone (PES), polycarbonate (Polycarbonate, PC) or A substrate made of polyimide (PI) and its derivatives.
  • the substrate 100 may be a rigid substrate such as a glass substrate, a stainless steel substrate, or the like.
  • a first region, a second region, and a third region are defined on the substrate 100, and correspond to the first thin film transistor 11, the second thin film transistor 12, and the capacitor 13, respectively.
  • Step S52 as shown in FIG. 5A, forming a first metal layer 200 on the substrate 100 and patterning the first metal layer 200 by a first patterning process, thereby respectively forming the first region, the second region, and the third region.
  • the region forms the first electrode 211 of the first thin film transistor 11 electrically connected to each other, the gate 212 of the second thin film transistor 12, and the first electrode 131 of the capacitor.
  • the plan view of the first metal layer 200 after being patterned is as shown in FIG. 5B.
  • the electrodes 131 are electrically connected to each other.
  • FIG. 5B shows an exemplary formed pattern
  • FIG. 5A is a schematic view for consideration of convenience of description and display, which do not correspond one-to-one in size and shape.
  • Step S53 as shown in FIG. 6, forming a first insulating layer 300 on the first metal layer 200 and patterning the first insulating layer 300 by a second patterning process to form vias 301 and exposing at least part of the first A first pole 211 of a thin film transistor 11.
  • the buffer layer 311 of the first thin film transistor 11, the gate insulating layer 312 of the second thin film transistor 12, and the dielectric layer 133 of the capacitor 13 are formed.
  • a chemical vapor deposition (PECVD) process may be employed in forming the first insulating layer 300, and the process is optimized to obtain a gate insulating layer 312 having a lower interface trap defect state density, and at the same time, due to improved quality,
  • the thickness of the first insulating layer 300 can be appropriately reduced, so that the capacitance value of the capacitor 13 can be effectively increased, and the display performance can be improved.
  • Step S54 as shown in FIG. 6, a semiconductor layer 400 is formed on the first insulating layer 300 and the semiconductor layer 400 is patterned by a third patterning process to form the active layer 410 and the second film of the first thin film transistor 11.
  • materials of the semiconductor layer 400 include, but are not limited to, silicon-based materials (a-Si, p-Si, etc.), metal oxide semiconductors (a-IGZO, ZnON, IZTO, etc.), and organic materials (hexathiophene, polythiophene, etc.) )Wait.
  • Step S55 as shown in FIG. 7, a second insulating layer 500 is formed on the semiconductor layer 400 and the second insulating layer 500 is patterned by a fourth patterning process to form on the active layer 410 of the first thin film transistor 11.
  • the gate insulating layer 511 forms an etch stop layer 512 and a dielectric layer 133 forming a capacitor 13 on the active layer 414 of the second thin film transistor 12.
  • the gate insulating layer 511 of the first thin film transistor 11 covers a portion of the active layer 410
  • the etch stop layer 512 of the second thin film transistor 12 covers a portion of the active layer 414.
  • Step S56 as shown in FIG. 8, a second metal layer 600 is formed on the second insulating layer 500 and the second metal layer 600 is patterned by a fifth patterning process to form a second electrode 611 of the first thin film transistor 11. And a gate 612, a first pole 613 and a second pole 614 of the second thin film transistor 12, and a second electrode 132 of the capacitor 13.
  • the second electrode 611 of the first thin film transistor 11 is located on a side of the gate insulating layer 511 away from the first electrode 211 thereof, and is overlapped with the active layer 410 of the first thin film transistor 11 without its gate insulating layer 511 a portion of the contact; the first and second electrodes 613, 614 of the second thin film transistor 12 are located on opposite sides of the etch stop layer 512, and the active layer 414 of the second thin film transistor 12 is not etched by the etch layer. 512 covered part of the contact.
  • the first thin film transistor 11 of the top gate structure electrically connected to each other, the second thin film transistor 12 of the bottom gate structure, and the capacitor 13 are formed on the substrate 100.
  • the first electrode 211 of the first thin film transistor 11, the gate 212 of the second thin film transistor 12, and the first electrode 131 of the capacitor 13 are electrically connected to each other, and the second electrode 132 of the capacitor 13 and the second thin film transistor 13 are One pole 613 is electrically connected.
  • a passivation layer 700 is formed on the second metal layer 600, and the passivation layer 700 is planarized, and then passivated by the sixth patterning process.
  • the layer 700 is patterned to form a via 701 and expose at least a portion of the first electrode 613 of the second thin film transistor 12; then a conductive layer 800 is formed on the passivation layer 700, and the conductive layer 800 fills the via 701 and the second
  • the bare portion of the first electrode 613 of the thin film transistor 12 is in contact, and the conductive layer is patterned to form the pixel electrode 141.
  • the conductive layer may be, for example, indium tin oxide (ITO) or a metal layer as needed.
  • an OLED device can be further formed on the pixel electrode 141.
  • a pixel circuit structure as shown in FIG. 2 is formed.
  • the via 701 can be opened at a position corresponding to the second pole 614 of the second thin film transistor 12 and expose at least a portion of the second pole 614 of the second thin film transistor 12, and the conductive layer 800 fills the via 701 and the second The bare portion of the second electrode 614 of the thin film transistor 12 is in contact as shown in FIG. 9B.
  • a pixel circuit structure as shown in FIG. 4 is formed.
  • step S54 and before step S55 the portion of the active layer 410 of the first thin film transistor 11 that is not covered by the gate insulating layer 511 of the first thin film transistor 11 and the second thin film transistor 12 may be further included.
  • the portion of the active layer 414 that is not covered by the etch barrier layer 512 is subjected to a conductor treatment.
  • the active layer 410 of the first thin film transistor 11 includes a first region 411, a second region 412, and a semiconductor channel region 413 between the first region 411 and the second region 412; the second thin film transistor 12
  • the active layer 414 includes a first region 415 that is electrically conductive, a second region 416, and a semiconductor channel region 417 between the first region 415 and the second region 416.
  • the first region 411 and the second region 412 of the first thin film transistor 11 are in contact with the first electrode 211 and the second electrode 611, respectively, and the first region 415 and the second region 416 of the second thin film transistor 12 are respectively connected to the first electrode 613 thereof.
  • the second pole 614 is in contact.
  • the conductor treatment of the active layer 410 of the first thin film transistor 11 and the active layer 414 of the second thin film transistor 12 is performed in the same process, for example, the conductor processing may include the first thin film transistor 11
  • the gate insulating layer 511 and the etch stop layer 512 of the second thin film transistor 12 are ion-implanted or plasma-treated on the active layer 410 of the first thin film transistor 11 and the active layer 414 of the second thin film transistor 12 as a mask.
  • the conductor treatment reduces the contact resistance between the first pole and the second pole of the thin film transistor and the active layer thereof, thereby improving the carrier mobility of the thin film transistor and further improving the switching speed and the driving current of the thin film transistor.
  • the gate insulating layer 511 of the first thin film transistor 11 is formed and The second insulating layer of the etch barrier layer 512 of the second thin film transistor 12 may cover the surface of the substrate including the active layer 410 and the active layer 414, respectively, and then form a via hole exposing the active layer through a patterning process, so as to facilitate A source or drain is formed in contact with the active layer.
  • the first thin film transistor 11 and the second thin film transistor 12 may be of an N type or a P type.
  • the first electrode 211 of the first thin film transistor 11 may be a source or a drain, and then the second electrode 611 may be a drain or a source, and the first region 411 is a source region or a drain region, respectively.
  • Region 413 is correspondingly a drain region or a source region.
  • the first electrode 613 of the second thin film transistor 12 may be a source or a drain, and then the second electrode 614 may be a drain or a source, and the first region 415 is a source region or a drain region, respectively.
  • Region 416 is correspondingly a drain region or a source region.
  • the patterning process referred to in the embodiments of the present disclosure includes processes including photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • the switching transistor of the top gate structure and the driving transistor of the bottom gate structure are simultaneously formed in the same process, and the process is easy to implement and cost-saving.
  • FIG. 10 is a schematic block diagram of an organic light emitting diode display device 20 applying the above pixel circuit according to an embodiment of the present disclosure.
  • the OLED display device 20 includes a plurality of pixel units 201 arranged in an array, each pixel unit including at least one organic light emitting diode and the above pixel circuit connected to the organic light emitting diode, and the organic light emitting diode is driven by the pixel circuit Glowing.
  • the organic light emitting diode display device 20 may further include a data driving circuit 6 and a gate driving circuit 7.
  • the data driving circuit 6 is for providing a data signal; the gate driving circuit 7 is for providing a scanning signal (for example, the signal Vscan), and may further be used for providing various control signals.
  • the data driving circuit 6 is electrically connected to the pixel unit 8 through the data line 61, and the gate driving circuit 7 is electrically connected to the pixel unit 8 through the gate line 71.
  • the data driving circuit 6 and the gate driving circuit 7 can be implemented as a semiconductor chip.
  • the display device may further include other components, such as a timing controller, a signal decoding circuit, a voltage conversion circuit, etc., and these components may be, for example, existing conventional components, and are not described herein again.
  • the pixel circuit adopts a switching transistor of a top gate structure and a driving transistor of a bottom gate structure, and combines the advantages of the two structures, so that the pixel circuit can have a comparison
  • the fast switching speed in turn, can have a large driving current, thereby improving the display performance of the display device.
  • the pixel circuit can simultaneously form a switching transistor of a top gate structure and a driving transistor of a bottom gate structure in the same process, and the process is easy to implement and cost-saving.

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Abstract

一种像素电路(10)，包括基板(100)以及设置于所述基板上(100)的第一薄膜晶体管(11)、第二薄膜晶体管(12)，其中，所述第一薄膜晶体管(11)为顶栅结构，所述第二薄膜晶体管(12)为底栅结构，所述第一薄膜晶体管(11)的第一极(211)和所述第二薄膜晶体管(12)的栅极(212)彼此电性连接，且同层设置于所述基板(100)上。该像素电路(10)具有较高的开关速度，同时具有较大的驱动电流，且制造方法易于实现，工艺成本较低。

Description

像素电路、其制造方法及显示装置 技术领域
本公开的实施例涉及一种像素电路、其制造方法以及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode,OLED)显示器具有主动发光、对比度高、响应速度快、轻薄等诸多优点，成为主要的新一代显示器之一。其工作原理是通过像素电路向阳极和阴极施加适当的电压，而使得位于阳极和阴极之间的有机发光层发光，从而显示图像。
薄膜晶体管(Thin-film Transistor,TFT)是像素电路中重要的器件，器件的结构及制作工艺都极大地影响着薄膜晶体管的性能。
发明内容
本公开的实施例提供一种像素电路，包括基板以及设置于所述基板上的第一薄膜晶体管、第二薄膜晶体管，其中，所述第一薄膜晶体管为顶栅结构，所述第二薄膜晶体管为底栅结构，所述第一薄膜晶体管的第一极和所述第二薄膜晶体管的栅极彼此电性连接，且同层设置于所述基板上。
本公开的实施例还提供一种上述像素电路的制造方法，包括：提供基板；在所述基板上形成第一薄膜晶体管和第二薄膜晶体管，其中，所述第一薄膜晶体管为顶栅结构，所述第二薄膜晶体管为底栅结构，通过在所述基板上形成第一金属层并对所述第一金属层图案化形成彼此电性连接且同层设置的所述第一薄膜晶体管的第一极及所述第二薄膜晶体管的栅极。
本公开的实施例还提供一种显示装置，包括如上所述的像素电路。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实 施例，而非对本公开的限制。
图1A是一种2T1C像素电路的示意图；图1B是另一种2T1C像素电路的示意图。
图2是本公开实施例提供的像素电路的剖面结构示意图。
图3是本公开实施例提供的像素电路的等效电路图。
图4是本公开实施例提供的变更实施例的剖面结构示意图。
图5A、图5B、图6-图8、图9A和图9B是根据本公开实施例的像素电路的阵列基板的示例性制造方法的各步骤的剖面示意图。
图10是本公开实施例提供的有机发光二极管显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
OLED显示装置通常包括多个按阵列排列的像素单元，每个像素单元包 括多个子像素，每个子像素包括像素驱动电路和OLED器件，像素驱动电路配置为基于数据信号驱动OLED发出预定强度的光。像素驱动电路通常包括2T1C像素电路，即利用两个TFT和一个存储电容Cs来实现驱动OLED发光的基本功能，其中，一个TFT为开关晶体管，主要起开关作用，控制数据信号的传输；另一个TFT为驱动晶体管，主要起驱动作用，为作为OLED器件的阴极或阳极的像素电极提供驱动电流。图1A和图1B分别示出了两种2T1C像素电路的示意图。
如图1A所示，一种2T1C像素驱动电路包括开关晶体管T1、驱动晶体管T2以及存储电容Cs。例如，该开关晶体管T1和驱动晶体管T2均为N型TFT。开关晶体管T1的栅极连接栅线(扫描线)以接收扫描信号(Vscan)，漏极连接到数据线以接收数据信号(Vdata)，源极连接到驱动晶体管T2的栅极；驱动晶体管T2的漏极连接到第一电源端(Vdd，高压端)，源极连接到OLED的正极端；存储电容Cs的一端连接到开关晶体管T1的源极以及驱动晶体管T2的栅极，另一端连接到驱动晶体管T2的漏极以及第一电源端；OLED的负极连接到第二电源端(Vss，低压端)，例如接地。该2T1C像素电路的驱动方式是将像素的明暗(灰阶)经由两个TFT和存储电容Cs来控制。当通过栅线施加扫描信号Vscan以开启开关晶体管T1时，数据驱动电路通过数据线送入的数据电压(Vdata)将经由开关晶体管T1对存储电容Cs充电，由此将数据电压存储在存储电容Cs中，且此存储的数据电压控制驱动晶体管N1的导通程度，由此控制流过驱动晶体管以驱动OLED发光的电流大小，即此电流决定该像素发光的灰阶。
如图1B所示，另一种2T1C像素驱动电路包括开关晶体管T1、驱动晶体管T2以及存储电容Cs，但是其连接方式略有改变。更具体而言，图1B的像素电路相对于图1A的变化之处包括：OLED的正极端连接到第一电源端(Vdd，高压端)而负极端连接到驱动晶体管T2的漏极，驱动晶体管T2的源极连接到第二电源端(Vss，低压端)，例如接地。存储电容Cs的一端连接到开关晶体管T1的源极以及驱动晶体管T2的栅极，另一端连接到驱动晶体管T2的源极以及第二电源端。该2T1C像素电路的工作方式基本上与图1A所示的像素电路基本相同，这里不再赘述。
例如，在上述2T1C的基础上，为了补偿例如驱动晶体管的阈值漂移、 电源线电阻导致的压降等，像素驱动电路可以进一步包括补偿电路，该补偿电路包括内部补偿电路或外部补偿电路，补偿电路可以包括晶体管、电容等。根据需要，像素驱动电路还可以包括复位电路、感测电路等。这里不再赘述。
薄膜晶体管的性能很大程度取决于其结构。薄膜晶体管的基本结构包括顶栅型结构和底栅型结构。通常顶栅型结构的薄膜晶体管具有较小的寄生电容从而能具有更快的开启速度，底栅型结构的薄膜晶体管具有较大的开态电流和电学稳定性能。局限于工艺技术，例如对于上述2T1C像素电路的制作工艺中，开关晶体管和驱动晶体管通常采用相同的结构，而很难将两种结构同时制作于同一基板上以兼具二者优点。
本公开的至少一个实施例提供一种像素电路、其制造方法及应用该像素电路的有机发光二极管显示装置，该像素电路采用顶栅型结构的开关晶体管和底栅型结构的驱动晶体管，结合两种晶体管结构的优势，使得像素电路既能具有较快的开关速度，又能具有较大的驱动电流，从而提高了显示装置的显示性能。在至少一个实施例中，可以在同一工艺中同时形成该像素电路的顶栅型结构的开关晶体管和底栅型结构的驱动晶体管，工艺易于实现且节约成本。
本公开实施例提供一种像素电路，包括基板以及设置于所述基板上的第一薄膜晶体管、第二薄膜晶体管，所述第一薄膜晶体管为顶栅结构，所述第二薄膜晶体管为底栅结构，所述第一薄膜晶体管的第一极和所述第二薄膜晶体管的栅极彼此电性连接，且同层设置于所述基板上。
本公开的另一个实施例还提供一种显示装置，其包括上述像素电路。
本公开的再一个实施例还提供一种像素电路的制造方法，其包括：提供基板；在所述基板上形成第一薄膜晶体管和第二薄膜晶体管，所述第一薄膜晶体管为顶栅结构，所述第二薄膜晶体管为底栅结构，通过在所述基板上形成第一金属层并对所述第一金属层图案化形成彼此电性连接且同层设置的所述第一薄膜晶体管的第一极及所述第二薄膜晶体管的栅极。
在本公开之中表述“同层设置”指代例如两个结构/图案由同一材料层通过一道构图工艺形成从而位于同一层，而非限定它们位于同一水平面 上。
以下将结合附图对本公开实施例提供的像素电路、其制造方法以及显示装置进行详细说明，以使得本公开实施例的技术方案更加清楚。
请参阅图2，图2为本公开一实施例的像素电路10的剖面结构示意图。像素电路10可应用于OLED显示装置，例如对应于2T1C像素驱动电路或包括2T1C单元的其他像素驱动电路。如图2所示，像素电路10包括基板100，其上定义一第一区域和第二区域，第一薄膜晶体管11设置于基板100上且位于该第一区域中，第二薄膜晶体管12设置于基板100上且位于该第二区域中。
第一薄膜晶体管11为顶栅结构，其包括依次层叠设置于基板100上的第一极211、缓冲层311、有源层410、栅极绝缘层511及第二极611、栅极612。有源层410包括第一区411、第二区412以及位于第一区411与第二区412之间的沟道区413。栅极绝缘层511位于沟道区413的上方且覆盖沟道区413；第一区411和第二区412未被栅极绝缘层511覆盖，第一区填充过孔301并与第一极211接触，第二区412与第二极611接触。
第二薄膜晶体管12为底栅结构，其包括依次层叠设置于基板100上的栅极212、栅极绝缘层312、有源层414、刻蚀阻挡层512、第一极613和第二极614。有源层414包括第一区415、第二区416以及位于第一区415与第二区416之间的沟道区417。刻蚀阻挡层512位于沟道区417的上方且覆盖沟道区417；第一区415和第二区416未被刻蚀阻挡层512覆盖，第一区415和第二区416分别与上方的第一极613和第二极614接触。
第一薄膜晶体管11和第二薄膜晶体管12为在同一工艺流程中形成，这在下文会有详细描述。第一薄膜晶体管11的第一极211与第二薄膜晶体管的栅极212彼此电性连接，且同层设置于基板100上。第一薄膜晶体管11的缓冲层311和第二薄膜晶体管12的栅极绝缘层312同层设置。第一薄膜晶体管11的有源层410与第二薄膜晶体管12的有源层414同层设置。第一薄膜晶体管11的栅极绝缘层511和第二薄膜晶体管12的刻蚀阻挡层512同层设置。第一薄膜晶体管11的第二极611与栅极612、第二薄膜晶体管12的第一极613与第二极614同层设置。
进一步地，像素电路10还可包括设置于基板100上的电容13，电容13包括第一电极131、第二电极132以及设置于第一电极131和第二电极132之间的介质层133。电容13的第一电极131与第一薄膜晶体管11的第一极211及第二薄膜晶体管12的栅极212同层设置于基板100上，且彼此电性连接。电容13的第二电极132与第一薄膜晶体管11的栅极612和第二极611、第二薄膜晶体管12的第一极613和第二极614同层设置，且电容13的第二电极132与第二薄膜晶体管12的第一极613与电性相连。电容13的介质层133与第一薄膜晶体管11的缓冲层311、第二薄膜晶体管12的栅极绝缘层312同层设置。
进一步地，像素电路10还可包括设置于第一薄膜晶体管11和第二薄膜晶体管12之上的钝化层700及设置于钝化层700之上的像素电极141，像素电极141与第二薄膜晶体管12通过过孔701电性连接。
之后，在像素电极141上形成OLED器件，该OLED器件包括叠层结构，该叠层结构包括阴极、阳极以及位于阴极和阳极之间的有机发光层。此外，该叠层结构还可以包括例如空穴注入层、空穴传输层、电子注入层、电子传输层等功能层。像素电极141可以为阴极或阳极，或者可以与阴极或阳极电连接。因此，像素电极141可以选择适当的导电材料制备，例如透明导电材料(氧化铟锡(ITO)等)或金属材料(例如铝或铝合金等)。此外，该OLED器件可以为顶发射型、底发射型或双面发射型等。
在本实施例中，像素电极141与第二薄膜晶体管12的第一极613电性连接，其等效电路如图3所示，其中第一薄膜晶体管11、第二薄膜晶体管12以及电容13分别对应图中的第一薄膜晶体管T1、第二薄膜晶体管T2以及存储电容Cs。以下将结合图3、并以第一薄膜晶体管T1和第二薄膜晶体管T2均为N型管，第一极为源极、第二极为漏极为例说明像素电路10的工作原理。
如图3所示，第一薄膜晶体管T1的栅极连接栅线(扫描线)以接收扫描信号(Vscan)，漏极连接到数据线以接收数据信号(Vdata)，源极连接到第二薄膜晶体管T2的栅极；第二薄膜晶体管T2的漏极连接到第一电源端(Vdd，高压端)，源极连接到像素电极，也就是OLED的正极端；存储电容Cs的第一电极连接到第一薄膜晶体管T1的源极以及第二薄膜晶体管T2 的栅极，第二电极连接到第二薄膜晶体管T2的源极以及像素电极；OLED的负极端连接到第二电源端(Vss，低压端)，例如接地。例如，根据需要，像素电极还可以与外部的补偿电路相连(图未示)，该补偿电路在存储电容Cs开始充电之前维持像素电极处于低电位。该2T1C像素电路的驱动方式是将像素的明暗(灰阶)经由两个TFT和存储电容Cs来控制。当通过栅线施加扫描信号Vscan以开启第一薄膜晶体管T1时，数据驱动电路通过数据线送入的数据电压(Vdata)将经由第一薄膜晶体管T1对存储电容Cs充电，由此将数据电压存储在存储电容Cs中，且此存储的数据电压控制第二薄膜晶体管T1的导通程度，由此控制流过第二薄膜晶体管T1以驱动OLED发光的电流大小，即此电流决定该像素发光的灰阶。
在另一个示例中，像素电极141可与第二薄膜晶体管12的第二极614电性连接，如图4所示。此时，像素电路10的等效电路即图1A中的电路。其工作原理不再赘述。
例如，第一薄膜晶体管11可为N型薄膜晶体管，也可为P型薄膜晶体管。第二薄膜晶体管12可为N型薄膜晶体管，也可为P型薄膜晶体管。第一薄膜晶体管11的第一极211可为源极或漏极，那么第二极611相应地可为漏极或源极，第一区411相应地为源极区或漏极区，第二区413相应地为漏极区或源极区。第二薄膜晶体管12的第一极613可为源极或漏极，那么第二极614相应地可为漏极或源极，第一区415相应地为源极区或漏极区，第二区416相应地为漏极区或源极区。
例如，第一薄膜晶体管11的有源层410与第二薄膜晶体管12的有源层414包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)、金属氧化物半导体(a-IGZO，ZnO，ZnON，IZTO等)以及有机物材料(六噻吩，聚噻吩等)。
例如，第一薄膜晶体管11的栅极612、第一极211、第二极611及第二薄膜晶体管12的栅极212、第一极613、第二极614、电容13的第一电极131和第二电极132的材料包括但不限于常用的电极材料如Ag，Cu，Al，Mo等，或多层金属如MoNb/Cu/MoNb等，或上述各种材料的合金如AlNd，MoNb等。
例如，第一薄膜晶体管11的第一区411和第二区412可以是经过导体化处理的导体，第一区411与第一极211接触而直接形成电连接，该结构具有如下优点：有效减小第一薄膜晶体管11的寄生电容从而提高电路的充电速度；降低有源层414与第一区411及第二区412的接触电阻，从而提高第一薄膜晶体管11的载流子迁移率；有效节省版图面积，提高像素的开口率。同样地，第二薄膜晶体管12的第一区415和第二区416也可以是经过导体化处理的导体从而降低有源层414与第一区415和第二区416的接触电阻，从而提高第二薄膜晶体管12的载流子迁移率。
例如，第一薄膜晶体管11的栅极绝缘层511、缓冲层311及第二薄膜晶体管12的栅极绝缘层312、刻蚀阻挡层512、电容13的介质层133的材料包括但不限于常规的介质材料，如SiOx、SiNx、SiON等介质材料，或各种有机绝缘材料，或High k材料如AlOx，HfOx，TaOx等。
例如，基板100可以为可弯曲的柔性基板，例如，各种塑料膜，如聚对苯二甲酸乙二醇酯(PET)、聚醚砜(polyether sulfone，PES)、聚碳酸酯(Polycarbonate，PC)或聚酰亚胺(PI)及其衍生物等制成的基板。或者，基板100可以刚性基板，例如，玻璃基板、不锈钢基板等。
本公开实施例及其变更实施例提供的像素电路，采用顶栅型结构的开关晶体管和底栅型结构的驱动晶体管，结合两种结构的优势，使得像素电路既能具有较快的开关速度，又能具有较大的驱动电流，从而提高了显示装置的显示性能。同时，第二薄膜晶体管为底栅型结构，具有遮光作用，可以改善NBTIS(Negative Bias Thermal Illumination Stress)测试中光照造成的薄膜晶体管显示不均的问题，从而降低像素补偿电路的补偿难度。
本公开的一实施例提供了上述像素电路的制造方法，该方法至少包括：提供基板；在所述基板上形成第一薄膜晶体管和第二薄膜晶体管，其中，所述第一薄膜晶体管为顶栅结构，所述第二薄膜晶体管为底栅结构，通过在所述基板上形成第一金属层并对所述第一金属层图案化形成彼此电性连接且同层设置的所述第一薄膜晶体管的第一极及所述第二薄膜晶体管的栅极。
以下结合图5A-图9B对本公开实施例提供的像素电路的示例性制造方 法进行描述。
步骤S51，提供基板100，对基板100进行清洗和干燥。基板100可以为可弯曲的柔性基板，例如，各种塑料膜，如聚对苯二甲酸乙二醇酯(PET)、聚醚砜(polyether sulfone，PES)、聚碳酸酯(Polycarbonate，PC)或聚酰亚胺(PI)及其衍生物等制成的基板。或者，基板100可以刚性基板，例如，玻璃基板、不锈钢基板等。在基板100上定义出第一区域、第二区域及第三区域，分别对应第一薄膜晶体管11、第二薄膜晶体管12和电容13。
步骤S52，如图5A所示，在基板100上形成第一金属层200并利用第一构图工艺对该第一金属层200进行图案化处理，从而分别在第一区域、第二区域及第三区域形成彼此电性连接的第一薄膜晶体管11的第一极211、第二薄膜晶体管12的栅极212及电容的第一电极131。第一金属层200经图案化处理后的平面图如图5B所示，从图中可看出，第一薄膜晶体管11的第一极211、第二薄膜晶体管12的栅极212及电容的第一电极131彼此电性连接。图5B所示为示例性形成的图案，图5A为出于方便描述和展示的考虑绘制的示意图，二者在尺寸和形状上并不一一对应。
步骤S53，如图6所示，在第一金属层200上形成第一绝缘层300并利用第二构图工艺对第一绝缘层300进行图案化以形成过孔301并露出至少部分的所述第一薄膜晶体管11的第一极211。这样形成了第一薄膜晶体管11的缓冲层311、第二薄膜晶体管12的栅极绝缘层312及电容13的介质层133。
例如，在形成第一绝缘层300时可以采用化学气相淀积(PECVD)工艺，并对该工艺进行优化，以获得界面陷阱缺陷态密度较低的栅极绝缘层312，同时由于质量得以提高，第一绝缘层300的厚度可以适当降低，如此可以有效增大电容13的电容值，提高显示性能。
步骤S54，如图6所示，在第一绝缘层300上形成半导体层400并利用第三构图工艺对半导体层400进行图案化处理以形成第一薄膜晶体管11的有源层410和第二薄膜晶体管12的有源层414，其中，第一薄膜晶体管11的有源层410填充过孔301并与第一薄膜晶体管11的第一极211的裸露部分接触。例如，半导体层400的材料包括但不限于硅基材料(a-Si，p-Si 等)、金属氧化物半导体(a-IGZO，ZnON，IZTO等)、以及有机物材料(六噻吩，聚噻吩等)等。
步骤S55，如图7所示，在半导体层400上形成第二绝缘层500并利用第四构图工艺对第二绝缘层500进行图案化处理以在第一薄膜晶体管11的有源层410上形成栅极绝缘层511、在第二薄膜晶体管12的有源层414上形成刻蚀阻挡层512以及形成电容13的介质层133。例如，第一薄膜晶体管11的栅极绝缘层511覆盖部分的有源层410，第二薄膜晶体管12的刻蚀阻挡层512覆盖部分的有源层414。
步骤S56，如图8所示，在第二绝缘层500上形成第二金属层600并利用第五构图工艺对第二金属层600进行图案化处理以形成第一薄膜晶体管11的第二极611和栅极612、第二薄膜晶体管12的第一极613和第二极614以及电容13的第二电极132。例如，第一薄膜晶体管11的第二极611位于其栅极绝缘层511远离其第一极211的一侧，并与第一薄膜晶体管11的有源层410未被其栅极绝缘层511覆盖的部分接触；第二薄膜晶体管12的第一极613和第二极614位于其刻蚀阻挡层512相对的两侧，分别与第二薄膜晶体管12的有源层414未被其刻蚀阻挡层512覆盖的部分接触。
这样，就在基板100上形成了彼此电性连接的顶栅型结构的第一薄膜晶体管11、底栅型结构的第二薄膜晶体管12及电容13。其中，第一薄膜晶体管11的第一极211、第二薄膜晶体管12的栅极212及电容13的第一极131彼此电性连接，电容13的第二电极132与第二薄膜晶体管13的第一极613电性连接。
如图9A所示，在上述步骤S56以后，还可包括步骤S57，在第二金属层600上形成钝化层700并对钝化层700进行平坦化处理，然后利用第六构图工艺对钝化层700进行图案化处理以形成过孔701，并露出至少部分的第二薄膜晶体管12的第一极613；然后钝化层700上形成导电层800，导电层800填充过孔701并与第二薄膜晶体管12的第一极613裸露的部分接触，对该导电层进行构图以形成像素电极141。该导电层根据需要可以例如为氧化铟锡(ITO)或金属层。之后，可以在像素电极141上进一步形成OLED器件。这样就形成如图2所示的像素电路结构。可变更地，过孔701可开在第二薄膜晶体管12的第二极614对应的位置并露出至少部分的第二薄膜晶体 管12的第二极614，导电层800填充过孔701并与第二薄膜晶体管12的第二极614裸露的部分接触，如图9B所示。这样就形成如图4所示的像素电路结构。
进一步地，在步骤S54之后且在步骤S55之前，还可包括：对第一薄膜晶体管11的有源层410未被第一薄膜晶体管11的栅极绝缘层511覆盖的部分和第二薄膜晶体管12的有源层414未被刻蚀阻挡层512覆盖的部分进行导体化处理。这样，第一薄膜晶体管11的有源层410包括导体化的第一区411、第二区412及位于第一区411与第二区412之间的半导体沟道区413；第二薄膜晶体管12的有源层414包括导体化的第一区415、第二区416及位于第一区415和第二区416之间的半导体沟道区417。第一薄膜晶体管11的第一区411和第二区412分别与其第一极211和第二极611接触，第二薄膜晶体管12的第一区415和第二区416分别与其第一极613和第二极614接触。对第一薄膜晶体管11的有源层410和第二薄膜晶体管12的有源层414的导体化处理是在同一道工艺中完成的，例如，该导体化处理可包括以第一薄膜晶体管11的栅极绝缘层511和第二薄膜晶体管12的刻蚀阻挡层512为掩膜对第一薄膜晶体管11的有源层410和第二薄膜晶体管12的有源层414进行离子注入或等离子处理等。该导体化处理降低了薄膜晶体管的第一极、第二极与其有源层的接触电阻，有利于提高薄膜晶体管的载流子迁移率，进一步提高薄膜晶体管的开关速度及驱动电流。
在另一个示例中，如果不需要对第一薄膜晶体管11的有源层410和第二薄膜晶体管12的有源层414的导体化处理，则形成第一薄膜晶体管11的栅极绝缘层511和第二薄膜晶体管12的刻蚀阻挡层512的第二绝缘层可以分别覆盖包括有源层410和有源层414在内的基板表面，然后经过构图工艺形成暴露有源层的过孔，以便于形成源极或漏极与有源层接触。
第一薄膜晶体管11和第二薄膜晶体管12可以是N型，也可以是P型。第一薄膜晶体管11的第一极211可为源极或漏极，那么第二极611相应地可为漏极或源极，第一区411相应地为源极区或漏极区，第二区413相应地为漏极区或源极区。第二薄膜晶体管12的第一极613可为源极或漏极，那么第二极614相应地可为漏极或源极，第一区415相应地为源极区或漏极区，第二区416相应地为漏极区或源极区。
本公开实施例所指的构图工艺包括通常包括光刻胶涂敷、曝光、显影、刻蚀、光刻胶剥离等工艺。
根据本公开实施例提供的像素电路的制造方法，在同一工艺中同时形成顶栅型结构的开关晶体管和底栅型结构的驱动晶体管，工艺易于实现且节约成本。
图10为本公开的一实施例提供的一种应用上述像素电路的有机发光二极管显示装置20的示意性框图。有机发光二极管显示装置20包括阵列排布的多个像素单元201，每个像素单元包括至少一个有机发光二极管及与该有机发光二极管连接的上述像素电路，该有机发光二极管在该像素电路的驱动下发光。
有机发光二极管显示装置20还可以包括数据驱动电路6和栅极驱动电路7。数据驱动电路6用于提供数据信号；栅极驱动电路7用于提供扫描信号(例如信号Vscan)，还可以进一步用于提供各种控制信号。数据驱动电路6通过数据线61与像素单元8电连接，栅极驱动电路7通过栅线71与像素单元8电连接。数据驱动电路6和栅极驱动电路7可以实现为半导体芯片。
该显示装置还可以包括其他部件，例如时序控制器、信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再赘述。
根据本公开实施例的像素电路、其制造方法以及显示装置，该像素电路采用顶栅型结构的开关晶体管和底栅型结构的驱动晶体管，结合两种结构的优势，使得像素电路既能具有较快的开关速度，又能具有较大的驱动电流，从而提高了显示装置的显示性能。该像素电路可在同一工艺中同时形成顶栅型结构的开关晶体管和底栅型结构的驱动晶体管，工艺易于实现且节约成本。
本领域技术人员可以理解的，除了基本的2T1C像素驱动电路之外，其它的像素驱动电路结构，例如5T1C、7T1C等nTmC(n、m为正整数)的驱动电路结构，只要其中对应开关晶体管的薄膜晶体管采用顶栅型结构、对应驱动晶体管的薄膜晶体管采用底栅型结构均为本公开所涵盖。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2017年8月1日递交的中国专利申请第201710646875.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (18)

  1. 一种像素电路，包括基板以及设置于所述基板上的第一薄膜晶体管、第二薄膜晶体管，其中，所述第一薄膜晶体管为顶栅结构，所述第二薄膜晶体管为底栅结构，所述第一薄膜晶体管的第一极和所述第二薄膜晶体管的栅极彼此电性连接，且同层设置于所述基板上。
  2. 如权利要求1所述的像素电路，还包括设置于所述基板上的电容，所述电容包括第一电极、第二电极以及设置于所述第一电极与所述第二电极之间的介质层，其中，所述电容的第一电极与所述第一薄膜晶体管的第一极及所述第二薄膜晶体管的栅极电性连接，且同层设置于所述基板上。
  3. 如权利要求2所述的像素电路，其中，所述第一薄膜晶体管的栅极和第二极、所述第二薄膜晶体管的第一极和第二极以及所述电容的第二电极同层设置，且所述第二薄膜晶体管的第一极与所述电容的第二电极电性相连。
  4. 如权利要求3所述的像素电路，其中，所述第一薄膜晶体管还包括设置于其第一极与有源层之间的缓冲层，所述缓冲层、所述第二薄膜晶体管的栅极绝缘层与所述电容的介质层同层设置。
  5. 如权利要求3所述的像素电路，还包括像素电极，其中，所述像素电极与所述第二薄膜晶体管的第一极及第所述电容的第二电极电性连接。
  6. 如权利要求3所述的像素电路，还包括像素电极，其中，所述像素电极与所述第二薄膜晶体管的第二极电性连接。
  7. 如权利要求1-6任意一项所述的像素电路，其中，所述第一薄膜晶体管的有源层与所述第二薄膜晶体管的有源层同层设置。
  8. 如权利要求1-6任意一项所述的像素电路，其中，所述第二薄膜晶体管还包括刻蚀阻挡层，所述刻蚀阻挡层与所述第一薄膜晶体管的栅极绝缘层同层设置。
  9. 如权利要求1-6任意一项所述的像素电路，其中，所述第一薄膜晶体管的有源层包括第一区、第二区及位于所述第一区和第二区之间的沟道区，所述第一薄膜晶体管的有源层的第一区与所述第一薄膜晶体管的第一极通过过孔电性连接，且所述第一区填充于所述过孔中。
  10. 如权利要求9所述的像素电路，其中，所述第一薄膜晶体管的有源 层的第一区和第二区以及所述第二薄膜晶体管的有源层的第一区和第二区为导体。
  11. 一种显示装置，其包括如权利要求1-10任意一项所述的像素电路。
  12. 一种像素电路的制造方法，包括：
    提供基板；
    在所述基板上形成第一薄膜晶体管和第二薄膜晶体管，其中，所述第一薄膜晶体管为顶栅结构，所述第二薄膜晶体管为底栅结构，通过在所述基板上形成第一金属层并对所述第一金属层图案化形成彼此电性连接且同层设置的所述第一薄膜晶体管的第一极及所述第二薄膜晶体管的栅极。
  13. 如权利要求12所述的像素电路的制造方法，其中，在形成第一薄膜晶体管和第二薄膜晶体管的同时还一并形成电容，在对所述第一金属层图案化的同时还一并形成所述电容的第一电极，所述第一电极与所述第一薄膜晶体管的第一极及所述第二薄膜晶体管的栅极电性连接。
  14. 如权利要求12所述的像素电路的制造方法，其中，在所述基板上形成第一薄膜晶体管和第二薄膜晶体管包括：
    在所述第一金属层上形成第一绝缘层并图案化所述第一绝缘层以露出至少部分的所述第一薄膜晶体管的第一极；
    在所述第一绝缘层上形成半导体层并图案化所述半导体层以形成所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层，其中，所述第一薄膜晶体管的有源层通过所述过孔与所述第一薄膜晶体管的第一极的裸露部分接触；
    在所述半导体层上形成第二绝缘层并图案化所述第二绝缘层以在所述第一薄膜晶体管的有源层上形成栅极绝缘层，以及在所述第二薄膜晶体管的有源层上形成刻蚀阻挡层；
    在所述第二绝缘层上形成第二金属层并图案化所述第二金属层以形成所述第一薄膜晶体管的第二极和栅极、以及所述第二薄膜晶体管的第一极和第二极。
  15. 如权利要求14所述的像素电路的制造方法，其中，在所述基板上形成所述第一薄膜晶体管和所述第二薄膜晶体管还包括：
    在图案化所述半导体层之后，形成所述第二绝缘层之前，对所述第一薄 膜晶体管的有源层未被所述第一薄膜晶体管的栅极绝缘层覆盖的部分和所述第二薄膜晶体管的有源层未被所述刻蚀阻挡层覆盖的部分进行导体化处理。
  16. 如权利要求15所述的像素电路的制造方法，其中，所述导体化处理包括以所述第一薄膜晶体管的栅极绝缘层和所述刻蚀阻挡层为掩膜对所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层进行离子注入。
  17. 如权利要求14-16任意一项所述的像素电路的制造方法，还包括：
    在所述第二金属层上形成介质层；
    对所述介质层进行图案化处理以露出至少部分所述第二薄膜晶体管的第一极，并在所述介质层上形成导电层，所述导电层与所述第二薄膜晶体管的第一极的裸露部分接触。
  18. 如权利要求14-16任意一项所述的像素电路的制造方法，还包括：
    在所述第二金属层上形成介质层；
    对所述介质层进行图案化处理以露出至少部分所述第二薄膜晶体管的第二极，并在所述介质层上形成导电层，所述导电层与所述第二薄膜晶体管的第二极的裸露部分接触。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110391283A (zh) * 2019-07-31 2019-10-29 上海天马微电子有限公司 有机发光显示面板和有机发光显示装置
EP3806151A1 (en) * 2019-10-08 2021-04-14 Imec VZW Thin-film transistor architecture for high resolution displays

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6799123B2 (ja) * 2018-09-19 2020-12-09 シャープ株式会社 アクティブマトリクス基板およびその製造方法
KR20200145882A (ko) * 2019-06-19 2020-12-31 삼성디스플레이 주식회사 표시 장치
CN110854133B (zh) 2019-10-28 2021-03-16 深圳市华星光电半导体显示技术有限公司 显示面板的制备方法及显示面板
CN110828579B (zh) * 2019-10-29 2021-08-03 深圳市华星光电半导体显示技术有限公司 背沟道蚀刻型结构有源层为igzo的tft器件及其制作方法
CN111063698B (zh) * 2019-12-18 2022-11-08 京东方科技集团股份有限公司 有机发光二极管阵列基板及制作方法、显示面板和装置
CN111384071B (zh) * 2020-03-25 2023-04-07 京东方科技集团股份有限公司 一种像素结构、阵列基板、显示装置和制作方法
CN111682075A (zh) * 2020-06-24 2020-09-18 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、移位寄存器和栅极驱动电路
CN112103339A (zh) * 2020-09-03 2020-12-18 Oppo广东移动通信有限公司 薄膜晶体管、像素电路、显示屏、电子设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101542735A (zh) * 2007-05-31 2009-09-23 松下电器产业株式会社 有机电致发光器件和其制造方法
CN101958339A (zh) * 2009-07-15 2011-01-26 三星移动显示器株式会社 有机发光显示装置及其制造方法
CN106486495A (zh) * 2015-08-27 2017-03-08 乐金显示有限公司 薄膜晶体管基板、显示器及其制造方法
US20170194405A1 (en) * 2015-08-13 2017-07-06 Shenzhen China Star Optoelectronics Technology Co., Ltd. Organic light emitting display and method of manufacturing the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100134872A1 (en) * 2006-11-21 2010-06-03 Koninklijke Philips Electronics, N.V. Switchable grating based on electrophoretic particle system
WO2008075625A1 (ja) * 2006-12-18 2008-06-26 Panasonic Corporation 半導体デバイス
US8633486B2 (en) * 2010-07-09 2014-01-21 Casio Computer Co., Ltd. Transistor structure and light emitting apparatus
CN202423298U (zh) * 2011-12-31 2012-09-05 京东方科技集团股份有限公司 一种tft、阵列基板以及显示器件
US9978826B2 (en) * 2014-12-06 2018-05-22 Lg Display Co., Ltd. Organic light emitting display device
KR102408898B1 (ko) * 2015-06-19 2022-06-16 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 이를 이용한 표시장치
KR102430575B1 (ko) 2015-08-26 2022-08-08 엘지디스플레이 주식회사 유기 발광 표시 장치 및 이의 제조 방법
KR102519942B1 (ko) * 2015-11-26 2023-04-11 엘지디스플레이 주식회사 유기발광 다이오드 표시장치용 박막 트랜지스터 기판
KR20180045964A (ko) * 2016-10-26 2018-05-08 삼성디스플레이 주식회사 표시 장치 및 그의 제조 방법
CN106652911B (zh) * 2017-02-24 2019-03-12 深圳市华星光电半导体显示技术有限公司 Oled像素驱动电路及oled显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101542735A (zh) * 2007-05-31 2009-09-23 松下电器产业株式会社 有机电致发光器件和其制造方法
CN101958339A (zh) * 2009-07-15 2011-01-26 三星移动显示器株式会社 有机发光显示装置及其制造方法
US20170194405A1 (en) * 2015-08-13 2017-07-06 Shenzhen China Star Optoelectronics Technology Co., Ltd. Organic light emitting display and method of manufacturing the same
CN106486495A (zh) * 2015-08-27 2017-03-08 乐金显示有限公司 薄膜晶体管基板、显示器及其制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3664142A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110391283A (zh) * 2019-07-31 2019-10-29 上海天马微电子有限公司 有机发光显示面板和有机发光显示装置
EP3806151A1 (en) * 2019-10-08 2021-04-14 Imec VZW Thin-film transistor architecture for high resolution displays

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