WO2019000373A1 - 用于测量时间的电路、方法及相关芯片、***和设备 - Google Patents
用于测量时间的电路、方法及相关芯片、***和设备 Download PDFInfo
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- WO2019000373A1 WO2019000373A1 PCT/CN2017/091048 CN2017091048W WO2019000373A1 WO 2019000373 A1 WO2019000373 A1 WO 2019000373A1 CN 2017091048 W CN2017091048 W CN 2017091048W WO 2019000373 A1 WO2019000373 A1 WO 2019000373A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
- G01S7/483—Details of pulse systems
- G01S7/486—Receivers
- G01S7/4865—Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
- G01S7/4866—Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak by fitting a model or function to the received signal
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
- G01S17/88—Lidar systems specially adapted for specific applications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
- G01S7/483—Details of pulse systems
- G01S7/484—Transmitters
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
Definitions
- the present application relates to the field of time measurement and, more particularly, to a circuit, method and related chip, system and apparatus for measuring time.
- a laser radar system also known as a light detection and ranging (LiDAR) system, is a perception system for the outside world.
- the detection process of the laser radar system mainly includes transmitting a laser signal (such as a laser pulse signal) to the outside; detecting a reflected signal of the laser signal; and determining a distance of the measured object according to a time difference between the emitted laser signal and the received reflected signal.
- the laser radar system can also reconstruct the three-dimensional information of the measured object by combining information such as the emission angle of the laser signal.
- planar sensing systems such as cameras, the laser radar system can know the three-dimensional information of the outside world. Therefore, the application of the laser radar system is more and more extensive.
- the laser radar system After receiving the reflected signal of the emitted laser signal, the laser radar system needs to measure the receiving time of the reflected signal through a time-to-digital converter (TDC), and the receiving time of the reflected signal and the laser signal. The launch time is compared to determine the distance of the measured object.
- TDC time-to-digital converter
- the TDC volume in the traditional Lidar system is relatively large, which limits the application of the Lidar system.
- the present application provides a circuit, method and related chip, system and apparatus for measuring time to reduce the volume of a lidar system.
- a circuit for measuring time comprising: a signal input terminal for receiving a signal to be tested; a delay chain, the delay chain comprising n delay units And the first delay unit of the delay chain is connected to the signal input terminal to The input end receives the signal to be tested, and the delay chain is configured to sequence the first rising edge from the first delay unit in response to the first delay unit receiving the signal to be tested Passed to the nth delay unit of the delay chain, wherein the first rising edge is a rising edge of the signal to be tested received by the first delay unit, where n is a positive integer greater than 2.
- a logic control unit wherein an input end of the logic control unit is connected to the signal input end to receive the signal to be tested from the signal input end, and an output end of the logic control unit and the delay chain
- the kth delay unit is connected
- the logic control unit is configured to transmit a second rising edge to the kth delay unit in response to the input of the logic control unit receiving the signal to be tested, to Passing the second rising edge sequentially from the kth delay unit to the nth delay unit
- the logic control unit further configured to pass the said to the kth delay unit After the second rising edge, and transmitted to the kth at the first rising edge Before the delay unit, transmitting a low level signal to the kth delay unit to sequentially transmit the low level signal from the kth delay unit to the nth delay unit, wherein
- the second rising edge is a rising edge of the signal to be tested received by the logic control unit, k is a positive integer, and 1 ⁇ k ⁇ n; and a latch unit is connected to the n delay units.
- a time measuring chip comprising: a circuit for measuring time according to the first aspect; and a processing circuit connected to the latch unit in the circuit for measuring time The processing circuit is configured to determine a time at which the signal input receives the signal to be tested according to an output signal of the n delay units stored in the latch unit.
- a laser detection and measurement system comprising: a transmitter configured to emit a laser signal; a receiver configured to receive a reflected signal corresponding to the laser signal, the reflected signal being an analog signal;
- the time measuring chip of the second aspect, the time measuring chip further comprising: a converting circuit connected to the circuit for measuring time, the converting circuit configured to convert the analog signal into a pulse form The signal to be tested is sent to the signal input end of the circuit for measuring time.
- the conversion circuit is coupled to the receiver and configured to receive the analog signal from the receiver.
- an automated apparatus comprising the laser detection and measurement system of the third aspect.
- a fifth aspect provides a method for measuring time, the method comprising: receiving a signal to be tested through a signal input end, wherein the signal input end is connected to a first delay unit of a delay chain, the delay The chain includes n delay units, each of which is connected to a latch unit, the signal The input terminal is further connected to the input end of the logic control unit, and the output end of the logic control unit is connected to the kth delay unit of the delay chain, wherein k and n are positive integers, n>2, 1 ⁇ K ⁇ n; in response to the first delay unit receiving the signal to be tested, sequentially transmitting a first rising edge from the first delay unit to the delay chain through the delay chain
- the nth delay unit, the first rising edge is a rising edge of the signal to be tested received by the first delay unit; and the input is received in response to an input of the logic control unit Transmitting, by the logic control unit, a second rising edge to the kth delay unit, to sequentially transmit the second rising edge from the kth delay unit
- the application realizes the function of TDC through a special circuit, which can reduce the volume and cost of the laser radar system.
- FIG. 1 is a diagram showing an example of the structure of a time measurement chip based on a delay chain.
- FIG. 2 is a schematic structural diagram of a circuit for measuring time according to an embodiment of the present invention.
- FIG. 3 is a schematic structural diagram of a circuit for measuring time according to another embodiment of the present invention.
- FIG. 4 is a schematic structural diagram of a circuit for measuring time according to another embodiment of the present invention.
- FIG. 5 is a schematic structural diagram of a circuit for measuring time according to another embodiment of the present invention.
- FIG. 6 is a schematic structural diagram of a time measurement chip according to an embodiment of the present invention.
- FIG. 7 is a schematic structural diagram of a LiDAR system according to an embodiment of the present invention.
- FIG. 8 is a schematic structural diagram of an automation device according to an embodiment of the present invention.
- FIG. 9 is a schematic flowchart of a method for measuring time according to an embodiment of the present invention.
- the embodiment of the present invention implements TDC through a dedicated circuit.
- the function can not only reduce the volume of the laser radar system, but also save the manufacturing cost of the laser radar system.
- the clock frequency of the chip is generally between MHz and GHz, that is, the chip is at the ns level every clock cycle.
- Lidar systems usually need to control the reception time measurement accuracy of the signal to be tested at the picosecond (ps) level. Therefore, the error of the reception time of the signal to be tested calculated directly based on the count value of the chip is equal to the clock period of the chip, that is, the error of the reception time of the signal to be tested calculated directly based on the count value of the chip is an error of ns level, and cannot be Meet the requirements of the laser radar system for time measurement accuracy.
- a feasible solution is to build a delay chain by using the internal device resources of the chip, thereby further subdividing the clock period of the ns level to obtain more fine time sampling information.
- the time-lapse measurement scheme based on the delay chain is introduced below with reference to FIG.
- FIG. 1 is a diagram showing an example of the structure of a time measurement chip based on a delay chain.
- the time measuring chip shown in FIG. 1 may include a circuit 10 for measuring time, and a counter 30.
- the circuit 10 can be a dedicated integrated circuit.
- the circuit 10 can be integrated, for example, in a field-programmable gate array (FPGA) chip or integrated in an application specific integrated circuit (ASIC) chip.
- FPGA field-programmable gate array
- ASIC application specific integrated circuit
- Circuitry 10 can include a delay chain 12, a latch unit 14, and a signal input 16.
- Signal input 16 can be used to receive the signal to be tested.
- the signal to be tested may be, for example, a pulse signal having a low level - a high level - a low level.
- the signal to be tested can be obtained by converting a analog signal by a conversion circuit (not shown in FIG. 1).
- the reflected signal received by the receiver of the lidar system is an analog signal, and the analog signal can be converted into a digital signal by a conversion circuit (such as a comparator) before sampling the reception time of the analog signal.
- the signal ie, the signal to be tested
- the signal is sampled by the circuit 10 for the receiving time of the rising edge of the signal to be tested, and the receiving time of the rising edge of the signal to be tested can be used to reflect the receiving time of the reflected signal.
- the delay chain 12 can include a plurality of delay units (i.e., the small squares of the sequential connections in FIG. 1) that are sequentially connected (or cascaded).
- the delay unit can be implemented by logic circuits inside the chip.
- circuit 10 can be integrated into an FPGA chip, and the delay unit can be a carry chain and/or a look-up table (lut) inside the FPGA chip.
- the delay units in the delay chain 12 may be located in the same slice of the FPGA chip, or may be located in different slices of the FPGA chip. Compared to the way in which the delay chain 12 is arranged across the slice, Arranging the delay chain 12 in the same slice can make the delay time of the delay chain 12 more stable and can simplify the wiring inside the chip.
- the delay time of the delay unit is generally between several ps and one hundred ps.
- the specific delay time of the delay unit is related to the type of logic circuit that constitutes the delay unit, the manufacturer of the chip, and the manufacturing process of the chip.
- the latch unit 14 can be used to latch the output signal of the delay unit.
- the latch unit 14 can be implemented, for example, by a register inside the chip.
- Each delay cell in delay chain 12 can be coupled to a register in latch unit 14.
- the CO end of each carry chain on the delay chain 12 can be connected to a register in the latch unit 14.
- the output signal of the CO end of the carry chain is a high level signal
- its corresponding register latches the digital signal 1
- the output signal of the CO end of the carry chain is a low level signal
- its corresponding register latches the digital signal 0.
- the delay chain 12 and the latch unit 14 may be located in the same slice, or may be located in different slices, which is not specifically limited in the embodiment of the present invention.
- the delay unit and the latch unit 14 can be placed in the same slice such that the delay of the trace from the delay unit to the latch unit 14 is controllable.
- the counter 30 can count the number of clock signals triggered by the system clock.
- the count value of the counter 30 can be defined as the coarse count C r
- the count time C r *T ck of the system clock is defined as the coarse time, where T ck represents the clock period of the system clock.
- the error of the coarse time is equal to the clock period T ck of the system clock. Since the clock period of the current chip is up to GHz, the error of the coarse time can be at least the error of the ns level.
- the delay time of the delay unit in the delay chain 12 is t d .
- the signal to be tested passes every t d time.
- the latch unit 14 latches the output signals of the delay units on the delay chain 12.
- the format type of the digital signal latched in the latch unit 14 is usually of the following format type "...111111110000.".
- T falling C r * T ck -C 2 * t d.
- the time-lapse measurement scheme based on the delay chain can refine the coarse time provided by the system clock to obtain refined time information of the signal to be tested.
- the error of the refinement time information is usually an error of the ps level.
- the structure of the circuit 10 can be further adjusted so that the rising edge of the signal to be tested can propagate with different delay units of the delay chain as a starting point in one clock cycle, thereby During the period, the rising edge of the signal to be measured can be sampled multiple times to obtain multiple sampling results. Then, the subsequent processing circuits can be used to average the plurality of sampling results, and the average value is taken as the receiving time of the rising edge of the signal to be tested. Through the above averaging operation, the time information calculated by the circuit 10 can be made more stable and accurate.
- the structure of the circuit 10 provided by the embodiment of the present invention is described in detail below with reference to FIG.
- circuit 10 for measuring time may include delay chain 12, latch unit 14, signal input 16 and logic control unit 18.
- the circuit 10 can be used to sample the time of the rising edge of the signal to be measured.
- Signal input 16 can be used to receive the signal to be tested.
- the signal to be tested may be a pulse signal having a low level - a high level - a low level.
- the signal to be tested can be obtained by converting a analog signal by a conversion circuit (not shown in FIG. 2).
- the reflected signal received by the receiver of the lidar system is an analog signal, and the analog signal can be converted into a digital signal by a conversion circuit (such as a comparator) before sampling the reception time of the analog signal.
- the signal ie, the signal to be tested
- the signal is sampled by the circuit 10 for the receiving time of the rising edge of the signal to be tested, and the receiving time of the rising edge of the signal to be tested can be used to indicate the receiving time of the reflected signal.
- Delay chain 12 can include n delay units.
- the first delay unit of the delay chain 12 can be coupled to the signal input 16 to receive the signal to be tested from the signal input. Before the arrival of the signal to be tested, the n delay units on the delay chain 12 may all be in an initial state (ie, a low state).
- the delay chain 12 may be configured to sequentially transmit the first rising edge from the first delay unit to the nth delay unit of the delay chain in response to the first delay unit receiving the signal to be tested.
- the first rising edge is a rising edge of the signal to be tested received by the first delay unit, where n is a positive integer greater than 2.
- An input of logic control unit 18 can be coupled to signal input 16 to receive a signal to be tested from signal input 16.
- the output of logic control unit 18 can be coupled to the kth delay unit of delay chain 12.
- the logic control unit 18 may be configured to transmit a second rising edge to the kth delay unit in response to the input of the logic control unit 18 receiving the signal to be tested to sequence the second rising edge from the kth delay unit Passed to the nth delay unit, where the second rising edge is the rising edge of the signal to be tested received by the logic control unit, k is a positive integer, and 1 ⁇ k ⁇ n.
- first rising edge and the second rising edge are both rising edges of the signal to be tested, except that the first rising edge propagates backward from the first delay unit of the delay chain 12, and the second rising edge Propagating backwards from the kth delay unit of delay chain 12.
- the signal to be tested has two propagation starting points in the delay chain 12, which are the first delay unit and the kth delay unit of the delay chain 12, respectively.
- the rising edge of the signal to be tested will appear at two different positions of the delay chain 12, that is, the position where the first rising edge is located, and the position where the second rising edge is located.
- the second rising edge propagates backward from the kth delay unit, causing the output signal of the delay unit that the second rising edge passes to change from the low state to the high state.
- the first rising edge is passed to the kth delay unit, and if the output signal of the kth delay unit remains high, the first rising edge cannot be sampled. Therefore, in order for the kth delay unit and its subsequent delay unit to sample the first rising edge, the kth delay unit and its subsequent delay need to be extended before the first rising edge reaches the kth delay unit.
- the time unit is sequentially reset to a low state.
- the logic control unit 18 may be further configured to: after transmitting the second rising edge to the kth delay unit, and before the first rising edge is passed to the kth delay unit, to the kth delay The time unit transmits a low level signal to sequentially pass the low level signal from the kth delay unit to the nth delay unit.
- the logic control unit 18 After the logic control unit 18 sends a low level signal to the kth delay unit, the low level signal will propagate backward with the kth delay unit as a starting point, so that the kth delay unit and its subsequent The delay unit is sequentially reset to a low state to prepare for continuing to propagate the first rising edge.
- the latch unit 14 can be connected to n delay units to latch the output signals of the n delay units.
- the latch unit 14 can be implemented by a register inside the chip.
- each delay cell in delay chain 12 may correspond to a register in latch unit 14.
- the delay unit is the carry chain
- the CO end of each carry chain on the delay chain 12 can be connected to a register.
- the register latches the digital signal 1.
- the register latches the digital signal 0.
- the delay chain 12 and the latch unit 14 may be located in the same slice, or may be located in different slices, which is not specifically limited in the embodiment of the present invention.
- the delay unit and the latch unit 14 can be placed in the same slice such that the delay of the trace from the delay unit to the latch unit 14 is controllable.
- the latch unit 14 can output the latch signal to a subsequent processing circuit to calculate the reception time of the rising edge of the signal to be tested.
- the specific processing of the processing circuit will be described in detail later with reference to specific embodiments.
- n is not specifically limited, and may be determined according to at least one of the following factors: the number of delay units that the signal to be tested can pass in one clock cycle, and the time of the circuit 10. The sampling accuracy requirement, the error range of the delay time of the delay unit, and the number of delay units between the first delay unit and the kth delay unit. Taking the operating frequency of the system clock as 200Mhz and the clock period of the system clock as 5ns as an example, assume that the signal to be tested can pass through 270 delay units and the kth delay unit in one clock cycle (ie 5ns). With 30 delay units separated from the first delay unit, n can be set to 300, which basically ensures that the rising edge of the signal to be tested is sampled twice in one clock cycle.
- the configuration of n may cause the signal to be tested to pass through the delay chain 12 for not less than 2 clock cycles. Since circuit 10 can sample twice on the rising edge of the signal to be tested in one clock cycle. If the configuration of n causes the signal to be tested to pass through the delay chain 12 for not less than 2 clock cycles, the circuit 10 can perform more sampling on the same signal to be tested, so that the sampling result of the rising edge is more accurate.
- n can be set to 600, so that the time for the signal to be tested to pass through the delay chain 12 can be basically guaranteed to be approximately 2 clock cycles, since each The clock cycle can sample the rising edge twice.
- a larger value can be configured for n if the internal resources of the chip allow.
- the value of k is not specifically limited in the embodiment of the present invention.
- the smaller the value of k the more the number of delay units that can be multiplexed on the first rising edge and the second rising edge, and the lower the construction cost of the delay chain 12.
- the smaller the value of k is, the closer the distance between the first rising edge and the second rising edge is, and the stronger the signal interference between the two is. Therefore, the value of k can be considered in consideration of the above factors.
- the value of k can be set to a value between 20 and 40.
- the value of k can be set to 32.
- the circuit for measuring time provided by the embodiment of the invention can reduce the volume of the laser radar system and save the cost of the laser radar system. Further, the circuit for measuring time provided by the embodiment of the present invention may perform multiple sampling on a rising edge of a signal to be tested in one clock cycle based on a delay chain, so that a rising edge of the subsequently calculated signal to be tested is obtained. The receiving time is more accurate.
- the logic control unit 18 sends a low level to the kth delay unit after passing the second rising edge to the kth delay unit and before the first rising edge is passed to the kth delay unit.
- the signal is sequentially reset to the states of the kth delay unit and the subsequent delay unit of the kth delay unit. It should be understood that there may be multiple ways to determine the timing of the transmission of the low-level signal, which is not specifically limited in the embodiment of the present invention.
- logic control unit 18 may employ a timer to trigger it to transmit the low level signal.
- the timing duration of the timer can be set to any time between the time that the logic control unit 18 passes the second rising edge to the kth delay unit and the time when the first rising edge is passed to the kth delay unit. For example, the time that the first rising edge is transmitted to the kth delay unit can be estimated, and the timing duration of the timer is set to be half of the time (the first rising edge is substantially passed to the first delay unit). And the middle position of the kth delay unit).
- the input of the logic control unit 18 may also be connected to the tth delay unit in the nth delay unit, where t is a positive integer and 1 ⁇ t ⁇ k;
- the logic control unit 18 can be configured to transmit a low level signal to the kth delay unit in response to the first rising edge being passed to the tth delay unit.
- t is not specifically limited in the embodiment of the present invention, and may be any value between 1 and k.
- the logic control unit 18 can detect the output signal of the tth delay unit, and when the output signal of the tth delay unit is converted from the low level signal to the high level signal, the logic control unit 18 determines the first The rising edge has been passed to the tth delay unit; then, the logic control unit 18 can send a low level signal to the kth delay unit, such that the delay of the kth delay unit and the kth delay unit The cells are sequentially reset to a low state.
- the embodiment of the present invention can accurately know the propagation position of the first rising edge in the delay chain, thereby making the selection of the trigger timing of the low level signal more reasonable.
- the triggering timing of the low-level signal provided by the embodiment of the present invention only needs to be determined based on the state of the output signal of the t-th delay unit, and is simple to implement.
- the embodiment of the present invention does not specifically limit the form of the logic control unit 18, and may be any circuit form capable of implementing the above functions.
- the logic control unit 18 can be implemented by one or more logic gate circuits inside the FPGA chip, or can be directly implemented by using lut. A specific implementation of the logic control unit 18 is presented below in conjunction with FIG.
- the logic control unit 18 may include an exclusive OR unit 181 (ie, an XOR unit in FIG. 4) and an OR unit 182 (ie, an OR unit in FIG. 4).
- the input of the exclusive OR unit 181 can be connected to the signal input terminal 16 and the tth delay unit.
- the input of unit or unit 182 may be coupled to the output of exclusive OR unit 181 and to the (k-1)th delay unit of delay chain 12. Or the output of unit 182 can be connected to the kth delay unit.
- the logic control unit 18 provided by the implementation of the present invention has a small number of circuit forms and is simple to implement.
- Phase 1 Before the signal to be tested is input to the signal input terminal 16, the state of the output signals of the 600 delay units is 0.
- Phase 2 The rising edge of the signal to be tested reaches the signal input terminal 16, and the state of the output signal of the first delay unit first changes from 0 to 1. Further, under the action of the exclusive OR unit 181, the state of the output signal of the 32nd delay unit is changed from 0 to 1. The state of the output signal of the remaining delay units on the delay chain is temporarily maintained at zero.
- Stage 3 When the first rising edge is transmitted to the 20th delay unit, the second rising edge reaches the (32+X)th delay unit, X is theoretically equal to 19, but is affected by factors such as processing techniques. The specific value of X will fluctuate. For example, the value of X will fluctuate between 12-28. Since the first rising edge reaches the 20th delay unit, under the action of the exclusive OR unit 181, the 32nd delay unit starts to deliver a low level signal.
- Stage 4 When the first rising edge is passed to the 31st delay unit, the output signal of the 32nd delay unit changes from 0 to 1 due to the action of the OR unit 182, and the first rising edge is transmitted.
- the main changes in the output signal state of the first 80 delay units are as follows:
- the first rising edge is passed to the third delay unit of the delay chain 12:
- the first rising edge is passed to the 20th delay unit of the delay chain 12, and the output signal state of the 32nd delay unit of the delay chain 12 changes from 1 to 0, and the low level signal is transmitted:
- the first rising edge is passed to the 23rd delay unit of the delay chain 12:
- the first rising edge is passed to the 32th delay unit of the delay chain 12:
- the first rising edge is passed to the 40th delay unit of the delay chain 12:
- the delay chain 12 has two rising edge sampling positions at the same time.
- the length of the delay chain 12 is 600, it is slightly larger. The maximum distance that can be transmitted in the two clock cycles of the rising edge of the signal to be tested. Therefore, through the delay chain 12, the four sampling results of the rising edge of the signal to be tested can be obtained in two clock cycles. Then, the average of 4 sampling results can be averaged as the final sampling result of the rising edge of the signal to be tested.
- circuit 10 is mainly exemplified by the application of the circuit 10 to the laser radar system.
- the embodiment of the present invention is not limited thereto, and the circuit 10 can be applied to any occasion where time sampling is required, and signals to be tested in different occasions.
- the physical meaning may be different, but the rising edge of the signal to be tested is sampled in a similar manner.
- n delay units in the delay chain 12 are cascaded together, that is, the n delay units are sequentially arranged in order.
- two adjacent delay units in the n delay units may be directly cascaded through signal lines, or may be indirectly cascaded through some devices.
- the (k-1)th delay unit and the kth delay unit on the delay chain 12 are indirectly cascaded by the OR unit 182.
- the embodiment of the invention also provides a time measuring chip.
- the time measurement chip 60 can include the circuit 10 and the processing circuit 62 described above.
- the processing circuit 62 can be coupled to the latch unit 14 in the circuit 10, and the processing circuit 62 can be configured to determine the time at which the signal input receives the signal to be tested based on the output signals of the n delay units stored in the latch unit 14. .
- the processing circuit 62 can implement functions such as rising edge detection and time calculation, and the functions of the processing circuit 62 will be described in detail below.
- processing circuit 62 can be used to detect the position of the first rising edge and the second rising edge in delay chain 12.
- the detection of the specific position of the rising edge in the delay chain may be: searching the state of the output signal of the delay unit of the delay chain 12, and finding two positions of the output signal from the state 1 to the state 0, the two positions That is, the position of the first rising edge and the second rising edge.
- the state of the output signal of the delay unit may be wrong due to signal interference or delay unit failure, etc. (for example, the state of the output signal of a delay unit should be 1, but the latch unit 14 records The state of the output signal of the delay unit is 0), which may cause an error in the calculation of the position of the first rising edge and/or the second rising edge.
- the processing circuit 62 When the positions of the first rising edge and the second rising edge are detected, the processing circuit 62 The number of delay units through which the first rising edge and the second rising edge propagate in one clock cycle can be separately calculated, thereby determining the respective receiving times of the first rising edge and the second rising edge, and determining the received receiving time. Take the average as the final result of the reception time of the rising edge of the signal to be tested.
- the embodiment of the present invention does not specifically limit the form of the processing circuit.
- it may be implemented by using lut, or may be implemented by other types of logic circuits in the chip.
- the time measurement chip 60 may further include: a conversion circuit 64.
- the conversion circuit 64 can be coupled to the circuit 10, which can be configured to convert the analog signal to a signal under test in the form of a pulse and to transmit the signal to be tested to the signal input 16 of the circuit 10.
- Embodiments of the present invention also provide a LiDAR system.
- the LiDAR system 70 can include a transmitter 72, a receiver 74, and a time measurement chip 60 as shown in FIG.
- Transmitter 72 can be configured to emit a laser signal.
- the receiver 74 can be configured to receive a reflected signal corresponding to the laser signal, the reflected signal being an analog signal.
- the conversion circuit 64 of the time measurement chip 60 can be coupled to the receiver 74 and configured to receive an analog signal from the receiver 74.
- Embodiments of the present invention also provide an automated device, such as a removable device.
- the automation device 80 can include a LiDAR system 70 as shown in FIG. Further, the automation device 80 can also include a housing for carrying the LiDAR system.
- the automation device 80 can be, for example, a drone, an unmanned vehicle or a robot (such as a walking robot).
- FIG. 9 is a schematic flowchart of a method for measuring time according to an embodiment of the present invention.
- the method of Figure 9 can be performed by the circuit 10 for measuring time above.
- the method of FIG. 9 may include steps 910-950, which are described in detail below.
- the delay chain includes n delay units, and the n delay units are all connected to the latch unit, and the signal The input end is also connected to the input end of the logic control unit, and the output end of the logic control unit is connected to the kth delay unit of the delay chain, wherein k and n are positive integers, n>2, 1 ⁇ k ⁇ n;
- the element passes a second rising edge to the kth delay unit to sequentially pass the second rising edge from the kth delay unit to the nth delay unit through the delay chain, wherein the second rising edge is a logic control unit The rising edge of the received signal to be tested;
- the output signals of the n delay units are latched by the latch unit.
- the input of the logic control unit is further connected to the tth delay unit in the nth delay unit, where t is a positive integer, and 1 ⁇ t ⁇ k; step 930 can The method includes: transmitting a low level signal to the kth delay unit through the logic control unit in response to the first rising edge being passed to the tth delay unit.
- the logic control unit may include an exclusive OR unit and or a unit.
- the input of the exclusive OR unit is connected to the signal input terminal and the tth delay unit.
- the input of the unit is connected to the output of the XOR unit and the (k-1)th delay unit of the delay chain, or the output of the unit is connected to the kth delay unit.
- the configuration of n is such that the signal to be tested passes through the delay chain for no less than 2 clock cycles.
- the circuitry for measuring time may be integrated in an FPGA chip or ASIC chip.
- the delay unit in the delay chain includes at least one of a carry chain and a lookup table.
- the delay elements in the delay chain are located in the same slice or different slices of the FPGA.
- the computer program product includes one or more computer instructions.
- the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
- the computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be from a website site, computer, server or data center By cable (for example, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (eg infrared, wireless, microwave, etc.) to another website site, computer, server or data center.
- cable for example, coaxial cable, optical fiber, digital subscriber line (DSL)
- wireless eg infrared, wireless, microwave, etc.
- the computer readable storage medium can be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that includes one or more available media.
- the usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a digital video disc (DVD)), or a semiconductor medium (such as a solid state disk (SSD)).
- a magnetic medium for example, a floppy disk, a hard disk, a magnetic tape
- an optical medium such as a digital video disc (DVD)
- a semiconductor medium such as a solid state disk (SSD)
- the disclosed systems, devices, and methods may be implemented in other manners.
- the device embodiments described above are merely illustrative.
- the division of the unit is only a logical function division.
- there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
- the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
- the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
- each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
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Abstract
Description
Claims (17)
- 一种用于测量时间的电路,其特征在于,所述电路包括:信号输入端,用于接收待测信号;延时链,所述延时链包括n个延时单元,且所述延时链的第1个延时单元与所述信号输入端相连,以从所述信号输入端接收所述待测信号,所述延时链被配置成响应于所述第1个延时单元接收到所述待测信号,将第一上升沿从所述第1个延时单元顺序传递至所述延时链的第n个延时单元,其中所述第一上升沿为所述第1延时单元接收到的所述待测信号的上升沿,其中n为大于2的正整数;逻辑控制单元,所述逻辑控制单元的输入端与所述信号输入端相连,以从所述信号输入端接收所述待测信号,所述逻辑控制单元的输出端与所述延时链的第k个延时单元相连,所述逻辑控制单元被配置成响应于所述逻辑控制单元的输入端接收到所述待测信号,向所述第k个延时单元传递第二上升沿,以将所述第二上升沿从所述第k个延时单元顺序传递至所述第n个延时单元,所述逻辑控制单元还被配置成在向所述第k个延时单元传递所述第二上升沿之后,并在所述第一上升沿传递至所述第k个延时单元之前,向所述第k个延时单元发送低电平信号,以将所述低电平信号从所述第k个延时单元顺序传递至所述第n个延时单元,其中所述第二上升沿为所述逻辑控制单元接收到的所述待测信号的上升沿,k为正整数,且1<k<n;锁存单元,与所述n个延时单元相连,用于锁存所述n个延时单元的输出信号。
- 如权利要求1所述的电路,其特征在于,所述逻辑控制单元的输入端还与所述第n个延时单元中的第t个延时单元相连,其中t为正整数,且1<t<k;所述逻辑控制单元被配置成响应于所述第一上升沿传递至所述第t个延时单元,向所述第k个延时单元发送所述低电平信号。
- 如权利要求2所述的电路,其特征在于,所述逻辑控制单元包括:异或单元,所述异或单元的输入端与所述信号输入端以及所述第t个延时单元相连;或单元,所述或单元的输入端与所述异或单元的输出端以及所述延时链的第(k-1)个延时单元相连,所述或单元的输出端与所述第k个延时单元相连。
- 如权利要求1-3中任一项所述的电路,其特征在于,n的配置使得所述待测信号经过所述延时链的时间不小于2个时钟周期。
- 如权利要求1-4中任一项所述的电路,其特征在于,所述电路集成在现场可编程门阵列FPGA芯片或专用集成电路ASIC芯片中。
- 如权利要求5所述的电路,其特征在于,所述电路集成在FPGA芯片中,所述延时链中的延时单元包括进位链和查找表中的至少一种。
- 如权利要求5或6所述的电路,其特征在于,所述电路集成在FPGA芯片中,所述延时链中的延时单元位于所述FPGA芯片的同一slice或不同slice中。
- 一种时间测量芯片,其特征在于,所述时间测量芯片包括:如权利要求1-7中任一项所述的用于测量时间的电路;处理电路,与所述用于测量时间的电路中的锁存单元相连,所述处理电路被配置成根据所述锁存单元中存储的所述n个延时单元的输出信号,确定所述信号输入端接收到所述待测信号的时间。
- 如权利要求8所述的时间测量芯片,其特征在于,所述时间测量芯片还包括:转换电路,所述转换电路与所述用于测量时间的电路相连,所述转换电路被配置成将模拟信号转换成脉冲形式的所述待测信号,并向所述用于测量时间的电路的信号输入端发送所述待测信号。
- 一种激光探测与测量***,其特征在于,包括:发射器,被配置成发射激光信号;接收器,被配置成接收所述激光信号对应的反射信号,所述反射信号为模拟信号;如权利要求9所述的时间测量芯片,所述时间测量芯片的转换电路与所述接收器相连,被配置成从所述接收器接收所述模拟信号。
- 一种自动化设备,其特征在于,包括如权利要求10所述的激光探测与测量***。
- 一种用于测量时间的方法,其特征在于,所述方法包括:通过信号输入端接收待测信号,所述信号输入端与延时链的第1个延时单元相连,所述延时链包括n个延时单元,所述n个延时单元均与锁存单元相连,所述信号输入端还与逻辑控制单元的输入端相连,所述逻辑控制单元 的输出端与所述延时链的第k个延时单元相连,其中k和n均为正整数,n>2,1<k<n;响应于所述第1个延时单元接收到所述待测信号,通过所述延时链将第一上升沿从所述第1个延时单元顺序传递至所述延时链的第n个延时单元,所述第一上升沿为所述第1延时单元接收到的所述待测信号的上升沿;响应于所述逻辑控制单元的输入端接收到所述待测信号,通过所述逻辑控制单元向所述第k个延时单元传递第二上升沿,以通过所述延时链将所述第二上升沿从所述第k个延时单元顺序传递至所述第n个延时单元,其中所述第二上升沿为所述逻辑控制单元接收到的所述待测信号的上升沿;在向所述第k个延时单元传递所述第二上升沿之后,并在所述第一上升沿传递至所述第k个延时单元之前,通过所述逻辑控制单元向所述第k个延时单元发送低电平信号,以将所述低电平信号从所述第k个延时单元顺序传递至所述第n个延时单元;通过所述锁存单元锁存所述n个延时单元的输出信号。
- 如权利要求12所述的方法,其特征在于,所述逻辑控制单元的输入端还与所述第n个延时单元中的第t个延时单元相连,其中t为正整数,且1<t<k;所述响应于所述逻辑控制单元的输入端接收到所述待测信号,通过所述逻辑控制单元向所述第k个延时单元传递第二上升沿,包括:响应于所述第一上升沿传递至所述第t个延时单元,通过所述逻辑控制单元向所述第k个延时单元发送所述低电平信号。
- 如权利要求13所述的方法,其特征在于,所述逻辑控制单元包括:异或单元,所述异或单元的输入端与所述信号输入端以及所述第t个延时单元相连;或单元,所述或单元的输入端与所述异或单元的输出端以及所述延时链的第(k-1)个延时单元相连,所述或单元的输出端与所述第k个延时单元相连。
- 如权利要求12-14中任一项所述的方法,其特征在于,n的配置使得所述待测信号经过所述延时链的时间不小于2个时钟周期。
- 如权利要求12-15中任一项所述的方法,其特征在于,所述延时链中的延时单元包括进位链和查找表中的至少一种。
- 如权利要求16所述的方法,其特征在于,所述延时链中的延时单 元位于同一slice或不同slice中。
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EP17916318.3A EP3647884B1 (en) | 2017-06-30 | 2017-06-30 | Circuit, method and related chip for time measurement, system, and device |
JP2019568365A JP6903849B2 (ja) | 2017-06-30 | 2017-06-30 | 時間測定回路、時間測定チップ、レーザー検出・測距システム、自動化装置、および時間測定方法 |
CN201780004389.9A CN108401445B (zh) | 2017-06-30 | 2017-06-30 | 用于测量时间的电路、方法及相关芯片、***和设备 |
PCT/CN2017/091048 WO2019000373A1 (zh) | 2017-06-30 | 2017-06-30 | 用于测量时间的电路、方法及相关芯片、***和设备 |
US16/721,438 US20200124709A1 (en) | 2017-06-30 | 2019-12-19 | Circuit, method and related chip for time measurement, system, and device |
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CN112506031B (zh) * | 2020-11-30 | 2021-09-21 | 中国计量科学研究院 | 一种激光干涉条纹信号的高精度时间间隔测量*** |
CN114637182B (zh) * | 2020-12-15 | 2023-12-01 | 武汉万集光电技术有限公司 | 基于fpga进位链的tdc细时间测量***及方法 |
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CN114779607B (zh) * | 2021-05-10 | 2023-11-28 | 深圳阜时科技有限公司 | 时间测量电路、时间测量方法、时间测量芯片、时间测量模组和电子设备 |
CN113325387A (zh) * | 2021-05-17 | 2021-08-31 | 武汉光迹融微科技有限公司 | 一种抗多激光雷达信号干扰的激光签名方法及装置 |
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CN108401445A (zh) | 2018-08-14 |
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EP3647884A4 (en) | 2021-01-27 |
JP6903849B2 (ja) | 2021-07-14 |
CN108401445B (zh) | 2021-11-19 |
EP3647884B1 (en) | 2022-04-13 |
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