WO2018228543A1 - Stretchable crystalline semiconductor nanowire and preparation method thereof - Google Patents

Stretchable crystalline semiconductor nanowire and preparation method thereof Download PDF

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WO2018228543A1
WO2018228543A1 PCT/CN2018/091544 CN2018091544W WO2018228543A1 WO 2018228543 A1 WO2018228543 A1 WO 2018228543A1 CN 2018091544 W CN2018091544 W CN 2018091544W WO 2018228543 A1 WO2018228543 A1 WO 2018228543A1
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nanowire
stretchable
crystalline semiconductor
crystalline
silicon
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PCT/CN2018/091544
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French (fr)
Chinese (zh)
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余林蔚
薛兆国
董泰阁
王军转
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南京大学
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Priority claimed from CN201710450420.3A external-priority patent/CN107460542A/en
Application filed by 南京大学 filed Critical 南京大学
Priority to EP18817489.0A priority Critical patent/EP3640374A4/en
Publication of WO2018228543A1 publication Critical patent/WO2018228543A1/en
Priority to US16/714,724 priority patent/US20200118818A1/en

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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/60—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape characterised by shape

Definitions

  • the present invention relates to the field of flexible stretchable electrons and devices, and relates to a method for fabricating a spring-structured crystalline nanowire having flexibility and stretchability by a micromachining process using a channel-guided planar nanowire growth technique on a substrate .
  • a method of channel-guided self-aligned self-aligned growth, transfer, and electrically integrated planar semiconductor nanowires prepared by a spring-structured crystalline nanowire.
  • Liquid-liquid-solid phase (SLS) growth mechanism The mechanism of SLS growth is similar to the VLS mechanism. The difference from the VLS mechanism is that during the growth of the VLS mechanism, the required raw materials are supplied by the gas phase; In the process, the required raw materials are supplied from the solution. Generally, a low melting point metal (such as In, Sn or Bi, etc.) is commonly used as a fluxdroplet in this method, which is equivalent to a catalyst in the VLS mechanism.
  • a low melting point metal such as In, Sn or Bi, etc.
  • Silicon-based materials are based on a wide range of industrial bases, mature processes and semiconductor fabrication techniques, and because of the similar properties of carbon-based materials in human structures, which are harmless to the human body, and nano-scale silicon materials are easily degraded, and silicon-based nanotechnology and flexible kola The combination of the field of electronics will bring great utility.
  • an object of the present invention is to provide a stretchable crystalline semiconductor nanowire and a method of preparing the same.
  • planar semiconductor nanowire devices are fabricated by directional growth, transfer, and integration methods along specific guiding channels.
  • the invention provides a stretchable crystalline semiconductor nanowire:
  • the stretchable crystalline semiconductor nanowires have an elongated body with a diameter between 20 and 200 nanometers, and the nanowires are crystalline inorganic semiconductor structures.
  • the stretchable crystalline semiconductor nanowire is a curved structure having a plurality of stretchable cells in an axial direction, the plurality of stretchable cells being sequentially connected to form a stretchable crystalline semiconductor nanowire.
  • the stretchable unit of the stretchable crystalline semiconductor nanowire is one or a combination of a circular arc shape, a semicircular shape, a half racetrack shape, a Z shape, a V shape, and an M shape.
  • the length in the maximum stretched state is greater than 1.5 times the length in the natural state, preferably 2 times or more, preferably 2.7 times.
  • crystalline nanowires are grown, the nanowires being single crystal nanowires such as Si, SiGe, Ge or GaAs.
  • the present invention provides a method of preparing a stretchable crystalline semiconductor nanowire, comprising the steps of:
  • the crystal nanowires are accurately grown along the guiding channel, and a deposition catalytic metal film block is vapor deposited at one end of the guiding channel as an initial point of formation of the metal droplets and the nanowire Starting position
  • the silicon wafer is a P-type or N-type single crystal or a polycrystalline silicon wafer whose surface is covered with a dielectric layer such as silicon dioxide or silicon nitride, and the glass is ordinary glass or quartz glass, and the polymer can withstand a certain high temperature. (>350 ° C) treatment, a flexible polymer compatible with a vacuum environment; the silica substrate thickness is greater than 250 nm.
  • step 5) comprises: again using a PECVD system to cover an amorphous semiconductor layer of a suitable thickness (several nanometers to hundreds of nanometers) as a precursor dielectric layer; for growing crystalline silicon, crystalline germanium or crystalline germanium silicon alloy nanometers
  • amorphous silicon, amorphous germanium and amorphous germanium silicon layers are used as precursors, and for other semiconductor materials, corresponding amorphous material thin films are used as precursors.
  • step 7) is further included: preparing the electrode by photolithography and evaporation techniques.
  • the method further includes the following steps:
  • Step 8) detaching the nanowire and the substrate by etching the liquid
  • Step 9) Transfer the detached spring nanowire array onto a flexible substrate, which may be any substrate having tensile properties.
  • the substrate used for growth may be a P-type or N-type single crystal silicon substrate having a silicon dioxide layer on the surface; a P-type or N-type polycrystalline silicon wafer having a silicon dioxide layer on the surface; or a common glass, quartz glass, or the like.
  • Amorphous substrate may be a P-type or N-type single crystal silicon substrate having a silicon dioxide layer on the surface; a P-type or N-type polycrystalline silicon wafer having a silicon dioxide layer on the surface; or a common glass, quartz glass, or the like.
  • the guiding channel is formed by a photolithography etching method; wherein the etching method is wet etching: an alkaline etching system such as potassium hydroxide (KOH) or sodium hydroxide (NaOH), or hydrofluoric acid + nitric acid (HF) +HNO3), hydrofluoric acid + nitric acid + acetic acid (HF + HNO3 + CH3COOH) and other acidic corrosion systems, may also be Ethylene Diamine Pyrocatechol (Ethylene Diamine Pyrocatechol) and other systems; or dry etching, that is, using ICP- The RIE is etched.
  • an alkaline etching system such as potassium hydroxide (KOH) or sodium hydroxide (NaOH), or hydrofluoric acid + nitric acid (HF) +HNO3), hydrofluoric acid + nitric acid + acetic acid (HF + HNO3 + CH3COOH) and other acidic corrosion systems, may also be Ethy
  • the metal electrode uses a PT (12 nm)-AL (80 nm) system, which may be a Ti-Au system, which is a Ni metal, and the metal contact uses a rapid thermal annealing process to improve contact performance.
  • a thermal evaporation system, a magnetron sputtering system, or an electron beam evaporation system can be used.
  • the surface of the substrate is etched by the etching liquid so that the spring structure crystal nanowires are separated from the substrate to facilitate the transfer.
  • Crystal nanowires are flexible, high performance devices with high stretchability.
  • the invention adopts the method of IP-SLS and the like to grow the channel-guided nanowires in PECVD, and uses the modern micromachining technology to fabricate the spring structure crystal nanowire array.
  • the IP-SLS method can grow planar nanowires, and combines step-channel guiding technology to grow high-quality, specific-shaped planar semiconductor single crystal nanowire arrays.
  • the self-localization and self-orientation of the nanowire growth can be achieved by the guiding channel formed by the photolithography technique and the positioned catalyst region. Since such nanowires and the guiding channel section can be effectively adjusted, peeling (such as etching peeling) and transfer onto other flexible substrates can be further performed. Since the nanowire array has electrode connections at both ends, the integration and use of the device can be facilitated.
  • the method for preparing the spring structure crystal nanowire of the invention has broad prospects in the field of flexible electronics and sensors.
  • the present invention utilizes the characteristics of planar nanowires for guiding growth for the first time, and the results show a super-flexible nanowire channel linear design and a stretchable crystalline semiconductor nanowire structure.
  • crystalline silicon as an example, crystalline silicon itself is not stretchable or brittle, and crystalline silicon film cannot be directly applied to stretchable electronic devices.
  • the existing mature crystalline silicon semiconductor technology process can be extended to the emerging flexible electronic application field, and a key technical basis for greatly improving the device characteristics and stability of the flexible electronic device is provided.
  • 1 is a flow chart of a process for preparing a spring structure crystal nanowire
  • FIG. 2 is a schematic diagram of a spring structure crystal nanowire array design
  • FIG. 2 is a schematic diagram of a spring structure crystal nanowire array design, wherein a blue (dark) region is a catalyst region (a)(b)(c)(d) respectively Four different spring-shaped curves;
  • Figure 3 is a SEM topography of a spring-structured crystal nanowire; in Figure 3, a spring-structured crystalline nanowire SEM topography, (a)(b)(c)(d) respectively represent four different ratios.
  • Figure 4 is a graph showing the electrical properties of a crystalline structured crystalline silicon nanowire.
  • FIG. 5(a) and (b) are examples of in-situ SEM mechanical stretching and synchronous electrical tests of a stretchable silicon nanowire, and FIG. 5(c) is a synchronous potential test result diagram; FIG. 5(d) and (e) A SEM image of a process in which the stretchable silicon nanowires are stretched to an elastic deformation limit of 270% and can be fully recovered.
  • the present invention provides a stretchable crystalline semiconductor nanowire having an elongated body.
  • the stretchable crystalline semiconductor nanowire is a curved structure having a plurality of stretchable cells in an axial direction, the plurality of stretchable cells being sequentially connected to form a stretchable crystalline semiconductor nanowire.
  • the nanowires are between 20 and 200 nanometers in diameter, and the nanowires are crystalline inorganic semiconductor structures.
  • FIG. 2 a schematic diagram of a crystal nanowire array design in which a blue (dark) region is a catalyst region (a), and (b) and (c) (d) respectively represent four different spring-shaped curves;
  • the nanowire is a curved structure having a plurality of interconnected stretchable units in an axial direction, and the stretchable unit is one or more of a circular arc shape, a semicircular shape, and a half racetrack shape.
  • the stretchable unit of the stretchable crystalline semiconductor nanowire is a circular arc shape, a semicircular shape, a half racetrack shape, or may be a Z shape, a V shape, an M shape (not shown), or one of them. Or a variety of combinations.
  • the length in the maximum stretched state is greater than 1.5 times the length in the natural state, preferably 2 times or more, preferably 2.7 times.
  • crystalline nanowires are grown, the nanowires being single crystal nanowires such as Si, SiGe, Ge or GaAs.
  • the substrate used for growth may be a P-type or N-type single crystal silicon substrate having a silicon dioxide layer on the surface; a P-type or N-type polycrystalline silicon wafer having a silicon dioxide layer on the surface; or a common glass, quartz glass, or the like.
  • Amorphous substrate may be a P-type or N-type single crystal silicon substrate having a silicon dioxide layer on the surface; a P-type or N-type polycrystalline silicon wafer having a silicon dioxide layer on the surface; or a common glass, quartz glass, or the like.
  • Fig. 3 is a SEM topographical view of a spring-structured crystal nanowire, an actual prepared SEM topography of a crystal structure crystal nanowire, (a) (b) a stretchable unit having a circular arc structure, and (c) (d) The stretching unit is a half-track structure. (a) (b)(c)(d) represent four different ratios, respectively.
  • Figure 4 is a graph showing the electrical properties of the prepared spring structured crystalline silicon nanowires.
  • Fig. 5(a)(b) in an in-situ scanning electron microscope, one of the silicon nanowires is mechanically stretched and subjected to synchronous electrical testing under the operation of a mechanical probe.
  • the test results are shown in Fig. 5(c), indicating that the electrical properties are stable during the tensile elastic deformation of the silicon nanowires.
  • the silicon nanowires can be mechanically stretched to the limit, and the length in the maximum tensile state is greater than 270% of the length in the natural state, and remains elastically deformed, after release. , can restore the original shape.
  • the present invention provides a method for preparing a stretchable crystalline semiconductor nanowire based on planar nanowire linear design and guiding, and the characteristic steps include:
  • the line shape of the guiding step can be freely designed and defined conveniently; in order to realize a stretchable flexible crystalline semiconductor channel
  • the structure is designed such that the step line is designed as a non-linear curved spring or a zigzag serpentine channel array, and a spring-shaped guiding channel having a depth of about 150 ⁇ 10 nm (not exceeding 350 nm) is formed on the substrate by photolithography etching.
  • crystal nanowires having a diameter of about 120 ⁇ 10 nm are accurately grown along the guiding channel to form a nanowire spring array; that is, by lithography lift-off or mask technology, Depositing a deposited catalytic metal film block at one end of the guiding channel as an initial point of formation of the metal droplets and a starting position of the nanowire;
  • a stretchable nanowire spring By transferring the detached spring nanowire array onto a flexible substrate, a stretchable nanowire spring can be fabricated, which can be widely used in the field of flexible electronics.
  • the flexible nanowire spring or related structure can be transferred to a flexible stretchable polymer substrate (a film is spin coated through the surface of the sample and transferred to the sacrificial layer for corrosion transfer, and directly manipulated using a nanomanipulator).
  • the substrate may be a silicon wafer, a glass, a ceramic sheet, and a polymer substrate resistant to high temperatures up to 350 °C.
  • the silicon dioxide substrate is a conventional silicon dioxide substrate having a thickness greater than 250 nm.
  • the silicon wafer may also be a P-type or N-type single crystal or a polycrystalline silicon wafer whose surface is covered with a dielectric layer such as silicon dioxide or silicon nitride, the glass is ordinary glass or quartz glass, and the polymer can withstand a certain high temperature (>350 ° C).
  • Handle a flexible polymer that is compatible with the vacuum environment.
  • step 3 the photocatalyst region is again used at the position of the channel using a photolithography alignment technique, and the crystal nanowire having a diameter of about 130 ⁇ 10 nm is accurately guided along the guide by a planar nanowire guided growth method.
  • Channel growth forming a spring-shaped nanowire; vapor deposition of In, Sn metal, forming a metal film pattern of several tens of nanometers at a specific position of the guiding channel; using plasma processing technology in a PECVD system at 350 ° C, power 2 At 5W, the metal film is condensed to form quasi-nano-catalytic particles with a diameter of several hundred nanometers to several micrometers; again, a PECVD system is used to cover a layer of amorphous silicon (a few nanometers to several hundred nanometers) of appropriate thickness.
  • the crystalline silicon is used as a precursor dielectric layer; it is annealed in a vacuum atmosphere at 350 ° C, and the nanowires are grown from the catalyst region along the guiding channel by using an IP-SLS growth mode to form and obtain a spring-structured nanowire.
  • the catalytic metal may be a low melting point metal indium, tin, gallium, lead, antimony or the like, and alloys and oxide materials thereof, and with the grown crystalline nanowire material. Matching precious metals such as gold, silver and copper.
  • the characteristic step in the step (2) comprises: firstly, using a photolithography technique to define a guiding step line shape of the planar nanowire in the photoresist layer, and then using a reactive plasma (RIE) or an inductive plasma (ICP) etching technique. Etching the pattern down into the substrate with an etch depth ranging from a few to a few hundred nanometers;
  • RIE reactive plasma
  • ICP inductive plasma
  • the guiding channel is formed by a photolithography etching method; wherein the etching method is wet etching: an alkaline etching system such as potassium hydroxide (KOH) or sodium hydroxide (NaOH), or hydrogen.
  • an alkaline etching system such as potassium hydroxide (KOH) or sodium hydroxide (NaOH), or hydrogen.
  • Acidic corrosion system such as hydrofluoric acid + nitric acid (HF + HNO3), hydrofluoric acid + nitric acid + acetic acid (HF + HNO3 + CH3COOH), or Ethylene Diamine Pyrocatechol; or dry engraving Etching, that is, etching by ICP-RIE.
  • the spring-shaped crystalline nanowires are grown, and the nanowires are crystalline materials such as Si, Ge, SiGe, GaAs, and the like.
  • the crystal nanowires have a diameter of 20-180 nm using any shape structure having tensile properties.
  • the characteristic step in the step (3) comprises: using a photolithography or mask technology, using a metal catalyst layer by thermal evaporation, magnetron sputtering, electron beam sputtering, pulsed laser sputtering, and atomic layer deposition.
  • a thin film of a catalytic metal layer such as indium or tin is deposited to form a metal film region of several micrometers, and intersects the guiding step at a specific starting position of the guiding channel.
  • the step (4) comprises: using a plasma treatment technology in a PECVD system, processing in a range of 200 ° C to 450 ° C, and a power of 0.2-100 watts, so that the metal film shrinks into a diameter of several tens of nanometers. Nanocatalytic particles up to several microns;
  • the characteristic step in the step (5) comprises: using a PECVD system to cover a layer of an amorphous semiconductor layer of a suitable thickness (several nanometers to several hundreds of nanometers) as a precursor dielectric layer.
  • a PECVD system for the growth of crystalline silicon, crystalline germanium or crystalline germanium-silicon alloy nanowires, amorphous silicon, amorphous germanium and amorphous germanium silicon layers are used as precursors.
  • a corresponding amorphous material film is used as a precursor.
  • the growth temperature of the planar nanowires is selected to be between 300 ° C and 600 ° C.
  • the nanowire growth process can be carried out under inert gas, reducing gas or vacuum conditions.
  • the planar shape of the grown planar nanowire is controlled by the edge of the guiding step, and a non-linear curved spring or a zigzag serpentine channel of a programmable design, and a fractal curved two-dimensional distributed structure of single-line communication can be obtained. Thereby achieving a stretchable crystalline silicon semiconductor nanowire channel.
  • a method of fabricating a crystalline semiconductor (including silicon, germanium, etc.) stretchable electronic device is accomplished based on planar nanowire-based linear design and guided growth techniques.
  • a crystalline semiconductor material utilizes a metal (indium, tin, gallium, antimony, etc.) catalytic particles to absorb an amorphous film, and a corresponding planar crystal state (single substance or alloy) is grown during the step of guiding the step movement.
  • Nanowire structure Since the guiding step can be freely programmed, a line-shape fully controllable, regular crystalline nanowire array can be customized to prepare a crystalline semiconductor nanowire structure having super-stretchability.
  • This technology can realize nano-channels of crystalline semiconductor materials such as crystalline silicon with high stretchability, and maintain excellent electrical modulation and device stability characteristics of crystalline semiconductor materials, so that high-performance flexible semiconductor electronic applications can be realized (for example, Stretching logic transistors, display control and drive devices, sensing and artificial skin and other emerging fields).
  • a technique for growth and transfer of a crystal nanowire of a spring structure It is a method of directional growth and transfer under a specific channel, and the steps are as follows:
  • the crystal substrate covering the oxide layer is treated by ultrasonic acid solution or ultrasonic treatment with acetone, alcohol and deionized water respectively to remove impurities adhering to the surface and expose the crystal clean surface.
  • the PECVD system is again used to cover a layer of amorphous silicon (a few nanometers to several hundred nanometers) of amorphous silicon as a precursor dielectric layer.
  • the electrodes are placed on both ends of the nanowire spring array.
  • the flexible nanowire spring or related structure can be transferred to a flexible stretchable polymer substrate (a film is spin coated through the surface of the sample and transferred to the sacrificial layer for corrosion transfer, and directly manipulated using a nanomanipulator).
  • a guiding channel having a depth of about 200 nm and a guiding channel of the spring structure are formed by photolithography etching, wherein the spring structure can be any curved shape having a stretchable property, between nodes and nodes The distance can be from 200 nm to 50 um.
  • the etching method of the channel can be wet etched: alkaline system such as potassium hydroxide (KOH) or sodium hydroxide (NaOH), or hydrofluoric acid + nitric acid (HF + HNO3), hydrofluoric acid + nitric acid +
  • alkaline system such as potassium hydroxide (KOH) or sodium hydroxide (NaOH), or hydrofluoric acid + nitric acid (HF + HNO3), hydrofluoric acid + nitric acid +
  • An acidic system such as acetic acid (HF+HNO3+CH3COOH) may be a system such as Ethylene Diamine Pyrocatechol or a dry etching system and etched by ICP-RIE.
  • the etching liquid used in the transferring step may be any liquid which can corrode the silica and slowly or not corrode the crystal nanowires.
  • the flexible substrate used for the transfer may be any substrate having tensile properties.
  • planarly grown nanowires may be planar single crystal nanowire arrays of Si, SiGe, Ge, GaAs, etc., and have a diameter distribution between 20 and 200 nm.
  • the metal electrode is fabricated by photolithography, and a thermal evaporation system, an electron beam evaporation system, a magnetron sputtering system, or the like can be used.
  • the metal electrode is contacted with a PT (12 nm)-AL (80 nm) system, which may be Ti-
  • the Au system which may be Ni metal, uses a rapid thermal annealing process to improve contact performance.
  • a more specific real-time example the preparation of a spring-structured crystalline nanowire on a 300 nm SiO 2 oxide layer substrate, including the following steps:
  • the silicon wafer can be a pure single crystal or polycrystalline silicon wafer.
  • a spring structure pattern is defined on the surface of the substrate by mask lithography, a channel is formed on the surface by ICP-RIE etching, and an array of bioprobe channels is formed after cleaning the photoresist.
  • a PECVD system plasma processing technology is used to form nano-catalytic particles having a diameter of several hundred nanometers to several micrometers at a power of 1-50 W; at a temperature of 350 ° C, nanometers having a diameter of several hundred nanometers are formed. Catalytic particles.
  • the catalytic droplets can be activated to absorb the surrounding amorphous silicon, thereby inducing the growth of planar silicon nanowires, while the nanowires will follow the guiding grooves.
  • the sidewalls are oriented to grow to form the desired channel.

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Abstract

A stretchable crystalline semiconductor nanowire and a preparation method thereof are provided. The stretchable crystalline semiconductor nanowire has a long and thin main body, a diameter of the nanowire is between 20 to 200 nm, and the nanowire has a crystalline inorganic semiconductor structure. The stretchable crystalline semiconductor nanowire has a bending structure having a plurality of stretchable units disposed along an axial direction, and the stretchable units are connected sequentially to form the stretchable crystalline semiconductor nanowire. A channel step-guided nanowire is grown by PECVD adopting a method such as IP-SLS, and a crystalline nanowire array having a spring structure is manufactured using modern micromachining technology. Since the nanowire and the guided channel cross-section can be effectively adjusted, stripping and transferring onto other flexible substrates can be further performed. The method of preparing a crystalline nanowire having a spring structure has broad prospects in applications related to the fields of flexible electronics and sensors.

Description

一种可拉伸晶体半导体纳米线及其制备方法Stretchable crystalline semiconductor nanowire and preparation method thereof 技术领域Technical field
本发明涉及柔性可拉伸电子和器件领域，涉及在衬底上利用沟道引导平面纳米线生长技术，通过微加工工艺，制作形成具有柔性和可拉伸性质的弹簧结构晶体纳米线的制作方法。尤其是沟道引导自定位自定向生长、转移、电学集成的平面半导体纳米线制备的弹簧结构晶体纳米线的方法。The present invention relates to the field of flexible stretchable electrons and devices, and relates to a method for fabricating a spring-structured crystalline nanowire having flexibility and stretchability by a micromachining process using a channel-guided planar nanowire growth technique on a substrate . In particular, a method of channel-guided self-aligned self-aligned growth, transfer, and electrically integrated planar semiconductor nanowires prepared by a spring-structured crystalline nanowire.
背景技术Background technique
随着当代电子显示产业的发展，柔性和可拉伸电子器件(尤其是显示器件)因为更易满足实际应用需求以及本身灵活的材料特性，在现代科技、国民经济和日常生活中的方方面面扮演着越来越重要的角色，在该研究领域里，材料的生长制备技术有着重要的地位。With the development of the modern electronic display industry, flexible and stretchable electronic devices (especially display devices) play a role in modern technology, national economy and daily life because they are more suitable for practical applications and flexible material properties. The more important role, the growth and preparation technology of materials plays an important role in this research field.
液-液相-固相(SLS)生长机制：SLS生长的机理类似于VLS机制，与VLS机制的区别仅在于，在VLS机制生长过程中，所需的原材料由气相提供；而在SLS机制生长过程中，所需的原料是从溶液中提供的，一般来说，此方法中常用低熔点金属(如In、Sn或Bi等)作为助溶剂(fluxdroplet)，相当于VLS机制中的催化剂。Liquid-liquid-solid phase (SLS) growth mechanism: The mechanism of SLS growth is similar to the VLS mechanism. The difference from the VLS mechanism is that during the growth of the VLS mechanism, the required raw materials are supplied by the gas phase; In the process, the required raw materials are supplied from the solution. Generally, a low melting point metal (such as In, Sn or Bi, etc.) is commonly used as a fluxdroplet in this method, which is equivalent to a catalyst in the VLS mechanism.
硅基材料因为广泛的工业基础，成熟的工艺和半导体制备技术，又由于人体构造的碳基材料属性相似，对人体无害，且纳米级硅材料易降解，将硅基纳米科技和柔性可拉伸电子领域相结合，将取得巨大的效用。Silicon-based materials are based on a wide range of industrial bases, mature processes and semiconductor fabrication techniques, and because of the similar properties of carbon-based materials in human structures, which are harmless to the human body, and nano-scale silicon materials are easily degraded, and silicon-based nanotechnology and flexible kola The combination of the field of electronics will bring great utility.
技术问题technical problem
可拉伸晶体纳米线弹簧结构的材料的生长是柔性和可拉伸电子器件的基础，现有技术未有很好的方法去解决。The growth of materials for stretchable crystalline nanowire spring structures is the basis for flexible and stretchable electronic devices, and there is no good way to solve them in the prior art.
发明内容Summary of the invention
针对上述问题，本发明的目的是，提供一种可拉伸晶体半导体纳米线及其制备方法。尤其是沿特定引导沟道定向生长、转移和集成方法制备平面半导体纳米线器件。In view of the above problems, an object of the present invention is to provide a stretchable crystalline semiconductor nanowire and a method of preparing the same. In particular, planar semiconductor nanowire devices are fabricated by directional growth, transfer, and integration methods along specific guiding channels.
根据本发明的一个方面，本发明提供了一种可拉伸晶体半导体纳米线：According to one aspect of the invention, the invention provides a stretchable crystalline semiconductor nanowire:
所述可拉伸晶体半导体纳米线具有细长的主体，所述纳米线直径在20-200纳米之间，所述纳米线为为晶态无机半导体结构。The stretchable crystalline semiconductor nanowires have an elongated body with a diameter between 20 and 200 nanometers, and the nanowires are crystalline inorganic semiconductor structures.
所述可拉伸晶体半导体纳米线为弯曲结构，在轴向方向具有多个可拉伸单元，所述多个可拉伸单元依次连接，从而形成可拉伸晶体半导体纳米线。The stretchable crystalline semiconductor nanowire is a curved structure having a plurality of stretchable cells in an axial direction, the plurality of stretchable cells being sequentially connected to form a stretchable crystalline semiconductor nanowire.
进一步地，可拉伸晶体半导体纳米线的可拉伸单元为圆弧形、半圆形、半跑道形、Z形、 V形、M形中的一种或多种组合。Further, the stretchable unit of the stretchable crystalline semiconductor nanowire is one or a combination of a circular arc shape, a semicircular shape, a half racetrack shape, a Z shape, a V shape, and an M shape.
进一步地，其最大拉伸状态下的长度大于自然状态下长度的1.5倍，最好为2倍以上，优选为2.7倍。Further, the length in the maximum stretched state is greater than 1.5 times the length in the natural state, preferably 2 times or more, preferably 2.7 times.
在一个实施例中，生长出晶体纳米线，所述纳米线是Si,SiGe,Ge或GaAs等单晶纳米线。In one embodiment, crystalline nanowires are grown, the nanowires being single crystal nanowires such as Si, SiGe, Ge or GaAs.
根据本发明的又一个方面，本发明提供了可拉伸晶体半导体纳米线的制备方法，包括如下步骤：According to still another aspect of the present invention, the present invention provides a method of preparing a stretchable crystalline semiconductor nanowire, comprising the steps of:
1)采用包括玻璃、二氧化硅片或者硅片衬底，去除衬底表面残余；1) removing the residual surface of the substrate by using a substrate comprising glass, silicon dioxide or silicon;
2)在衬底表面刻蚀一定深度的台阶，进而沿台阶刻蚀制作特定的引导沟道；2) etching a step of a certain depth on the surface of the substrate, and then etching a specific guiding channel along the step etching;
3)通过平面纳米线引导生长方法，使晶体纳米线精确地沿着所述引导沟道生长，在引导沟道一端蒸镀淀积催化金属薄膜块，作为金属液滴的形成初始点和纳米线的起始位置；3) by a planar nanowire guided growth method, the crystal nanowires are accurately grown along the guiding channel, and a deposition catalytic metal film block is vapor deposited at one end of the guiding channel as an initial point of formation of the metal droplets and the nanowire Starting position
4)在PECVD***中利用包括氢气的还原性等离子体处理金属薄膜，去除表面的氧化层，并使之形成直径在几十纳米到一个微米之间的纳米金属催化颗粒；4) treating the metal thin film with a reducing plasma including hydrogen in a PECVD system, removing the oxide layer on the surface, and forming the nano metal catalytic particles having a diameter of several tens of nanometers to one micrometer;
5)淀积覆盖一层适当厚度的非晶半导体层作为前驱体介质；5) depositing an amorphous semiconductor layer covered with a suitable thickness as a precursor medium;
6)在真空中或者非氧化性气氛中退火生长，温度在250℃以上，使得金属液滴开始顺着引导台阶运动，吸收非晶层并沿途淀积出晶态的纳米线结构。6) Annealing in a vacuum or in a non-oxidizing atmosphere at a temperature above 250 ° C, so that the metal droplets begin to move along the guiding step, absorbing the amorphous layer and depositing a crystalline nanowire structure along the way.
进一步地，步骤1)中硅片为表面覆盖二氧化硅或者氮化硅等介质层的P型或者N型单晶或者多晶硅片，玻璃为普通玻璃或者石英玻璃，聚合物可为能承受一定高温(>350℃)处理，与真空环境相兼容的柔性聚合物；所述二氧化硅衬底厚度大于250nm。Further, in the step 1), the silicon wafer is a P-type or N-type single crystal or a polycrystalline silicon wafer whose surface is covered with a dielectric layer such as silicon dioxide or silicon nitride, and the glass is ordinary glass or quartz glass, and the polymer can withstand a certain high temperature. (>350 ° C) treatment, a flexible polymer compatible with a vacuum environment; the silica substrate thickness is greater than 250 nm.
进一步地，步骤5)包括：再次使用PECVD***覆盖一层适当厚度(几纳米到几百纳米)的非晶半导体层作为前驱体介质层；对于生长晶硅、晶锗或者晶态锗硅合金纳米线，相应采用非晶硅、非晶锗和非晶锗硅层作为前驱体；而对于其它半导体材料则采用相应的非晶材料薄膜作为前驱体。Further, step 5) comprises: again using a PECVD system to cover an amorphous semiconductor layer of a suitable thickness (several nanometers to hundreds of nanometers) as a precursor dielectric layer; for growing crystalline silicon, crystalline germanium or crystalline germanium silicon alloy nanometers For the line, amorphous silicon, amorphous germanium and amorphous germanium silicon layers are used as precursors, and for other semiconductor materials, corresponding amorphous material thin films are used as precursors.
在一个实施例中，还包括步骤7)：通过光刻和蒸镀技术制备电极。In one embodiment, step 7) is further included: preparing the electrode by photolithography and evaporation techniques.
在一个实施例中，还包括以下步骤：In one embodiment, the method further includes the following steps:
步骤8)通过刻蚀液体，使得纳米线和衬底脱离；Step 8) detaching the nanowire and the substrate by etching the liquid;
步骤9)把脱离的弹簧纳米线阵列转移到柔性衬底上，所使用的柔性衬底可以是任意具有拉伸性质的衬底。Step 9) Transfer the detached spring nanowire array onto a flexible substrate, which may be any substrate having tensile properties.
生长所用衬底可以是P型或者N型单晶硅衬底，表面有二氧化硅层；可以是P型或者N型多晶硅片，表面有二氧化硅层；也可以是普通玻璃，石英玻璃等非晶体衬底。The substrate used for growth may be a P-type or N-type single crystal silicon substrate having a silicon dioxide layer on the surface; a P-type or N-type polycrystalline silicon wafer having a silicon dioxide layer on the surface; or a common glass, quartz glass, or the like. Amorphous substrate.
通过光刻刻蚀方法制作引导沟道；其中刻蚀方法用湿法刻蚀：氢氧化钾(KOH)、氢氧化钠 (NaOH)等碱性腐蚀体系，也可以是氢氟酸+硝酸(HF+HNO3)、氢氟酸+硝酸+醋酸(HF+HNO3+CH3COOH)等酸性腐蚀体系，还可以是乙二胺邻苯二酚(EthyleneDiaminePyrocatechol)等体系；或者采用干法刻蚀，即利用ICP-RIE进行刻蚀。The guiding channel is formed by a photolithography etching method; wherein the etching method is wet etching: an alkaline etching system such as potassium hydroxide (KOH) or sodium hydroxide (NaOH), or hydrofluoric acid + nitric acid (HF) +HNO3), hydrofluoric acid + nitric acid + acetic acid (HF + HNO3 + CH3COOH) and other acidic corrosion systems, may also be Ethylene Diamine Pyrocatechol (Ethylene Diamine Pyrocatechol) and other systems; or dry etching, that is, using ICP- The RIE is etched.
金属电极使用PT(12nm)-AL(80nm)体系,可以是Ti-Au体系，是Ni金属，金属接触均使用快速热退火过程提高接触性能。可使用热蒸发***、磁控溅射***或者电子束蒸发***。The metal electrode uses a PT (12 nm)-AL (80 nm) system, which may be a Ti-Au system, which is a Ni metal, and the metal contact uses a rapid thermal annealing process to improve contact performance. A thermal evaporation system, a magnetron sputtering system, or an electron beam evaporation system can be used.
利用刻蚀液体腐蚀衬底表面，使得弹簧结构晶体纳米线与衬底脱离，方便完成转移。The surface of the substrate is etched by the etching liquid so that the spring structure crystal nanowires are separated from the substrate to facilitate the transfer.
弹簧结构晶体纳米线是具有高度可拉伸性的柔性高性能器件。Spring Structures Crystal nanowires are flexible, high performance devices with high stretchability.
本发明的有益效果Advantageous effects of the present invention
本发明采用IP-SLS等方法在PECVD中生长沟道台阶引导的纳米线，并利用现代微加工技术进行制作成弹簧结构晶体纳米线阵列。IP-SLS方法可以生长平面纳米线，结合台阶沟道引导技术就可以生长出高质量、特定形状的平面半导体单晶纳米线阵列。通过光刻蚀技术形成的引导沟道和定位的催化剂区域后就可实现纳米线生长的自定位、自定向。由于此类纳米线与引导沟道截面可以有效调节，可以进一步进行剥离(如腐蚀法剥离)和转移到其他柔性衬底之上。由于纳米线阵列两端有电极连接，可以方便的进行器件的集成和使用。本发明制备弹簧结构晶体纳米线的方法在柔性电子领域、传感器的应用方面有着广阔的前景。The invention adopts the method of IP-SLS and the like to grow the channel-guided nanowires in PECVD, and uses the modern micromachining technology to fabricate the spring structure crystal nanowire array. The IP-SLS method can grow planar nanowires, and combines step-channel guiding technology to grow high-quality, specific-shaped planar semiconductor single crystal nanowire arrays. The self-localization and self-orientation of the nanowire growth can be achieved by the guiding channel formed by the photolithography technique and the positioned catalyst region. Since such nanowires and the guiding channel section can be effectively adjusted, peeling (such as etching peeling) and transfer onto other flexible substrates can be further performed. Since the nanowire array has electrode connections at both ends, the integration and use of the device can be facilitated. The method for preparing the spring structure crystal nanowire of the invention has broad prospects in the field of flexible electronics and sensors.
本发明首次利用平面纳米线可引导生长的特性，成果展示了超柔性纳米线沟道线形设计和可拉伸的晶态半导体纳米线结构。以晶硅为例，晶硅本身不可拉伸也易碎，晶硅薄膜无法直接应用于可拉伸电子器件应用。通过此发明技术，可以将现有成熟的晶硅半导体技术工艺拓展到新兴的柔性电子应用领域，为大幅提升柔性电子器件的器件特性和稳定性提供关键技术基础。The present invention utilizes the characteristics of planar nanowires for guiding growth for the first time, and the results show a super-flexible nanowire channel linear design and a stretchable crystalline semiconductor nanowire structure. Taking crystalline silicon as an example, crystalline silicon itself is not stretchable or brittle, and crystalline silicon film cannot be directly applied to stretchable electronic devices. Through the invention technology, the existing mature crystalline silicon semiconductor technology process can be extended to the emerging flexible electronic application field, and a key technical basis for greatly improving the device characteristics and stability of the flexible electronic device is provided.
附图说明DRAWINGS
图1为弹簧结构晶体纳米线制备过程流程图；1 is a flow chart of a process for preparing a spring structure crystal nanowire;
图2为弹簧结构晶体纳米线阵列设计示意图；图2中，弹簧结构晶体纳米线阵列设计示意图，其中蓝色(深色)区域为催化剂区域(a)(b)(c)(d)分别表示四种不同的弹簧形曲线；2 is a schematic diagram of a spring structure crystal nanowire array design; FIG. 2 is a schematic diagram of a spring structure crystal nanowire array design, wherein a blue (dark) region is a catalyst region (a)(b)(c)(d) respectively Four different spring-shaped curves;
图3为弹簧结构晶体纳米线SEM形貌图；图3中，弹簧结构晶体纳米线SEM形貌图，(a)(b)(c)(d)分别表示四种不同的比例。Figure 3 is a SEM topography of a spring-structured crystal nanowire; in Figure 3, a spring-structured crystalline nanowire SEM topography, (a)(b)(c)(d) respectively represent four different ratios.
图4为弹簧结构晶态硅纳米线电学性能图。Figure 4 is a graph showing the electrical properties of a crystalline structured crystalline silicon nanowire.
图5(a)和(b)为举例的一种可拉伸硅纳米线的原位SEM力学拉伸和同步电学测试，图5(c)为同步电位测试结果图；图5(d)和(e)为此可拉伸硅纳米线被拉伸到弹性形变极限270％并可以完全恢复的过程SEM图。5(a) and (b) are examples of in-situ SEM mechanical stretching and synchronous electrical tests of a stretchable silicon nanowire, and FIG. 5(c) is a synchronous potential test result diagram; FIG. 5(d) and (e) A SEM image of a process in which the stretchable silicon nanowires are stretched to an elastic deformation limit of 270% and can be fully recovered.
具体实施方式detailed description
为使本发明的目的、技术方案、作用和优点更加明白，以下结合具体实例，对本发明进行进一步的详细解说。In order to make the objects, the technical solutions, the functions and the advantages of the present invention more comprehensible, the present invention will be further explained in detail below with reference to specific examples.
如图2所示，本发明提供了一种可拉伸晶体半导体纳米线，所述可拉伸晶体半导体纳米线具有细长的主体。所述可拉伸晶体半导体纳米线为弯曲结构，在轴向方向具有多个可拉伸单元，所述多个可拉伸单元依次连接，从而形成可拉伸晶体半导体纳米线。As shown in Figure 2, the present invention provides a stretchable crystalline semiconductor nanowire having an elongated body. The stretchable crystalline semiconductor nanowire is a curved structure having a plurality of stretchable cells in an axial direction, the plurality of stretchable cells being sequentially connected to form a stretchable crystalline semiconductor nanowire.
进一步地，所述纳米线直径在20-200纳米之间，所述纳米线为为晶态无机半导体结构。Further, the nanowires are between 20 and 200 nanometers in diameter, and the nanowires are crystalline inorganic semiconductor structures.
如图2所示，晶体纳米线阵列设计示意图，其中，蓝色(深色)区域为催化剂区域(a)(b)(c)(d)分别表示四种不同的弹簧形曲线；从图可知，所述纳米线为弯曲结构，在轴向方向具有多个相互连接的可拉伸单元，所述可拉伸单元为圆弧形、半圆形、半跑道形中的一个或多个。As shown in FIG. 2, a schematic diagram of a crystal nanowire array design in which a blue (dark) region is a catalyst region (a), and (b) and (c) (d) respectively represent four different spring-shaped curves; The nanowire is a curved structure having a plurality of interconnected stretchable units in an axial direction, and the stretchable unit is one or more of a circular arc shape, a semicircular shape, and a half racetrack shape.
进一步地，可拉伸晶体半导体纳米线的可拉伸单元为圆弧形、半圆形、半跑道形，也可以为Z形、V形、M形(未示出)，或其中的一种或多种组合。Further, the stretchable unit of the stretchable crystalline semiconductor nanowire is a circular arc shape, a semicircular shape, a half racetrack shape, or may be a Z shape, a V shape, an M shape (not shown), or one of them. Or a variety of combinations.
进一步地，其最大拉伸状态下的长度大于自然状态下长度的1.5倍，最好为2倍以上，优选为2.7倍。Further, the length in the maximum stretched state is greater than 1.5 times the length in the natural state, preferably 2 times or more, preferably 2.7 times.
在一个实施例中，生长出晶体纳米线，所述纳米线是Si,SiGe,Ge或GaAs等单晶纳米线。In one embodiment, crystalline nanowires are grown, the nanowires being single crystal nanowires such as Si, SiGe, Ge or GaAs.
生长所用衬底可以是P型或者N型单晶硅衬底，表面有二氧化硅层；可以是P型或者N型多晶硅片，表面有二氧化硅层；也可以是普通玻璃，石英玻璃等非晶体衬底。The substrate used for growth may be a P-type or N-type single crystal silicon substrate having a silicon dioxide layer on the surface; a P-type or N-type polycrystalline silicon wafer having a silicon dioxide layer on the surface; or a common glass, quartz glass, or the like. Amorphous substrate.
图3为弹簧结构晶体纳米线SEM形貌图，实际制备出的弹簧结构晶体纳米线SEM形貌图，(a)(b)可拉伸单元为圆弧形结构、(c)(d)可拉伸单元为半跑道形结构。(a)(b)(c)(d)分别表示四种不同的比例。Fig. 3 is a SEM topographical view of a spring-structured crystal nanowire, an actual prepared SEM topography of a crystal structure crystal nanowire, (a) (b) a stretchable unit having a circular arc structure, and (c) (d) The stretching unit is a half-track structure. (a) (b)(c)(d) represent four different ratios, respectively.
图4为制备出的弹簧结构晶态硅纳米线的电学性能图。Figure 4 is a graph showing the electrical properties of the prepared spring structured crystalline silicon nanowires.
如图5(a)(b)为举例，在原位扫描电镜中，在机械探针的操作下，力学拉伸其中一种硅纳米线并对其进行同步电学测试。测试结果如图5(c)所示，表明在硅纳米线拉伸弹性形变的过程中，电学性质稳定。As an example, as shown in Fig. 5(a)(b), in an in-situ scanning electron microscope, one of the silicon nanowires is mechanically stretched and subjected to synchronous electrical testing under the operation of a mechanical probe. The test results are shown in Fig. 5(c), indicating that the electrical properties are stable during the tensile elastic deformation of the silicon nanowires.
如图5(d)(e)所示，此种硅纳米线可以被力学拉伸到极限，其最大拉伸状态下的长度大于自然状态下长度的270％下，仍保持弹性形变，释放后，可以恢复原形。As shown in Fig. 5(d)(e), the silicon nanowires can be mechanically stretched to the limit, and the length in the maximum tensile state is greater than 270% of the length in the natural state, and remains elastically deformed, after release. , can restore the original shape.
根据本发明的又一个方面，如附图1所示，本发明提供了一种基于平面纳米线线形设计和引导的可拉伸晶体半导体纳米线的制备方法，其特征步骤包括：According to still another aspect of the present invention, as shown in FIG. 1, the present invention provides a method for preparing a stretchable crystalline semiconductor nanowire based on planar nanowire linear design and guiding, and the characteristic steps include:
1)以玻璃、二氧化硅片或者硅片等衬底，对玻璃、二氧化硅片或者硅片等衬底进行标准 化清洗，去除表面有机物和金属残余；1) Standardizing the substrate such as glass, silicon dioxide or silicon wafer with a substrate such as glass, silicon dioxide or silicon wafer to remove surface organic matter and metal residues;
2)利用光刻技术(或表面图案刻蚀技术)在衬底表面刻蚀一定深度的台阶，此引导台阶的线形可以自由方便地设计和定义；为了实现可拉伸的柔性晶态半导体沟道结构，将台阶线形设计成非直线的弯曲的弹簧或zigzag蛇形沟道形阵列，在衬底上通过光刻刻蚀技术制作出深度约150±10nm(不超过350nm)弹簧形的引导沟道阵列，以及更为空间弛豫的单线连通的分形弯曲二维分布结构等；2) etching a certain depth step on the surface of the substrate by using a photolithography technique (or surface pattern etching technique), the line shape of the guiding step can be freely designed and defined conveniently; in order to realize a stretchable flexible crystalline semiconductor channel The structure is designed such that the step line is designed as a non-linear curved spring or a zigzag serpentine channel array, and a spring-shaped guiding channel having a depth of about 150±10 nm (not exceeding 350 nm) is formed on the substrate by photolithography etching. Array, and a more spatially relaxed single-line connected fractal curved two-dimensional distribution structure;
3)通过平面纳米线引导生长方法，使直径约120±10nm直径的晶体纳米线精确地沿着所述引导沟道生长，形成纳米线弹簧阵列；即通过光刻lift-off或者掩模板技术，在引导沟道一端蒸镀淀积催化金属薄膜块，作为金属液滴的形成初始点和纳米线的起始位置；3) by a planar nanowire guided growth method, crystal nanowires having a diameter of about 120±10 nm are accurately grown along the guiding channel to form a nanowire spring array; that is, by lithography lift-off or mask technology, Depositing a deposited catalytic metal film block at one end of the guiding channel as an initial point of formation of the metal droplets and a starting position of the nanowire;
4)在PECVD***中利用氢气等还原性等离子体处理金属薄膜，去除表面的氧化层，并使之形成直径在几十纳米到一个微米之间的纳米金属催化颗粒；4) treating the metal thin film by a reducing plasma such as hydrogen in a PECVD system, removing the oxide layer on the surface, and forming the nano metal catalytic particles having a diameter of several tens of nanometers to one micrometer;
5)淀积覆盖一层适当厚度的非晶半导体层作为前驱体介质；5) depositing an amorphous semiconductor layer covered with a suitable thickness as a precursor medium;
6)在真空中或者非氧化性气氛中退火(温度在250℃以上)生长，使得金属液滴开始顺着引导台阶运动，吸收非晶层并沿途淀积出晶态的纳米线结构；6) annealing in a vacuum or in a non-oxidizing atmosphere (temperature above 250 ° C), so that the metal droplets begin to move along the guiding step, absorbing the amorphous layer and depositing a crystalline nanowire structure along the way;
7)通过光刻和蒸镀技术在纳米线弹簧阵列的两端处制备电极；7) preparing electrodes at both ends of the nanowire spring array by photolithography and evaporation techniques;
8)通过刻蚀液体使得纳米线弹簧和衬底脱离；8) detaching the nanowire spring from the substrate by etching the liquid;
9)把脱离的弹簧纳米线阵列转移到柔性衬底上，即可制作出可拉伸的纳米线弹簧，可以广泛应用于柔性电子领域。柔性纳米线弹簧或相关结构可被转移到柔性可拉伸聚合物衬底上(通过样品表面旋涂一层薄膜，并配合牺牲层腐蚀转移，以及直接利用纳米机械手选择操纵)。9) By transferring the detached spring nanowire array onto a flexible substrate, a stretchable nanowire spring can be fabricated, which can be widely used in the field of flexible electronics. The flexible nanowire spring or related structure can be transferred to a flexible stretchable polymer substrate (a film is spin coated through the surface of the sample and transferred to the sacrificial layer for corrosion transfer, and directly manipulated using a nanomanipulator).
进一步地，步骤(1)中其特征所述衬底可为硅片、玻璃、陶瓷片以及可耐高温到350℃的聚合物衬底。所述二氧化硅衬底为普通二氧化硅衬底，厚度大于250nm。硅片还可为表面覆盖二氧化硅或者氮化硅等介质层的P型或者N型单晶或者多晶硅片，玻璃为普通玻璃或者石英玻璃，聚合物可为能承受一定高温(>350℃)处理，与真空环境相兼容的柔性聚合物。Further, in the step (1), the substrate may be a silicon wafer, a glass, a ceramic sheet, and a polymer substrate resistant to high temperatures up to 350 °C. The silicon dioxide substrate is a conventional silicon dioxide substrate having a thickness greater than 250 nm. The silicon wafer may also be a P-type or N-type single crystal or a polycrystalline silicon wafer whose surface is covered with a dielectric layer such as silicon dioxide or silicon nitride, the glass is ordinary glass or quartz glass, and the polymer can withstand a certain high temperature (>350 ° C). Handle, a flexible polymer that is compatible with the vacuum environment.
进一步地，步骤3)中，再次使用光刻对准技术在沟道的位置上催化剂区域，通过平面纳米线引导生长方法，使直径约130±10nm直径的晶体纳米线精确地沿着所述引导沟道生长，形成弹簧形状的纳米线；蒸镀In,Sn金属，在于引导沟道特定位置形成几十纳米的金属膜图案；在PECVD***中利用等离子体处理技术，在350℃、功率2-5W时进行处理，使金属膜缩球形成直径在几百纳米到几微米之间的准纳米催化颗粒；再次使用PECVD***覆盖一层适当厚度的非晶硅(几纳米到几百纳米)的非晶硅作为前驱体介质层；在真空氛围下，350℃环境中退火，利用IP-SLS生长模式，使得纳米线从催化剂区域沿着引导沟道生长，形成并获得弹簧 结构的纳米线。Further, in step 3), the photocatalyst region is again used at the position of the channel using a photolithography alignment technique, and the crystal nanowire having a diameter of about 130±10 nm is accurately guided along the guide by a planar nanowire guided growth method. Channel growth, forming a spring-shaped nanowire; vapor deposition of In, Sn metal, forming a metal film pattern of several tens of nanometers at a specific position of the guiding channel; using plasma processing technology in a PECVD system at 350 ° C, power 2 At 5W, the metal film is condensed to form quasi-nano-catalytic particles with a diameter of several hundred nanometers to several micrometers; again, a PECVD system is used to cover a layer of amorphous silicon (a few nanometers to several hundred nanometers) of appropriate thickness. The crystalline silicon is used as a precursor dielectric layer; it is annealed in a vacuum atmosphere at 350 ° C, and the nanowires are grown from the catalyst region along the guiding channel by using an IP-SLS growth mode to form and obtain a spring-structured nanowire.
进一步地，步骤(3)中其特征所述催化金属可为低熔点金属铟、锡、镓、铅、铋等，以及它们的合金和氧化物材料，及与所生长的晶态纳米线材料相匹配的金、银、铜等贵金属。Further, in the step (3), the catalytic metal may be a low melting point metal indium, tin, gallium, lead, antimony or the like, and alloys and oxide materials thereof, and with the grown crystalline nanowire material. Matching precious metals such as gold, silver and copper.
进一步地，步骤(2)中其特征步骤包括：首先使用光刻技术在光刻胶层定义平面纳米线的引导台阶线形，然后利用反应等离子体(RIE)或者感应等离子体(ICP)刻蚀技术将图形向下刻蚀到衬底之中，其刻蚀深度在几个到几百纳米范围；Further, the characteristic step in the step (2) comprises: firstly, using a photolithography technique to define a guiding step line shape of the planar nanowire in the photoresist layer, and then using a reactive plasma (RIE) or an inductive plasma (ICP) etching technique. Etching the pattern down into the substrate with an etch depth ranging from a few to a few hundred nanometers;
在一个实施例中，通过光刻刻蚀方法制作引导沟道；其中刻蚀方法用湿法刻蚀：氢氧化钾(KOH)、氢氧化钠(NaOH)等碱性腐蚀体系，也可以是氢氟酸+硝酸(HF+HNO3)、氢氟酸+硝酸+醋酸(HF+HNO3+CH3COOH)等酸性腐蚀体系，还可以是乙二胺邻苯二酚(EthyleneDiaminePyrocatechol)等体系；或者采用干法刻蚀，即利用ICP-RIE进行刻蚀。In one embodiment, the guiding channel is formed by a photolithography etching method; wherein the etching method is wet etching: an alkaline etching system such as potassium hydroxide (KOH) or sodium hydroxide (NaOH), or hydrogen. Acidic corrosion system such as hydrofluoric acid + nitric acid (HF + HNO3), hydrofluoric acid + nitric acid + acetic acid (HF + HNO3 + CH3COOH), or Ethylene Diamine Pyrocatechol; or dry engraving Etching, that is, etching by ICP-RIE.
在一个实施例中，生长出其中弹簧形晶体纳米线，纳米线为Si，Ge,SiGe,GaAs等晶体材料。使用任意具有拉伸性质的形状结构，晶体纳米线直径在20-180nm。In one embodiment, the spring-shaped crystalline nanowires are grown, and the nanowires are crystalline materials such as Si, Ge, SiGe, GaAs, and the like. The crystal nanowires have a diameter of 20-180 nm using any shape structure having tensile properties.
进一步地，步骤(3)中其特征步骤包括：利用光刻或者掩模板技术，采用金属催化层通过热蒸发、磁控溅射、电子束溅射、脉冲激光溅射和原子层淀积等工艺，蒸镀铟、锡等催化金属层薄膜，使之形成几个微米的金属膜区域，并在引导沟道特定起始位置与引导台阶交叉。Further, the characteristic step in the step (3) comprises: using a photolithography or mask technology, using a metal catalyst layer by thermal evaporation, magnetron sputtering, electron beam sputtering, pulsed laser sputtering, and atomic layer deposition. A thin film of a catalytic metal layer such as indium or tin is deposited to form a metal film region of several micrometers, and intersects the guiding step at a specific starting position of the guiding channel.
进一步地，步骤(4)中包括：在PECVD***中利用等离子体处理技术，在200℃到450℃范围内、功率0.2-100瓦之间进行处理，使金属膜缩球形成直径在几十纳米到几个微米之间的纳米催化颗粒；Further, the step (4) comprises: using a plasma treatment technology in a PECVD system, processing in a range of 200 ° C to 450 ° C, and a power of 0.2-100 watts, so that the metal film shrinks into a diameter of several tens of nanometers. Nanocatalytic particles up to several microns;
进一步地，步骤(5)中其特征步骤包括：再次使用PECVD***覆盖一层适当厚度(几纳米到几百纳米)的非晶半导体层作为前驱体介质层。对于生长晶硅、晶锗或者晶态锗硅合金纳米线，相应采用非晶硅、非晶锗和非晶锗硅层作为前驱体。而对于其它半导体材料则采用相应的非晶材料薄膜作为前驱体。Further, the characteristic step in the step (5) comprises: using a PECVD system to cover a layer of an amorphous semiconductor layer of a suitable thickness (several nanometers to several hundreds of nanometers) as a precursor dielectric layer. For the growth of crystalline silicon, crystalline germanium or crystalline germanium-silicon alloy nanowires, amorphous silicon, amorphous germanium and amorphous germanium silicon layers are used as precursors. For other semiconductor materials, a corresponding amorphous material film is used as a precursor.
进一步地，步骤(6)中：针对不同半导体材料，平面纳米线的生长温度选择在300℃到600℃之间。纳米线生长过程可在惰性气体、还原性气体或者真空条件下进行。Further, in the step (6): for different semiconductor materials, the growth temperature of the planar nanowires is selected to be between 300 ° C and 600 ° C. The nanowire growth process can be carried out under inert gas, reducing gas or vacuum conditions.
进一步地，步骤(7)中：所生长的平面纳米线线形由引导台阶边缘所控制，可以获得可编程设计的非直线弯曲弹簧或zigzag蛇形沟道，以及单线连通的分形弯曲二维分布结构，从而实现可拉伸的晶硅半导体纳米线沟道。Further, in the step (7): the planar shape of the grown planar nanowire is controlled by the edge of the guiding step, and a non-linear curved spring or a zigzag serpentine channel of a programmable design, and a fractal curved two-dimensional distributed structure of single-line communication can be obtained. Thereby achieving a stretchable crystalline silicon semiconductor nanowire channel.
在又一个实施例中，基于平面纳米线的线形设计和引导生长技术，实现晶态半导体(包括硅、锗等)可拉伸电子器件的制备方法。利用常规光刻、刻蚀技术，或者其它模板和表面加工技术，在玻璃或者晶硅衬底上制作特定形貌的引导台阶，以非晶态薄膜(利用非晶硅、非晶锗 以及其它非晶态无机半导体材料)作为前驱体，利用金属(铟、锡、镓、铋等)催化颗粒吸收非晶薄膜，在顺延引导台阶运动的过程中，生长出对应的平面晶态(单质或者合金)纳米线结构。由于引导台阶可以自由编程设计，故而可以定制线形(line-shape)完全可控、规则的晶态纳米线阵列，进而制备出具有超可拉伸性的晶态半导体纳米线结构。此技术可实现具有高可拉伸性的晶硅等晶态半导体材料纳米沟道，保持了晶体半导体材料的优异电学可调制以及器件稳定特性，故而可以实现高性能的柔性半导体电子应用(例如可拉伸逻辑晶体管，显示控制和驱动器件，传感和人造皮肤等新兴领域)。In yet another embodiment, a method of fabricating a crystalline semiconductor (including silicon, germanium, etc.) stretchable electronic device is accomplished based on planar nanowire-based linear design and guided growth techniques. Using conventional lithography, etching techniques, or other stencil and surface processing techniques to create a specific morphological guide step on a glass or crystalline silicon substrate, using amorphous films (using amorphous silicon, amorphous germanium, and other non- As a precursor, a crystalline inorganic semiconductor material utilizes a metal (indium, tin, gallium, antimony, etc.) catalytic particles to absorb an amorphous film, and a corresponding planar crystal state (single substance or alloy) is grown during the step of guiding the step movement. Nanowire structure. Since the guiding step can be freely programmed, a line-shape fully controllable, regular crystalline nanowire array can be customized to prepare a crystalline semiconductor nanowire structure having super-stretchability. This technology can realize nano-channels of crystalline semiconductor materials such as crystalline silicon with high stretchability, and maintain excellent electrical modulation and device stability characteristics of crystalline semiconductor materials, so that high-performance flexible semiconductor electronic applications can be realized (for example, Stretching logic transistors, display control and drive devices, sensing and artificial skin and other emerging fields).
具体而言，一种弹簧结构的晶体纳米线的生长、转移的技术。是特定沟道下的定向生长、转移的方法，其步骤如下：Specifically, a technique for growth and transfer of a crystal nanowire of a spring structure. It is a method of directional growth and transfer under a specific channel, and the steps are as follows:
1)通过酸碱热溶液或者分别通过丙酮、酒精、去离子水超声处理对覆盖氧化层的晶体衬底进行处理，去除表面附着的杂质，暴露出晶体洁净表面。1) The crystal substrate covering the oxide layer is treated by ultrasonic acid solution or ultrasonic treatment with acetone, alcohol and deionized water respectively to remove impurities adhering to the surface and expose the crystal clean surface.
2)利用光刻刻蚀技术定义弹簧结构的引导生长沟道阵列，再次使用光刻对准技术在沟道的特定位置上定义催化剂区域。利用光刻技术(或表面图案刻蚀技术)形成一定深度的引导台阶；2) Defining the guided growth channel array of the spring structure using photolithographic etching techniques, again using photolithographic alignment techniques to define the catalyst regions at specific locations on the channel. Forming a certain depth of the guiding step by using a photolithography technique (or surface pattern etching technique);
3)通过光刻lift-off或者掩模板技术，在引导沟道一端蒸镀淀积催化金属薄膜块；蒸镀In,Sn金属，通过liftoff，使之仅存在于引导沟道特定位置形成几十纳米的金属膜图案；3) by vapor deposition lift-off or mask technology, vapor deposition of a catalytic metal film block at one end of the guiding channel; evaporation of In, Sn metal, by liftoff, so that only a certain number of locations in the guiding channel are formed Nano metal film pattern;
4)在PECVD***中利用等离子体处理技术，在350℃、功率2-5W时进行处理，使金属膜缩球形成直径在几百纳米到几微米之间的准纳米催化颗粒；4) using a plasma treatment technique in a PECVD system, processing at 350 ° C, power 2-5W, so that the metal film shrinks to form quasi-nano-catalytic particles having a diameter of several hundred nanometers to several micrometers;
5)再次使用PECVD***覆盖一层适当厚度的非晶硅(几纳米到几百纳米)的非晶硅作为前驱体介质层。5) The PECVD system is again used to cover a layer of amorphous silicon (a few nanometers to several hundred nanometers) of amorphous silicon as a precursor dielectric layer.
6)在真空中或者非氧化性气氛中退火(温度在280℃以上)生长，使得金属液滴开始顺着引导台阶运动，吸收非晶层并沿途淀积出晶态的纳米线结构；尤其是在真空氛围下，350℃环境中退火，利用IP-SLS生长模式，使得纳米线从催化剂区域沿着特定引导沟道生长，形成并获得弹簧状的纳米线。6) annealing in a vacuum or in a non-oxidizing atmosphere (temperature above 280 ° C), so that the metal droplets begin to move along the guiding step, absorbing the amorphous layer and depositing a crystalline nanowire structure along the way; especially Annealing in a vacuum atmosphere at 350 ° C, using the IP-SLS growth mode, allows the nanowires to grow from the catalyst region along a specific guiding channel to form and obtain spring-like nanowires.
7)再次利用光刻对准技术和金属蒸镀技术，在纳米线弹簧阵列的两端搭上电极。7) Using the lithography alignment technique and the metal evaporation technique again, the electrodes are placed on both ends of the nanowire spring array.
8)使用HF对样品表面进行刻蚀，使得纳米线和衬底脱离。8) Etching the surface of the sample with HF to detach the nanowire from the substrate.
9)把与衬底脱离的纳米线弹簧阵列转移到柔性衬底上。柔性纳米线弹簧或相关结构可被转移到柔性可拉伸聚合物衬底上(通过样品表面旋涂一层薄膜，并配合牺牲层腐蚀转移，以及直接利用纳米机械手选择操纵)。9) Transfer the array of nanowire springs detached from the substrate onto the flexible substrate. The flexible nanowire spring or related structure can be transferred to a flexible stretchable polymer substrate (a film is spin coated through the surface of the sample and transferred to the sacrificial layer for corrosion transfer, and directly manipulated using a nanomanipulator).
进一步地，通过光刻刻蚀制作出深度约200nm的引导沟道，弹簧结构的引导沟道(见图 1)，其中弹簧结构可以是任意具有可拉伸性质的弯曲形态，节点与节点之间的距离可以为200nm～50um。沟道的刻蚀方法可用湿法刻蚀：氢氧化钾(KOH)、氢氧化钠(NaOH)等碱性体系，也可以是氢氟酸+硝酸(HF+HNO3)、氢氟酸+硝酸+醋酸(HF+HNO3+CH3COOH)等酸性体系，还可以是乙二胺邻苯二酚(EthyleneDiaminePyrocatechol)等体系；也可以是干法刻蚀体系，利用ICP-RIE进行刻蚀。Further, a guiding channel having a depth of about 200 nm and a guiding channel of the spring structure (see FIG. 1) are formed by photolithography etching, wherein the spring structure can be any curved shape having a stretchable property, between nodes and nodes The distance can be from 200 nm to 50 um. The etching method of the channel can be wet etched: alkaline system such as potassium hydroxide (KOH) or sodium hydroxide (NaOH), or hydrofluoric acid + nitric acid (HF + HNO3), hydrofluoric acid + nitric acid + An acidic system such as acetic acid (HF+HNO3+CH3COOH) may be a system such as Ethylene Diamine Pyrocatechol or a dry etching system and etched by ICP-RIE.
进一步地，转移步骤使用的刻蚀液体可以是任意能腐蚀二氧化硅而缓慢或者不腐蚀晶体纳米线的液体。转移所使用的柔性衬底可以是任意具有拉伸性质的衬底。Further, the etching liquid used in the transferring step may be any liquid which can corrode the silica and slowly or not corrode the crystal nanowires. The flexible substrate used for the transfer may be any substrate having tensile properties.
进一步地，平面生长的纳米线可以是Si,SiGe,Ge,GaAs等平面单晶纳米线阵列，直径分布在20～200nm之间。Further, the planarly grown nanowires may be planar single crystal nanowire arrays of Si, SiGe, Ge, GaAs, etc., and have a diameter distribution between 20 and 200 nm.
进一步地，利用光刻蒸镀技术制作金属电极，可使用热蒸发***、电子束蒸发***和磁控溅射***等，金属电极接触使用PT(12nm)-AL(80nm)体系,可以是Ti-Au体系，可以是Ni金属，金属电极接触均使用快速热退火过程提高接触性能。Further, the metal electrode is fabricated by photolithography, and a thermal evaporation system, an electron beam evaporation system, a magnetron sputtering system, or the like can be used. The metal electrode is contacted with a PT (12 nm)-AL (80 nm) system, which may be Ti- The Au system, which may be Ni metal, uses a rapid thermal annealing process to improve contact performance.
一个更具体的实时例：300nmSiO 2氧化层衬底上弹簧结构晶体纳米线制备，包括以下步骤： A more specific real-time example: the preparation of a spring-structured crystalline nanowire on a 300 nm SiO 2 oxide layer substrate, including the following steps:
1)采用300nmSiO2氧化层衬底(经表面氧化的硅片)，分别使用丙酮、酒精、去离子水超声处理，去除衬底表面附着的杂质。硅片可采用纯单晶或多晶硅硅片。1) Using a 300 nm SiO2 oxide substrate (surface-oxidized silicon wafer), ultrasonic treatment with acetone, alcohol, and deionized water, respectively, to remove impurities attached to the surface of the substrate. The silicon wafer can be a pure single crystal or polycrystalline silicon wafer.
2)通过有掩膜光刻技术在衬底表面定义弹簧结构图案，使用ICP-RIE刻蚀在表面形成沟道，清洗光刻胶之后形成生物探针沟道的阵列。2) A spring structure pattern is defined on the surface of the substrate by mask lithography, a channel is formed on the surface by ICP-RIE etching, and an array of bioprobe channels is formed after cleaning the photoresist.
3)在PECVD***中，在1-50W功率下利用等离子体处理技术使之形成直径在几百纳米到几个微米之间的纳米催化颗粒；350℃的温度下形成直径在几百纳米的纳米催化颗粒。3) In a PECVD system, plasma processing technology is used to form nano-catalytic particles having a diameter of several hundred nanometers to several micrometers at a power of 1-50 W; at a temperature of 350 ° C, nanometers having a diameter of several hundred nanometers are formed. Catalytic particles.
4)继续在PECVD***中覆盖一层适当厚度的非晶硅层作为前驱体介质层；300℃-400℃下覆盖一层适当厚度的非晶硅层。真空中或者氢气、氮气等非氧化性气氛中退火在400℃下，催化液滴被激活后可以吸收周围的非晶硅，从而可以诱导生长出平面硅纳米线，同时纳米线会沿着引导沟道侧壁定向生长，形成所需的沟道。4) Continue to cover the PECVD system with a layer of amorphous silicon of appropriate thickness as the precursor dielectric layer; cover an amorphous silicon layer of appropriate thickness from 300 °C to 400 °C. Annealing in a vacuum or in a non-oxidizing atmosphere such as hydrogen or nitrogen at 400 ° C, the catalytic droplets can be activated to absorb the surrounding amorphous silicon, thereby inducing the growth of planar silicon nanowires, while the nanowires will follow the guiding grooves. The sidewalls are oriented to grow to form the desired channel.
5)在氢气氛围中利用等离子体处理表面残余的非晶硅15分钟直至表面颜色恢复正常色泽。5) The residual amorphous silicon on the surface was treated with plasma in a hydrogen atmosphere for 15 minutes until the surface color returned to normal color.
6)再次使用光刻定义电极图案，使用电子束蒸发技术，蒸镀12nm钛和60nm金，之后清洗掉的光刻胶和残余的金属。6) The lithography was again used to define the electrode pattern, and electron beam evaporation technique was used to evaporate 12 nm of titanium and 60 nm of gold, followed by cleaning of the photoresist and residual metal.
7)使用PMMA旋涂在衬底表面，再使用4％浓度的HF溶液刻蚀衬底，使PMMA薄膜带着晶态纳米线弹簧阵列和衬底脱离。7) Spin coating on the surface of the substrate using PMMA, and etching the substrate with a 4% strength HF solution to detach the PMMA film from the crystalline nanowire spring array and the substrate.
8)使用PDMS薄膜把和衬底脱离的PMMA薄膜和上面的弹簧结构晶体纳米线捞起来，再使 用溶剂把PMMA薄膜溶解，弹簧结构晶体纳米线就转移到了柔性衬底PDMS上。8) Using a PDMS film, the PMMA film detached from the substrate and the above-mentioned spring structure crystal nanowires were picked up, and then the solvent was used to dissolve the PMMA film, and the spring structure crystal nanowires were transferred to the flexible substrate PDMS.
如上所述，可较好地实现本发明。对于本领域的技术人员而言，在不脱离本发明的原理和精神的情况下对这些实施例进行变化、修改、替换、整合和变型仍落入本发明的保护范围内。本发明中未进行特殊说明或限定的部分，均采用现有技术实施。As described above, the present invention can be preferably carried out. It is to be understood by those skilled in the art that variations, modifications, substitutions, combinations and variations of these embodiments are possible without departing from the spirit and scope of the invention. The parts which are not specifically described or limited in the present invention are all implemented by the prior art.

Claims (10)

  1. 一种可拉伸晶体半导体纳米线，其特征在于：所述纳米线具有细长的主体，所述纳米线直径在20-200纳米之间，所述纳米线为为晶态无机半导体结构。A stretchable crystalline semiconductor nanowire, characterized in that the nanowire has an elongated body, the nanowire has a diameter of between 20 and 200 nanometers, and the nanowire is a crystalline inorganic semiconductor structure.
  2. 根据权利要求1所述的可拉伸晶体半导体纳米线，其特征在于：所述纳米线为弯曲结构，在轴向方向具有多个可拉伸单元，所述多个可拉伸单元依次连接，从而形成可拉伸晶体半导体纳米线。The stretchable crystalline semiconductor nanowire according to claim 1, wherein the nanowire is a curved structure having a plurality of stretchable units in an axial direction, and the plurality of stretchable units are sequentially connected. Thereby a stretchable crystalline semiconductor nanowire is formed.
  3. 根据权利要求2所述的可拉伸晶体半导体纳米线，其特征在于：所述可拉伸单元为圆弧形、半圆形、半跑道形、Z形、V形、M形中的一种或多种组合。The stretchable crystalline semiconductor nanowire according to claim 2, wherein the stretchable unit is one of a circular arc shape, a semicircular shape, a half racetrack shape, a Z shape, a V shape, and an M shape. Or a variety of combinations.
  4. 根据权利要求2所述的可拉伸晶体半导体纳米线，其特征在于：所述纳米线最大拉伸状态下的长度大于自然状态下长度的1.5倍，优选为2.7倍。The stretchable crystalline semiconductor nanowire according to claim 2, wherein the length of the nanowire in the maximum stretched state is greater than 1.5 times, preferably 2.7 times, the length in the natural state.
  5. 根据权利要求2-4任一项所述的可拉伸晶体半导体纳米线，其特征在于：所述纳米线是Si,SiGe,Ge或GaAs单晶纳米线。The stretchable crystalline semiconductor nanowire according to any one of claims 2 to 4, wherein the nanowire is a Si, SiGe, Ge or GaAs single crystal nanowire.
  6. 一种如权利要求1所述的可拉伸晶体半导体纳米线的制备方法，其特征在于，包括如下步骤：A method for preparing a stretchable crystalline semiconductor nanowire according to claim 1, comprising the steps of:
    1)采用包括玻璃、二氧化硅片或者硅片衬底，去除衬底表面残余；1) removing the residual surface of the substrate by using a substrate comprising glass, silicon dioxide or silicon;
    2)在衬底表面刻蚀一定深度的台阶，进而沿台阶刻蚀制作出特定的引导沟道；2) etching a step of a certain depth on the surface of the substrate, and then etching a specific guiding channel along the step etching;
    3)通过平面纳米线引导生长方法，使晶体纳米线精确地沿着所述引导沟道生长，在引导沟道一端蒸镀淀积催化金属薄膜块，作为金属液滴的形成初始点和纳米线的起始位置；3) by a planar nanowire guided growth method, the crystal nanowires are accurately grown along the guiding channel, and a deposition catalytic metal film block is vapor deposited at one end of the guiding channel as an initial point of formation of the metal droplets and the nanowire Starting position
    4)在PECVD***中利用包括氢气的还原性等离子体处理金属薄膜，去除表面的氧化层，并使之形成直径在几十纳米到一个微米之间的纳米金属催化颗粒；4) treating the metal thin film with a reducing plasma including hydrogen in a PECVD system, removing the oxide layer on the surface, and forming the nano metal catalytic particles having a diameter of several tens of nanometers to one micrometer;
    5)淀积覆盖一层适当厚度的非晶半导体层作为前驱体介质；5) depositing an amorphous semiconductor layer covered with a suitable thickness as a precursor medium;
    6)在真空中或者非氧化性气氛中退火生长，温度在250℃以上，使得金属液滴开始顺着引导台阶运动，吸收非晶层并沿途淀积出晶态的纳米线结构。6) Annealing in a vacuum or in a non-oxidizing atmosphere at a temperature above 250 ° C, so that the metal droplets begin to move along the guiding step, absorbing the amorphous layer and depositing a crystalline nanowire structure along the way.
  7. 根据权利要求6所述的可拉伸晶体半导体纳米线制备方法，步骤1)中硅片为表面覆盖二氧化硅或者氮化硅等介质层的P型或者N型单晶或者多晶硅片，玻璃为普通玻璃或者石英玻璃，聚合物可为能承受一定高温(>350℃)处理，与真空环境相兼容的柔性聚合物；所述二氧化硅衬底厚度大于250nm。The method for preparing a stretchable crystalline semiconductor nanowire according to claim 6, wherein the silicon wafer is a P-type or N-type single crystal or a polycrystalline silicon wafer whose surface is covered with a dielectric layer such as silicon dioxide or silicon nitride, and the glass is Ordinary glass or quartz glass, the polymer may be a flexible polymer that can withstand a certain high temperature (>350 ° C) treatment, compatible with the vacuum environment; the thickness of the silica substrate is greater than 250 nm.
  8. 根据权利要求6所述的可拉伸晶体半导体纳米线制备方法，步骤5)包括：再次使用PECVD***覆盖一层适当厚度的非晶半导体层作为前驱体介质层；对于生长晶硅、晶锗或者晶态锗硅合金纳米线，相应采用非晶硅、非晶锗和非晶锗硅层作为前驱体；而对于其它半导体材料则采用相应的非晶材料薄膜作为前驱体。The method for preparing a stretchable crystalline semiconductor nanowire according to claim 6, wherein the step 5) comprises: again using a PECVD system to cover a layer of an amorphous semiconductor layer of a suitable thickness as a precursor dielectric layer; for growing crystalline silicon, germanium or The crystalline silicon germanium alloy nanowires adopt amorphous silicon, amorphous germanium and amorphous germanium silicon layers as precursors, and for other semiconductor materials, corresponding amorphous material thin films are used as precursors.
  9. 根据权利要求6所述的可拉伸晶体半导体纳米线制备方法，还包括步骤7)：通过光刻和蒸镀技术制备电极。The method of preparing a stretchable crystalline semiconductor nanowire according to claim 6, further comprising the step of: preparing an electrode by photolithography and evaporation techniques.
  10. 根据权利要求9所述的可拉伸晶体半导体纳米线的制备方法，其特征是，还包括以下步骤：The method for preparing a stretchable crystalline semiconductor nanowire according to claim 9, further comprising the steps of:
    步骤8)通过刻蚀液体，使得纳米线和衬底脱离；Step 8) detaching the nanowire and the substrate by etching the liquid;
    步骤9)把脱离的弹簧纳米线阵列转移到柔性衬底上，所使用的柔性衬底可以是任意具有拉伸性质的衬底。Step 9) Transfer the detached spring nanowire array onto a flexible substrate, which may be any substrate having tensile properties.
PCT/CN2018/091544 2017-06-15 2018-06-15 Stretchable crystalline semiconductor nanowire and preparation method thereof WO2018228543A1 (en)

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