WO2017080340A1 - Nanowire giant piezo-resistive property measurement device and manufacturing method therefor - Google Patents

Nanowire giant piezo-resistive property measurement device and manufacturing method therefor Download PDF

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WO2017080340A1
WO2017080340A1 PCT/CN2016/102073 CN2016102073W WO2017080340A1 WO 2017080340 A1 WO2017080340 A1 WO 2017080340A1 CN 2016102073 W CN2016102073 W CN 2016102073W WO 2017080340 A1 WO2017080340 A1 WO 2017080340A1
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nanowire
silicon
nanowires
etching
oxide layer
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PCT/CN2016/102073
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French (fr)
Chinese (zh)
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张加宏
赵阳
李敏
杨敏
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南京信息工程大学
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y15/00—Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R3/00—Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips

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  • the invention relates to a nanowire giant piezoresistive characteristic measuring device and a manufacturing method thereof, and belongs to the technical field of micro-nano electromechanical systems.
  • nanowires As a typical one-dimensional semiconductor nanomaterial, nanowires have the characteristics of general nanomaterials, compatibility with modern large-scale integrated circuit technology, easy preparation in large quantities, and easy surface modification. Because the semiconductor properties of nanowires show unique electrical, mechanical, thermal, and chemical properties, their research and application areas cover a wide range of fields from chemical, physical, biological, environmental sensors, field effect transistors, and logic circuits. In addition, silicon nanowires also exhibit field emission, thermal conductivity, visible light luminescence and quantum confinement effects different from bulk silicon materials, and have great potential applications in nanoelectronic devices, optoelectronic devices and new energy sources. .
  • the giant piezoresistive effect has become the most interesting feature due to its potential use in electromechanical sensors and strain engineering.
  • the preparation methods are as follows: 1. Reducing the diameter of the nanowires by repeated thermal oxidation and etching processes to form a significant quantum confinement effect to enhance the nanometers.
  • the piezoresistive characteristics of the wire 2. Surface modification of the nanowire by a chemical process; 3. Preparation of a semiconductor-metal heterostructure.
  • the current characterization of nanostructured piezoresistive coefficients can be divided into two main categories: one is based on Atomic Force Microscope (AFM) or other probe technology loading methods, the main feature is the need for AFM/ Probe integrated nanomechanical sensor and nano
  • the meter precision actuator requires nano-manipulation technology to assemble the nanostructure onto the needle tip and so on.
  • AFM Atomic Force Microscope
  • Such experimental test systems are very complicated and the experimental costs are also very expensive.
  • the size of the AFM tip structure is much larger than that of the nanostructure, and the control accuracy during mechanical loading is difficult to reach the nanometer scale.
  • most AFM mechanical loading experiments are performed in Scanning Electron Microscopy (SEM), which affects the measurement of electrical characteristics.
  • the other is to use the micro-electro-mechanical system micro-actuator to load the nano-structure.
  • MEMS driving devices piezoelectric driving, electrostatic comb driving and thermal driving.
  • the measurement of the resistance is measured by two points. The existence of factors such as resistance undoubtedly increases the measurement error of the piezoresistive coefficient of the nanowire.
  • the present invention provides a nanowire giant piezoresistive characteristic measuring device and a manufacturing method thereof.
  • a nanowire giant piezoresistive characteristic measuring device comprises: a nanowire, a platinum resistance temperature sensor, an electrothermal actuator, a displacement sensor based on capacitance measurement, an electrode, a load sensor based on capacitance measurement, the platinum resistance temperature sensor, and an electric heating
  • An actuator, a displacement sensor based on capacitance measurement, and a load sensor based on capacitance measurement are sequentially connected, and the number of electrodes is set to four, the four The electrodes are disposed between the displacement sensor based on the capacitance measurement and the load sensor based on the capacitance measurement, and nanowires are disposed between the two horizontally placed electrodes, and electrodes are disposed on the lower sides of the nanowires.
  • a calibration probe that is coupled to a load sensor based on capacitance measurements.
  • the invention further comprises an electrical insulation module, characterized in that: between the electrothermal actuator and the displacement sensor based on the capacitance measurement, between the displacement sensor and the electrode based on the capacitance measurement, and between the electrode and the load sensor based on the capacitance measurement, based on the capacitance An electrical insulation module is provided between the measured load cell and the calibration probe.
  • the nanowires are made of externally grown silicon nanowires, and surface-modified by silver nanoparticles prepared on the nanowires to form a giant piezoresistive property.
  • the nanowires are chemical vapor deposition methods for synthesizing silicon germanium radial heterostructure nanowires having giant piezoresistive properties based on radial and axial growth control.
  • the nanowires are self-assembled by solution meteorological method to self-assemble silicon germanium longitudinal heterojunction nanowires having giant piezoresistive properties.
  • the nanowire adopts STM tip operation to prepare the nanowire with giant piezoresistive characteristics to position, align, and tighten the nanowires on the upper surface of the two suspension electrodes, and use the electron beam to induce deposition of the nanowires.
  • the array is attached to the suspension electrode.
  • a method for manufacturing a nanowire giant piezoresistive characteristic measuring device comprising: the following steps:
  • Step 1 Select 25 ⁇ m of top silicon, bury 2 ⁇ m of oxide layer, and 300 ⁇ m of SOI silicon wafer of bottom silicon.
  • the silicon wafer is placed in a mixed solution of acetone, hydrogen peroxide and concentrated sulfuric acid for ultrasonic cleaning, and then repeatedly cleaned with deionized water. Then, the cleaned silicon wafer is placed in a diluted HF solution to remove the oxide layer on the surface of the silicon wafer;
  • Step 2 depositing a 1 ⁇ m SiO 2 oxide layer on the top layer and the bottom layer of the SOI wafer by LPCVD technology;
  • Step Three forming a platinum resistance region is etched by RIE technique SiO 2 top oxide layer; etching by DRIE technique platinum resistance region;
  • Step 4 etching the top SiO 2 oxide layer by RIE technique to form a boron doped resistance region; boron doping is performed in the resistance region by a diffusion process, and the resistivity of the resistive region is set to 1.7 to 1.9 ⁇ 10 ⁇ 5 ⁇ ⁇ m, forming a P-type doped silicon resistance region;
  • Step 5 etching the SiO 2 oxide layer on the silicon surface by BOE using a buffer oxide
  • Step 6 etching the underlying SiO 2 oxide layer by an RIE technique to form an insulating module pattern
  • Step 7 spin-coating a photoresist on the bottom layer of the SOI silicon wafer; forming a oxide layer etching mask pattern by using a mask;
  • Step 8 etching the underlying silicon by 100 ⁇ m by DRIE technology
  • Step 9 etching the underlying SiO 2 oxide layer not protected by the photoresist by an RIE technique
  • Step 10 etching the underlying silicon not protected by the photoresist and the oxide layer by DRIE technology
  • Step 11 forming a platinum resistive pattern using a positive photoresist, and using a stripping process to form a platinum unit of a temperature unit on the SiO 2 buried layer;
  • Step 12 forming a pattern of electrodes and lead regions using a positive photoresist; sputtering aluminum, using a stripping process to form leads and an aluminum upper electrode;
  • Step 13 etching the SiO2 buried layer by RIE technology to expose the insulating module
  • Step 14 stripping the residual photoresist, the underlying SiO 2 oxide layer
  • Step 15 The device structure is completed by DRIE technology on the top layer silicon to form a complete structure and then annealed, and the aluminum lower electrode is formed on the measurement substrate by photolithography, etching, and stripping processes.
  • the nanowire giant piezoresistive characteristic measuring device and the manufacturing method thereof provided by the present invention use a combination of an external electric field and a chemical process surface modification to modify the surface state structure of the nanowire, or use self-grown silicon.
  • the heterostructure is used to complete the preparation of nanowires with giant piezoresistive properties.
  • the nanowire giant piezoresistive characteristic measuring device is completed by using a standard CMOS process compatible MEMS technology suitable for mass production, and the MEMS measuring device can simultaneously measure the mechanical characteristics and electrical characteristics of the nanowire, thereby completing the characterization of the piezoresistive coefficient. And can be applied to a variety of different measurement samples.
  • the measuring device obtains the elongation and load data of the nanowire through the capacitance digital conversion chip which is externally connected to the displacement sensor and the load sensor, and thus does not depend on the scanning electron microscope imaging, thereby avoiding the measurement of the electrical characteristics by the electron beam irradiation. influences.
  • the measuring device also integrates a temperature sensor for temperature compensation of the piezoresistive coefficient, reducing the influence of the environmental system, thereby completing the high piezoresistive coefficient of various measurement samples. The purpose of precision measurement.
  • the present invention provides a method for preparing five kinds of nanowires having giant piezoresistive characteristics, and the MEMS measuring device with giant piezoresistive characteristics has the ability to apply a bias electric field, and can modulate the piezoresistive characteristics of the nanowires.
  • the invention integrates the MEMS temperature sensor with the measuring device for temperature compensation, ensures the consistency, and improves the accuracy of the giant piezoresistive coefficient.
  • the present invention combines the four-probe structure to eliminate the influence of contact resistance and thereby make the measurement result of the nanowire giant piezoresistive coefficient more accurate.
  • the present invention provides a higher sampling rate that can be captured in emergent events such as plastic deformation and corrupted data points.
  • the apparatus of the present invention can be characterized outside the vacuum chamber to make it easier to study the effects of environmental factors on the properties of the nanomaterial, such as gas, light or temperature.
  • the measurement sample of the present invention may be a two-dimensional film, a one-dimensional nanostructure, and the nanostructure may be a single semiconductor nanowire structure, which may be a heterojunction nanowire or a nanowire array.
  • FIG. 1 is a schematic structural view of a nanowire giant piezoresistive characteristic measuring device
  • FIG. 2 is a working flow chart of a nanowire giant piezoresistive characteristic measuring device
  • FIG. 3 is a flow chart of a preparation process of a nanowire giant piezoresistive characteristic measuring device
  • FIG. 4 is a schematic view showing the preparation of a silicon germanium radial heterojunction nanowire
  • FIG. 5 is a schematic view showing growth of a silicon germanium longitudinal heterojunction nanowire
  • Figure 6 is a schematic view showing the operation of the STM probe to fix the nanowires on the electrodes
  • FIG. 7 is a schematic view of nanowires self-growth on an electrode
  • FIG. 8 is a flow chart of a MEMS process prepared by an integrated measurement structure of an electron beam lithography nanowire;
  • FIG. 9 is a schematic structural view of four electrodes of a nanowire
  • Figure 10 is a mechanical model of a mechanical characterization device for a nanowire sample
  • Figure 11 is a flow chart of temperature compensation for wavelet neural network based on improved genetic algorithm.
  • a nanowire giant piezoresistive characteristic measuring device is a platinum resistance temperature sensor 1 for temperature compensation from left to right, and an electrothermal actuator 2 for driving a displacement sensor and a nanowire. And load sensor movement; displacement sensor 3 based on capacitance measurement for measuring the displacement of the thermal actuator while achieving the drive voltage decoupling function of the thermal actuator; four electrodes 4 for four-probe measurement; Nanowire 6 with giant piezoresistive characteristics; load sensor 9 based on capacitance measurement for measuring the displacement and tension of itself; calibration probe 10 for calibrating the force sensor. All of the above units are stabilized in the same plane by a set of beams anchored to the top silicon to ensure uniform distribution of the entire nanowire specimen.
  • the electrothermal actuator 2 and the displacement sensor 3, the displacement sensor 3 and the electrode 4, the electrode 4 and the load sensor 9, the load sensor 9 and the calibration probe 10 are respectively mechanically connected through the electrically insulating modules 11 of the four SOI buried layers, Independent electrical measurements are provided for nanowire samples; also used for mechanical connection of load sensor 9 to calibration probe 10 for efficient measurement.
  • the two suspension electrodes 4 are mechanically connected to the nanowires 6.
  • a measuring step of a nanowire giant piezoresistive characteristic measuring device in the first step, the displacement sensor and the load sensor are calibrated under a microscope; and in the second step, the electrothermal actuator is driven as a driving device through an insulation module.
  • the displacement sensor moves to the left, and the nanowire is moved to the left by the insulation module, and the nanowire is also moved to the left by the insulation module;
  • the third step is the capacitance digital conversion by the load sensor and the displacement sensor based on the capacitance measurement
  • the chip obtains the load and elongation data of the nanowire, and at the same time, the piezoresistive change is obtained by the measurement of the four probes; in the fourth step, the piezoresistive effect is characterized by the strain coefficient.
  • the device structure is completed by DRIE technology on the top layer silicon to form a complete structure and then annealed, and the aluminum lower electrode is formed on the measurement substrate by photolithography, etching and stripping processes.
  • the calibration of the load sensor and the displacement sensor is completed.
  • the data sampling rate for device calibration is 45 Hz.
  • the displacement sensor and the electrothermal actuator are moved to the left, and the displacement of the displacement sensor in the microscopic imaging and the displacement of the capacitance digital conversion chip circuit corresponding to the displacement are read out.
  • the voltage is output, and the relationship between the displacement sensors and the corresponding voltage outputs is obtained.
  • the probe device is used to push the calibration probe to move, and the displacement of the load sensor in the microscopic imaging and the output voltage of the capacitance digital conversion chip circuit corresponding to the displacement are read out, and the relationship between the load sensor and the corresponding voltage output is obtained.
  • the load cell is calibrated using a precision microbalance to obtain the relationship between displacement and load.
  • the invention provides five nanowire setting methods with giant piezoresistive characteristics, as follows:
  • Example 1 Silicon nanowires with silver
  • the oxide film on the nanowire is treated with hydrofluoric acid, the surface of the nanowire of silicon is passivated by hydrogen, and the silicon nanoparticle whose surface is passivated by hydrogen is put into the silver nitrate solution, and the nanometer of silver is prepared on the silicon nanowire. particle.
  • Example 2 Silicon germanium radial heterojunction nanowires
  • Gold nanoclusters are deposited on oxidized silicon wafers and placed in a quartz tube furnace.
  • silane was used as the lead gas, so that the silicon nanowire core was grown at an axial growth rate of about 2 ⁇ m/min, and then p-type silicon shell was deposited using silane and 100 ppm helium diborane as a lead gas. And at a radial growth rate of 10 nm/min.
  • ⁇ nanowire 10% The relevant argon gas was grown at an axial growth rate of 0.72 um/min, and the crucible was deposited in the furnace at a radial velocity of 10 nm/min by changing the positional environment of the growth substrate.
  • Nanowires of various core-shell structures such as Si/Ge, Ge/Si, or Si/Ge/Si, Ge/Si/Ge, etc., can be completed by repeating the above process.
  • the process flow chart is shown in Figure 4.
  • a clean silicon wafer washed with an organic solvent is placed in a vacuum sputtering coating machine, and a layer of about 10 nm of tin is sputtered on the surface of the silicon wafer, heated to 600 ° C, and tin is agglomerated into nanoparticles;
  • silane gas is obtained by thermal decomposition of wrong silane, and then silane gas is used as a lead gas to grow silicon nano-fragments on the surface of the tin nano-particle catalyst layer, and the reaction is completed and then (Ar + 5% H 2 ) gas is introduced.
  • the residual precursor gas is removed; in the third step, the triphenyl decane liquid is thermally decomposed at 420-440 ° C to obtain a decane gas, which is then used as a lead gas for growing the yttrium nano-segment on the silicon nano-fragment.
  • the ruthenium nano-fragment was grown, and after completion of the reaction, an (Ar + 5% H 2 ) gas was introduced to remove residual residual precursor gases.
  • the silicon germanium heterojunction nanowires of the abrupt interface are formed by repeating the above two steps repeatedly, and the structure is until a suitable length of silicon germanium heterojunction nanowires (Si/Ge/Si/Ge) is grown.
  • the process flow chart is shown in Figure 5.
  • the STM (sweep-to-tunnel microscope) tip operation was used to position, align, and tighten the nanowires on the upper surfaces of the two suspension electrodes, and the electron beam induced deposition.
  • the nanowire array is fixed to the suspension electrode, and the effect is shown in Fig. 6.
  • a thin oxide layer of 30-60 nm is formed on the model, and then lithographically positioned to remove oxidation of the sidewall of the trench
  • the layer forms a window for growing silicon nanowires.
  • Photolithography is used to assist in locating the growth region, and a high-density tin-nanoparticle catalyst is obtained in the growth region by electrodeposition, and the substrate is immersed in a microemulsion containing a tin salt solution, a hydrofluoric acid solution, and a surfactant during deposition. Particles having a radius of 10-20 nm.
  • the silane (PS) is thermally decomposed at 450-470 ° C to obtain silane gas; then the silane gas is used as a lead gas to grow silicon nanowires on the surface of the tin nanoparticle catalyst layer, so that the suspended electrodes are connected through the nanowire array, and the nano
  • the surface is subjected to surface modification treatment of Ba, Hf, and Zr doping to increase the surface state density and increase the surface effect and piezoresistive characteristics, as shown in FIG.
  • the oxide film on the nanowire is treated with hydrofluoric acid, the surface of the nanowire of silicon is passivated by hydrogen, and the silicon nanoparticle whose surface is passivated by hydrogen is put into a silver nitrate solution, and silver is prepared on the silicon nanowire.
  • the first step is to spin-coat the SOI wafer on the negative photoresist, and then soft-bake after coating the glue; the second step is to scan the surface of the photoresist to obtain the required nano-line pattern and device of various sizes.
  • the third step is to develop the exposed pattern, and then remove the exposed portion to complete the device structure by the DRIE technique on the top silicon; finally, remove the unexposed portion of the photoresist.
  • a lower electrode is formed on the measurement structure substrate by a photolithography, etching, and lift-off process.
  • the initial resistance of the nanowire is obtained.
  • the horizontal direction is provided by two electrodes nanowires constant current source I, two vertical electrodes provide a voltage V 0 nanowires, the nanowires to give the initial resistance D1
  • V 0 nanowires The distance between the nanowires between the two electrodes in the vertical direction, and the distance between the nanowires between the two electrodes in the horizontal direction of d0; as previously emphasized, a bias voltage is applied between the suspension electrode of the nanowire and the substrate, and the depletion is performed.
  • the pinch-off of the nanowire conductive channel forming portion can facilitate the full realization of the nanowire giant piezoresistive property.
  • the electrothermal actuator acts as a driving device to push the displacement capacitance sensor to move to the left through the insulation module, and simultaneously pulls the nanowire to the left through the insulation module, and the nanowire moves the load sensor to the left through the insulation module.
  • k s d s k f d f
  • F a k a d a + k s d s
  • k s , k a , k f are the stiffness of the nanowire, load cell, and electrothermal actuator
  • d s , d a , d f are the displacement of the nanowire, load cell, and electrothermal actuator, respectively
  • the force F generated by the electrothermal actuator a 2NEA ⁇ Tsin ⁇ , where ⁇ is the thermal expansion coefficient of silicon, ⁇ T is the average temperature of the V-shaped beam, N being the number of V-shaped beam, a is the cross sectional area of the V-beam.
  • the stiffness k s of the nanowire can be obtained by the ratio of load sensor load to displacement corresponding to the output voltage.
  • the nanowire stiffness k s F/d s
  • the nanowire stress ⁇ F/S
  • F is the load sensor load
  • S is the cross-sectional area of the nanowire.
  • the mechanical properties and electrical properties of the nanowires were measured, and the giant piezoresistive effect of the nanowires was characterized.
  • the temperature and resistivity of the sample to be tested have a direct relationship, which affects the measurement of the piezoresistive coefficient. Therefore, the temperature of the sample to be tested must be grasped before the measurement. If the temperature of the sample is not suitable for the measurement. , will affect the final piezoresistive coefficient, it must be modified based on the improved genetic algorithm wavelet neural network model, the specific process shown in Figure 11:
  • Step 1 Population initialization: randomly initialize the population, encode the link weight between the input layer and the hidden layer of the wavelet neural network, the link weight of the hidden layer to the output layer, the scaled silver and the translation factor, and generate an initial population of a certain scale. .
  • Step 2 According to the link weight, expansion and translation factor of the wavelet neural network obtained by the individual.
  • the measured piezoresistive coefficient and temperature data are input as training data, and the error between the predicted output and the target value of the system is obtained as the fitness value F after training the wavelet neural network.
  • Step 3 Perform selection, crossover and mutation operations.
  • Step 4 Determine whether the evolution is over.
  • the fitness value satisfies the relationship
  • the genetic algorithm reaches the set number of iterations. After satisfying these two conditions, the weight, scaling and translation factors of the search can be used. Wavelet neural network calculation.
  • the invention realizes the measurement of mechanical characteristics and electrical characteristics of various measurement samples through the nanowire giant piezoresistive characteristic measuring device and the MEMS measuring method thereof, and characterizes the piezoresistive coefficient. It can be extended to other types of nanowires, such as the measurement of mechanical, electrical and piezoresistive properties of metal-silicon heterojunction nanowires.

Abstract

Provided are a nanowire giant piezo-resistive property measurement device and a manufacturing method therefor. The measurement device comprises: a nanowire (6); a platinum resistance temperature sensor (1); an electrothermal actuator (2); a capacitive measurement-based displacement sensor (3); an electrode (4); and a capacitive measurement-based load sensor (9). The platinum resistance temperature sensor (1), the electrothermal actuator (2), the displacement sensor (3), and the load sensor (9) are connected sequentially. There are four electrodes (4). The four electrodes (4) are disposed between the displacement sensor (3) and the load sensor (9). The nanowire (6) is disposed between two horizontally placed electrodes (4). The electrodes (4) are disposed at an upper side and a lower side of the nanowire (6). The measurement device and the manufacturing method therefor can realize concurrent measurement of a mechanical property and an electrical property of the nanowire (6), thereby completing characterization of a piezo-resistive coefficient. The invention is applicable to a variety of measurement samples.

Description

纳米线巨压阻特性测量装置及其制造方法Nanowire giant piezoresistive characteristic measuring device and manufacturing method thereof 技术领域Technical field
本发明涉及纳米线巨压阻特性测量装置及其制造方法，属于微纳机电***技术领域。The invention relates to a nanowire giant piezoresistive characteristic measuring device and a manufacturing method thereof, and belongs to the technical field of micro-nano electromechanical systems.
背景技术Background technique
纳米线作为典型的一维半导体纳米材料，除具有一般纳米材料的特征外，还具有与现代大规模集成电路工艺相兼容，易于大量制备，且便于表面修饰等特点。由于纳米线的半导体性质显示出独特的电学、力学、热学和化学特性，使其研究范围及应用领域覆盖了从化学、物理、生物、环境传感器、场效应晶体管和逻辑电路等众多领域。除此之外，硅纳米线还显示出不同于体硅材料的场发射、热导率、可见光致发光及量子限制效应，在纳米电子器件、光电子器件以及新能源等方面具有巨大的潜在应用价值。As a typical one-dimensional semiconductor nanomaterial, nanowires have the characteristics of general nanomaterials, compatibility with modern large-scale integrated circuit technology, easy preparation in large quantities, and easy surface modification. Because the semiconductor properties of nanowires show unique electrical, mechanical, thermal, and chemical properties, their research and application areas cover a wide range of fields from chemical, physical, biological, environmental sensors, field effect transistors, and logic circuits. In addition, silicon nanowires also exhibit field emission, thermal conductivity, visible light luminescence and quantum confinement effects different from bulk silicon materials, and have great potential applications in nanoelectronic devices, optoelectronic devices and new energy sources. .
一方面，在探索纳米线的性能与应用时，巨压阻效应由于其在机电传感器和应变工程中潜在的利用价值成为人们所最感兴趣的特性。尽管如此，目前纳米线巨压阻结构的制备还是比较困难的，其制备方法主要有：1、通过反复的热氧化与腐蚀工艺减薄减小纳米线的直径形成显著的量子限制效应来提升纳米线的压阻特性；2、利用化学工艺对纳米线进行表面修饰；3、制备半导体-金属异质结构。On the one hand, when exploring the performance and application of nanowires, the giant piezoresistive effect has become the most interesting feature due to its potential use in electromechanical sensors and strain engineering. Despite this, the preparation of nanowire giant piezoresistive structures is still difficult. The preparation methods are as follows: 1. Reducing the diameter of the nanowires by repeated thermal oxidation and etching processes to form a significant quantum confinement effect to enhance the nanometers. The piezoresistive characteristics of the wire; 2. Surface modification of the nanowire by a chemical process; 3. Preparation of a semiconductor-metal heterostructure.
另一方面，目前对纳米结构压阻系数的表征主要可以分成两大类：一类是基于原子力显微镜(Atomic Force Microscope,AFM)或者是其他探针技术的加载方法，主要特点在于需要对AFM/探针集成纳米力学传感器以及纳 米精度执行器、需要采用纳米操纵技术把纳米结构组装到针尖上去等等。但这类实验测试***十分复杂，实验成本也十分昂贵。而且，AFM针尖结构的尺寸要比纳米结构大得多，机械加载过程中的控制精度很难达到纳米量级。此外，大多数AFM机械加载实验都是在扫描电子显微镜(Scanning Electron Microscopy,SEM)内进行，SEM的成像技术会对电气特性的测量产生影响。另一类则是利用微电子机械***微驱动器对纳米结构进行加载，目前主要有压电驱动、静电梳齿驱动、热驱动三种MEMS驱动器件，其电阻的测量全部采用两点测量，由于接触电阻等因素的存在，无疑加大了纳米线的压阻系数的测量误差。On the other hand, the current characterization of nanostructured piezoresistive coefficients can be divided into two main categories: one is based on Atomic Force Microscope (AFM) or other probe technology loading methods, the main feature is the need for AFM/ Probe integrated nanomechanical sensor and nano The meter precision actuator requires nano-manipulation technology to assemble the nanostructure onto the needle tip and so on. However, such experimental test systems are very complicated and the experimental costs are also very expensive. Moreover, the size of the AFM tip structure is much larger than that of the nanostructure, and the control accuracy during mechanical loading is difficult to reach the nanometer scale. In addition, most AFM mechanical loading experiments are performed in Scanning Electron Microscopy (SEM), which affects the measurement of electrical characteristics. The other is to use the micro-electro-mechanical system micro-actuator to load the nano-structure. At present, there are mainly three kinds of MEMS driving devices: piezoelectric driving, electrostatic comb driving and thermal driving. The measurement of the resistance is measured by two points. The existence of factors such as resistance undoubtedly increases the measurement error of the piezoresistive coefficient of the nanowire.
值得注意的是，由于温度漂移使得半导体巨压阻传感器的灵敏度和稳定性产生一定影响，而且降低了测量的精度，所以针对应用于各种温度环境的半导体压阻传感器需要考虑其温度漂移效应，然而目前针对纳米线的压阻系数的温度特性的研究却较少，因而迫切需要相关的测量与研究方法。It is worth noting that the temperature drift causes the sensitivity and stability of the semiconductor giant piezoresistive sensor to have a certain influence, and the measurement accuracy is lowered. Therefore, the semiconductor piezoresistive sensor applied to various temperature environments needs to consider the temperature drift effect. However, there are few studies on the temperature characteristics of the piezoresistive coefficient of nanowires, so relevant measurement and research methods are urgently needed.
发明内容Summary of the invention
目的：为了克服现有技术中存在的不足，本发明提供一种纳米线巨压阻特性测量装置及其制造方法。OBJECTIVE: To overcome the deficiencies in the prior art, the present invention provides a nanowire giant piezoresistive characteristic measuring device and a manufacturing method thereof.
技术方案：为解决上述技术问题，本发明采用的技术方案为：Technical Solution: In order to solve the above technical problems, the technical solution adopted by the present invention is:
一种纳米线巨压阻特性测量装置，包括：纳米线、铂电阻温度传感器、电热致动器、基于电容测量的位移传感器、电极、基于电容测量的负荷传感器，所述铂电阻温度传感器、电热致动器、基于电容测量的位移传感器、基于电容测量的负荷传感器依次连接，所述电极数量设置为四个，所述四 个电极设置在基于电容测量的位移传感器与基于电容测量的负荷传感器之间，两个水平放置的电极之间设置有纳米线，所述纳米线上下两侧均设置有电极。A nanowire giant piezoresistive characteristic measuring device comprises: a nanowire, a platinum resistance temperature sensor, an electrothermal actuator, a displacement sensor based on capacitance measurement, an electrode, a load sensor based on capacitance measurement, the platinum resistance temperature sensor, and an electric heating An actuator, a displacement sensor based on capacitance measurement, and a load sensor based on capacitance measurement are sequentially connected, and the number of electrodes is set to four, the four The electrodes are disposed between the displacement sensor based on the capacitance measurement and the load sensor based on the capacitance measurement, and nanowires are disposed between the two horizontally placed electrodes, and electrodes are disposed on the lower sides of the nanowires.
还包括校准探针，所述校准探针与基于电容测量的负荷传感器相连接。Also included is a calibration probe that is coupled to a load sensor based on capacitance measurements.
还包括电气绝缘模块，其特征在于：所述电热致动器与基于电容测量的位移传感器之间，基于电容测量的位移传感器与电极之间，电极与基于电容测量的负荷传感器之间，基于电容测量的负荷传感器与校准探针之间均设置有电气绝缘模块。The invention further comprises an electrical insulation module, characterized in that: between the electrothermal actuator and the displacement sensor based on the capacitance measurement, between the displacement sensor and the electrode based on the capacitance measurement, and between the electrode and the load sensor based on the capacitance measurement, based on the capacitance An electrical insulation module is provided between the measured load cell and the calibration probe.
所述纳米线采用外生长硅纳米线，通过在纳米线上制备银的纳米粒子对其进行表面修饰形成巨压阻特性。The nanowires are made of externally grown silicon nanowires, and surface-modified by silver nanoparticles prepared on the nanowires to form a giant piezoresistive property.
所述纳米线采用化学气相沉积方法，基于径向与轴向生长的控制合成具有巨压阻特性的硅锗径向异质结构纳米线。The nanowires are chemical vapor deposition methods for synthesizing silicon germanium radial heterostructure nanowires having giant piezoresistive properties based on radial and axial growth control.
所述纳米线采用溶液气象法自生长自组装具有巨压阻特性的硅锗纵向异质结纳米线。The nanowires are self-assembled by solution meteorological method to self-assemble silicon germanium longitudinal heterojunction nanowires having giant piezoresistive properties.
所述纳米线采用STM针尖操作将制备完成的具有巨压阻特性的纳米线在两个悬挂电极上表面相应位置进行定位、校准、拉紧纳米线等装配操作，利用电子束诱导沉积将纳米线阵列固定在悬挂电极上。The nanowire adopts STM tip operation to prepare the nanowire with giant piezoresistive characteristics to position, align, and tighten the nanowires on the upper surface of the two suspension electrodes, and use the electron beam to induce deposition of the nanowires. The array is attached to the suspension electrode.
纳米线巨压阻特性测量装置制造方法，其特征在于：包括如下步骤：A method for manufacturing a nanowire giant piezoresistive characteristic measuring device, comprising: the following steps:
步骤一：选用顶层硅25μm，掩埋氧化层2μm，底层硅300μm的SOI硅片，将硅片先后放入丙酮、双氧水和浓硫酸的混合溶液中进行超声清洗，再用去离子水反复清洗干净；然后将清洗干净的硅片放入稀释的HF溶液中反应，以除去硅片表面的氧化层； Step 1: Select 25 μm of top silicon, bury 2 μm of oxide layer, and 300 μm of SOI silicon wafer of bottom silicon. The silicon wafer is placed in a mixed solution of acetone, hydrogen peroxide and concentrated sulfuric acid for ultrasonic cleaning, and then repeatedly cleaned with deionized water. Then, the cleaned silicon wafer is placed in a diluted HF solution to remove the oxide layer on the surface of the silicon wafer;
步骤二：通过LPCVD技术在SOI硅片的顶层与底层硅沉积1μm的SiO2氧化层；Step 2: depositing a 1 μm SiO 2 oxide layer on the top layer and the bottom layer of the SOI wafer by LPCVD technology;
步骤三：通过RIE技术刻蚀顶层SiO2氧化层形成铂电阻区域；通过DRIE技术刻蚀铂电阻区域；Step Three: forming a platinum resistance region is etched by RIE technique SiO 2 top oxide layer; etching by DRIE technique platinum resistance region;
步骤四：通过RIE技术刻蚀顶层SiO2氧化层，形成硼掺杂电阻区；通过扩散工艺，在电阻区进行硼掺杂，所述电阻区的电阻率设置为1.7～1.9×10-5Ω·m，形成P型掺杂硅电阻区；Step 4: etching the top SiO 2 oxide layer by RIE technique to form a boron doped resistance region; boron doping is performed in the resistance region by a diffusion process, and the resistivity of the resistive region is set to 1.7 to 1.9×10 −5 Ω · m, forming a P-type doped silicon resistance region;
步骤五：采用缓冲氧化物蚀刻BOE剥离硅表面的SiO2氧化层；Step 5: etching the SiO 2 oxide layer on the silicon surface by BOE using a buffer oxide;
步骤六：通过RIE技术刻蚀底层SiO2氧化层，形成绝缘模块图形；Step 6: etching the underlying SiO 2 oxide layer by an RIE technique to form an insulating module pattern;
步骤七：在SOI硅片底层旋涂光刻胶；利用掩膜版，光刻形成氧化物层蚀刻掩膜图案；Step 7: spin-coating a photoresist on the bottom layer of the SOI silicon wafer; forming a oxide layer etching mask pattern by using a mask;
步骤八：通过DRIE技术对底层硅刻蚀100μm；Step 8: etching the underlying silicon by 100 μm by DRIE technology;
步骤九：通过RIE技术刻蚀未被光刻胶保护的底层SiO2氧化层；Step 9: etching the underlying SiO 2 oxide layer not protected by the photoresist by an RIE technique;
步骤十：通过DRIE技术对未被光刻胶与氧化层保护的底层硅刻蚀；Step 10: etching the underlying silicon not protected by the photoresist and the oxide layer by DRIE technology;
步骤十一：使用正性光刻胶形成铂金电阻图形，采用剥离工艺方法，在SiO2掩埋层上制作出温度单元的铂金电阻；Step 11: forming a platinum resistive pattern using a positive photoresist, and using a stripping process to form a platinum unit of a temperature unit on the SiO 2 buried layer;
步骤十二：使用正性光刻胶形成电极及引线区图形；溅射铝，采用剥离工艺方法，形成引线与铝上电极；Step 12: forming a pattern of electrodes and lead regions using a positive photoresist; sputtering aluminum, using a stripping process to form leads and an aluminum upper electrode;
步骤十三：通过RIE技术刻蚀SiO2掩埋层，露出绝缘模块；Step 13: etching the SiO2 buried layer by RIE technology to expose the insulating module;
步骤十四：剥离残余光刻胶，底层的SiO2氧化层； Step 14: stripping the residual photoresist, the underlying SiO 2 oxide layer;
步骤十五：通过DRIE技术对顶层硅刻蚀完成器件结构，形成完整结构后退火，利用光刻、刻蚀、剥离工艺在测量结构衬底形成铝下电极。Step 15: The device structure is completed by DRIE technology on the top layer silicon to form a complete structure and then annealed, and the aluminum lower electrode is formed on the measurement substrate by photolithography, etching, and stripping processes.
有益效果：本发明提供的纳米线巨压阻特性测量装置及其制造方法，采用外置电场与化学工艺表面修饰相结合的方法对纳米线的表面态结构进行改性，或者利用自生长的硅锗异质结构来完成具有巨压阻特性的纳米线制备。[Advantageous Effects] The nanowire giant piezoresistive characteristic measuring device and the manufacturing method thereof provided by the present invention use a combination of an external electric field and a chemical process surface modification to modify the surface state structure of the nanowire, or use self-grown silicon. The heterostructure is used to complete the preparation of nanowires with giant piezoresistive properties.
采用适合于大批量生产的标准CMOS工艺兼容的MEMS技术完成纳米线巨压阻特性测量装置，该MEMS测量装置可以实现纳米线的机械特性与电气特性的同时测量，从而完成压阻系数的表征，并且可适用于多种不同测量样本。The nanowire giant piezoresistive characteristic measuring device is completed by using a standard CMOS process compatible MEMS technology suitable for mass production, and the MEMS measuring device can simultaneously measure the mechanical characteristics and electrical characteristics of the nanowire, thereby completing the characterization of the piezoresistive coefficient. And can be applied to a variety of different measurement samples.
该测量装置通过基于电容测量的位移传感器与负荷传感器外接的电容数字转换芯片得到纳米线的伸长和负荷数据，因而不依赖于扫描式电子显微镜成像，从而避免了电子束照射对电气特性测量的影响。同时针对被测样品的温度影响压阻系数测量的问题，该测量装置还集成了温度传感器用于压阻系数的温度补偿，降低环境***的影响，从而完成多种测量样本巨压阻系数的高精度测量的目的。The measuring device obtains the elongation and load data of the nanowire through the capacitance digital conversion chip which is externally connected to the displacement sensor and the load sensor, and thus does not depend on the scanning electron microscope imaging, thereby avoiding the measurement of the electrical characteristics by the electron beam irradiation. influences. At the same time, for the problem that the temperature of the sample to be tested affects the piezoresistive coefficient measurement, the measuring device also integrates a temperature sensor for temperature compensation of the piezoresistive coefficient, reducing the influence of the environmental system, thereby completing the high piezoresistive coefficient of various measurement samples. The purpose of precision measurement.
1.本发明提供了5种具有巨压阻特性的纳米线的制备方法，巨压阻特性的MEMS测量装置具有施加偏置电场的能力，可以调制纳米线的压阻特性。1. The present invention provides a method for preparing five kinds of nanowires having giant piezoresistive characteristics, and the MEMS measuring device with giant piezoresistive characteristics has the ability to apply a bias electric field, and can modulate the piezoresistive characteristics of the nanowires.
2.本发明将MEMS温度传感器与测量装置集成在一起进行温度补偿，保证其一致性，提高了巨压阻系数精确度。 2. The invention integrates the MEMS temperature sensor with the measuring device for temperature compensation, ensures the consistency, and improves the accuracy of the giant piezoresistive coefficient.
3.本发明结合四探针结构消除了接触电阻的影响从而使得纳米线巨压阻系数的测量结果更加精确。3. The present invention combines the four-probe structure to eliminate the influence of contact resistance and thereby make the measurement result of the nanowire giant piezoresistive coefficient more accurate.
4.本发明提供了一个更高的采样率，在突发事件，例如：塑性变形和破坏的数据点都可以捕获。4. The present invention provides a higher sampling rate that can be captured in emergent events such as plastic deformation and corrupted data points.
5.本发明所涉及的装置可置于真空室外部表征，使其更容易研究环境因素对纳米材料的特性，如气、光或温度的影响。5. The apparatus of the present invention can be characterized outside the vacuum chamber to make it easier to study the effects of environmental factors on the properties of the nanomaterial, such as gas, light or temperature.
6.本发明获取的所有测量数据力和位移，不依靠扫描式电子显微镜成像，避免了电子束照射对样品的电气特性测量的影响。6. All measurement data forces and displacements obtained by the present invention are not imaged by scanning electron microscopy, and the influence of electron beam irradiation on the measurement of electrical characteristics of the sample is avoided.
7.本发明的测量样本可以是二维薄膜，一维纳米结构，其纳米结构可为单一的半导体纳米线结构，可为异质结纳米线，也可为纳米线阵列。7. The measurement sample of the present invention may be a two-dimensional film, a one-dimensional nanostructure, and the nanostructure may be a single semiconductor nanowire structure, which may be a heterojunction nanowire or a nanowire array.
附图说明DRAWINGS
图1为纳米线巨压阻特性测量装置的结构示意图；1 is a schematic structural view of a nanowire giant piezoresistive characteristic measuring device;
图2为纳米线巨压阻特性测量装置的工作流程图；2 is a working flow chart of a nanowire giant piezoresistive characteristic measuring device;
图3为纳米线巨压阻特性测量装置制备工艺流程图；3 is a flow chart of a preparation process of a nanowire giant piezoresistive characteristic measuring device;
图4为硅锗径向异质结纳米线的制备示意图；4 is a schematic view showing the preparation of a silicon germanium radial heterojunction nanowire;
图5为硅锗纵向异质结纳米线的生长示意图；5 is a schematic view showing growth of a silicon germanium longitudinal heterojunction nanowire;
图6为STM探针操作将纳米线固定于电极上的示意图；Figure 6 is a schematic view showing the operation of the STM probe to fix the nanowires on the electrodes;
图7为纳米线自生长于电极上的示意图；7 is a schematic view of nanowires self-growth on an electrode;
图8为电子束光刻纳米线的集成测量结构制备的MEMS工艺流程图；8 is a flow chart of a MEMS process prepared by an integrated measurement structure of an electron beam lithography nanowire;
图9为纳米线四个电极测量的结构示意图；9 is a schematic structural view of four electrodes of a nanowire;
图10为纳米线样本的力学表征装置的机械模型； Figure 10 is a mechanical model of a mechanical characterization device for a nanowire sample;
图11为基于改进遗传算法的小波神经网络温度补偿流程图。Figure 11 is a flow chart of temperature compensation for wavelet neural network based on improved genetic algorithm.
具体实施方式detailed description
下面结合附图对本发明作更进一步的说明。The present invention will be further described below in conjunction with the accompanying drawings.
如图1所示，一种纳米线巨压阻特性测量装置自左向右分别是铂电阻温度传感器1，用于温度补偿；电热致动器2，用来作为驱动装置使位移传感器、纳米线以及负荷传感器移动；基于电容测量的位移传感器3，用来测量热致动器的位移，同时实现为热致动器的驱动电压去耦功能；用于四探针测量的四个电极4；具有巨压阻特性的纳米线6；基于电容测量的负荷传感器9，用来完成本身的位移与拉力的测量；校正探针10，用于为力传感器进行校准。上述所有单元由一组锚定在顶层硅的梁来稳定在同一平面内做单轴运动，以确保整个纳米线标本均布载荷。As shown in FIG. 1 , a nanowire giant piezoresistive characteristic measuring device is a platinum resistance temperature sensor 1 for temperature compensation from left to right, and an electrothermal actuator 2 for driving a displacement sensor and a nanowire. And load sensor movement; displacement sensor 3 based on capacitance measurement for measuring the displacement of the thermal actuator while achieving the drive voltage decoupling function of the thermal actuator; four electrodes 4 for four-probe measurement; Nanowire 6 with giant piezoresistive characteristics; load sensor 9 based on capacitance measurement for measuring the displacement and tension of itself; calibration probe 10 for calibrating the force sensor. All of the above units are stabilized in the same plane by a set of beams anchored to the top silicon to ensure uniform distribution of the entire nanowire specimen.
电热致动器2与位移传感器3，位移传感器3与电极4，电极4与负荷传感器9，负荷传感器9与校准探针10分别通过四个SOI掩埋层的电气绝缘模块11来实现机械连接，以对纳米线样本提供独立的电气测量；也用于负荷传感器9与校准探针10的机械连接，实现有效测量。两个悬挂电极4与纳米线6实现机械连接。The electrothermal actuator 2 and the displacement sensor 3, the displacement sensor 3 and the electrode 4, the electrode 4 and the load sensor 9, the load sensor 9 and the calibration probe 10 are respectively mechanically connected through the electrically insulating modules 11 of the four SOI buried layers, Independent electrical measurements are provided for nanowire samples; also used for mechanical connection of load sensor 9 to calibration probe 10 for efficient measurement. The two suspension electrodes 4 are mechanically connected to the nanowires 6.
如图2所示，一种纳米线巨压阻特性测量装置的测量步骤：第一步，在显微镜下完成位移传感器与负荷传感器校准；第二步，电热致动器作为驱动装置通过绝缘模块推动位移传感器向左移动，同时通过绝缘模块拉动纳米线向左移动，而纳米线也通过绝缘模块拉动负荷传感器向左移动；第三步，通过基于电容测量的负荷传感器和位移传感器外接的电容数字转换 芯片得到纳米线的负荷和伸长数据，与此同时通过四探针的测量得到压阻变化；第四步，通过应变系数表征压阻效应。As shown in FIG. 2, a measuring step of a nanowire giant piezoresistive characteristic measuring device: in the first step, the displacement sensor and the load sensor are calibrated under a microscope; and in the second step, the electrothermal actuator is driven as a driving device through an insulation module. The displacement sensor moves to the left, and the nanowire is moved to the left by the insulation module, and the nanowire is also moved to the left by the insulation module; the third step is the capacitance digital conversion by the load sensor and the displacement sensor based on the capacitance measurement The chip obtains the load and elongation data of the nanowire, and at the same time, the piezoresistive change is obtained by the measurement of the four probes; in the fourth step, the piezoresistive effect is characterized by the strain coefficient.
如图3所示，一种纳米线巨压阻特性测量装置的制备方法，该方法具体步骤：As shown in FIG. 3, a method for preparing a nanowire giant piezoresistive characteristic measuring device, the specific steps of the method:
1)选用顶层硅25μm，掩埋氧化层2μm，底层硅300μm的SOI硅片，将硅片先后放入丙酮、双氧水和浓硫酸的混合溶液中进行超声清洗，再用去离子水反复清洗干净；然后将清洗干净的硅片放入稀释的HF溶液中反应，以除去硅片表面的氧化层；1) Select 25μm of top silicon, bury 2μm of oxide layer, 300μm of SOI silicon wafer of bottom silicon, place the silicon wafer in ultrasonic solution of acetone, hydrogen peroxide and concentrated sulfuric acid, then wash it again with deionized water; then The cleaned silicon wafer is placed in a diluted HF solution to remove the oxide layer on the surface of the silicon wafer;
2)通过LPCVD技术在SOI硅片的顶层与底层硅沉积1μm的SiO2氧化层；2) depositing a 1 μm SiO 2 oxide layer on the top and bottom silicon of the SOI wafer by LPCVD technique;
3)通过RIE(反应离子蚀刻)技术刻蚀顶层SiO2氧化层形成铂电阻区域；通过DRIE(深反应离子蚀刻)技术刻蚀铂电阻区域；3) etching a top SiO 2 oxide layer by a RIE (Reactive Ion Etching) technique to form a platinum resistance region; etching the platinum resistance region by a DRIE (Deep Reactive Ion Etching) technique;
4)通过RIE技术刻蚀顶层SiO2氧化层，形成硼掺杂电阻区；通过扩散工艺，在电阻区进行硼掺杂(电阻率：1.7～1.9×10-5Ω·m)，形成P型掺杂硅电阻区；4) etching the top SiO 2 oxide layer by RIE technique to form a boron doped resistance region; boron doping (resistivity: 1.7 to 1.9×10 -5 Ω·m) in the resistance region by a diffusion process to form a P-type Doped silicon resistance region;
5)采用缓冲氧化物蚀刻(BOE)剥离硅表面的SiO2氧化层；5) using the SiO 2 oxide layer is buffered oxide etch (BOE) peeling off the silicon surface;
6)通过RIE技术刻蚀底层SiO2氧化层，形成绝缘模块图形；6) etching the underlying SiO 2 oxide layer by RIE technique to form an insulating module pattern;
7)在SOI硅片底层旋涂光刻胶；利用掩膜版，光刻形成氧化物层蚀刻掩膜图案； 7) spin-coating a photoresist on the bottom layer of the SOI wafer; forming a oxide layer etching mask pattern by using a mask;
8)通过DRIE技术对底层硅刻蚀100μm；8) etching the underlying silicon by 100 μm by DRIE technique;
9)通过RIE技术刻蚀未被光刻胶保护的底层SiO2氧化层；9) etching the underlying SiO 2 oxide layer not protected by the photoresist by an RIE technique;
10)通过DRIE技术对未被光刻胶与氧化层保护的底层硅刻蚀；10) etching the underlying silicon that is not protected by the photoresist and the oxide layer by DRIE technology;
11)使用正性光刻胶形成铂金电阻图形，采用剥离工艺方法，在SiO2掩埋层上制作出温度单元的铂金电阻；11) forming a platinum resistance pattern using a positive photoresist, and using a stripping process to form a platinum unit of a temperature unit on the SiO 2 buried layer;
12)使用正性光刻胶形成电极及引线区图形；溅射铝，采用剥离工艺方法，形成及引线与铝上电极；12) forming a pattern of electrodes and lead regions using a positive photoresist; sputtering aluminum, forming a lead and an aluminum upper electrode by a lift-off process;
13)通过RIE技术刻蚀SiO2掩埋层，露出绝缘模块；13) etching the SiO 2 buried layer by RIE technology to expose the insulating module;
14)剥离残余光刻胶，底层的SiO2氧化层；14) stripping the residual photoresist, the underlying SiO 2 oxide layer;
15)通过DRIE技术对顶层硅刻蚀完成器件结构，形成完整结构后退火，利用光刻、刻蚀、剥离工艺在测量结构衬底形成铝下电极。15) The device structure is completed by DRIE technology on the top layer silicon to form a complete structure and then annealed, and the aluminum lower electrode is formed on the measurement substrate by photolithography, etching and stripping processes.
值得注意的是，在MEMS测量装置的悬挂电极与衬底之间加入偏置电压，可以耗尽纳米线中导电沟道形成部分区域夹断从而有利于实现纳米线巨压阻特性。It is worth noting that the addition of a bias voltage between the suspension electrode of the MEMS measuring device and the substrate can deplete the pinch-off portion of the conductive channel forming portion in the nanowire to facilitate the nano-scale giant piezoresistive property.
其次完成负荷传感器与位移传感器的校准。装置校准的数据采样率为45Hz。给电热制动器上电后使位移传感器与电热致动器向左移动，读出在显微成像中位移传感器的位移和与位移相对应电容数字转换芯片电路的输 出电压，得到位移传感器分别与相对应的电压输出的关系。使用探针设备推动校正探针移动，读出在显微成像中负荷传感器的位移和与位移相对应电容数字转换芯片电路的输出电压，得到负荷传感器分别与相对应的电压输出的关系。同时使用精密微量天平校准负荷传感器，得到位移与负荷的关系。Secondly, the calibration of the load sensor and the displacement sensor is completed. The data sampling rate for device calibration is 45 Hz. After the electric brake is powered on, the displacement sensor and the electrothermal actuator are moved to the left, and the displacement of the displacement sensor in the microscopic imaging and the displacement of the capacitance digital conversion chip circuit corresponding to the displacement are read out. The voltage is output, and the relationship between the displacement sensors and the corresponding voltage outputs is obtained. The probe device is used to push the calibration probe to move, and the displacement of the load sensor in the microscopic imaging and the output voltage of the capacitance digital conversion chip circuit corresponding to the displacement are read out, and the relationship between the load sensor and the corresponding voltage output is obtained. At the same time, the load cell is calibrated using a precision microbalance to obtain the relationship between displacement and load.
本发明给出了5种具有巨压阻特性的纳米线设置方法，具体如下：The invention provides five nanowire setting methods with giant piezoresistive characteristics, as follows:
实施例1：带银的硅纳米线Example 1: Silicon nanowires with silver
Si纳米线制备的实验过程为:首先用2％的HF溶液(HF:H2O＝1:50)对Si片清洗3分钟，以去除Si片表面的自然氧化层；接着，将硅片先后放入丙酮、双氧水和浓硫酸的混合溶液中进行超声清洗，再用去离子水反复清洗干净；然后利用真空蒸发镀膜机蒸发高纯Au，在Si衬底表面沉积一定厚度的金属催化剂；最后，将沉积好金属催化剂的样品放置在自动控温管式氧化炉的石英管中，在温度为800-1100℃和一定流量的保护气氛下，进行高温退火以生长Si纳米线。用氢氟酸处理掉纳米线上氧化膜，硅的纳米线的表面被氢钝化，把表面被氢所钝化的硅纳米放入硝酸银溶液中，在硅纳米线上制备了银的纳米粒子。The experimental procedure for the preparation of Si nanowires is as follows: firstly, the Si wafer is cleaned with a 2% HF solution (HF: H 2 O = 1:50) for 3 minutes to remove the natural oxide layer on the surface of the Si wafer; It is ultrasonically cleaned in a mixed solution of acetone, hydrogen peroxide and concentrated sulfuric acid, and then repeatedly cleaned with deionized water; then, a high-purity Au is evaporated by a vacuum evaporation coating machine to deposit a certain thickness of the metal catalyst on the surface of the Si substrate; The sample in which the metal catalyst was deposited was placed in a quartz tube of an automatic temperature control tube oxidizing furnace, and subjected to high temperature annealing to grow Si nanowires under a protective atmosphere at a temperature of 800-1100 ° C and a certain flow rate. The oxide film on the nanowire is treated with hydrofluoric acid, the surface of the nanowire of silicon is passivated by hydrogen, and the silicon nanoparticle whose surface is passivated by hydrogen is put into the silver nitrate solution, and the nanometer of silver is prepared on the silicon nanowire. particle.
实施例2：硅锗径向异质结纳米线Example 2: Silicon germanium radial heterojunction nanowires
金纳米簇沉积在氧化的硅晶片，并放置在一石英管式炉。在450℃条件下，使用硅烷作为前导气体，使得硅纳米线芯在轴向约以2μm/min的增长率生长，然后使用硅烷和100ppm氦气的乙硼烷作为前导气体沉积p型硅壳，并以10nm/min的径向生长速率。随后在380℃条件下，锗纳米线10％ 的相关氩气中以轴向生长速率为0.72um/min的速率生长，而锗壳在炉内通过改变生长衬底的位置环境以10nm/min的径向速度沉积。通过重复以上工艺可以完成各种壳核结构的纳米线，如Si/Ge，Ge/Si，或者Si/Ge/Si，Ge/Si/Ge等。其工艺流程图如图4。Gold nanoclusters are deposited on oxidized silicon wafers and placed in a quartz tube furnace. At 450 ° C, silane was used as the lead gas, so that the silicon nanowire core was grown at an axial growth rate of about 2 μm/min, and then p-type silicon shell was deposited using silane and 100 ppm helium diborane as a lead gas. And at a radial growth rate of 10 nm/min. Then at 380 ° C, 锗 nanowire 10% The relevant argon gas was grown at an axial growth rate of 0.72 um/min, and the crucible was deposited in the furnace at a radial velocity of 10 nm/min by changing the positional environment of the growth substrate. Nanowires of various core-shell structures, such as Si/Ge, Ge/Si, or Si/Ge/Si, Ge/Si/Ge, etc., can be completed by repeating the above process. The process flow chart is shown in Figure 4.
实施例3：硅锗纵向异质结纳米线Example 3: Silicon germanium longitudinal heterojunction nanowires
第一步，将用有机溶剂洗好的干净硅片置于真空溅射镀膜仪中，在硅片表面溅射一层大约10nm的锡，加热到600℃，锡团聚成纳米颗粒；第二步，在450-470℃下,通过笨硅烷热分解得到硅烷气，然后将硅烷气体作为前导气体在锡纳米颗粒催化剂层表面生长硅纳米片段，反应完全后通入(Ar+5％H2)气体，清除残余的不同前导气体；第三步，在420-440℃下，将三苯基锗烷液体热分解得到锗烷气体，然后将之作为生长锗纳米片段的前导气体，在硅纳米片段上生长锗纳米片段，反应完全后通入(Ar+5％H2)气体，清除残余的不同前导气体。通过反复重复以上两个步骤形成突变界面的硅锗异质结纳米线，其结构直至生长出合适长度的硅锗异质结纳米线(Si/Ge/Si/Ge)。其工艺流程图如图5。In the first step, a clean silicon wafer washed with an organic solvent is placed in a vacuum sputtering coating machine, and a layer of about 10 nm of tin is sputtered on the surface of the silicon wafer, heated to 600 ° C, and tin is agglomerated into nanoparticles; At 450-470 ° C, silane gas is obtained by thermal decomposition of stupid silane, and then silane gas is used as a lead gas to grow silicon nano-fragments on the surface of the tin nano-particle catalyst layer, and the reaction is completed and then (Ar + 5% H 2 ) gas is introduced. The residual precursor gas is removed; in the third step, the triphenyl decane liquid is thermally decomposed at 420-440 ° C to obtain a decane gas, which is then used as a lead gas for growing the yttrium nano-segment on the silicon nano-fragment. The ruthenium nano-fragment was grown, and after completion of the reaction, an (Ar + 5% H 2 ) gas was introduced to remove residual residual precursor gases. The silicon germanium heterojunction nanowires of the abrupt interface are formed by repeating the above two steps repeatedly, and the structure is until a suitable length of silicon germanium heterojunction nanowires (Si/Ge/Si/Ge) is grown. The process flow chart is shown in Figure 5.
针对上述三种实施案例，利用STM(扫到隧道显微镜)针尖操作将制备完成的纳米线在两个悬挂电极上表面相应位置进行定位、校准、拉紧纳米线等装配操作，利用电子束诱导沉积将纳米线阵列固定在悬挂电极，其效果见图6。For the above three implementation cases, the STM (sweep-to-tunnel microscope) tip operation was used to position, align, and tighten the nanowires on the upper surfaces of the two suspension electrodes, and the electron beam induced deposition. The nanowire array is fixed to the suspension electrode, and the effect is shown in Fig. 6.
实施例4：自生长的表面修饰的硅纳米线Example 4: Self-grown surface-modified silicon nanowires
在模型上形成30-60纳米薄的氧化层，再光刻定位去除槽侧壁的氧化 层，形成生长硅纳米线的窗口。采用光刻辅助定位生长区域，利用电沉积方法在生长区域得到高密度的锡纳米颗粒催化剂，沉积过程中将衬底浸没在含有锡盐溶液、氢氟酸溶液和表面活性剂的微乳液中，成半径为10-20纳米的颗粒。将笨硅烷(PS)在450-470℃下进行热分解，得到硅烷气；后以硅烷气体作为前导气体在锡纳米颗粒催化剂层表面生长硅纳米线，使得悬挂电极通过纳米线阵相连，对纳米线进行Ba,Hf,Zr掺杂的表面修饰处理，提高表面态密度，增加表面效应和压阻特性，如图7所示。A thin oxide layer of 30-60 nm is formed on the model, and then lithographically positioned to remove oxidation of the sidewall of the trench The layer forms a window for growing silicon nanowires. Photolithography is used to assist in locating the growth region, and a high-density tin-nanoparticle catalyst is obtained in the growth region by electrodeposition, and the substrate is immersed in a microemulsion containing a tin salt solution, a hydrofluoric acid solution, and a surfactant during deposition. Particles having a radius of 10-20 nm. The silane (PS) is thermally decomposed at 450-470 ° C to obtain silane gas; then the silane gas is used as a lead gas to grow silicon nanowires on the surface of the tin nanoparticle catalyst layer, so that the suspended electrodes are connected through the nanowire array, and the nano The surface is subjected to surface modification treatment of Ba, Hf, and Zr doping to increase the surface state density and increase the surface effect and piezoresistive characteristics, as shown in FIG.
实施例5：基于MEMS工艺的表面修饰硅纳米线Example 5: Surface Modified Silicon Nanowires Based on MEMS Process
针对上述结构完成了负荷传感器与位移传感器的校准，运用电子束光刻纳米线，完成硅纳米线巨压阻特性测量装置的制备，如图8所示。具体步骤如下：The calibration of the load cell and the displacement sensor was completed for the above structure, and the electron beam lithography nanowire was used to complete the preparation of the silicon nanowire giant piezoresistive characteristic measuring device, as shown in FIG. Specific steps are as follows:
1)选用顶层硅25μm，掩埋氧化层2μm，底层硅300μm的SOI硅片，将硅片先后放入丙酮、双氧水和浓硫酸的混合溶液中进行超声清洗，再用去离子水反复清洗干净；然后将清洗干净的硅片放入稀释的HF溶液中反应，以除去硅片表面的氧化层；1) Select 25μm of top silicon, bury 2μm of oxide layer, 300μm of SOI silicon wafer of bottom silicon, place the silicon wafer in ultrasonic solution of acetone, hydrogen peroxide and concentrated sulfuric acid, then wash it again with deionized water; then The cleaned silicon wafer is placed in a diluted HF solution to remove the oxide layer on the surface of the silicon wafer;
2)通过LPCVD技术在SOI硅片的顶层与底层硅沉积1um的SiO2氧化层；2) 1um oxide layer of SiO 2 is deposited on the top and bottom silicon SOI wafer by LPCVD technique;
3)通过RIE(反应离子蚀刻)技术刻蚀顶层SiO2氧化层形成铂电阻区域；通过DRIE(深反应离子蚀刻)技术刻蚀铂电阻区域； 3) etching a top SiO 2 oxide layer by a RIE (Reactive Ion Etching) technique to form a platinum resistance region; etching the platinum resistance region by a DRIE (Deep Reactive Ion Etching) technique;
4)通过RIE技术刻蚀顶层SiO2氧化层，形成硼掺杂电阻区；通过扩散工艺，在电阻区进行硼掺杂(电阻率：1.7～1.9×10-5Ω·m)，形成P型掺杂硅电阻区；4) etching the top SiO 2 oxide layer by RIE technique to form a boron doped resistance region; boron doping (resistivity: 1.7 to 1.9×10 -5 Ω·m) in the resistance region by a diffusion process to form a P-type Doped silicon resistance region;
5)采用缓冲氧化物蚀刻(BOE)剥离硅表面的SiO2氧化层；5) stripping the SiO 2 oxide layer on the silicon surface by buffer oxide etching (BOE);
6)通过RIE技术刻蚀底层SiO2氧化层，形成绝缘模块图形；6) etching the underlying SiO 2 oxide layer by RIE technique to form an insulating module pattern;
7)在SOI硅片底层旋涂光刻胶；利用掩膜版，光刻形成氧化物层蚀刻掩膜图案；7) spin-coating a photoresist on the bottom layer of the SOI wafer; forming a oxide layer etching mask pattern by using a mask;
8)通过DRIE技术对底层硅刻蚀100μm；8) etching the underlying silicon by 100 μm by DRIE technique;
9)通过RIE技术刻蚀未被光刻胶保护的底层SiO2氧化层；9) etching the underlying SiO 2 oxide layer not protected by the photoresist by an RIE technique;
10)通过DRIE技术对未被光刻胶与氧化层保护的底层硅刻蚀；10) etching the underlying silicon that is not protected by the photoresist and the oxide layer by DRIE technology;
11)通过RIE技术刻蚀SiO2掩埋层，露出绝缘模块，剥离残余光刻胶，底层的SiO2氧化层；11) is etched by RIE techniques the buried SiO 2 layer to expose the insulation module, the peeling residual photoresist, the underlying oxide layer SiO 2;
12)使用正性光刻胶形成铂金电阻图形，采用剥离工艺方法，在SiO2掩埋层上制作出温度单元的铂金电阻；12) forming a platinum resistance pattern using a positive photoresist, and using a stripping process to form a platinum unit of a temperature unit on the SiO 2 buried layer;
13)用LPCVD方法在SOI硅片顶层积淀一层1μm的氮化硅，采用RIE的方法刻蚀出纳米线区域； 13) depositing a layer of 1 μm silicon nitride on the top layer of the SOI silicon wafer by LPCVD method, and etching the nanowire region by RIE;
14)在1100度纯氧环境下氧化上层硅，采用BOE溶液腐蚀掉二氧化硅，然后进行多次同样环境下氧化，腐蚀二氧化硅，直到纳米线厚度达到100nm；对纳米线区域掺杂Hf，Ba或者Zr；14) oxidize the upper layer of silicon in a 1100 degree pure oxygen environment, etch the silicon dioxide with a BOE solution, and then oxidize the same environment multiple times to etch the silicon dioxide until the nanowire thickness reaches 100 nm; doping the nanowire region with Hf , Ba or Zr;
15)用氢氟酸处理掉纳米线上氧化膜，硅的纳米线的表面被氢钝化，把表面被氢所钝化的硅纳米放入硝酸银溶液中，在硅纳米线上制备了银的纳米粒子；采用RIE的方法刻蚀掉残余的氮化硅；15) The oxide film on the nanowire is treated with hydrofluoric acid, the surface of the nanowire of silicon is passivated by hydrogen, and the silicon nanoparticle whose surface is passivated by hydrogen is put into a silver nitrate solution, and silver is prepared on the silicon nanowire. Nanoparticles; RIE is used to etch away residual silicon nitride;
16)使用正性光刻胶形成电极及引线区图形；溅射铝，采用剥离工艺方法，形成及引线与铝电极；16) forming a pattern of electrodes and lead regions using a positive photoresist; sputtering aluminum, forming a lead and an aluminum electrode by a lift-off process;
17)第一步是将SOI硅片旋涂上负光刻胶，涂胶后进行软烘；第二步电子束在光刻胶表面扫描得到需要的各种尺寸的纳米线线条图形及其器件图形；第三步将曝光的图形进行显影，然后去除曝光的部分通过DRIE技术对顶层硅刻蚀完成器件结构；最后将未曝光部分的光刻胶去除。利用光刻、刻蚀、剥离工艺在测量结构衬底形成下电极。17) The first step is to spin-coat the SOI wafer on the negative photoresist, and then soft-bake after coating the glue; the second step is to scan the surface of the photoresist to obtain the required nano-line pattern and device of various sizes. The third step is to develop the exposed pattern, and then remove the exposed portion to complete the device structure by the DRIE technique on the top silicon; finally, remove the unexposed portion of the photoresist. A lower electrode is formed on the measurement structure substrate by a photolithography, etching, and lift-off process.
然后，求得纳米线初始电阻。如图9所示，通过水平方向两个电极为纳米线提供恒流源I，垂直方向两个电极为纳米线提供电压V0，得到纳米线的初始电阻
Figure PCTCN2016102073-appb-000001
d1垂直方向两个电极之间纳米线的距离，d0水平方向两个电极之间纳米线的距离；如前面所强调的，同时在纳米线悬挂电极与衬底之间加入偏置电压，耗尽纳米线导电沟道形成部分区域夹断可有利于充分实现纳米线巨压阻特性。 Then, the initial resistance of the nanowire is obtained. 9, the horizontal direction is provided by two electrodes nanowires constant current source I, two vertical electrodes provide a voltage V 0 nanowires, the nanowires to give the initial resistance
Figure PCTCN2016102073-appb-000001
D1 The distance between the nanowires between the two electrodes in the vertical direction, and the distance between the nanowires between the two electrodes in the horizontal direction of d0; as previously emphasized, a bias voltage is applied between the suspension electrode of the nanowire and the substrate, and the depletion is performed. The pinch-off of the nanowire conductive channel forming portion can facilitate the full realization of the nanowire giant piezoresistive property.
随之，为电热致动器提供电压，使整个装置工作。电热致动器作为驱动装置通过绝缘模块推动位移电容传感器向左移动移动，同时通过绝缘模块拉动纳米线向左移动，纳米线通过绝缘模块拉动负荷传感器向左移动。纳米线拉伸长度ds为纳米为位移传感器的位移da减去负荷传感器的位移df，求得纳米线应变ε＝ds/d0。纳米线长度伸长度ds后,垂直方向两个电极的电压变为V1,纳米线变化后的电阻R1为
Figure PCTCN2016102073-appb-000002
ΔR＝R1-R0。通过压阻系数
Figure PCTCN2016102073-appb-000003
表征压阻效应。Along with this, a voltage is supplied to the electrothermal actuator to operate the entire device. The electrothermal actuator acts as a driving device to push the displacement capacitance sensor to move to the left through the insulation module, and simultaneously pulls the nanowire to the left through the insulation module, and the nanowire moves the load sensor to the left through the insulation module. The nanowire tensile length d s is nanometer as the displacement d a of the displacement sensor minus the displacement d f of the load cell, and the nanowire strain ε=d s /d 0 is obtained . After the length of the nanowire is d s , the voltage of the two electrodes in the vertical direction becomes V 1 , and the resistance R 1 after the change of the nanowire is
Figure PCTCN2016102073-appb-000002
ΔR = R 1 - R 0 . Piezoresistive coefficient
Figure PCTCN2016102073-appb-000003
Characterize the piezoresistive effect.
如图10，由于纳米线的样品成为该装置的测试过程中的机械***的一部分，ksds＝kfdf；Fa＝kada+ksds，其中ks、ka、kf分别为纳米线、负荷传感器、电热致动器的刚度；ds、da、df分别为纳米线、负荷传感器、电热致动器的位移；电热致动器产生的力Fa＝2NEAαΔTsinθ，其中α是硅的热膨胀系数，ΔT是V型梁的平均温度，N是V型梁的数目，A是V型梁的横截面积。纳米线的刚度ks可由输出电压所对应的负荷传感器负荷与位移之比得到。可得纳米线刚度ks＝F/ds，纳米线应力δ＝F/S，F为负荷传感器负荷，S为纳米线的横截面积。从而得到纳米线杨氏模E＝δ/ε。As shown in Figure 10, since the sample of the nanowire becomes part of the mechanical system during the testing of the device, k s d s = k f d f; F a = k a d a + k s d s , where k s , k a , k f are the stiffness of the nanowire, load cell, and electrothermal actuator; d s , d a , d f are the displacement of the nanowire, load cell, and electrothermal actuator, respectively; and the force F generated by the electrothermal actuator a = 2NEAαΔTsinθ, where α is the thermal expansion coefficient of silicon, ΔT is the average temperature of the V-shaped beam, N being the number of V-shaped beam, a is the cross sectional area of the V-beam. The stiffness k s of the nanowire can be obtained by the ratio of load sensor load to displacement corresponding to the output voltage. The nanowire stiffness k s =F/d s , the nanowire stress δ=F/S, F is the load sensor load, and S is the cross-sectional area of the nanowire. Thus, the nanowire Young's modulus E = δ / ε is obtained.
通过以上步骤完成了纳米线机械特性与电气特性的测量，同时表征了纳米线的巨压阻效应。在测量过程中，被测样品的温度和电阻率有直接的关系，从而影响压阻系数的测量，所以在测量之前首先要掌握被测样品的温度，如果测量时样片的温度不在适合测量的范围，就会影响到最终的压阻系数，则必须采用基于改进遗传算法的小波神经网络模型进行修正，具体流程如图11所示： Through the above steps, the mechanical properties and electrical properties of the nanowires were measured, and the giant piezoresistive effect of the nanowires was characterized. During the measurement process, the temperature and resistivity of the sample to be tested have a direct relationship, which affects the measurement of the piezoresistive coefficient. Therefore, the temperature of the sample to be tested must be grasped before the measurement. If the temperature of the sample is not suitable for the measurement. , will affect the final piezoresistive coefficient, it must be modified based on the improved genetic algorithm wavelet neural network model, the specific process shown in Figure 11:
步骤1：种群初始化：随机初始化种群，对小波神经网络输入层和隐层之间的链接权值、隐层到输出层的链接权值、伸缩银子和平移因子进行编码，产生一定规模的初始化种群。Step 1: Population initialization: randomly initialize the population, encode the link weight between the input layer and the hidden layer of the wavelet neural network, the link weight of the hidden layer to the output layer, the scaled silver and the translation factor, and generate an initial population of a certain scale. .
步骤2：根据个体得到的小波神经网络的链接权值，伸缩和平移因子。输入测量得到的压阻系数与温度数据作为训练数据，训练小波神经网络后得到***的预测输出与目标值之间的误差作为适应值F。Step 2: According to the link weight, expansion and translation factor of the wavelet neural network obtained by the individual. The measured piezoresistive coefficient and temperature data are input as training data, and the error between the predicted output and the target value of the system is obtained as the fitness value F after training the wavelet neural network.
步骤3：进行选择，交叉和变异操作。Step 3: Perform selection, crossover and mutation operations.
步骤4：判断进化是否结束，这里由两个结束条件：适应度值是否满足关系，遗传算法达到设定的迭代数，满足这两个条件就可以利用搜索完成的权值，伸缩和平移因子进行小波神经网络计算。Step 4: Determine whether the evolution is over. Here are two end conditions: whether the fitness value satisfies the relationship, and the genetic algorithm reaches the set number of iterations. After satisfying these two conditions, the weight, scaling and translation factors of the search can be used. Wavelet neural network calculation.
本发明通过纳米线巨压阻特性测量装置及其MEMS测量方法，实现多种测量样本的机械特性与电气特性的测量，并表征压阻系数。可以拓展到其他类型的纳米线，比如金属-硅异质结纳米线的力学、电学和压阻特性的测量。The invention realizes the measurement of mechanical characteristics and electrical characteristics of various measurement samples through the nanowire giant piezoresistive characteristic measuring device and the MEMS measuring method thereof, and characterizes the piezoresistive coefficient. It can be extended to other types of nanowires, such as the measurement of mechanical, electrical and piezoresistive properties of metal-silicon heterojunction nanowires.
以上所述仅是本发明的优选实施方式，应当指出：对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。 The above description is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art can also make several improvements and retouchings without departing from the principles of the present invention. It should be considered as the scope of protection of the present invention.

Claims (8)

  1. 一种纳米线巨压阻特性测量装置，其特征在于：包括：纳米线、铂电阻温度传感器、电热致动器、基于电容测量的位移传感器、电极、基于电容测量的负荷传感器，所述铂电阻温度传感器、电热致动器、基于电容测量的位移传感器、基于电容测量的负荷传感器依次连接，所述电极数量设置为四个，所述四个电极设置在基于电容测量的位移传感器与基于电容测量的负荷传感器之间，两个水平放置的电极之间设置有纳米线，所述纳米线上下两侧均设置有电极。A nanowire giant piezoresistive characteristic measuring device, comprising: a nanowire, a platinum resistance temperature sensor, an electrothermal actuator, a displacement sensor based on capacitance measurement, an electrode, a load sensor based on capacitance measurement, the platinum resistance A temperature sensor, an electrothermal actuator, a displacement sensor based on capacitance measurement, a load sensor based on capacitance measurement are sequentially connected, the number of electrodes is set to four, and the four electrodes are disposed on a displacement sensor based on capacitance measurement and based on capacitance measurement Between the load sensors, nanowires are disposed between the two horizontally placed electrodes, and electrodes are disposed on both sides of the nanowires.
  2. 根据权利要求1所述的纳米线巨压阻特性测量装置，其特征在于：还包括校准探针，所述校准探针与基于电容测量的负荷传感器相连接。The nanowire giant piezoresistive characteristic measuring apparatus according to claim 1, further comprising a calibration probe connected to the load sensor based on the capacitance measurement.
  3. 根据权利要求2所述的纳米线巨压阻特性测量装置及其制造方法，还包括电气绝缘模块，其特征在于：所述电热致动器与基于电容测量的位移传感器之间，基于电容测量的位移传感器与电极之间，电极与基于电容测量的负荷传感器之间，基于电容测量的负荷传感器与校准探针之间均设置有电气绝缘模块。The nanowire giant piezoresistive characteristic measuring device and the method of manufacturing the same according to claim 2, further comprising an electrical insulation module, wherein the electrothermal actuator and the displacement sensor based on capacitance measurement are based on capacitance measurement An electrical insulation module is disposed between the displacement sensor and the electrode, between the electrode and the load sensor based on the capacitance measurement, and between the load sensor based on the capacitance measurement and the calibration probe.
  4. 根据权利要求1所述的纳米线巨压阻特性测量装置中设置纳米线的方法，其特征在于：所述纳米线采用外生长硅纳米线，通过在纳米线上制备银的纳米粒子对其进行表面修饰形成巨压阻特性。The method for disposing nanowires in a nanowire giant piezoresistive characteristic measuring device according to claim 1, wherein the nanowires are grown by using externally grown silicon nanowires by preparing silver nanoparticles on the nanowires. The surface modification forms a giant piezoresistive property.
  5. 根据权利要求1所述的纳米线巨压阻特性测量装置中设置纳米线的方法，其特征在于：所述纳米线采用化学气相沉积方法，基于径向与轴向生长的控制合成具有巨压阻特性的硅锗径向异质结构纳米线。The method for setting nanowires in a nanowire giant piezoresistive characteristic measuring device according to claim 1, wherein the nanowires are chemical vapor deposition, and the composite pressure based on radial and axial growth has a giant piezoresistive resistance. Characteristics of silicon germanium radial heterostructure nanowires.
  6. 根据权利要求1所述的纳米线巨压阻特性测量装置中设置纳米线的方 法，其特征在于：所述纳米线采用溶液气象法自生长自组装具有巨压阻特性的硅锗纵向异质结纳米线。The method for setting a nanowire in a nanowire giant piezoresistive characteristic measuring device according to claim The method is characterized in that: the nanowire adopts a solution meteorological method to self-assemble and assemble a silicon germanium longitudinal heterojunction nanowire having a giant piezoresistive property.
  7. 根据权利要求1所述的纳米线巨压阻特性测量装置中设置纳米线的方法，其特征在于：所述纳米线采用STM针尖操作将制备完成的具有巨压阻特性的纳米线在两个悬挂电极上表面相应位置进行定位、校准、拉紧纳米线等装配操作，利用电子束诱导沉积将纳米线阵列固定在悬挂电极上。The method for setting nanowires in a nanowire giant piezoresistive characteristic measuring device according to claim 1, wherein the nanowires are operated by an STM tip to prepare the nanowires having giant piezoresistive characteristics in two suspensions. The corresponding positions on the upper surface of the electrode are used for positioning, aligning, and tightening the nanowires, and the nanowire array is fixed on the suspension electrode by electron beam induced deposition.
  8. 纳米线巨压阻特性测量装置制造方法，其特征在于：包括如下步骤：A method for manufacturing a nanowire giant piezoresistive characteristic measuring device, comprising: the following steps:
    步骤一：选用顶层硅25μm，掩埋氧化层2μm，底层硅300μm的SOI硅片，将硅片先后放入丙酮、双氧水和浓硫酸的混合溶液中进行超声清洗，再用去离子水反复清洗干净；然后将清洗干净的硅片放入稀释的HF溶液中反应，以除去硅片表面的氧化层；Step 1: Select 25 μm of top silicon, bury 2 μm of oxide layer, and 300 μm of SOI silicon wafer of bottom silicon. The silicon wafer is placed in a mixed solution of acetone, hydrogen peroxide and concentrated sulfuric acid for ultrasonic cleaning, and then repeatedly cleaned with deionized water. Then, the cleaned silicon wafer is placed in a diluted HF solution to remove the oxide layer on the surface of the silicon wafer;
    步骤二：通过LPCVD技术在SOI硅片的顶层与底层硅沉积1μm的SiO2氧化层；Step two: 1μm oxide layer of SiO 2 is deposited on the top and bottom silicon SOI wafer by LPCVD technique;
    步骤三：通过RIE技术刻蚀顶层SiO2氧化层形成铂电阻区域；通过DRIE技术刻蚀铂电阻区域；Step 3: etching a top SiO 2 oxide layer by a RIE technique to form a platinum resistance region; etching the platinum resistance region by a DRIE technique;
    步骤四：通过RIE技术刻蚀顶层SiO2氧化层，形成硼掺杂电阻区；通过扩散工艺，在电阻区进行硼掺杂，所述电阻区的电阻率设置为1.7～1.9×10-5Ω·m，形成P型掺杂硅电阻区；Step 4: etching the top SiO 2 oxide layer by RIE technique to form a boron doped resistance region; boron doping is performed in the resistance region by a diffusion process, and the resistivity of the resistive region is set to 1.7 to 1.9×10 −5 Ω · m, forming a P-type doped silicon resistance region;
    步骤五：采用缓冲氧化物蚀刻BOE剥离硅表面的SiO2氧化层；Step 5: etching the SiO 2 oxide layer on the silicon surface by BOE using a buffer oxide;
    步骤六：通过RIE技术刻蚀底层SiO2氧化层，形成绝缘模块图形； Step 6: etching the underlying SiO 2 oxide layer by an RIE technique to form an insulating module pattern;
    步骤七：在SOI硅片底层旋涂光刻胶；利用掩膜版，光刻形成氧化物层蚀刻掩膜图案；Step 7: spin-coating a photoresist on the bottom layer of the SOI silicon wafer; forming a oxide layer etching mask pattern by using a mask;
    步骤八：通过DRIE技术对底层硅刻蚀100μm；Step 8: etching the underlying silicon by 100 μm by DRIE technology;
    步骤九：通过RIE技术刻蚀未被光刻胶保护的底层SiO2氧化层；Step 9: etching the underlying SiO 2 oxide layer not protected by the photoresist by an RIE technique;
    步骤十：通过DRIE技术对未被光刻胶与氧化层保护的底层硅刻蚀；Step 10: etching the underlying silicon not protected by the photoresist and the oxide layer by DRIE technology;
    步骤十一：使用正性光刻胶形成铂金电阻图形，采用剥离工艺方法，在SiO2掩埋层上制作出温度单元的铂金电阻；Step 11: forming a platinum resistive pattern using a positive photoresist, and using a stripping process to form a platinum unit of a temperature unit on the SiO 2 buried layer;
    步骤十二：使用正性光刻胶形成电极及引线区图形；溅射铝，采用剥离工艺方法，形成引线与铝上电极；Step 12: forming a pattern of electrodes and lead regions using a positive photoresist; sputtering aluminum, using a stripping process to form leads and an aluminum upper electrode;
    步骤十三：通过RIE技术刻蚀SiO2掩埋层，露出绝缘模块；Step 13: etching the SiO2 buried layer by RIE technology to expose the insulating module;
    步骤十四：剥离残余光刻胶，底层的SiO2氧化层；Step 14: stripping the residual photoresist, the underlying SiO 2 oxide layer;
    步骤十五：通过DRIE技术对顶层硅刻蚀完成器件结构，形成完整结构后退火，利用光刻、刻蚀、剥离工艺在测量结构衬底形成铝下电极。 Step 15: The device structure is completed by DRIE technology on the top layer silicon to form a complete structure and then annealed, and the aluminum lower electrode is formed on the measurement substrate by photolithography, etching, and stripping processes.
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