WO2018227422A1 - 一种开关电源及其软启动电路 - Google Patents

一种开关电源及其软启动电路 Download PDF

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Publication number
WO2018227422A1
WO2018227422A1 PCT/CN2017/088215 CN2017088215W WO2018227422A1 WO 2018227422 A1 WO2018227422 A1 WO 2018227422A1 CN 2017088215 W CN2017088215 W CN 2017088215W WO 2018227422 A1 WO2018227422 A1 WO 2018227422A1
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Prior art keywords
switch
power supply
voltage
switching power
resistor
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PCT/CN2017/088215
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English (en)
French (fr)
Inventor
陈忠
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上海明石光电科技有限公司
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Priority to PCT/CN2017/088215 priority Critical patent/WO2018227422A1/zh
Publication of WO2018227422A1 publication Critical patent/WO2018227422A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters

Definitions

  • the invention relates to the technical field of switching power supplies, and in particular to a switching power supply and a soft start circuit thereof.
  • Switching power supplies have been widely used in various power supply applications due to high conversion efficiency and high power density. Since the power conversion component of the power converter in the switching power supply operates at a high frequency, a filter capacitor C is usually provided at the input end of the rear converter to filter out high frequency noise and improve external electromagnetic interference; It is a schematic diagram of the structure of a common switching power supply.
  • a charging current Ich will be generated.
  • the filter inductor L and the rectifier bridge are used to charge the filter capacitor C.
  • the resistive impedance of the charging circuit is very high. Small, and the phase of the AC mains AC is random, and may be near the peak of the AC voltage close to 90 degrees at the instant of starting, so the peak value of the charging current Ich may be large, such as amps or ten amps or more.
  • the startup surge current that becomes the switching power supply generates large current stress on the input device of the switching power supply and may even cause damage to these devices.
  • a negative temperature coefficient thermistor NTC is serially connected to the input end of the switching power supply.
  • the switch K0 When the switch K0 is closed, the magnitude of the charging current of the filter capacitor C is limited by the resistance of the thermistor NTC, thereby reducing the amplitude of the starting surge current to some extent.
  • the resistance of the thermistor NTC is usually selected from 10 to 20 ohms. This resistance is not significantly reduced. The magnitude of the small inrush current is not sufficient to significantly reduce the magnitude of the startup surge voltage on the filter capacitor after the rectifier bridge.
  • the present invention provides a switching power supply and a soft start circuit thereof to solve the prior art.
  • the problem of starting surge current and starting surge voltage cannot be effectively reduced.
  • a soft start circuit of a switching power supply is connected between a filter capacitor of a switching power supply and a reference ground;
  • the soft start circuit of the switching power supply includes: a control unit, an on/off switch, a first resistor, a second resistor, and a third resistor ;among them:
  • the first resistor and the second resistor are connected in series between the filter capacitor and a reference ground, and the connection point in series is connected to the first input end of the control unit;
  • the on/off switch and the third resistor are connected in series between the filter capacitor and a reference ground;
  • the second resistor and the third resistor are both connected to a reference ground;
  • the sum of the resistances of the first resistor and the second resistor is greater than or equal to 100 kilohms;
  • the control unit is configured to generate a control signal according to the voltage sampling signal received by the first input terminal, and output the control signal to the control end of the on/off switch to enable the on and off in an initial stage after the switching power supply is powered on
  • the switch is kept in an off state, and the on/off switch is controlled to be turned on and off in a preset state after the switching power supply is powered on, so that the filter capacitor is intermittently charged under a preset differential pressure. And controlling the on/off switch to remain in an on state after the voltage on the filter capacitor satisfies a preset condition and after the switch power supply is turned on.
  • the initial phase, the adjustment phase, and the locking phase are all divided by a corresponding preset duration
  • the preset condition is that the amplitude of the voltage sampling signal is less than a preset amplitude.
  • the ratio of the resistance of the first resistor to the second resistor is less than a preset ratio.
  • the preset rule is: controlling the on/off switch to be turned on when the voltage sampling signal falls to the reference voltage reference signal; and controlling the on/off switch to be turned off after a preset on-time .
  • connection point of the on/off switch in series with the third resistor is connected to a second input end of the control unit;
  • the control signal is a voltage sampling signal received by the control unit according to the first input end and a Generated by the current sampling signal received by the two inputs;
  • the preset rule is: when the voltage sampling signal falls to the reference voltage reference signal, the on/off switch is controlled to be turned on; and when the current sampling signal crosses zero, the on/off switch is controlled to be turned off;
  • the preset rule is: when the voltage sampling signal falls to the reference voltage reference signal, controlling the on/off switch to be turned on; and after the preset on-time, or when the current sampling signal crosses zero And controlling the on/off switch to be turned off.
  • control unit comprises: a first hysteresis comparator, a first start timer, a first monostable timer, a first D flip-flop and a first OR gate; wherein:
  • the non-inverting input terminal of the first hysteresis comparator receives the voltage sampling signal
  • the inverting input terminal of the first hysteresis comparator receives the reference voltage reference signal
  • An output of the first hysteresis comparator is coupled to an input of the first monostable timer
  • the output end of the first start timer is connected to the data end of the first D flip-flop
  • An output end of the first monostable timer is connected to a rising edge trigger end of the first D flip-flop and an input end of the first OR gate;
  • An output end of the first D flip-flop is connected to another input end of the first OR gate
  • the output of the first OR gate outputs the control signal.
  • the preset rule is: controlling the on/off switch to be turned on when the voltage sampling signal falls to a reference voltage reference signal; and controlling the on/off switch when the current sampling signal crosses zero
  • the control unit includes: a second hysteresis comparator, a first zero-crossing comparator, a second start timer, an edge trigger, a second D flip-flop, and a second OR gate; wherein:
  • the non-inverting input terminal of the second hysteresis comparator receives the voltage sampling signal
  • the inverting input terminal of the second hysteresis comparator receives the reference voltage reference signal
  • An output end of the second hysteresis comparator is connected to a set end of the edge trigger
  • the input end of the first zero-crossing comparator receives the current sampling signal
  • An output end of the first zero-crossing comparator is connected to a reset end of the edge trigger
  • the output end of the second start timer is connected to the data end of the second D flip-flop
  • An output end of the edge trigger is connected to a rising edge trigger end of the second D flip-flop and an input end of the OR gate;
  • An output end of the second D flip-flop is connected to another input end of the second OR gate
  • the preset rule is: controlling the on/off switch to be turned on when the voltage sampling signal falls to the reference voltage reference signal; and after the preset on-time, or when the current sampling signal crosses zero, the control is When the on/off switch is turned off, the control unit includes: a third hysteresis comparator, a second zero-crossing comparator, a third start timer, a second monostable timer, a third D flip-flop, and a Tri-or gate and fourth or gate; where:
  • the non-inverting input terminal of the third hysteresis comparator receives the voltage sampling signal
  • the inverting input terminal of the third hysteresis comparator receives the reference voltage reference signal
  • An output of the third hysteresis comparator is coupled to an input of the second monostable timer
  • An output of the second monostable timer is coupled to an input of the third OR gate
  • the input end of the second zero-crossing comparator receives the current sampling signal
  • An output of the second zero-crossing comparator is coupled to another input of the third OR gate
  • the output end of the third start timer is connected to the data end of the third D flip-flop
  • An output end of the third OR gate is connected to a rising edge trigger end of the third D flip-flop and an input end of the fourth OR gate;
  • An output end of the third D flip-flop is connected to another input end of the fourth OR gate
  • the output of the fourth OR gate outputs the control signal.
  • control unit is: a single chip microcomputer or a programmable logic controller PLC.
  • control unit is disposed on the integrated circuit chip, or the control unit and the on/off switch are both disposed on the integrated circuit chip.
  • a switching power supply comprising: a filter inductor, a mains switch, a rectifier bridge, a filter capacitor, a post-stage converter, and a soft start circuit of the switching power supply of any of the above;
  • the AC mains is connected to the two input ends of the rectifier bridge via the filter inductor and the mains switch respectively;
  • the positive end of the output end of the rectifier bridge is sequentially connected to the negative end of the output end of the rectifier bridge and the reference ground through the filter capacitor and the soft start circuit of the switching power supply;
  • the post-stage converter is connected in parallel with the filter capacitor.
  • the application provides a soft start circuit of a switching power supply, which is controlled by a control unit to output a control signal to the control end of the on/off switch, so that the on/off switch remains in an off state during an initial phase after the switching power supply is powered on, and the filter capacitor is passed through at this time.
  • the limitation of the first resistance and the second resistance of the large resistance value in series keeps the charging current of the filter capacitor in a small range and the charging voltage grows slowly; and controls the on/off switch in the adjustment phase after the switching power supply is powered on
  • the filter capacitor is intermittently charged under a preset differential pressure to ensure that each charging current is small, and the charging voltage exhibits step-by-cycle step-by-step climbing; finally, the on-off switch is controlled.
  • the switch capacitor remains in the on state, so that the filter capacitor does not have a large charging current before the inverter enters the normal working state.
  • Charging voltage step The circuit is controlled by the control unit, so that the charging current on the filter capacitor is small and the charging voltage can be gradually increased in the above stage after the power is turned on, thereby effectively reducing the startup surge current of the switching power supply and starting up. Surge voltage.
  • FIG. 1 is a schematic structural view of a switching power supply provided by the prior art
  • FIG. 2 is a schematic diagram of waveforms of a switching power supply provided by the prior art
  • FIG. 3 is a schematic structural diagram of a switching power supply provided by the prior art
  • FIG. 4 is a schematic structural diagram of a switching power supply provided by the prior art
  • FIG. 5 is a schematic structural diagram of a switching power supply according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a switching power supply according to another embodiment of the present application.
  • FIG. 7 is a schematic diagram of a waveform of an initial stage after a switching power supply is powered on according to another embodiment of the present application.
  • FIG. 8 is a schematic diagram of waveforms of a regulation phase after powering on a switching power supply according to another embodiment of the present application.
  • FIG. 9 is a schematic diagram of a waveform entering a locking phase after powering on a switching power supply according to another embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a control unit according to another embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a waveform of a adjustment phase after a switching power supply is powered on according to another embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a control unit according to another embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a control unit according to another embodiment of the present application.
  • the invention provides a soft start circuit of a switching power supply to solve the problem that the prior art cannot effectively reduce the startup surge current and the startup surge voltage.
  • the soft start circuit of the switching power supply is connected between the filter capacitor C of the switching power supply and the reference ground;
  • the soft start circuit of the switching power supply is as shown in the broken line frame in FIG. 5: the control unit, The on/off switch K1, the first resistor R1, the second resistor R2, and the third resistor R3; wherein:
  • the first resistor R1 and the second resistor R2 are connected in series between the filter capacitor C and the reference ground, and the connection point of the series is connected to the first input end of the control unit;
  • the on/off switch K1 and the third resistor R3 are connected in series between the filter capacitor C and the reference ground;
  • the second resistor R2 and the third resistor R3 are both connected to a reference ground;
  • the sum of the resistances of the first resistor R1 and the second resistor R2 is greater than or equal to 100 kilohms; preferably, the sum of the resistances of the first resistor R1 and the second resistor R2 may be in the order of one hundred kiloohms or megaohms; It is not specifically limited, and it is within the scope of protection of this application depending on its specific application environment.
  • the control unit is configured to generate a control signal according to the voltage sampling signal VS1 received by the first input terminal, and output the control signal to the control end of the on/off switch K1 to disconnect the current during the initial stage after the switching power supply is powered on.
  • the K1 keeps the off state, and the control on/off switch K1 is turned on and off in a preset state after the switching power supply is powered on, so that the filter capacitor C is intermittently charged under the preset differential pressure, and is controlled.
  • the on/off switch K1 maintains an on state after the voltage on the filter capacitor C satisfies the preset condition and is turned on in the lock phase after the switching power supply is powered on.
  • the on/off switch K1 may be a field effect transistor, or a bipolar transistor, or an insulated gate field effect transistor, or a switching device such as a thyristor device, which is not specifically limited herein, depending on the specific application environment, Within the scope of protection of this application.
  • the control signal outputted to the control terminal of the on/off switch K1 by the control unit causes the on/off switch K1 to remain in the off state in the initial stage after the switching power supply is powered on, and at this time, the first resistance of the large resistance value connected in series with the filter capacitor C
  • the limitation of R1 and the second resistor R2 is such that the charging current of the filter capacitor C is kept in a small range and the charging voltage is slowly increased; and the on-off switch K1 is controlled by a preset rule during the adjustment phase after the switching power supply is powered on.
  • the filter capacitor C is intermittently charged under a preset differential pressure to ensure that each charging current is small, and the charging voltage is stepped up by cycle; finally, the on/off switch K1 is controlled on the switching power supply. After the conduction in the lock phase after the electric conduction, the conduction state is maintained, so that the filter capacitor C does not have a large charging current and a charging voltage step before the post-stage converter enters the normal working state.
  • the initial phase, the adjustment phase and the locking phase are divided by a corresponding preset duration, that is, the preset condition is that the adjustment phase duration reaches a corresponding preset duration.
  • the preset duration can be obtained according to analysis or experiment, and the preset duration of each phase is set by the control unit; for example, in the initial stage, the output of the control unit keeps the on/off switch K1 closed.
  • the off state after several tens of milliseconds after the start of the initial phase, the control unit starts to work, and the on/off switch K1 is controlled to be turned on and off, so that the switching power supply enters the adjustment phase; by adjusting the preset period of time by the adjustment phase, it may be several Milliseconds to a few seconds, according to actual needs, the amplitude of the voltage sampling signal should be less than the preset amplitude, the voltage on the filter capacitor C (AC mains AC minus the first resistor R1 and the second resistor R2 The voltage divider gradually rises to the appropriate voltage, and the rear converter will enter the normal working state. At this time, the control unit controls the on/off switch K1 to be turned on, so that the switching power supply will enter the locking phase.
  • the preset condition is that the amplitude of the voltage sampling signal is less than a preset amplitude, that is, the locking phase is powered.
  • the time at which the amplitude of the voltage sampling signal VS1 is less than the preset amplitude is the starting time.
  • the amplitude of the voltage sampling signal VS1 is less than the preset amplitude, indicating that the voltage on the filter capacitor C has risen to a suitable voltage, the latter converter can enter a normal working state, and the control unit will control the switching power supply to enter the locking phase.
  • control unit For the division of the above-mentioned various stages, it can be set by the control unit according to the specific practical application environment, and is not specifically limited herein, and is within the protection scope of the present application.
  • the prior art also has the technical solution shown in FIG. 4: when the switch K0 is closed and the power is turned on, the switch unit K1 is first turned off by the delay unit, and the AC mains AC pairs the filter capacitor C.
  • the charging circuit includes a series resistor R.
  • the resistance of this resistor R is usually selected to be several hundred ohms, which is enough to limit the magnitude of the charging current, thereby suppressing excessive startup surge current and starting surge voltage.
  • the delay unit controls the switch K1 to close, thereby reducing the excessive power consumption that may occur on the resistor R.
  • the post-stage converter starts to work, and the operating current required for the operation of the post-stage converter flows through the switch K1 without passing through the resistor R.
  • the switch K1 is closed by the delay, the impedance of the charging circuit becomes smaller again, and a slightly smaller inrush current is still generated.
  • the soft start circuit of the switching power supply provided by the embodiment is controlled by the control unit, so that the charging current of the filter capacitor C is compared in each of the above stages after the power is turned on.
  • the charging voltage can be gradually increased, thereby significantly suppressing the amplitude of the starting surge current of the switching power supply, and at the same time, the voltage across the filter capacitor C required for the operation of the rear converter is slowly increased, thereby eliminating the Surge voltage overshoot at both ends of the filter capacitor C.
  • this control process there is no possibility that the electronic device is subjected to excessive current stress or voltage stress, that is, the reliability of the power supply product can be improved by the above soft start process.
  • control unit capable of realizing the above functions may be in various forms according to specific application environments, and in particular, for the preset rules of the adjustment phase, the specific implementation form of the control unit may be various.
  • connection point of the on/off switch K1 and the third resistor R3 in series is connected to the second input end of the control unit;
  • control signal is generated by the control unit according to the voltage sampling signal VS1 received by the first input terminal and the current sampling signal VS2 received by the second input terminal;
  • the corresponding preset rule is: when the voltage sampling signal VS1 falls to the reference voltage reference signal, the control on/off switch K1 is turned on; and when the current sampling signal VS2 crosses zero, the control on/off switch K1 is turned off.
  • the charging circuit of the AC mains AC to the filter capacitor C includes a first resistor R1 and a second resistor R2, and the sum of the resistances of the first resistor R1 and the second resistor R2 is relatively large, and is greater than or equal to 100 thousand. Ohm, such as 1 mega ohm or more, makes the charging current to the filter capacitor C very small, less than 1 mA.
  • Figure 7 shows the signal waveform of the switching power supply in the initial stage.
  • the sinusoidal voltage of the AC mains AC (the first waveform in Figure 7) is filtered by the inductor L, the rectifier bridge, the first resistor R1 and the second in series.
  • the resistor R2 charges the filter capacitor C. Since the sum of the resistances of the first resistor R1 and the second resistor R2 is large, the charging current is small, and the charging circuit has a large time constant, so that the voltage across the filter capacitor C is presented.
  • the process of slowly rising (the second waveform in Figure 7).
  • the voltage drop across the high-frequency filter inductor L is negligible, and the conduction voltage drop of the rectifier diode in the rectifier bridge is negligible. Therefore, in the case that the on/off switch K1 is kept off, the voltage at one end of the reference ground, that is, the voltage at the connection point of the filter capacitor C and the first resistor R1, can be expressed as an AC sinusoidal mains voltage (after rectification).
  • the voltage obtained by subtracting the voltage across the filter capacitor C that is, the third waveform in FIG. This waveform is characterized by a rectified local sine wave with dead time, and as the voltage across the filter capacitor C rises due to charging, the dead time of this local sine wave gradually increases and the amplitude decreasing gradually.
  • the fourth waveform in FIG. 7 is the voltage waveform of the reference ground at the connection point of the first sampling resistor R1 and the second resistor R2, that is, the waveform of the voltage sampling signal VS1 sent to the first input end of the control unit, which is only FIG.
  • the waveform of the third waveform is obtained by simple voltage division of the first resistor R1 and the second resistor R2.
  • the on/off switch K1 is kept in the off state, and thus the current sampling resistor in series with the on/off switch K1, that is, the third resistor R3, the sampled signal is always Zero, that is, the current sampling signal VS2 sent to the second input of the control unit is always Zero.
  • the current sampling signal VS2 is a signal that characterizes the value of the current flowing through the on/off switch K1 by a voltage value.
  • control unit can start working after an appropriate delay waiting time, such as several tens of milliseconds, so that the switching power supply enters the adjustment phase.
  • the #1 waveform is the voltage waveform of the AC mains AC received by the switching power supply;
  • #2 waveform is the current waveform of the AC mains AC received by the switching power supply
  • the #3 waveform is the voltage waveform across the filter capacitor C. This voltage is used to power the post-stage converter.
  • the waveform of #4 is a voltage waveform of one end of the on/off switch K1 relative to the reference ground, that is, a voltage waveform of the filter capacitor C and the first resistor R1 at a reference ground;
  • the #5 waveform is a waveform of the voltage sampling signal VS1 sent to the first input end of the control unit after being divided by the resistor;
  • the waveform of #6 is the waveform of the control signal output by the control unit, and the control signal is sent to the control end of the on/off switch K1;
  • the #7 waveform is a voltage signal on the third resistor R3 in series with the on/off switch K1, that is, the current sampling signal VS2 is sent to the second input end of the control unit;
  • control unit In the adjustment phase, the control unit first maintains the output control signal at a low level, so that the on/off switch K1 remains in the off state while monitoring the falling process of the voltage sampling signal VS1.
  • the control unit compares the received voltage sampling signal VS1 with the reference voltage reference signal Vref1 inside the control unit, as shown in the fifth waveform in FIG.
  • the control signal outputted by the control unit becomes a high level corresponding to the time t1 in FIG. 8, so that the on/off switch K1 enters an on state.
  • the on/off switch K1 is kept in the on state, since the on-resistance of the on/off switch K1 is small, and the resistance of the third resistor R3 connected in series is also small, the potential of one end of the on/off switch K1 is pulled. Low Up to almost equal to the reference ground, so that the first resistor R1 and the second resistor R2 are nearly grounded, and the voltage sampling signal VS1 is approximately equal to zero.
  • the control signal outputted by the control unit is converted to a high level, which makes the on/off switch K1 enter an on state, and the AC mains AC is connected to the filter capacitor C due to the conduction of the on/off switch K1.
  • Generate charging Due to the series connection of the third resistor R3 and the on/off switch K1, the charging current generates a current sampling signal VS2 on the third resistor R3, which is sent to the second input of the control unit.
  • the charging current gradually decreases.
  • the charging process ends and the charging current drops to zero.
  • the control unit always monitors the current sampling signal VS2 reflecting the change in the charging current during this charging process. When the current sampling signal VS2 falls to zero, the control signal outputted by the control unit generates a low level, thereby turning off the on/off switch K1.
  • the control signal outputted from the control unit is converted to a high level so that the on/off switch K1 is turned on at time t1 until the control signal output from the control unit is converted to a low level so that the on/off switch K1 is turned off at the time t2, this time It is the on-time of the on/off switch K1, which is called Ton.
  • Ton the on-time of the on/off switch K1, which is called Ton.
  • the on/off switch K1 is about to start to be turned on, but is not yet turned on.
  • the voltage sampling signal VS1 is a positive voltage signal, and the voltage sampling signal VS1 is from the voltage at one end of the on/off switch K1
  • the voltage is divided by the first resistor R1 and the second resistor R2, which means that at time t1, the pass One end of the disconnect switch K1 has a positive voltage to the reference ground.
  • the voltage of one end of the on/off switch K1 to the reference ground is equal to the voltage obtained by subtracting the voltage across the filter capacitor C from the AC mains AC voltage, and then subtracting the filter inductor L and the rectifier bridge voltage drop, and the filter inductor L and The voltage drop of the rectifier bridge is relatively low. Therefore, it can be understood that at the time t1, the voltage value of the reference switch K1 at one end of the reference ground characterizes the voltage instantaneous value of the AC mains AC at the moment and the voltage at both ends of the filter capacitor C. The difference in values. Therefore, the voltage sampling signal VS1 monitored by the control unit is a positive voltage, indicating that the instantaneous value of the AC mains AC is greater than the voltage value across the filter capacitor C at this moment, and the difference can be expressed by the following formula:
  • Vac(t1) represents the instantaneous value of the voltage of the AC mains AC at time t1
  • Vc(t1) represents the voltage value across the filter capacitor C at time t1.
  • the reference voltage reference signal Vref1 is a constant constant constant reference value, such as 1.2
  • the voltage difference Vac(t1) - Vc(t1) depends only on the resistance values of the first resistor R1 and the second resistor R2. ratio. Therefore, the ratio of the resistance values of the first resistor R1 and the second resistor R2 is appropriately selected to be a relatively small value, that is, the ratio of the resistance values of the first resistor R1 and the second resistor R2 is smaller than the preset ratio by the resistance selection.
  • the result of the above voltage difference Vac(t1)-Vc(t1) can be a relatively small value, which means that when the on/off switch K1 is turned on, the AC mains AC voltage instantaneous value is compared with the filter capacitor.
  • the instantaneous value of the voltage across C is not much more than, for example, only 10 volts or 20 volts, that is, the preset differential pressure described in the above embodiment. Therefore, the charging current generated during the charging process is not large, and the peak value of the charging current is not high. For example, the peak value is only several tens of milliamps, which ensures that no inrush current is generated.
  • the ratio of the resistances of the first resistor R1 and the second resistor R2 may be 10, 20, or 30, etc., as long as it is less than a preset ratio, such as less than 50, which is not specifically limited herein;
  • the resistance of the first resistor R1 can be selected to be 2.7 megaohms
  • the resistance of the second resistor R2 can be selected to be 240 kilo ohms; depending on the application environment, it is within the protection scope of the present application.
  • the charging current generated by the charging process is relatively small, and even if the filter inductor L exists in the charging circuit, the energy storage can be released in a relatively short time.
  • the #2 waveform depicts the current waveform provided by the AC mains AC.
  • the charging current is generated from the time t1, and the charging current has dropped to zero at time t2. Therefore, at the time t2, that is, when the on-time Ton of the on-off switch K1 ends, there is no inductive energy storage in the loop, and when the on-off switch K1 enters the off state, the back-off switch K1 does not have a back-EM potential at both ends, belonging to Safe shutdown.
  • the control signal outputted by the control unit is converted to a low level, the on/off switch K1 is turned off, the control unit starts to re-detect the voltage sampling signal VS1, and the control unit realizes through the hysteresis comparator. Slightly the rising process of the voltage sampling signal VS1, and only monitoring the falling process of the voltage sampling signal VS1 until the next time t3, the control unit again monitors that the voltage sampling signal VS1 is lower than the reference voltage reference signal Vref1, thus opening The judgment and control process of the next cycle.
  • the control unit detects the voltage sampling signal VS1 and the current sampling signal VS2 on a cycle-by-cycle basis, and controls the on and off of the on/off switch K1 on a cycle-by-cycle basis.
  • This process is synchronized with the sinusoidal nature of the AC mains AC.
  • the on/off switch K1 is turned on and off during a certain period of time during which the voltage drops across it.
  • the AC city The charging current of the AC capacitor to the filter capacitor C exhibits a relatively small amplitude, and the voltage across the filter capacitor C exhibits a step-by-cycle step-by-cycle climb. This mode of operation causes the inrush current and surge voltage at the time of startup to be completely eliminated.
  • control unit In the adjustment phase, the control unit synchronously monitors the state of the internal start timer at each rising edge of the control signal. When it is determined that the state is an active level, the circuit device will enter the lower lock phase.
  • the control unit contains a start-up timer that also starts working when the control unit starts working.
  • the start timer sets a delay time for determining when the switching power supply enters the lock phase from the aforementioned adjustment phase.
  • the control signal output by the control unit will continue to maintain a high level, so that the on/off switch K1 is maintained in an on state, so that the voltage across the filter capacitor C is the rectified voltage of the AC mains AC, thereby
  • the post-stage converter can start working.
  • the waveforms of the various operating points can be seen in Figure 9.
  • the added #8 waveform describes the output signal that starts the timer.
  • the start timer When the start time of the timer is reached, the start timer outputs a high enable enable signal.
  • the control unit de- latches the current state of the output signal of the start timer each time the control signal is at a rising edge of a high level.
  • the control signal output by the control unit will maintain the operating mode of the previous adjustment phase. If the current state latched is a valid high level, the control signal output by the control unit will continue to output a high level, so that the on/off switch K1 is maintained in an on state, and the switching power supply enters the lock phase.
  • the control signal outputted by the control unit is converted to the rising edge of the high level, and the output state of the corresponding start timer (#8 waveform) is low, and thus the control unit outputs The control signal will become low when the current sampling signal VS2 crosses zero, that is, at times t2 and t4, and then the on/off switch K1 is turned off.
  • the output state of the start timer goes high.
  • the control signal output from the control unit is not immediately converted to a high level, but needs to wait until the rising edge of the control signal at time t6 to latch to the state of starting the timer. From the time t6, the control signal is always maintained at a high level, and the switch unit enters the lock phase.
  • the output state of the start timer is synchronously sampled by the control unit with the rising edge of its control signal, that is, the moment when the on/off switch K1 enters the normally-on state, and does not generate any large recharging current. Therefore, the circuit device is switched from the regulation phase to the lock phase, and no large surge current and surge voltage are generated.
  • control unit includes: a second hysteresis comparator U1, a first zero-crossing comparator, a second start timer, an edge trigger, a second D flip-flop, and a second OR gate; wherein:
  • the non-inverting input terminal of the second hysteresis comparator U2 receives the voltage sampling signal VS1;
  • the inverting input terminal of the second hysteresis comparator U2 receives the reference voltage reference signal
  • the output end of the second hysteresis comparator U2 is connected to the set end of the edge flip flop;
  • the input of the first zero-crossing comparator receives the current sampling signal VS2;
  • the output of the first zero-crossing comparator is connected to the reset end of the edge flip-flop
  • the output end of the second start timer is connected to the data end of the second D flip-flop
  • the output end of the edge flip-flop is connected to the rising edge trigger end of the second D flip-flop and one input end of the second OR gate;
  • the output of the second D flip-flop is connected to the other input of the second OR gate
  • the output of the second OR gate outputs a control signal.
  • the edge trigger can be an edge type RS flip-flop.
  • the control unit includes a hysteresis comparator for receiving the voltage sampling signal VS1, and comparing the voltage sampling signal VS1 with the reference voltage reference signal Vref1, the output of the second hysteresis comparator U2 The result is sent to the set end of an edge trigger.
  • the second hysteresis comparator U2 When the lower reference voltage reference signal Vref1 occurs during the falling of the voltage sampling signal VS1, the second hysteresis comparator U2 outputs a low level, and the falling edge of the low level causes the output terminal Q1 of the edge flip-flop to be set.
  • the control signal is converted to a high level via the second OR gate, so that the on/off switch K1 enters an on state.
  • the first zero-crossing comparator When the charging current drops to zero, that is, when the current sampling signal VS2 falls to zero, the first zero-crossing comparator generates a falling edge from high to low, and the falling edge signal is sent to the reset end Reset of the edge trigger, so that The output terminal Q1 of the edge flip-flop is set to a low level, and the control signal is converted to a low level via the second OR gate, thereby causing the on-off switch K1 to enter an off state.
  • control unit again waits for the falling process of the voltage sampling signal VS1 to proceed to the judgment of the next cycle.
  • the control unit also includes a second start timer that sets a delay wait time for determining when the control unit enters the lock phase from the aforementioned adjustment phase.
  • the delay time set by the second start timer may be several milliseconds to several seconds, and is set according to actual needs, and is not specifically limited herein, and is within the protection scope of the present application.
  • the second start-up timer has an output signal that indicates that the control unit is still in the regulation phase when it is low. When the signal goes high, it indicates that the delay wait time has expired and the control unit is about to enter the lock phase.
  • the output signal of the second start timer is sent to the data terminal D of a second D flip-flop, and the rising edge of the second D flip-flop CK receives a signal from the output terminal Q1 of the aforementioned edge flip-flop, the second D
  • the output Q2 of the flip flop is sent to the other input of the aforementioned second OR gate.
  • the output of the second start timer is low, which makes the data terminal D of the second D flip-flop low.
  • Each rising edge of the rising edge trigger terminal CK from the edge flip-flop output terminal Q1 to the second D flip-flop causes the level signal latched by the second D flip-flop to be low level, thus the second The output Q2 signal of the D flip-flop is low. Due to the second OR gate, the level change of the control signal depends only on the signal of the edge flip-flop output Q1.
  • the output of the second start timer becomes a high level, which causes the data terminal D of the second D flip-flop to also become a high level, the high level signal
  • the second D flip-flop output will not be set high immediately, but wait for the rising edge of the second D flip-flop to trigger a rising edge signal.
  • the rising edge of the second D flip-flop triggers a rising edge, thereby performing the high level of the data terminal D of the second D flip-flop.
  • Latching causes the signal of the second D flip-flop output Q2 to go high.
  • the high level signal of the second D flip-flop output Q2 enters the OR gate such that the control signal remains at a high level. Thereafter, since the output of the second start timer remains at a high level, the control signal is also maintained at a high level. In this way, the control unit enters the lock phase, and the on/off switch K1 is also maintained in the on state.
  • the soft start circuit provided by the embodiment completes the whole process from the initial stage, the adjustment stage and the lock stage from the power-on, and the power converter of the power supply starts to work.
  • another embodiment of the present invention further provides a soft start circuit of another specific switching power supply
  • the preset rule is: when the voltage sampling signal VS1 falls to the reference voltage reference signal The control on/off switch K1 is turned on; and after the preset on-time is long, the control on-off switch K1 is turned off.
  • the control unit outputs a condition of a high level, which is consistent with the foregoing scheme, and is also at a time when the falling edge of the voltage sampling signal VS1 appears lower than the reference voltage reference signal Vref1, as shown at time t1 in FIG. 11;
  • the difference is that after the time t1, the time when the control signal remains high is determined by a timer with a fixed delay time.
  • the Ton representing the duration of the high level of the control signal is fixed.
  • the preset on-time from the time t1 to the time t3, and the fixed preset on-time is better, should be ensured to be greater than the time when the current sampling signal VS2 crosses zero, that is, from t1 to t2.
  • the control signal is at a high level, the on/off switch K1 is turned on, and the AC mains AC generates a charging current to the filter capacitor C; as the charging current decreases, at time t2, the current sampling signal VS2 falls to Zero indicates that the charging current has ended; however, the control signal remains high until the next t3 time, causing the control signal to go low, thereby turning off the on/off switch K1.
  • the control unit restarts detecting the falling edge process of the voltage sampling signal VS1 to proceed to the control process of the next cycle.
  • the timing of the fixed preset on-time Ton can be realized by a one-shot timer located inside the control unit, and the preset on-time Ton defined can be in the range of 100 microseconds to 500 microseconds. Since the magnitude of the aforementioned charging current is small, the time during which the charging current drops by zero is short, and the timer time of 100 to 500 microseconds is sufficient.
  • the control unit includes: a first hysteresis comparator U1, a first start timer, a first monostable timer, a first D flip-flop, and a first OR gate; wherein:
  • the non-inverting input terminal of the first hysteresis comparator U1 receives the voltage sampling signal VS1;
  • the inverting input terminal of the first hysteresis comparator U1 receives the reference voltage reference signal
  • the output of the first hysteresis comparator U1 is connected to the input of the first monostable timer;
  • the output end of the first start timer is connected to the data end of the first D flip-flop
  • the output of the first monostable timer is connected to the rising edge trigger end of the first D flip-flop and one input end of the first OR gate;
  • the output of the first D flip-flop is connected to the other input of the first OR gate
  • the output of the first OR gate outputs a control signal.
  • connection point of the on/off switch K1 and the third resistor R3 in series is connected to the second input end of the control unit;
  • control signal is generated by the control unit according to the voltage sampling signal VS1 received by the first input terminal and the current sampling signal VS2 received by the second input terminal;
  • the corresponding preset rule is: when the voltage sampling signal VS1 falls to the reference voltage reference signal, the control on/off switch K1 is turned on; and after the preset conduction time, or when the current sampling signal VS2 crosses zero, the on/off switch is controlled. K1 is turned off.
  • the control unit includes: a third hysteresis comparator U3, a second zero-crossing comparator, a third start timer, a second one-shot timer, a third D flip-flop, and a third Tri-or gate U4 and fourth or gate U5; where:
  • the non-inverting input terminal of the third hysteresis comparator U3 receives the voltage sampling signal VS1;
  • the inverting input terminal of the third hysteresis comparator U3 receives the reference voltage reference signal
  • the output of the third hysteresis comparator U3 is connected to the input of the second monostable timer;
  • the output of the second monostable timer is connected to an input of the third OR gate U4;
  • the input of the second zero-crossing comparator receives the current sampling signal VS2;
  • the output of the second zero-crossing comparator is connected to the other input of the third OR gate U4;
  • the output end of the third start timer is connected to the data end of the third D flip-flop
  • the output end of the third OR gate U4 is connected to the rising edge trigger end of the third D flip-flop and one input end of the fourth OR gate U5;
  • the output of the third D flip-flop is connected to the other input of the fourth OR gate U5;
  • the output of the fourth OR gate U5 outputs a control signal.
  • the control unit contains an edge-triggered second monostable timer.
  • the third hysteresis comparator U3 When the control unit detects that the falling process of the voltage sampling signal VS1 occurs below the reference voltage reference signal Vref1, the third hysteresis comparator U3 outputs an edge change of an active level and sends it to the trigger input of the second monostable timer. Therefore, the output terminal A of the second monostable timer is immediately set to a high level, and the control signal is set to a high level via the third OR gate U4, and at the same time, the second monostable trigger starts to start the preset guide.
  • the timing of the Ton is long.
  • the current sampling signal VS2 is still fed to a second zero-crossing comparator, and its comparison output B is also set to a high level via the third OR gate U4.
  • the second zero-crossing comparator output B is set low, but since the timing of the second monostable timer has not ended yet, the signal at the A terminal in Figure 13 is still high. Therefore, the control signal is still at a high level after the third OR gate U4, and the on/off switch K1 remains in an on state.
  • the signal at the A terminal changes to a low level, because at this time, the signal of the output terminal B of the second zero-crossing comparator has first changed to a low level, which makes After the three-OR gate U4, the control signal goes low, thereby turning off the on/off switch K1.
  • the timing time of the second monostable timer is set to ensure a time greater than zero crossing of the current sampling signal VS2, this makes, in general, the current sampling signal VS2 and the second zero-crossing comparator The result does not directly affect the level change of the control signal.
  • the time is greater than the monostable timing time. Therefore, more preferably than FIG. 12, referring to FIG. 13, the current sampling signal VS2 and the second zero-crossing comparator are still Reserved, at this time, due to the third OR gate U4, the condition that the control signal changes to a low level is still the current sampling signal VS2 Determined by zero crossing.
  • control unit may be implemented by an integrated circuit chip, such as the hardware circuit shown in FIG. 10, FIG. 12 and FIG. 13 is disposed on the integrated circuit chip, or together with the on/off switch K1. It can be disposed on the integrated circuit chip together, and is not specifically limited herein, and may be determined according to the specific application environment, and is within the protection scope of the present application.
  • a software controller such as a single chip microcomputer or a PLC (Programmable Logic Controller) may be used instead of the above hardware circuit to implement the function of the control unit, which is not specifically limited herein. It can be determined according to its specific application environment, and is within the protection scope of the present application.
  • FIG. 5 or FIG. 6 Another embodiment of the present invention further provides a switching power supply, as shown in FIG. 5 or FIG. 6, including: a filter inductor L, a mains switch K0, a rectifier bridge, a filter capacitor C, a post-stage converter, and any of the above embodiments. a soft-start circuit for a switching power supply;
  • the AC mains AC is connected to the two input ends of the rectifier bridge through the filter inductor L and the mains switch K0;
  • the positive terminal of the output end of the rectifier bridge sequentially passes through the filter capacitor C and the soft start circuit of the switching power supply, and is connected to the negative terminal of the output end of the rectifier bridge and the reference ground;
  • the post-stage converter is connected in parallel with the filter capacitor C.
  • the post-stage converter is: a flyback topology, a buck-boost topology or a buck topology, which is within the protection scope of the present application, depending on the environment.

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Abstract

一种开关电源及其软启动电路，通过控制单元输出至通断开关（K1）控制端的控制信号，使通断开关（K1）在开关电源上电之后的初始阶段内保持关断状态，由于大阻值的第一电阻（R1）和第二电阻（R2）的限制，使得滤波电容（C）的充电电流保持在很小的范围内，充电电压缓慢增长；并控制通断开关（K1）在调节阶段内以预设规律导通和关断，使滤波电容（C）间断性地在预设压差下进行充电，以保证每次充电电流都很小，充电电压呈现逐个周期的台阶爬升；最后控制通断开关（K1）在滤波电容（C）上的电压满足预设条件之后，锁定阶段内导通后即保持导通状态，使后级变换器进入正常工作状态之前滤波电容（C）也不会出现大的充电电流和充电电压阶跃；有效减小了开关电源的开机浪涌电流和开机浪涌电压。

Description

一种开关电源及其软启动电路 技术领域
本发明涉及开关电源技术领域，尤其涉及一种开关电源及其软启动电路。
背景技术
开关电源，由于高转换效率、高功率密度，已经被大量使用在各种供电场合。由于开关电源中后级变换器的功率变换部件工作在高频，因此通常在后级变换器的输入端设置一个滤波电容C，以滤除高频噪声，改善对外的电磁干扰；图1所示为常见的开关电源的结构示意图。
参见图1，在开关K0闭合、交流市电AC接入的开机瞬间，将会产生一个充电电流Ich，经滤波电感L、整流桥，对滤波电容C充电；由于这个充电回路的电阻性阻抗非常小，且交流市电AC的相位是随机的、在开机瞬间有可能处在接近90度的AC电压峰值附近，因此导致该充电电流Ich的峰值可能较大，如达数安培或十安培以上，成为开关电源的开机浪涌电流，对开关电源输入端器件产生较大的电流应力，甚至可能导致这些器件的损坏。另外，在该开机浪涌电流流经滤波电感L时，滤波电感L将会产生储能，这个储能释放时产生的电流也会流经整流桥并对滤波电容C充电。在此情况下，滤波电容C上的电压幅度表现为明显的欠阻尼过冲响应，该电压的峰值有时高达700V，成为开关电源的开机浪涌电压。由于该滤波电容C上的电压也即后级变换器的工作电压，而工作电压过高容易导致后级变换器中的器件承受过高的电压应力而发生永久性损毁。图2所示为开关电源在t0时刻开机的波形展示。
为了避免较大的开机浪涌电流和开机浪涌电压损坏器件，参见图3，现有技术在图1的基础上，在开关电源输入端串入一个负温度系数的热敏电阻NTC。当开关K0闭合瞬间，通过热敏电阻NTC的阻值限制滤波电容C的充电电流的幅度，从而在一定程度上降低了开机浪涌电流的幅度。但是由于热敏电阻NTC所用材料电阻率的局限性，以及考虑到热敏电阻NTC的工作功耗，热敏电阻NTC阻值通常选择范围只能为10到20欧姆，这个阻值不足以显著减小浪涌电流的幅度，进而也不足以显著减小整流桥后滤波电容上的开机浪涌电压的幅度。
发明内容
有鉴于此，本发明提供了一种开关电源及其软启动电路，以解决现有技术 无法有效减小开机浪涌电流和开机浪涌电压的问题。
为了实现上述目的，本发明实施例提供的技术方案如下：
一种开关电源的软启动电路，连接于开关电源的滤波电容与参考地之间；所述开关电源的软启动电路包括：控制单元、通断开关、第一电阻、第二电阻及第三电阻；其中：
所述第一电阻与所述第二电阻串联连接于所述滤波电容与参考地之间，串联的连接点与所述控制单元的第一输入端相连；
所述通断开关与所述第三电阻串联连接于所述滤波电容与参考地之间；
所述第二电阻与所述第三电阻均与参考地相连；
所述第一电阻与所述第二电阻的阻值之和大于等于100千欧姆；
所述控制单元用于根据第一输入端接收的电压采样信号，生成控制信号并输出至所述通断开关的控制端，以在所述开关电源上电之后的初始阶段内使所述通断开关保持关断状态，控制所述通断开关在所述开关电源上电之后的调节阶段内以预设规律导通和关断、使所述滤波电容间断性地在预设压差下进行充电，并控制所述通断开关在所述滤波电容上的电压满足预设条件之后、所述开关电源上电之后的锁定阶段内导通后即保持导通状态。
优选的，所述初始阶段、所述调节阶段及所述锁定阶段均以相应的预设时长进行划分；
或者，所述预设条件为所述电压采样信号的幅度小于预设幅度。
优选的，所述第一电阻与所述第二电阻的阻值之比小于预设比值。
优选的，所述预设规律为：在所述电压采样信号下降到基准电压参考信号时，控制所述通断开关导通；并在预设导通时长之后，控制所述通断开关关断。
优选的，所述通断开关与所述第三电阻串联的连接点与所述控制单元的第二输入端相连；
所述控制信号是所述控制单元根据第一输入端接收的电压采样信号和第 二输入端接收的电流采样信号而生成的；
所述预设规律为：在所述电压采样信号下降到基准电压参考信号时，控制所述通断开关导通；并在所述电流采样信号过零时，控制所述通断开关关断；
或者，所述预设规律为：在所述电压采样信号下降到基准电压参考信号时，控制所述通断开关导通；并在预设导通时长之后，或者所述电流采样信号过零时，控制所述通断开关关断。
优选的，所述控制单元包括：第一滞环比较器、第一启动定时器、第一单稳态定时器、第一D触发器及第一或门；其中：
所述第一滞环比较器的同相输入端接收所述电压采样信号；
所述第一滞环比较器的反相输入端接收所述基准电压参考信号；
所述第一滞环比较器的输出端与所述第一单稳态定时器的输入端相连；
所述第一启动定时器的输出端与所述第一D触发器的数据端相连；
所述第一单稳态定时器的输出端与所述第一D触发器的上升沿触发端及所述第一或门的一个输入端相连；
所述第一D触发器的输出端与所述第一或门的另一个输入端相连；
所述第一或门的输出端输出所述控制信号。
优选的，所述预设规律为：在所述电压采样信号下降到基准电压参考信号时，控制所述通断开关导通；并在所述电流采样信号过零时，控制所述通断开关关断时，所述控制单元包括：第二滞环比较器、第一过零比较器、第二启动定时器、边沿触发器、第二D触发器及第二或门；其中：
所述第二滞环比较器的同相输入端接收所述电压采样信号；
所述第二滞环比较器的反相输入端接收所述基准电压参考信号；
所述第二滞环比较器的输出端与所述边沿触发器的置位端相连；
所述第一过零比较器的输入端接收所述电流采样信号；
所述第一过零比较器的输出端与所述边沿触发器的复位端相连；
所述第二启动定时器的输出端与所述第二D触发器的数据端相连；
所述边沿触发器的输出端与所述第二D触发器的上升沿触发端及所述或门的一个输入端相连；
所述第二D触发器的输出端与所述第二或门的另一个输入端相连；
所述第二或门的输出端输出所述控制信号；
所述预设规律为：在所述电压采样信号下降到基准电压参考信号时，控制所述通断开关导通；并在预设导通时长之后，或者所述电流采样信号过零时，控制所述通断开关关断时，所述控制单元包括：第三滞环比较器、第二过零比较器、第三启动定时器、第二单稳态定时器、第三D触发器、第三或门及第四或门；其中：
所述第三滞环比较器的同相输入端接收所述电压采样信号；
所述第三滞环比较器的反相输入端接收所述基准电压参考信号；
所述第三滞环比较器的输出端与所述第二单稳态定时器的输入端相连；
所述第二单稳态定时器的输出端与所述第三或门的一个输入端相连；
所述第二过零比较器的输入端接收所述电流采样信号；
所述第二过零比较器的输出端与所述第三或门的另一个输入端相连；
所述第三启动定时器的输出端与所述第三D触发器的数据端相连；
所述第三或门的输出端与所述第三D触发器的上升沿触发端及所述第四或门的一个输入端相连；
所述第三D触发器的输出端与所述第四或门的另一个输入端相连；
所述第四或门的输出端输出所述控制信号。
优选的，所述控制单元为：单片机或者可编程序逻辑控制器PLC。
优选的，所述控制单元设置于集成电路芯片上，或者所述控制单元与所述通断开关均设置于集成电路芯片上。
一种开关电源，包括：滤波电感、市电开关、整流桥、滤波电容、后级变换器及上述任一所述的开关电源的软启动电路；其中：
交流市电分别经过所述滤波电感及所述市电开关与所述整流桥的两个输入端相连；
所述整流桥的输出端正极依次通过所述滤波电容和所述开关电源的软启动电路，与所述整流桥的输出端负极和参考地相连；
所述后级变换器与所述滤波电容并联。
本申请提供一种开关电源的软启动电路，通过控制单元输出至通断开关控制端的控制信号，使通断开关在开关电源上电之后的初始阶段内保持关断状态，此时通过与滤波电容串联的大阻值的第一电阻和第二电阻的限制，使得滤波电容的充电电流保持在很小的范围内、充电电压缓慢增长；并控制通断开关在开关电源上电之后的调节阶段内以预设规律导通和关断、使滤波电容间断性地在预设压差下进行充电，以保证每次充电电流都很小、充电电压呈现逐个周期的台阶爬升；最后控制通断开关在滤波电容上的电压满足预设条件之后、开关电源上电之后的锁定阶段内导通后即保持导通状态，使后级变换器进入正常工作状态之前滤波电容也不会出现大的充电电流和充电电压阶跃。本电路通过该控制单元的控制，使得开关电源在上电之后的上述阶段内，其滤波电容上的充电电流较小、充电电压能够逐步增加，有效减小了开关电源的开机浪涌电流和开机浪涌电压。
附图说明
图1为现有技术提供的一种开关电源的结构示意图；
图2为现有技术提供的开关电源开机时的波形示意图；
图3为现有技术提供的开关电源的结构示意图；
图4为现有技术提供的开关电源的结构示意图；
图5为本申请实施例提供的开关电源的结构示意图；
图6为本申请另一实施例提供的开关电源的结构示意图；
图7为本申请另一实施例提供的开关电源上电之后初始阶段的波形示意图；
图8为本申请另一实施例提供的开关电源上电之后调节阶段的波形示意图；
图9为本申请另一实施例提供的开关电源上电之后进入锁定阶段的波形示意图；
图10为本申请另一实施例提供的控制单元的结构示意图；
图11为本申请另一实施例提供的开关电源上电之后调节阶段的波形示意图；
图12为本申请另一实施例提供的控制单元的结构示意图；
图13为本申请另一实施例提供的控制单元的结构示意图。
具体实施方式
为了进一步了解本发明，下面结合实施例对本发明优选实施方案进行描述，但是应当理解，这些描述只是为进一步说明本发明的特征和优点，而不是对本发明权利要求的限制。
本发明提供了一种开关电源的软启动电路，以解决现有技术无法有效减小开机浪涌电流和开机浪涌电压的问题。
具体的，该开关电源的软启动电路，参见图5，连接于开关电源的滤波电容C与参考地之间；开关电源的软启动电路如图5中的虚线框内所示包括：控制单元、通断开关K1、第一电阻R1、第二电阻R2及第三电阻R3；其中：
第一电阻R1与第二电阻R2串联连接于滤波电容C与参考地之间，串联的连接点与控制单元的第一输入端相连；
通断开关K1与第三电阻R3串联连接于滤波电容C与参考地之间；
第二电阻R2与第三电阻R3均与参考地相连；
第一电阻R1与第二电阻R2的阻值之和大于等于100千欧姆；较佳的，第一电阻R1与第二电阻R2的阻值之和可以取百千欧姆级或者兆欧姆级；此处不做具体限定，视其具体应用环境而定，均在本申请的保护范围内。
控制单元用于根据第一输入端接收的电压采样信号VS1，生成控制信号并输出至通断开关K1的控制端，以在开关电源上电之后的初始阶段内使通断开 关K1保持关断状态，控制通断开关K1在开关电源上电之后的调节阶段内以预设规律导通和关断、使滤波电容C间断性地在预设压差下进行充电，并控制通断开关K1在滤波电容C上的电压满足预设条件之后、开关电源上电之后的锁定阶段内导通后即保持导通状态。
通断开关K1可以是场效应管，或双极型晶体管，或绝缘栅型场效应晶体管，或可控硅器件等开关型器件，此处不做具体限定，视其具体应用环境而定，均在本申请的保护范围内。
具体的工作原理为：
通过控制单元输出至通断开关K1控制端的控制信号，使通断开关K1在开关电源上电之后的初始阶段内保持关断状态，此时通过与滤波电容C串联的大阻值的第一电阻R1和第二电阻R2的限制，使得滤波电容C的充电电流保持在很小的范围内、充电电压缓慢增长；并控制通断开关K1在开关电源上电之后的调节阶段内以预设规律导通和关断、使滤波电容C间断性地在预设压差下进行充电，以保证每次充电电流都很小、充电电压呈现逐个周期的台阶爬升；最后控制通断开关K1在开关电源上电之后的锁定阶段内导通后即保持导通状态，使后级变换器进入正常工作状态之前滤波电容C也不会出现大的充电电流和充电电压阶跃。
优选的，其初始阶段、调节阶段及锁定阶段均以相应的预设时长进行划分，即该预设条件为调节阶段持续时间达到相应的预设时长。在具体的实际应用中，可以根据分析或者实验得到合适的预设时长，再通过控制单元对各个阶段的预设时长进行设置；比如，在初始阶段，控制单元的输出使得通断开关K1保持关断状态；在初始阶段起始后的几十毫秒后，控制单元开始工作，控制通断开关K1间断导通，使开关电源进入调节阶段；通过调节阶段一段预设时长的调节，可以是几个毫秒到几秒钟，根据实际需要而设定，其电压采样信号的幅度应已小于预设幅度，滤波电容C上的电压(交流市电AC减去第一电阻R1和第二电阻R2上的分压)逐步上升到合适的电压，后级变换器将进入正常工作状态，此时控制单元控制通断开关K1导通后即常通，使该开关电源将进入锁定阶段。
或者，该预设条件为电压采样信号的幅度小于预设幅度，即锁定阶段以电 压采样信号VS1的幅度小于预设幅度的时刻为起始时刻。电压采样信号VS1的幅度小于预设幅度，说明滤波电容C上的电压已上升到合适的电压，后级变换器可以进入正常工作状态，控制单元将控制该开关电源将进入锁定阶段。
对于上述各个阶段的划分，可以根据具体的实际应用环境通过控制单元进行设定，此处不做具体限定，均在本申请的保护范围内。
值得说明的是，现有技术中也存在图4所示的技术方案：当开关K0闭合、电源上电时，通过延时单元首先控制开关K1保持断开，则交流市电AC对滤波电容C的充电回路中，包含了一个串联电阻R，这个电阻R的阻值通常选择几百欧姆，足以限制充电电流的幅度，从而抑制产生过大的开机浪涌电流与开机浪涌电压。经过延时单元设定的一个延时时间后，延时单元再控制开关K1闭合，从而减小电阻R上可能产生的过大功耗。在此之后，后级变换器开始工作，后级变换器工作时所需的工作电流流经开关K1，而不经过电阻R。但是图4所示的现有技术方案中，当开关K1经延时闭合时，充电回路的阻抗再次变小，仍然会产生一个稍小的浪涌电流。
与现有技术相比，本实施例提供的该开关电源的软启动电路，通过该控制单元的控制，使得开关电源在上电之后的上述各个阶段内，其滤波电容C上的充电电流均较小、充电电压能够逐步增加，进而实现将开关电源的开机浪涌电流幅度进行显著的抑制，同时，使得后级变换器工作所需的滤波电容C两端的电压呈现缓慢的上升，从而也消除了滤波电容C两端的浪涌电压过冲现象。在此控制过程中，不会出现电子器件承受过大的电流应力或电压应力的情况，也即，通过上述软启动过程，能够提高电源产品的可靠性。
值得说明的是，能够实现上述功能的控制单元，可以是根据具体应用环境进行不同具体设置的多种形式，尤其是针对调节阶段的预设规律，该控制单元的具体实现形式可以有多种。
比如，在上述实施例及图5的基础之上，参见图6，通断开关K1与第三电阻R3串联的连接点与控制单元的第二输入端相连；
此时，该控制信号是控制单元根据第一输入端接收的电压采样信号VS1和第二输入端接收的电流采样信号VS2而生成的；
相应的预设规律为：在电压采样信号VS1下降到基准电压参考信号时，控制通断开关K1导通；并在电流采样信号VS2过零时，控制通断开关K1关断。
具体的，在初始阶段，市电开关K0闭合，此时控制单元尚未开始工作，控制单元输出的控制信号为低电平，通断开关K1为关断状态。在此阶段，交流市电AC对滤波电容C的充电回路中包含了第一电阻R1和第二电阻R2，由于第一电阻R1和第二电阻R2的阻值之和比较大，大于等于100千欧姆，比如1兆欧姆以上，使得对滤波电容C的充电电流非常小，小于1毫安。因此，使得在交流市电AC接入的瞬间，完全不存在开机浪涌电流；同时，由于第一电阻R1和第二电阻R2的大阻值，使得对滤波电容C充电的时间常数很大，因而滤波电容C是被缓慢充电，其上的电压是缓慢上升的，从而完全消除了开机瞬时的浪涌电压过冲现象。
图7所示为该开关电源在初始阶段的信号波形图，交流市电AC的正弦电压(图7中的第一个波形)经滤波电感L、整流桥、串联的第一电阻R1和第二电阻R2，对滤波电容C充电，由于第一电阻R1和第二电阻R2的阻值之和较大，充电电流很小，且充电回路具有较大的时间常数，使得滤波电容C两端的电压呈现缓慢上升的过程(图7中的第二个波形)。
由于交流市电AC为工频(50或60赫兹)，高频滤波电感L上的压降可以忽略不计，整流桥中的整流二极管的导通压降可以忽略不计。因而，在通断开关K1保持关断的情况下，其一端对参考地的电压，也即滤波电容C与第一电阻R1连接点处的电压，可以表达为交流正弦市电电压(经过整流)减去滤波电容C两端电压得到的电压，即图7中的第三个波形。这个波形的特征为一个经过整流的带有死区时间的局部正弦波，并且随着滤波电容C由于充电而导致的两端电压逐渐升高，这个局部正弦波的死区时间逐渐增大、幅度逐渐下降。
图7中的第四个波形为第一采样电阻R1与第二电阻R2连接点处对参考地的电压波形，也即送至控制单元第一输入端的电压采样信号VS1的波形，其只是图7中第三个波形经过第一电阻R1和第二电阻R2的简单分压后得到的波形。
在此初始阶段，由于控制单元输出的控制信号保持低电平，使得通断开关K1保持关断状态，因而与通断开关K1串联的电流采样电阻，即第三电阻R3，采样到的信号始终为零，即送至控制单元第二输入端的电流采样信号VS2始终 为零。该电流采样信号VS2为一个通过电压值表征流过通断开关K1的电流值的信号。
在上述初始阶段，已经完全消除了开机瞬间的浪涌电流与浪涌电压，但开关电源还需要让后级变换器开始工作，并且要实现在后级变换器开始工作之前的任何时间段，均不会出现浪涌电流和浪涌电压。因此，需要使该开关电源进入接下来的调节阶段。
具体的实际应用中，可以通过控制单元经过适当的延时等待时间后，如几十毫秒，开始工作，使开关电源进入调节阶段。
当控制单元开始工作，调节阶段具体的时序波形参见图8。结合图5描述的开关电源的结构示意图，图8中的每个波形的说明如下：
#1波形为开关电源接收的交流市电AC的电压波形；
#2波形为开关电源接收的交流市电AC的电流波形；
#3波形为滤波电容C两端的电压波形，这个电压用于给后级变换器供电；
#4波形为通断开关K1的一端相对参考地的电压波形，即滤波电容C与第一电阻R1连接点处对参考地的电压波形；
#5波形为经电阻分压后送至控制单元第一输入端的电压采样信号VS1波形；
#6波形为控制单元输出的控制信号的波形，该控制信号送至通断开关K1的控制端；
#7波形为与通断开关K1串联的第三电阻R3上的电压信号，也即电流采样信号VS2，送至控制单元的第二输入端；
调节阶段中，控制单元首先将输出的控制信号保持低电平，使得通断开关K1保持关断状态，同时监测电压采样信号VS1的下降过程。控制单元将接收到的电压采样信号VS1和控制单元内部的基准电压参考信号Vref1进行比较，见图8中的第5个波形。
当出现电压采样信号VS1低于基准电压参考信号Vref1信号时，对应图8中的t1时刻，控制单元输出的控制信号变成高电平，使得通断开关K1进入导通状态。当通断开关K1保持导通状态时，由于通断开关K1的导通电阻很小，同时与之串联的第三电阻R3的阻值也很小，使得通断开关K1的一端的电位被拉低 到几乎等于参考地，因而第一电阻R1和第二电阻R2近乎接地，电压采样信号VS1近似等于零。
从t1时刻开始，控制单元输出的控制信号转换为高电平，该高电平使得通断开关K1进入导通状态，随之交流市电AC因通断开关K1的导通而对滤波电容C产生充电。由于第三电阻R3与通断开关K1的串联，使得该充电电流在第三电阻R3上生成一个电流采样信号VS2，该信号被送至控制单元的第二输入端。在上述的充电过程中，随着滤波电容C两端电压的上升，充电电流逐渐减小。当滤波电容C两端电压被充电至与交流市电AC相同的电压值时，充电过程结束，充电电流下降至零。控制单元在此充电过程中始终监测着反映充电电流变化的电流采样信号VS2。当电流采样信号VS2下降至零的时刻，控制单元输出的控制信号产生低电平，从而关闭通断开关K1。
从控制单元输出的控制信号转换为高电平使得通断开关K1导通的时刻t1，一直到控制单元输出的控制信号转换为低电平使得通断开关K1关断的t2时刻，这段时间就是通断开关K1的导通时间，称为Ton。上述过程可以参见图8中的#5、#6、#7波形。
在上述的t1时刻，即电压采样信号VS1即将开始低于基准电压参考信号Vref1的时刻，此时通断开关K1即将开始导通，但尚未导通。此时由于电压采样信号VS1为一个正的电压信号，且电压采样信号VS1来自于通断开关K1一端的电压经过第一电阻R1和第二电阻R2的分压，这意味着在t1时刻，通断开关K1的一端对参考地存在一个正电压。参见图5，通断开关K1一端对参考地的电压，等于交流市电AC电压减去滤波电容C两端电压得到的电压，再减去滤波电感L和整流桥压降，而滤波电感L和整流桥压降相对很低可以忽略，因此，可以理解为，在t1时刻，通断开关K1一端对参考地的电压值表征了交流市电AC此刻的电压瞬时值与滤波电容C两端此刻电压值的差值。由此，控制单元监测到的电压采样信号VS1为正电压，说明在此刻交流市电AC的瞬时值大于滤波电容C两端的电压值，且其差值可以由如下公式表达：
Vac(t1)-Vc(t1)＝Vref1×(1+R1/R2)
其中，Vac(t1)表示在t1时刻交流市电AC的电压瞬时值，Vc(t1)表示在t1时刻滤波电容C两端的电压值。
根据上式，在t1时刻，交流市电AC与滤波电容C两端电压之间存在电压差Vac(t1)-Vc(t1)，因此，紧接着，当控制单元输出的控制信号转换为高电平使得通断开关K1进入导通状态时，必然会产生一个交流市电AC对滤波电容C的充电过程，以及对应的一个充电电流。
根据上式，由于基准电压参考信号Vref1是恒定为常数的基准值，比如1.2，使得该电压差Vac(t1)-Vc(t1)仅取决于第一电阻R1和第二电阻R2的阻值之比。因此，适当地选择第一电阻R1和第二电阻R2的阻值之比为一个比较小的值，即通过阻值选择使第一电阻R1与第二电阻R2的阻值之比小于预设比值，就可以让上述电压差Vac(t1)-Vc(t1)的结果为一个比较小的值，这意味着，当通断开关K1在导通瞬时，交流市电AC电压瞬时值相比滤波电容C两端电压瞬时值超出得并不多，例如只有10伏或20伏，也即上述实施例中所述的预设压差。因而随之在充电过程中产生的充电电流不会大，充电电流的峰值也不会高，例如峰值只有几十毫安，这样就确保了不会产生浪涌电流。在具体的实际应用中，第一电阻R1和第二电阻R2的阻值之比可以是10、20或者30等，只要小于预设比值即可，比如小于50，此处不做具体限定；较佳的，第一电阻R1的阻值可以选2.7兆欧，第二电阻R2的阻值可以选240千欧；具体还可以视其应用环境而定，均在本申请的保护范围内。
同理，如此小的充电电流，意味着比较小的能量，对滤波电容C充电的结果，只是让滤波电容C两端的电压有一个比较小的阶跃变化，见图8中#3波形，从t1到t2期间的变化，这就消除了滤波电容C两端电压出现浪涌电压过冲的现象。
依据上述的描述，充电过程产生的充电电流比较小，即使在充电回路中存在滤波电感L，其储能也可以在比较短的时间内释放完。从图8中可以看到，#2波形描绘了交流市电AC提供的电流波形。从t1时刻开始产生充电电流，到t2时刻时，该充电电流已经下降为零。因此在t2时刻，即通断开关K1的导通时间Ton结束时，回路中不存在电感性储能，通断开关K1进入关断状态时，通断开关K1两端不会出现反电势，属于安全关断。
从t2时刻开始，控制单元输出的控制信号转换为低电平，关闭通断开关K1，控制单元开始重新检测电压采样信号VS1，控制单元内通过滞环比较器实现忽 略电压采样信号VS1的上升过程，而只监测电压采样信号VS1的下降过程，直至进入到下一个时刻t3，控制单元再次监测到电压采样信号VS1低于基准电压参考信号Vref1的状态，这样就开启了下一个周期的判断与控制过程。
如图8所描述，控制单元逐个周期地检测电压采样信号VS1和电流采样信号VS2，逐个周期地控制通断开关K1的导通与关断。这个过程同步于交流市电AC的正弦性状，通断开关K1在其两端电压下降过程中的某个时间段，实施导通与关断，在每个周期通断开关导通期间，交流市电AC对滤波电容C的充电电流呈现比较小的幅度，滤波电容C两端电压呈现逐个周期的台阶爬升，这样的工作模式使得开机时的浪涌电流与浪涌电压被完全地消除了。
在调节阶段，控制单元在控制信号每个高电平的上升沿，同步监测内部的启动定时器的状态，当判断到该状态为有效电平时，则电路装置将进入下锁定阶段。
控制单元包含一个启动定时器，在控制单元开始工作时，该启动定时器也开始工作。启动定时器设定一个延时时间，用于决定开关电源何时从前述的调节阶段进入锁定阶段。在锁定阶段，控制单元输出的控制信号将持续维持一个高电平，从而使得通断开关K1一直维持导通状态，这样滤波电容C两端电压就是交流市电AC经整流后的电压，从而使得后级变换器可以开始工作。
从调节阶段转换到锁定阶段，各个工作点的波形可以参见图9。在图8的基础之上，增加的#8波形描述了启动定时器的输出信号。当启动定时器的定时时间达到时，启动定时器输出一个高电平的使能有效信号。控制单元在控制信号每次为高电平的上升沿时刻，去锁存启动定时器的输出信号的当前状态。当锁存到的当前状态为无效的低电平时，控制单元输出的控制信号将维持之前调节阶段的工作模式。如果锁存到的当前状态为有效的高电平时，则控制单元输出的控制信号将持续输出高电平，使得通断开关K1一直维持导通状态，使开关电源进入锁定阶段。
依据图9的描述，在t1和t3时刻，控制单元输出的控制信号转换为高电平的上升沿时刻，对应的启动定时器的输出状态(#8波形)为低电平，因而控制单元输出的控制信号会在电流采样信号VS2过零时变成低电平，即t2、t4时刻，进而关断通断开关K1。
在一个任选的t5时刻，启动定时器的输出状态变为高电平。此时，并不会马上让控制单元输出的控制信号转换为高电平，而是需要等到t6时刻控制信号的上升沿才锁存到启动定时器的状态。从t6时刻开始，控制信号始终维持高电平，开关单元进入锁定阶段。
在随后的t7时刻，充电电流下降为零，而控制信号由于被锁定，所以继续维持高电平。
再随后，交流市电AC电压过零。接着，随着交流市电AC的再次上升，至t8时刻，交流市电AC电压超过滤波电容C两端电压时，再次产生对滤波电容C的充电电流。由于交流市电AC是从零开始按照正弦缓慢上升的，这使得这次的充电电流呈现比较小的幅度，见图9中#2波形的t8至t9时间段。
依据上述描述，可以理解为，启动定时器的输出状态是被控制单元以其控制信号的上升沿同步采样的，也就是说，通断开关K1进入常通状态的时刻，不会产生任何大的充电电流。因此，本电路装置从调节阶段转入锁定阶段，同样不会产生大的浪涌电流与浪涌电压。
优选的，参见图10，该控制单元包括：第二滞环比较器U1、第一过零比较器、第二启动定时器、边沿触发器、第二D触发器及第二或门；其中：
第二滞环比较器U2的同相输入端接收电压采样信号VS1；
第二滞环比较器U2的反相输入端接收基准电压参考信号；
第二滞环比较器U2的输出端与边沿触发器的置位端相连；
第一过零比较器的输入端接收电流采样信号VS2；
第一过零比较器的输出端与边沿触发器的复位端相连；
第二启动定时器的输出端与第二D触发器的数据端相连；
边沿触发器的输出端与第二D触发器的上升沿触发端及第二或门的一个输入端相连；
第二D触发器的输出端与第二或门的另一个输入端相连；
第二或门的输出端输出控制信号。
该可以边沿触发器为边沿型RS触发器。
控制单元包含一个滞环比较器，用于接收电压采样信号VS1，将此电压采样信号VS1与基准电压参考信号Vref1进行比较，该第二滞环比较器U2的输出 结果送至一个边沿触发器的置位端Set。在电压采样信号VS1的下降过程中出现低于基准电压参考信号Vref1时，该第二滞环比较器U2输出一个低电平，该低电平发生的下降沿使得边沿触发器的输出端Q1置为高电平，经第二或门使得控制信号转换为高电平，从而使通断开关K1进入导通状态。
当通断开关K1开始导通时，产生一个对滤波电容C的充电电流，该充电电流经过与通断开关K1串联的第三电阻R3，第三电阻R3上得到的电流采样信号VS2通过控制单元的第二输入端被送至第一过零比较器。当充电电流下降为零时，即电流采样信号VS2下降为零时，第一过零比较器产生一个从高到低的下降沿，该下降沿信号送至前述边沿触发器的复位端Reset，使得边沿触发器的输出端Q1置为低电平，经第二或门使得控制信号转换为低电平，从而使通断开关K1进入关断状态。
其后，控制单元再次开始等待电压采样信号VS1的下降过程，从而进入下一个周期的判断。
控制单元还包含一个第二启动定时器，其设定了一个延时等待时间，用于决定控制单元何时从前述的调节阶段进入锁定阶段。第二启动定时器设定的延时等待时间可以是几个毫秒到几秒钟，根据实际需要而设定，此处不做具体限定，均在本申请的保护范围内。
第二启动定时器有一个输出信号，该信号为低电平时表示控制单元仍处在调节阶段。当该信号变为高电平时，表示延时等待时间已结束，控制单元即将进入锁定阶段。
第二启动定时器的输出信号送至一个第二D触发器的数据端D，该第二D触发器的上升沿触发端CK接收信号来自于前述边沿触发器的输出端Q1，该第二D触发器的输出端Q2送至前述第二或门的另一个输入端。
当第二启动定时器的延时等待时间尚未结束时，第二启动定时器的输出为低电平，这使得第二D触发器的数据端D为低电平。来自于边沿触发器输出端Q1输出至第二D触发器的上升沿触发端CK的每个上升沿使得该第二D触发器锁存到的电平信号均为低电平，因而该第二D触发器的输出端Q2信号均为低电平。由于第二或门，使得控制信号的电平变化仅取决于边沿触发器输出端Q1的信号。
当第二启动定时器的延时等待时间结束时，第二启动定时器的输出变为高电平，这使得第二D触发器的数据端D也变为高电平，这个高电平信号不会马上让第二D触发器输出置高，而是要等待第二D触发器的上升沿触发端CK出现上升沿信号。当来自于前述边沿触发器输出端Q1的信号变为高电平时刻，第二D触发器的上升沿触发端CK出现上升沿，从而将第二D触发器的数据端D的高电平进行锁存，使得第二D触发器输出端Q2的信号变为高电平。第二D触发器输出端Q2的高电平信号进入或门，使得控制信号保持为高电平。此后，由于第二启动定时器的输出保持高电平不变，使得控制信号也维持高电平。这样，控制单元就进入锁定阶段，通断开关K1也一直维持导通状态。
至此，本实施例提供的软启动电路完成了从上电开始的初始阶段、调节阶段、锁定阶段的全过程，电源的后级变换器开始工作。
或者，仅在图5的基础之上，本发明另一实施例还提供了另外一种具体的开关电源的软启动电路，其预设规律为：在电压采样信号VS1下降到基准电压参考信号时，控制通断开关K1导通；并在预设导通时长之后，控制通断开关K1关断。
此时，调节阶段中，控制单元输出高电平的条件，与前述方案一致，同样是在电压采样信号VS1的下降沿出现低于基准电压参考信号Vref1的时刻，见图11中的t1时刻；所不同的是，在t1时刻后，控制信号保持高电平的时间是由一个固定延时时间的定时器决定的，见图11中代表控制信号高电平持续时间长度的Ton是固定不变的，即从t1时刻到t3时刻的预设导通时长，并且这个固定的预设导通时长较佳的情况下应被确保大于电流采样信号VS2过零的时间，即t1时刻至t2时刻。
从t1时刻开始，控制信号为高电平，通断开关K1导通，交流市电AC产生对滤波电容C的充电电流；随着充电电流的减小，在t2时刻，电流采样信号VS2下降为零，表明充电电流已经结束；但控制信号依然维持高电平，直至接下来的t3时刻，才使得控制信号变为低电平，从而关断通断开关K1。接下来，控制单元重新开始检测电压采样信号VS1的下降沿过程，以便进入下个周期的控制过程。
由于t2时刻充电电流已经过零结束，在其后的t3时刻关断通断开关K1还是属于安全关断。
对于这个固定的预设导通时长Ton的定时，可以由一个位于控制单元内部的单稳态定时器实现，其所定义的预设导通时长Ton，可以在100微秒至500微秒范围。由于前述充电电流的幅度较小，使得充电电流下降过零的时间较短，100至500微秒的定时器时间已经足够。
这里所描述的是调节阶段的控制过程，对于锁定阶段的判断控制，则与前述方案相同，这里不在赘述。
优选的，参见图12，控制单元包括：第一滞环比较器U1、第一启动定时器、第一单稳态定时器、第一D触发器及第一或门；其中：
第一滞环比较器U1的同相输入端接收电压采样信号VS1；
第一滞环比较器U1的反相输入端接收基准电压参考信号；
第一滞环比较器U1的输出端与第一单稳态定时器的输入端相连；
第一启动定时器的输出端与第一D触发器的数据端相连；
第一单稳态定时器的输出端与第一D触发器的上升沿触发端及第一或门的一个输入端相连；
第一D触发器的输出端与第一或门的另一个输入端相连；
第一或门的输出端输出控制信号。
更为优选的，在图5的基础之上，参见图6，通断开关K1与第三电阻R3串联的连接点与控制单元的第二输入端相连；
此时，该控制信号是控制单元根据第一输入端接收的电压采样信号VS1和第二输入端接收的电流采样信号VS2而生成的；
相应的预设规律为：在电压采样信号VS1下降到基准电压参考信号时，控制通断开关K1导通；并在预设导通时长之后，或者电流采样信号VS2过零时，控制通断开关K1关断。
此时，优选的，参见图13，控制单元包括：第三滞环比较器U3、第二过零比较器、第三启动定时器、第二单稳态定时器、第三D触发器、第三或门U4及第四或门U5；其中：
第三滞环比较器U3的同相输入端接收电压采样信号VS1；
第三滞环比较器U3的反相输入端接收基准电压参考信号；
第三滞环比较器U3的输出端与第二单稳态定时器的输入端相连；
第二单稳态定时器的输出端与第三或门U4的一个输入端相连；
第二过零比较器的输入端接收电流采样信号VS2；
第二过零比较器的输出端与第三或门U4的另一个输入端相连；
第三启动定时器的输出端与第三D触发器的数据端相连；
第三或门U4的输出端与第三D触发器的上升沿触发端及第四或门U5的一个输入端相连；
第三D触发器的输出端与第四或门U5的另一个输入端相连；
第四或门U5的输出端输出控制信号。
控制单元包含一个边沿触发的第二单稳态定时器。当控制单元监测到电压采样信号VS1的下降过程出现低于基准电压参考信号Vref1时，第三滞环比较器U3输出一个有效电平的边沿变化，送至第二单稳态定时器的触发输入端，使得第二单稳态定时器的输出端A马上置高电平，经第三或门U4使控制信号置高电平，与此同时，第二单稳态触发器开始启动预设导通时长Ton的定时。
此时，电流采样信号VS2依然被送入一个第二过零比较器，并且其比较输出B也同样经第三或门U4使控制信号置高电平。当电流采样信号VS2过零时，第二过零比较器输出B置低电平，但由于此时第二单稳态定时器的定时时间尚未结束，即图13中A端的信号仍然为高电平，因而经过第三或门U4使得控制信号仍然为高电平，通断开关K1保持导通状态。
当第二单稳态定时器的定时时间达到时，其A端的信号变为低电平，由于此时第二过零比较器输出端B的信号已经先行变为低电平，这使得经第三或门U4后控制信号变为低电平，从而关断通断开关K1。
在此方案中，由于第二单稳态定时器的定时时间被设置成确保大于电流采样信号VS2发生过零的时间，这使得，在一般情况下，电流采样信号VS2及第二过零比较器结果并不直接影响控制信号的电平变化。但为了防止在极端情况下，电流采样信号VS2发生过零的时间大于单稳态定时时间，因而，比图12更为优选的，参见图13，电流采样信号VS2及第二过零比较器仍然保留，此时，由于第三或门U4，控制信号改变为低电平的条件仍然是由电流采样信号VS2 过零而决定的。
值得说明的是，上述实施例中，该控制单元可以通过集成电路芯片来实现，比如将图10、图12和图13所示的硬件电路设置于集成电路芯片上，或者连同通断开关K1也可以一同设置于集成电路芯片上，此处不做具体限定，可以视其具体应用环境而定，均在本申请的保护范围内。
另外，在具体的实际应用中，还可以采用单片机、PLC(Programmable Logic Controller，可编程序逻辑控制器)等软件控制器代替上述硬件电路来实现该控制单元的功能，此处不做具体限定，可以视其具体应用环境而定，均在本申请的保护范围内。
本发明另一实施例还提供了一种开关电源，参见图5或图6，包括：滤波电感L、市电开关K0、整流桥、滤波电容C、后级变换器及上述任一实施例的开关电源的软启动电路；其中：
交流市电AC分别经过滤波电感L及市电开关K0与整流桥的两个输入端相连；
整流桥的输出端正极依次通过滤波电容C和开关电源的软启动电路，与整流桥的输出端负极和参考地相连；
后级变换器与滤波电容C并联。
优选的，后级变换器为：反激拓扑、升降压拓扑或者降压拓扑，视其具体由于环境而定，均在本申请的保护范围内。
具体的工作原理与上述实施例相同，此处不再一一赘述。
本发明中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
以上仅是本发明的优选实施方式，使本领域技术人员能够理解或实现本发明。对这些实施例的多种修改对本领域的技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施 例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (10)

  1. 一种开关电源的软启动电路，其特征在于，连接于开关电源的滤波电容与参考地之间；所述开关电源的软启动电路包括：控制单元、通断开关、第一电阻、第二电阻及第三电阻；其中：
    所述第一电阻与所述第二电阻串联连接于所述滤波电容与参考地之间，串联的连接点与所述控制单元的第一输入端相连；
    所述通断开关与所述第三电阻串联连接于所述滤波电容与参考地之间；
    所述第二电阻与所述第三电阻均与参考地相连；
    所述第一电阻与所述第二电阻的阻值之和大于等于100千欧姆；
    所述控制单元用于根据第一输入端接收的电压采样信号，生成控制信号并输出至所述通断开关的控制端，以在所述开关电源上电之后的初始阶段内使所述通断开关保持关断状态，控制所述通断开关在所述开关电源上电之后的调节阶段内以预设规律导通和关断、使所述滤波电容间断性地在预设压差下进行充电，并控制所述通断开关在所述滤波电容上的电压满足预设条件之后、所述开关电源上电之后的锁定阶段内导通后即保持导通状态。
  2. 根据权利要求1所述的开关电源的软启动电路，其特征在于，所述初始阶段、所述调节阶段及所述锁定阶段均以相应的预设时长进行划分；
    或者，所述预设条件为所述电压采样信号的幅度小于预设幅度。
  3. 根据权利要求1所述的开关电源的软启动电路，其特征在于，所述第一电阻与所述第二电阻的阻值之比小于预设比值。
  4. 根据权利要求1所述的开关电源的软启动电路，其特征在于，所述预设规律为：在所述电压采样信号下降到基准电压参考信号时，控制所述通断开关导通；并在预设导通时长之后，控制所述通断开关关断。
  5. 根据权利要求1所述的开关电源的软启动电路，其特征在于，所述通 断开关与所述第三电阻串联的连接点与所述控制单元的第二输入端相连；
    所述控制信号是所述控制单元根据第一输入端接收的电压采样信号和第二输入端接收的电流采样信号而生成的；
    所述预设规律为：在所述电压采样信号下降到基准电压参考信号时，控制所述通断开关导通；并在所述电流采样信号过零时，控制所述通断开关关断；
    或者，所述预设规律为：在所述电压采样信号下降到基准电压参考信号时，控制所述通断开关导通；并在预设导通时长之后，或者所述电流采样信号过零时，控制所述通断开关关断。
  6. 根据权利要求4所述的开关电源的软启动电路，其特征在于，所述控制单元包括：第一滞环比较器、第一启动定时器、第一单稳态定时器、第一D触发器及第一或门；其中：
    所述第一滞环比较器的同相输入端接收所述电压采样信号；
    所述第一滞环比较器的反相输入端接收所述基准电压参考信号；
    所述第一滞环比较器的输出端与所述第一单稳态定时器的输入端相连；
    所述第一启动定时器的输出端与所述第一D触发器的数据端相连；
    所述第一单稳态定时器的输出端与所述第一D触发器的上升沿触发端及所述第一或门的一个输入端相连；
    所述第一D触发器的输出端与所述第一或门的另一个输入端相连；
    所述第一或门的输出端输出所述控制信号。
  7. 根据权利要求5所述的开关电源的软启动电路，其特征在于，所述预设规律为：在所述电压采样信号下降到基准电压参考信号时，控制所述通断开关导通；并在所述电流采样信号过零时，控制所述通断开关关断时，所述控制单元包括：第二滞环比较器、第一过零比较器、第二启动定时器、边沿触发器、第二D触发器及第二或门；其中：
    所述第二滞环比较器的同相输入端接收所述电压采样信号；
    所述第二滞环比较器的反相输入端接收所述基准电压参考信号；
    所述第二滞环比较器的输出端与所述边沿触发器的置位端相连；
    所述第一过零比较器的输入端接收所述电流采样信号；
    所述第一过零比较器的输出端与所述边沿触发器的复位端相连；
    所述第二启动定时器的输出端与所述第二D触发器的数据端相连；
    所述边沿触发器的输出端与所述第二D触发器的上升沿触发端及所述或门的一个输入端相连；
    所述第二D触发器的输出端与所述第二或门的另一个输入端相连；
    所述第二或门的输出端输出所述控制信号；
    所述预设规律为：在所述电压采样信号下降到基准电压参考信号时，控制所述通断开关导通；并在预设导通时长之后，或者所述电流采样信号过零时，控制所述通断开关关断时，所述控制单元包括：第三滞环比较器、第二过零比较器、第三启动定时器、第二单稳态定时器、第三D触发器、第三或门及第四或门；其中：
    所述第三滞环比较器的同相输入端接收所述电压采样信号；
    所述第三滞环比较器的反相输入端接收所述基准电压参考信号；
    所述第三滞环比较器的输出端与所述第二单稳态定时器的输入端相连；
    所述第二单稳态定时器的输出端与所述第三或门的一个输入端相连；
    所述第二过零比较器的输入端接收所述电流采样信号；
    所述第二过零比较器的输出端与所述第三或门的另一个输入端相连；
    所述第三启动定时器的输出端与所述第三D触发器的数据端相连；
    所述第三或门的输出端与所述第三D触发器的上升沿触发端及所述第四或门的一个输入端相连；
    所述第三D触发器的输出端与所述第四或门的另一个输入端相连；
    所述第四或门的输出端输出所述控制信号。
  8. 根据权利要求1至5任一所述的开关电源的软启动电路，其特征在于，所述控制单元为：单片机或者可编程序逻辑控制器PLC。
  9. 根据权利要求1至7任一所述的开关电源的软启动电路，其特征在于，所述控制单元设置于集成电路芯片上，或者所述控制单元与所述通断开关均设置于集成电路芯片上。
  10. 一种开关电源，其特征在于，包括：滤波电感、市电开关、整流桥、滤波电容、后级变换器及权利要求1至9任一所述的开关电源的软启动电路；其中：
    交流市电分别经过所述滤波电感及所述市电开关与所述整流桥的两个输入端相连；
    所述整流桥的输出端正极依次通过所述滤波电容和所述开关电源的软启动电路，与所述整流桥的输出端负极和参考地相连；
    所述后级变换器与所述滤波电容并联。
PCT/CN2017/088215 2017-06-14 2017-06-14 一种开关电源及其软启动电路 WO2018227422A1 (zh)

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