WO2018218971A1 - 显示面板、显示装置及显示面板的制作方法 - Google Patents
显示面板、显示装置及显示面板的制作方法 Download PDFInfo
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- WO2018218971A1 WO2018218971A1 PCT/CN2018/072480 CN2018072480W WO2018218971A1 WO 2018218971 A1 WO2018218971 A1 WO 2018218971A1 CN 2018072480 W CN2018072480 W CN 2018072480W WO 2018218971 A1 WO2018218971 A1 WO 2018218971A1
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- Prior art keywords
- display substrate
- connection
- connection hole
- flip chip
- display
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 224
- 239000004020 conductor Substances 0.000 claims abstract description 53
- 230000000149 penetrating effect Effects 0.000 claims abstract description 22
- 230000008569 process Effects 0.000 claims description 21
- 238000005553 drilling Methods 0.000 claims description 4
- 239000010409 thin film Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 67
- 238000005452 bending Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000004080 punching Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/1613—Constructional details or arrangements for portable computers
- G06F1/1633—Constructional details or arrangements of portable computers not specific to the type of enclosures covered by groups G06F1/1615 - G06F1/1626
- G06F1/1637—Details related to the display arrangement, including those related to the mounting of the display in the housing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/1613—Constructional details or arrangements for portable computers
- G06F1/1633—Constructional details or arrangements of portable computers not specific to the type of enclosures covered by groups G06F1/1615 - G06F1/1626
- G06F1/1637—Details related to the display arrangement, including those related to the mounting of the display in the housing
- G06F1/1652—Details related to the display arrangement, including those related to the mounting of the display in the housing the display being flexible, e.g. mimicking a sheet of paper, or rollable
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
Definitions
- the present disclosure relates to the field of display technologies, and in particular, to a display panel, a display device, and a method of fabricating the display panel.
- Display products with narrow bezels eg, cell phones (especially full-screen phones) or wearable devices (eg, smart watches) attract a large number of consumers because they enable users to have a better viewing experience.
- the Pad Bending process is the only solution for implementing a display panel with a narrow bezel.
- the display panel manufactured by the connection terminal bending process has many problems, and there is a display failure phenomenon caused by cracks in the inorganic insulating layer.
- the prior art terminal bending technology also increases process difficulty and manufacturing cost, and reduces production efficiency.
- the formation of the terminal bending region P requires an increase in space, and the display product produced by the connection terminal bending process has a low utilization ratio to the substrate.
- connection terminals also simply referred to as terminals
- embodiments of the present disclosure provide a display panel, a display device, and a method of fabricating the display panel.
- a display panel includes: a display substrate having a first surface and a second surface opposite to the first surface, the display substrate including a display area and a non-display area, the non- The display area includes a first portion and a second portion at least on opposite sides of the display area; a first connection terminal located at the first portion and located on the first surface; and a first connection hole located at the a part, and the first connecting hole penetrates at least the display substrate; the second connecting terminal is located at the second portion and is located on the first surface; the second connecting hole is located at the second portion, and The second connection hole penetrates at least the display substrate; the flip chip is located on the second surface of the display substrate, the flip chip comprises a third connection terminal; and the conductive material is respectively disposed on the corresponding a first connection hole and a second connection hole; wherein the first connection terminal and the second connection terminal of the display substrate respectively pass through a conductive material located in the first connection hole and the second connection hole Electrically connecting with the corresponding third connection
- the display panel may further include a bonding layer disposed between the flip chip and the second surface of the display substrate.
- connection hole and the second connection hole and a conductive material corresponding to the at least one connection hole penetrate the display substrate and the bonding layer;
- a third connection terminal corresponding to one of the connection holes is disposed on a side of the flip chip that faces the display substrate.
- At least one of the first connection hole and the second connection hole and a conductive material corresponding to the at least one connection hole penetrate the display substrate, the bonding layer, and the flip chip And a third connection terminal corresponding to the at least one connection hole is disposed on a side of the flip chip that faces away from the display substrate.
- the first connection terminal is electrically connected to a first wiring in a display area of the display substrate
- the second connection terminal is electrically connected to a second wiring in a display area of the display substrate, A wiring and a second wiring are alternately arranged.
- the first connection hole is in one-to-one correspondence with the first connection terminal
- the second connection hole is in one-to-one correspondence with the second connection terminal
- the first connection terminal and the second connection are The size of the terminal is larger than the aperture of the corresponding connection hole.
- the apertures of the first connection hole and the second connection hole are greater than or equal to 25 ⁇ m; an orthographic projection of the first connection terminal and the second connection terminal on the display substrate covers a corresponding connection hole at The orthographic projection on the display substrate.
- the first connection terminal or the second connection terminal is adapted to be one or more of the following: a clock connection terminal, a data connection terminal, a high level connection terminal, and a low level connection terminal.
- the display panel may further include: an integrated circuit chip on a side of the flip chip facing away from the display substrate; and a flexible circuit board on the display wafer facing away from the display substrate One side is bonded to the flip chip.
- the display substrate is a flexible display substrate.
- a display device which may include a display panel according to the foregoing description and any embodiments to be described below.
- a method of fabricating a display panel includes: providing a display substrate having a first surface and a second surface opposite to the first surface, the display substrate including a display area and a non- a display area, the non-display area including a first portion and a second portion at least on opposite sides of the display area, and a first connection terminal formed on the first portion of the non-display area and on the first surface And forming a second connection terminal on the second portion of the non-display area and on the first surface; providing a flip chip assembly on the display substrate, wherein the flip chip assembly comprises a flip chip The flip chip is bonded to the second side of the display substrate, the flip chip has a third connection terminal; forming a first connection hole, the first connection hole is in the non-display area a portion, and at least extending through the display substrate; forming a second connection hole, the second connection hole being in the second portion of the non-display area, and extending at least through the display substrate; and in the first
- providing a flip chip assembly on the display substrate includes bonding a flip chip to a second side of the display substrate through a bonding layer.
- At least one of the first connection hole and the second connection hole is formed to penetrate the display substrate and the bonding layer, and a conductive material corresponding to the at least one connection hole Also formed through the display substrate and the bonding layer, and a third connection terminal corresponding to the at least one connection hole is disposed on a side of the flip chip that faces the display substrate.
- At least one of the first connection hole and the second connection hole is formed to penetrate the display substrate, the bonding layer, and the flip chip, and the at least one a conductive material corresponding to the connection hole penetrates the display substrate, the bonding layer, and the flip chip, and a third connection terminal corresponding to the at least one connection hole is disposed away from the display substrate of the flip chip One side.
- the first connection hole is in one-to-one correspondence with the first connection terminal
- the second connection hole is in one-to-one correspondence with the second connection terminal
- the first and second connection terminals are Each of the orthographic projections on the display substrate covers a corresponding connection hole.
- forming the first connection hole and forming the second connection hole are performed by a laser drilling process.
- the fabricating method may further include bonding a flexible circuit board to the flip chip on a side of the flip chip that is provided with the integrated circuit chip.
- the flip chip assembly further includes an integrated circuit chip disposed on a side of the flip chip that faces away from the display substrate.
- the forming the first connection hole and the forming the second connection hole are performed; forming the first connection hole and the second connection After the holes, the forming of the conductive material in the first connection holes and the second connection holes is performed.
- FIG. 1 is a schematic structural view of a display panel in the prior art
- FIGS. 2a to 2h are schematic structural views of a display panel according to an embodiment of the present disclosure.
- connection hole and a connection terminal are schematic structural views of a connection hole and a connection terminal according to an embodiment of the present disclosure
- connection terminal of a flip chip and a connection terminal on a display surface of the display substrate and a connection hole (electrical connection) according to an embodiment of the present disclosure
- 5a and 5b are flowcharts of a method of fabricating a display panel according to an embodiment of the present disclosure
- FIG. 6 is a schematic structural diagram of a display panel corresponding to each step in the method for fabricating a display panel according to an embodiment of the present disclosure
- Figure 7 is a schematic cross-sectional view of the display panel taken along line AA of Figure 6d;
- Figure 8 is a cross-sectional view of the display panel of Figure 6e taken along line BB.
- connection means that one element/node/feature may be mechanically, electrically, logically or indirectly or indirectly with another element/node/feature, unless otherwise explicitly stated. Linked in other ways to allow interaction. That is, "connected” is intended to include both direct and indirect connections of the elements or other features, including the connection of one or more intermediate elements.
- ordinal numbers such as “first”, “second”, “third”, etc. are used to avoid confusion of constituent elements, and are not used in any order of priority.
- FIG. 1 is a schematic view showing the structure of a display panel prepared by a terminal bending technique according to the prior art.
- the substrate terminal portion is bent to achieve a reduced frame (relative to the case where it is not bent).
- the bending also causes terminals (not shown) on the substrate to face the flip chip (COF) for electrical connection.
- COF flip chip
- the inorganic insulating layer may cause cracks, resulting in display failure.
- an inorganic insulating layer connecting the bent portion P of the terminal is removed by adding a mask process; and then an organic insulating layer is formed in the bent portion P of the connecting terminal by adding another Mask process;
- an organic insulating layer is formed in the bent portion P of the connecting terminal by adding another Mask process;
- the two Mask processes are added, which increases the process difficulty and the manufacturing cost, and reduces the production efficiency.
- the formation of the bent portion P of the connection terminal requires an increase in space, and the display product produced by the connection terminal bending process has a low utilization rate for the base substrate.
- the display panel 200 includes a display substrate 201.
- the display substrate 201 has a first surface 2011 and a second surface 2013 opposite to the first surface.
- the display substrate 201 may have a display area 2015 (see FIG. 4b) and a non-display area (eg, an edge portion of the display panel outside the display area 2015). Therefore, the first side 2011 may sometimes be referred to as a display surface.
- a polarizer (Pol) 210 is disposed in association with the display area.
- the non-display area may include a first portion and a second portion at least on opposite sides of the display area.
- a first connection terminal 211 may be formed at a first side of the display area.
- a first connection hole 2051 penetrating the display substrate.
- a second connection terminal 2013 may be formed at a second side opposite the first side, that is, at a portion (second portion) of the non-display area on the second side of the display area and at least The second connection hole 2053 of the substrate is displayed.
- connection terminal and the second connection terminal may be disposed on the first surface.
- connection hole 205" it may refer to or include first connection hole 2051 and second connection hole 2053 as appropriate.
- terminal is intended to include any electrically conductive component suitable for providing or receiving electrical connections, including but not limited to pads, wires, taps, and the like.
- Display panel 200 also includes a flip chip assembly (not labeled).
- the flip chip module may include a flip chip 202.
- the flip chip assembly may further include an integrated circuit chip 204 attached to the flip chip 202.
- the flip chip 202 may be disposed on a side of the display substrate 201 opposite to the first surface (ie, the second surface).
- the integrated circuit chip 204 may be attached to a side of the flip chip 202 that faces away from the display substrate 201.
- a flip chip (correspondingly, a flip chip assembly) may be bonded to the second side of the display substrate opposite the first side by a bonding layer 203.
- the flip chip 202 can have a third connection terminal 208 (as best seen in Figure 3).
- There is no limitation on the manner of mechanical coupling and/or electrical connection of the flip chip 202 and the integrated circuit chip 204 there is no limitation on the manner of mechanical coupling and/or electrical connection of the flip chip 202 and the integrated circuit chip 204, and any person skilled in the art can appropriately
- the first and second connection holes may be disposed such that their orthographic projections on the display substrate are within the orthographic projection of the outer edge of the flip chip on the display substrate.
- the flip chip can be integrally formed.
- a flip chip can be fabricated substantially entirely on the back side (i.e., the second side) of the display substrate to accommodate double side punching.
- the COF can be made larger, providing sufficient space for the wiring thereon, so that the wiring thereon can be fabricated in a single layer.
- the COF is usually relatively small, so the wiring on it usually needs to be made into two layers or more layers, and the process is difficult. Therefore, according to the embodiments of the present disclosure, the manufacturing process can be simplified, the manufacturing cost can be reduced, and the design flexibility can be increased.
- the bonding layer 203 may be formed of different materials.
- the bonding layer 203 may be an insulating bonding layer formed of an insulating material (for example, an insulating bonding material).
- the bonding layer 203 may be formed of, for example, an anisotropic conductive paste.
- connection holes 205 are formed through at least the display substrate 201 and the bonding layer 203.
- the connection hole 205 is filled with a conductive material 206 to form an electrical connection (also referred to as a via or via connection, also designated 206).
- the bonding layer 203 may be an insulating bonding layer.
- the bonding layer 203 may be formed of an anisotropic conductive paste, for example, in some cases, it may be desirable to provide an electrical connection to the back side of the display substrate through the flip chip.
- connection terminal 211 at the first side and the connection terminal 213 at the second side may be connected to the connection terminal 208 provided on the flip chip 202 through respective conductive materials (e.g., via connectors) 206, respectively.
- connection terminal 207 is divided into two parts, which are respectively disposed at the first side and the second side of the display substrate (that is, disposed in the first portion and the second portion of the non-display area).
- the connection terminal 211 at the first side is connected to the corresponding connection terminal 208 on the flip chip 202 through the conductive material 206 in the connection hole 205 (2051) at the first side.
- the connection terminal 213 at the second side is connected to the corresponding connection terminal 208 on the flip chip 202 through the conductive material 206 in the connection hole 205 (2053) at the second side.
- connection holes 205 at the first side or the second side is reduced, so that the size at the edge portion of the display panel (which may correspond to the non-display area) can be reduced or minimized, facilitating the display panel Narrow border design. Therefore, while ensuring high resolution, a display panel having a narrower bezel is obtained.
- each of the connection holes 205 may be disposed through the display substrate 201 and the bonding layer 203.
- the connection terminal 208 may be disposed on a side of the flip chip 202 facing the display substrate 201.
- each of the connection holes 205 may be disposed through the display substrate 201, the bonding layer 203, and the flip chip 202.
- the connection terminal 208 may be disposed on a side of the flip chip 202 facing away from the display substrate 201.
- connection holes 205 may be disposed through the display substrate 201 and the bonding layer 203, and the connection terminals corresponding to the partial connection holes 205 may respectively pass through the conductive portions in the portion of the connection holes 205.
- the material 206 is connected to a corresponding connection terminal 208 disposed on the side of the flip chip 202 facing the display substrate 201.
- a part of the connection holes 205 may be disposed to penetrate through the display substrate 201, the bonding layer 203, and the flip chip 202, and the connection terminals corresponding to the other partial connection holes are respectively connected through the conductive material 206 in the portion connection holes 205.
- connection hole penetrating through the display substrate 201 and the bonding layer 203, and a connection hole penetrating through the display substrate 201, the bonding layer 203, and the flip chip 202 may be simultaneously present at the first side.
- a connection hole penetrating through the display substrate 201 and the bonding layer 203, and a connection hole penetrating through the display substrate 201, the bonding layer 203, and the flip chip 202 may be simultaneously present at the second side.
- the present disclosure is not limited to this. In this way, you can increase the flexibility of your design, such as component placement and routing.
- connection hole 2051 penetrating through the display substrate 201 and the bonding layer 203 at the first side it is also possible to have only the connection hole 2051 penetrating through the display substrate 201 and the bonding layer 203 at the first side, and there is only a through hole at the second side.
- a connection hole 2053 of the substrate 201, the bonding layer 203, and the flip chip 202 is displayed.
- FIG. 2g and FIG. 2h only the connection hole 2051 penetrating through the display substrate 201, the bonding layer 203, and the flip chip 202 is present at the first side of the display region, and the second of the display region is provided.
- the first side and the second side of the display area are in a non-display area on the first side.
- each of the connection holes 205 at the first side and each of the connection holes 205 at the second side are disposed to penetrate the display substrate 201 and the bonding layer 203; or the respective connection holes 205 and the second side at the first side
- Each of the connection holes 205 is provided to penetrate through the display substrate 201, the bonding layer 203, and the flip chip 202. Both of these arrangements can make the depths of all the connection holes 205 on the display substrate 201 the same. Therefore, the process parameters can be set only once, and all the connection holes 205 can be formed, which simplifies the manufacturing process and improves the production efficiency.
- the first connection terminal 211 may be electrically connected to the first wiring 2071 in the display area of the display substrate, the second connection terminal and the display
- the second wiring 2072 in the display area of the substrate is electrically connected.
- the first wiring 2071 and the second wiring 2072 may be alternately arranged.
- the number of the connection terminals at the first side can be made the same as the number of the connection terminals at the second side, so that the number of the connection holes 205 at the first side and the number of the connection holes 205 at the second side
- connection terminal eg, the connection terminal 211 at the first side, the connection terminal 213 at the second side
- the connection terminal may be used as a clock connection terminal, a data connection terminal, a high level ( One or more of VDD) connection terminals and low level (VSS) connection terminals.
- VDD high level connection terminal
- VSS low level connection terminals
- connection terminal at the first side and the connection terminal at the second side simultaneously include a high-level connection terminal and a low-level connection terminal
- the high-level connection terminal and the low-level connection terminal are in the first Simultaneously routing at one side and the second side, thereby avoiding the phenomenon that the upper and lower brightness of the display panel is not uniform due to the IR drop of the high-level connection terminal and the low-level connection terminal to some extent, A more uniform display of brightness can be achieved.
- connection holes 205 are generally arranged to correspond one-to-one with corresponding connection terminals (eg, the connection terminals 208 and the connection terminals 211 or 213).
- FIG. 3 is a schematic structural view of a connection hole and a connection terminal according to an embodiment of the present disclosure.
- 4a and 4b are schematic views showing the connection relationship between the connection terminals of the flip chip and the connection terminals on the display surface of the display substrate and the connection holes (electrical connectors) according to the embodiment of the present disclosure.
- the dimension a of the connection terminal 208 is larger than the aperture d of the connection hole 205 (that is, larger than the diameter of the connector in the connection hole); this may also be the case for the connection terminal 211 or 213.
- the connection terminals are arranged such that their orthographic projections on the display substrate 201 cover the corresponding connection holes 205 to provide a reliable electrical connection.
- the connection terminals 208 may be correspondingly distributed at both ends of the flip chip 202, and the two ends of the flip chip 202 respectively correspond to the first side and the second side of the display substrate 201.
- connection terminals 208 / 211 / 213 may be any shape, such as a triangle, a square or a circle.
- the diameter of the connection terminal is set to be larger than the aperture of the corresponding connection hole 205.
- the shape of the connection terminal is square, as shown in Fig. 3, the side length a of the connection terminal is larger than the aperture d of the connection hole 205. This can be the case for the connection terminals 208/211/213.
- the flip chip may also include terminals that are connected to the pins of the integrated circuit chip 204 (shown in shaded portions in the figure). Therein is shown a terminal M connected to the connection terminal 208 by a wire (which may be disposed in the same layer as the connection terminal 208); and a terminal N not connected to the connection terminal 208 (which may be disposed in the same layer as the connection terminal 208, or may be The connection terminal 208 is set in a different layer).
- connection terminals 208 of the flip chip 202 may be large in number and high in density.
- a laser drilling process may be employed.
- the connection hole 205 having the desired aperture and hole depth can be obtained by controlling the diameter and energy of the laser.
- the connection holes 205 can also be made by other processes known to those skilled in the art.
- the aperture d of each of the connection holes 205 is set to be greater than or equal to 25 ⁇ m, that is, the minimum value of the aperture d of each of the connection holes 205 may be 25 ⁇ m.
- the dimensions of the various components at both ends of the first side of the display panel ie, the first side and the second side of the display area) can be minimized to further achieve a narrow bezel.
- the conductive material 206 may be formed of a conductive material (eg, a metal material) having a small electrical resistivity and a good electrical conductivity.
- a conductive material eg, a metal material
- the conductive material 206 can also be other materials having electrical conductivity, such as indium tin oxide, indium zinc oxide or graphene.
- the display substrate 201 may be a flexible display substrate or a rigid display substrate.
- the display substrate 201 is a flexible display substrate, such as an Organic Light Emitting Diodes (OLED) display substrate, or a Quantum Dot Light Emitting Diodes (QLED) display substrate.
- OLED Organic Light Emitting Diodes
- QLED Quantum Dot Light Emitting Diodes
- the display panel may further include a flexible circuit board 209 attached to a portion of the flip chip.
- the power, charge, control signals, and the like required for pixel driving in the display panel can be provided by an external flexible printed circuit (FPC).
- the flexible circuit board 209 may be bonded to the side of the flip chip 202 facing away from the display substrate 201.
- power and control signals and the like can be transmitted to the display panel through the flip chip 202 and the electrical connector 206, for example to the terminals 211-213 of the display panel.
- the electrical connection between the flexible circuit board and the display substrate can be provided by the aforementioned electrical connectors or additional electrical connectors.
- the display area of the first side of the display substrate 201 may be further included.
- a polarizer (Pol) 210 is provided in association with it.
- the polarizer 210 can be any suitable polarizer known in the art or developed in the future, and can be attached to the display area using any attachment technique known in the art or developed in the future. Here, further detailed description thereof is omitted.
- a method of fabricating a display panel is also provided.
- 5a and 5b respectively illustrate a flow chart of a method of fabricating a display panel in accordance with some embodiments of the present disclosure.
- a display substrate 201 is provided.
- the display substrate 201 may have a first face 2011 and an opposite second face 2013.
- the display substrate 201 may have a display area and a non-display area around the display area.
- the hole 2051 is connected.
- a second connection terminal 213 is formed at a second side opposite to the first side (ie, a portion (second portion) of the non-display area on the second side of the display area) and at least through the display a second connection hole 2053 of the substrate.
- the flip chip 202 is bonded to the side of the display substrate opposite to the first surface (face 2013) to bond the flip chip assembly to the display substrate.
- the flip chip assembly includes the flip chip 202.
- the flip chip assembly may further include an integrated circuit chip 204.
- the integrated circuit chip 204 may be disposed on a side of the flip chip that faces away from the display substrate.
- the flip chip may have a third connection terminal 208.
- a flip chip may be attached to the face 2013 of the display substrate opposite to the first face 2011 by a bonding layer (eg, an insulating glue or an anisotropic conductive paste) 203.
- the bonding layer or a portion thereof herein may be formed of an anisotropic conductive paste.
- the first connection hole and the second connection hole may be disposed such that their orthographic projection on the display substrate is within an orthographic projection of the outer edge of the flip chip on the display substrate.
- a conductive material 206 (such as, but not limited to, a conductive paste) is formed (eg, filled) in the first and second connection holes to form a corresponding electrical connection (also indicated at 206).
- the first connection terminal 211 and the second connection terminal 213 may be electrically connected to respective third connection terminals 208 of the flip chip by respective electrical connectors. In this way, a reliable electrical connection between the electrical connector and the corresponding terminal can be provided.
- a display substrate 201 is provided.
- the display substrate 201 may have a first face 2011 and an opposite second face 2013.
- the display substrate may have a display area and a non-display area.
- the non-display area includes a first portion and a second portion at least on opposite sides of the display area.
- a first connection terminal 211 is formed at a first side of the display area.
- a second connection terminal 213 is formed at a second side opposite the first side, that is, at a portion (second portion) of the non-display area on the second side of the display area.
- a flip chip assembly is disposed on the display substrate.
- the flip chip assembly includes a flip chip.
- the flip chip assembly can include a flip chip and an integrated circuit chip.
- the flip chip 202 may be disposed on the surface 2013 of the display substrate opposite to the first surface.
- An integrated circuit chip 204 can be attached to a side of the flip chip that faces away from the display substrate.
- a flip chip may be attached to the second face 2013 of the display substrate opposite the first face by a bonding layer (eg, an anisotropic conductive paste) 203.
- step S603 a first connection hole is formed.
- a first connection hole 2051 penetrating at least the display substrate may be formed in the first portion of the non-display area.
- a second connection hole is formed.
- a second connection hole 2053 extending through at least the display substrate may be formed in the second portion of the non-display area.
- Steps S603 and S604 (that is, formation of the first connection hole and the second connection hole) may be performed simultaneously or separately. According to various embodiments, steps S603 and S604 may also be performed before or after S602.
- a conductive material 206 is formed in the first and second connection holes. Thereby, corresponding electrical connectors are formed.
- the first connection terminal and the second connection terminal are respectively electrically connected to respective third connection terminals of the flip chip by respective conductive materials.
- electrical connection to the display substrate such as electricity between the flip chip (or integrated circuit chip thereon) and the display substrate, may be provided at least by the conductive material (and the above-described terminals, etc.) connection.
- the first connection hole and the second connection hole may be disposed such that their orthographic projection on the display substrate is within an orthographic projection of the outer edge of the flip chip on the display substrate.
- the step of forming the connection holes through the display substrate may be performed before or after bonding the flip chip (or the flip chip assembly).
- the step of forming a conductive material can be performed before or after the step of setting up the COF assembly.
- the forming the first connection hole and the forming the second connection hole may be performed after the flip chip assembly is disposed on the display substrate. In some implementations, forming the conductive material in the first connection hole and the second connection hole may be performed after forming the first connection hole and the second connection hole.
- providing the flip chip assembly to the face of the display substrate opposite the first side can include a variety of implementations.
- an integrated circuit chip may be disposed on the flip chip; thereafter, the flip chip is attached to a side (face) of the display substrate away from the first face, for example, by a conductive paste.
- the manner in which the flip chip module is disposed to the display substrate is not limited thereto as long as the integrated circuit chip is finally attached to the flip chip and the flip chip is attached to the display substrate.
- a plurality of connection holes extending through at least the display substrate and the bonding layer are respectively formed at the first side of the first surface and the second side opposite to the first side, which may be implemented by the following steps. Forming a plurality of connection holes through the display substrate and the bonding layer at a first side of the first side and a second side opposite to the first side, respectively, such that the connection terminal at the first side and the second side
- the connection terminals are respectively connected to the connection terminals provided on the side of the flip chip facing the display substrate by a conductive material.
- a plurality of connection holes extending through at least the display substrate and the bonding layer are respectively formed at the first side of the first surface and the second side opposite to the first side, and can also be implemented by the following steps. Forming a plurality of connection holes penetrating through the display substrate, the bonding layer, and the flip chip at a first side of the first side and a second side opposite to the first side, such that the connection terminal at the first side and the The connection terminals at the two sides are respectively connected to the connection terminals disposed on the flip chip away from the display substrate by a conductive material.
- connection holes extending through at least the display substrate and the bonding layer are respectively formed at the first side of the first surface and the second side opposite to the first side.
- a partial connection hole penetrating through the display substrate and the bonding layer is formed at a first side of the first face and a second side opposite to the first side, respectively, such that the connection terminal at the first side and the connection terminal at the second side Connected to the connection terminal disposed on the side of the flip chip facing the display substrate through the conductive material in the portion of the connection hole;
- connection terminals at the side are respectively connected to the connecting terminals disposed on the side of the flip chip facing away from the display substrate through the conductive material in the remaining portion connecting holes.
- connection holes extending through at least the display substrate and the bonding layer are respectively formed at the first side of the first surface and the second side opposite to the first side, and the following steps may also be achieve:
- connection holes penetrating the display substrate and the bonding layer at the first side of the first surface such that the connection terminals at the first side are connected to the connection terminals disposed on the flip chip facing the display substrate through the conductive material; a plurality of connection holes penetrating through the display substrate, the bonding layer and the flip chip are formed at a second side of the first side opposite to the first side, such that the connection terminals at the second side are connected to the flip chip by a conductive material a connection terminal that faces away from the display substrate; or,
- connection terminals at the first side are connected to the connection disposed on the flip chip away from the display substrate by a conductive material
- a plurality of connection holes penetrating through the display substrate and the bonding layer at a second side of the first surface opposite to the first side such that the connection terminals at the second side are connected to the flip chip by a conductive material A connection terminal facing the display substrate.
- At least one of the first connection hole and the second connection hole and a conductive material corresponding to the at least one connection hole may be configured to penetrate the display substrate and the bonding layer.
- a third connection terminal corresponding to the at least one connection hole may be disposed on a side of the flip chip that faces the display substrate.
- At least one of the first connection hole and the second connection hole and a conductive material corresponding to the at least one connection hole may be configured to penetrate the display substrate, the bonding layer, and The flip chip.
- a third connection terminal corresponding to the at least one connection hole may be disposed on a side of the flip chip that faces away from the display substrate.
- the first connection holes may be in one-to-one correspondence with the first connection terminals.
- the second connection hole may have a one-to-one correspondence with the second connection terminal.
- Each of the first and second connection terminals may have a size larger than a diameter of the corresponding connection hole.
- An orthographic projection of each of the first and second connection terminals on the display substrate may be configured to cover a corresponding connection hole.
- the method further includes the step of bonding the flexible circuit board to the flip chip on a side of the flip chip in which the integrated circuit chip is disposed.
- an integrated circuit chip may be disposed on the flip chip, and the flexible circuit board may be bonded to the side of the flip chip on which the integrated circuit chip is disposed.
- the step of bonding the flexible circuit board on the side where the flip chip is provided with the integrated circuit chip may be performed before or after the integrated circuit chip is disposed on the flip chip.
- a flip chip may be bonded to the second side of the display substrate by a bonding layer such as, but not limited to, an anisotropic conductive paste.
- a partial connection aperture eg, a first connection aperture
- an electrical connector corresponding thereto can be configured to extend through the display substrate and the bonding layer.
- a third connection terminal corresponding to the connection hole may be disposed on a side of the flip chip that faces the display substrate.
- a partial connection hole eg, a second connection hole
- an electrical connection corresponding thereto penetrate the display substrate, the bonding layer, and the flip chip.
- a third connection terminal corresponding to the connection hole may be disposed on a side of the flip chip that faces away from the display substrate.
- the flip chip can be integral.
- the method may further include bonding a flexible circuit board to the flip chip on a side of the flip chip that is provided with the integrated circuit chip.
- FIGS. 6a to 6e respectively illustrate structural diagrams of display panels corresponding to certain steps in a method of fabricating a display panel according to some embodiments of the present disclosure.
- Figure 7 is a schematic cross-sectional view of the display panel of Figure 6d taken along line AA.
- Figure 8 is a cross-sectional view of the display panel of Figure 6e taken along line BB.
- a method of fabricating a display panel in accordance with some embodiments of the present disclosure is described below in conjunction with FIGS. 6a-6e, 7-8, and 2a-2d.
- a display substrate 201 is provided.
- a polarizer 210 may be attached to the display area of the display substrate 201.
- a first connection terminal may be formed at a first side of the first face, that is, at a portion (first portion) of the non-display area on the first side of the display area.
- a second connection terminal is formed at a second side opposite the first side, that is, at a portion (second portion) of the non-display area on the second side of the display area.
- the flip chip module may include a flip chip 202.
- the flip chip assembly can further include an integrated circuit chip 204.
- an integrated circuit chip 204 can be disposed on the flip chip 202.
- the flexible circuit board 209 may also be bonded (attached) to the side of the flip chip 202 on which the integrated circuit chip 204 is disposed.
- the flip chip 202 can have one or more connection terminals 208. The connection terminals 208 may be disposed on different surfaces or different layers of the flip chip 202 according to different needs.
- the flip chip 202 is bonded to the side of the display substrate 201 facing away from the first surface (ie, the second side), for example, by the bonding layer 203.
- the integrated circuit chip 204 may be disposed on a side of the flip chip 202 facing away from the display substrate 201.
- the punching may be performed from the first side of the display substrate 201 by, for example, a laser puncturing process, at the first side of the first side (ie, in the non-display area). a portion (first portion) on the first side of the display area and a second side opposite the first side (that is, a portion (second portion) on the second side of the display area in the non-display area) A plurality of connection holes 2051 and 2053 penetrating the display substrate 201 and the bonding layer 203 are formed. The remaining connection terminal portions 211/213 after punching and the connection terminals 208 on the flip chip are also schematically shown in FIG.
- connection holes may be arranged such that its orthographic projection on the display substrate is located within the orthographic projection of the outer edge of the flip chip on the display substrate.
- connection holes 205 may correspond to the connection terminal 208 of the flip chip 202 facing the display substrate 201, and correspond to the connection terminals 211/213 on the first surface of the display substrate, respectively.
- the size of the connection terminal 208/211/213 may be set larger than the aperture of the connection hole 205.
- the connection terminals 208/211/213 may be disposed such that the orthographic projection on the display substrate 201 covers the corresponding connection hole 205.
- connection terminal 208 is shown in Figures 2a and 2b.
- FIGS. 2c and 2d The detailed process of producing the display panel as shown in FIGS. 2c and 2d is similar to the detailed process of fabricating the display panel shown in FIGS. 2a and 2b, the difference being mainly in the steps of forming the connection hole 205 and the position setting of the connection terminal 208. It is different.
- Figures 6e and 8 show schematic structures as an alternative implementation of the connection hole forming step of Figure 6d. The steps before Figure 6e can be substantially the same as those shown in Figures 6a-c. Therefore, only the differences between the display panel shown in FIG. 2c and FIG. 2d and the display panel shown in FIG. 2a and FIG. 2b are described here, and the repeated points are not described again.
- a laser drilling process may be employed, from the side of the display substrate 201 facing away from the first side, that is, from the side of the flip chip, at the first side of the display area and opposite to the first side
- the two sides i.e., the first portion and the second portion of the non-display area respectively form a plurality of connection holes 205 penetrating through the flip chip 202, the bonding layer 203, and the display substrate 201, as shown in Figs. 6e and 8.
- each of the connection holes 205 and each of the connection terminals 208 of the flip chip 20 facing away from the display substrate 201 may be disposed in a one-to-one correspondence.
- the connection terminal 208 may have a size larger than the aperture of the connection hole 205.
- the orthographic projection of the connection terminal 208 on the display substrate 201 covers the corresponding connection hole 205.
- the connection terminals 211/213 can also be configured as such.
- connection terminal 208 as shown in Figures 2c and 2d.
- the display panel according to an embodiment of the present disclosure can be applied to a wide variety of display devices including, but not limited to, mobile phones, tablet computers, televisions, displays, notebook computers, digital photo frames, navigators, smart watches, fitness wristbands, individuals. Any product or component that has a display function, such as a digital assistant.
- display device reference may be made to the embodiment of the above display panel, and the repeated description is omitted.
- connection terminal bending process is omitted, so that the connection terminal bending region does not exist at the edge of the display panel, thereby making the frame of the display panel narrower.
- the number of connection holes at the first side or the second side is reduced, achieving a narrow bezel design of the display panel. Therefore, while ensuring high resolution, a display panel having a narrower bezel is obtained.
- the substrate utilization efficiency can be improved, the yield can be improved, the manufacturing process can be simplified, and/or the manufacturing cost can be reduced.
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Abstract
一种显示面板(200)、显示装置及显示面板(200)的制作方法,其中显示面板(200)包括:显示基板(201),具有第一面(2011)以及与第一面(2011)相对的第二面(2013),显示基板(201)包括显示区(2015)以及非显示区,非显示区包括至少位于显示区(2015)相对的两侧的第一部分和第二部分;第一连接端子(211),位于第一部分,且位于第一面(2011)上;第一连接孔(2051),位于第一部分,且第一连接孔(2051)至少贯穿显示基板(201);第二连接端子(213),位于第二部分,且位于第一面(2011)上;第二连接孔(2053),位于第二部分,且第二连接孔(2053)至少贯穿显示基板(201);覆晶薄膜(202),位于显示基板(201)的第二面(2013),覆晶薄膜(202)包括第三连接端子(208);导电材料(206),导电材料(206)分别设置在相应的第一连接孔(2051)和第二连接孔(2053)中;其中显示基板(201)的第一连接端子(211)和第二连接端子(213)分别通过位于第一连接孔(2051)和第二连接孔(2053)中的导电材料(206)与相应的第三连接端子(208)电连接;其中,第一连接孔(2051)和第二连接孔(2053)在显示基板(201)上的正投影位于覆晶薄膜(202)的外边缘在显示基板(201)上的正投影内。
Description
相关申请的交叉引用
本申请要求于2017年5月27日提交的中国申请201710392688.6的优先权,并通过引用将其全文并入在此。
本公开涉及显示技术领域,尤其涉及显示面板、显示装置及显示面板的制作方法。
随着显示技术的不断进步,显示面板在显示产品中的运用越来越广泛。具有窄边框(Narrow Bezel)的显示产品(比如,手机(特别是全面屏手机)或穿戴设备(例如,智能手表)因其可以使用户获得较好的观看体验,吸引了大量的消费者。
目前,连接端子弯折(Pad Bending)工艺是实现具有窄边框的显示面板的唯一方案。但是采用连接端子弯折工艺制作的显示面板的不良问题较多,存在无机绝缘层产生裂纹导致的显示失效现象。另外,现有技术的端子弯折技术还增加工艺难度和制造成本,降低了生产效率。此外,端子弯折区域P的形成需要增加空间,并且采用连接端子弯折工艺制作的显示产品对衬底基板的利用率较低。
另一方面,高分辨率(PPI)的显示面板因其具有较好的视觉效果,已逐渐成为显示行业的发展趋势。然而,分辨率越高,显示面板中所需设置的连接端子(也可简称为端子)越多。在这种情况下,实现较窄的边框设计成为挑战。
因此,存在对具有高分辨率并具有较窄边框的显示产品及其制造方法的需求。
发明内容
有鉴于此,本公开的实施例提供了一种显示面板、显示装置及显示面板的制作方法。
根据本公开一个方面,提供了一种显示面板,包括:显示基板,具有第一面以及与所述第一面相对的第二面,所述显示基板包括显示区以及非显示区,所述非显示区包括至少位于所述显示区相对的两侧的第一部分和第二部分;第一连接端子,位于所述第一部分,且位于所述第一面上;第一连接孔,位于所述第一部分,且所述第一连接孔至少贯穿所述 显示基板;第二连接端子,位于所述第二部分,且位于所述第一面上;第二连接孔,位于所述第二部分,且所述第二连接孔至少贯穿所述显示基板;覆晶薄膜,位于所述显示基板的第二面,所述覆晶薄膜包括第三连接端子;导电材料,所述导电材料分别设置在相应的第一连接孔和第二连接孔中;其中所述显示基板的第一连接端子和第二连接端子分别通过位于所述第一连接孔和所述第二连接孔中的导电材料与相应的第三连接端子电连接;其中,所述第一连接孔和第二连接孔在显示基板上的正投影位于所述覆晶薄膜的外边缘在显示基板上的正投影内。
在一些实施例中,所述显示面板还可以包括:接合层,设置在所述覆晶薄膜和所述显示基板的第二面之间。
在一些实施例中,所述第一连接孔和第二连接孔中的至少一个连接孔以及与该至少一个连接孔对应的导电材料贯穿所述显示基板和所述接合层;其中与所述至少一个连接孔对应的第三连接端子设置于所述覆晶薄膜的面向所述显示基板的一侧。
在一些实施例中,所述第一连接孔和第二连接孔中的至少一个连接孔以及与该至少一个连接孔对应的导电材料贯穿所述显示基板、所述接合层和所述覆晶薄膜;其中与所述至少一个连接孔对应的第三连接端子设置于所述覆晶薄膜的背离所述显示基板的一侧。
在一些实施例中,所述第一连接端子与所述显示基板的显示区域中的第一布线电连接,所述第二连接端子与所述显示基板的显示区域中第二布线电连接,第一布线和第二布线交替设置。
在一些实施例中,所述第一连接孔与所述第一连接端子一一对应,所述第二连接孔与所述第二连接端子一一对应,所述第一连接端子和第二连接端子的尺寸大于对应的连接孔的孔径。
在一些实施例中,所述第一连接孔和第二连接孔的孔径大于或等于25μm;所述第一连接端子和第二连接端子在所述显示基板上的正投影覆盖对应的连接孔在所述显示基板上的正投影。
在一些实施例中,所述第一连接端子或所述第二连接端子适于作为下列中的一个或多个:时钟连接端子、数据连接端子、高电平连接端子、低电平连接端子。
在一些实施例中,所述显示面板还可以包括:集成电路芯片,位于所述覆晶薄膜背离所述显示基板的一侧;以及柔性电路板,在所述覆晶薄膜的背离所述显示基板的一侧接合到所述覆晶薄膜。
在一些实施例中,所述显示基板为柔性显示基板。
根据本公开另一方面,提供了一种显示装置,其可以包括根据前面描述的以及下面将描述任意实施例的显示面板。
根据本公开又一方面,提供了一种显示面板的制作方法,包括:提供显示基板,其具有第一面以及与所述第一面相对的第二面,所述显示基板包括显示区以及非显示区,所述非显示区包括至少位于所述显示区相对的两侧的第一部分和第二部分,在所述非显示区的第一部分且在所述第一面上形成有第一连接端子,以及在所述非显示区的第二部分且在所述第一面上形成有第二连接端子;在所述显示基板上设置覆晶薄膜组件,其中所述覆晶薄膜组件包括覆晶薄膜,其中所述覆晶薄膜被接合到所述显示基板的第二面,所述覆晶薄膜具有第三连接端子;形成第一连接孔,所述第一连接孔在所述非显示区的第一部分,并至少贯穿所述显示基板;形成第二连接孔,所述第二连接孔在所述非显示区的第二部分,并至少贯穿所述显示基板;以及在所述第一连接孔和第二连接孔中形成导电材料,其中,所述第一连接端子和所述第二连接端子分别通过相应的导电材料电连接到所述覆晶薄膜的相应的第三连接端子,其中,所述第一连接孔和第二连接孔被设置为其在显示基板上的正投影在所述覆晶薄膜的外边缘在显示基板上的正投影内。
在一些实施例中,在所述显示基板上设置覆晶薄膜组件包括:通过接合层,将覆晶薄膜接合到所述显示基板的第二面上。
在一些实施例中,所述第一连接孔和所述第二连接孔中的至少一个连接孔被形成为贯穿所述显示基板和所述接合层,与所述至少一个连接孔对应的导电材料也被形成为贯穿所述显示基板和所述接合层,并且与所述至少一个连接孔对应的第三连接端子设置于所述覆晶薄膜的面对所述显示基板的一侧。
在一些实施例中,所述第一连接孔和所述第二连接孔中的至少一个连接孔被形成为贯穿所述显示基板、所述接合层和所述覆晶薄膜,与所述至少一个连接孔对应的导电材料贯穿所述显示基板、所述接合层和所述覆晶薄膜,并且与所述至少一个连接孔对应的第三连接端子设置于所述覆晶薄膜的背离所述显示基板的一侧。
在一些实施例中,所述第一连接孔与所述第一连接端子一一对应,所述第二连接孔与所述第二连接端子一一对应,所述第一和第二连接端子中的每一个在所述显示基板上的正投影覆盖对应的连接孔。
在一些实施例中,形成第一连接孔和形成第二连接孔是通过激光打孔工艺进行的。
在一些实施例中,所述制作方法还可以包括:在所述覆晶薄膜的设置有所述集成电路芯片的一侧将柔性电路板接合到所述覆晶薄膜。
在一些实施例中,所述覆晶薄膜组件还包括设置在所述覆晶薄膜的背离所述显示基板一侧的集成电路芯片。
在一些实施例中,在所述显示基板上设置覆晶薄膜组件之后,执行所述形成第一连接孔和所述形成第二连接孔;在形成所述第一连接孔和所述第二连接孔之后,执行所述在所述第一连接孔和所述第二连接孔中形成导电材料。
通过以下参照附图对本发明的示例性实施例的详细描述,本发明的其它特征及其优点将会变得清楚。
附图构成本说明书的一部分,其描述了本公开的示例性实施例,并且连同说明书一起用于解释本发明的原理,在附图中:
图1为现有技术中显示面板的结构示意图;
图2a至图2h分别为本公开实施例的显示面板的结构示意图;
图3为本公开实施例的连接孔与连接端子的结构示意图;
图4a和4b为本公开实施例的覆晶薄膜的连接端子以及显示基板的显示面上的连接端子与连接孔(电连接件)的连接关系的示意图;
图5a和5b为本公开实施例的显示面板的制作方法的流程图;
图6a至图6e分别为实施本公开实施例的显示面板的制作方法中的各步骤对应的显示面板的结构示意图;
图7为图6d中显示面板沿AA线的截面示意图;
图8为图6e中显示面板沿BB线的截面示意图。
注意,在以下说明的实施方式中,有时在不同的附图之间共同使用同一附图标记来表示相同部分或具有相同功能的部分,而省略其重复说明。在本说明书中,使用相似的标号和字母表示类似项,因此,一旦某一项在一个附图中被定义,则在随后的附图中不需要对其进行进一步讨论。
下面,参照附图对本说明书所公开的发明的实施方式进行详细说明。但应理解,对各种实施例的描述仅仅是说明性的,在任何意义上都不是对本申请所要求保护的发明的限制。除非另有具体说明或者上下文或其原理明示或者暗示,在示例性实施例中的组件和步骤的相对布置、表达式和数值等不作为对本申请所要保护的发明的限制。在本说明书中,对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论,但在适当情况下,所述技术、方法和设备应当被视为说明书的一部分。
本文中所用的术语,仅仅是为了描述特定的实施例,而不意图限制本公开。应理解的是,“包括/包含”一词在本文中使用时,说明存在所指出的特征、整体、步骤、操作、单元和/或组件,但是并不排除存在或增加一个或多个其它特征、整体、步骤、操作、单元和/或组件以及/或者它们的组合。
如在此所使用的,除非另外明确说明,术语“连接”意指一个元件/节点/特征可以与另一元件/节点/特征以直接的或间接的方式在机械上、电学上、逻辑上或以其它方式连结以允许相互作用。也就是说,“连接”意图包含元件或其它特征的直接连接和间接连接,包括利用一个或多个中间元件的连接。
在本公开中,诸如“第一”、“第二”、“第三”等的序数词是为了避免构成要素的混淆而标记的,而不用于在任何方面上的优先次序。
应理解,附图中各膜/层仅出于示意性的目的而示出,其尺寸和形状并不表示其实际尺寸和形状。
图1示出了根据现有技术的端子弯折技术制备的显示面板的结构示意图。如图1所示,将基板端子部弯折以实现减小的边框(相对于不弯折的情况)。弯折还使得基板上的端子(未示出)面对覆晶薄膜(COF)来进行电连接。然而,在端子弯折区域P,无机绝缘层会产生裂纹,导致显示失效。现有技术中通过增加一道掩膜(Mask)工艺,以去除连接端子弯折区域P的无机绝缘层;之后再通过增加另一道Mask工艺,在连接端子弯折区域P形成一有机绝缘层;从而来避免在弯折过程中端子弯折区域P的无机绝缘层产生裂纹导致的显示失效现象。虽然这在一定程度上避免无机绝缘层产生裂纹导致的显示失效现象,但增加了两道Mask工艺,增加了工艺难度和制造成本,降低了生产效率。此外,连接端子弯折区域P的形成需要增加空间,并且采用连接端子弯折工艺制作的显示产品对衬底基板的利 用率较低。
另一方面,高分辨率(PPI)的显示面板因其具有较好的视觉效果,已逐渐成为显示行业的发展趋势。然而,分辨率越高,显示面板中所需设置的布线(例如电源线、地线、各种信号线等)以及对应的连接端子(也可简称为端子)越多。这可能不利于窄边框的实现。在分辨率较高的情况下,实现较窄的边框设计成为挑战。
图2a至图2h示出了根据本公开一些实施例的显示面板的结构示意图。如图2a和2b所示,显示面板200包括显示基板201。显示基板201具有第一面2011以及与第一面相对的第二面2013。显示基板201可以具有显示区2015(见图4b)以及非显示区(例如,显示面板在显示区2015外的边缘部分)。因此,第一面2011有时也可以称为显示面。在显示基板上,与显示区相关联地设置有偏光片(Polarizer,Pol)210。
在本公开的一些实施例中,非显示区可以包括至少位于所述显示区相对的两侧的第一部分和第二部分。如图2a和2b中所示,在所述显示区的第一侧处,也即,在非显示区的在显示区的第一侧的部分(第一部分),可以形成有第一连接端子211和至少贯穿所述显示基板的第一连接孔2051。在与所述第一侧相对的第二侧处,也即,在非显示区的在显示区的第二侧的部分(第二部分),可以形成有第二连接端子2013和至少贯穿所述显示基板的第二连接孔2053。第一连接端子和第二连接端子可以设置在第一面上。在本文中,使用数字205来共同地指示连接孔。例如,当称呼“连接孔205”时,在适当时其可以指代或者包括第一连接孔2051和第二连接孔2053。另外,在本申请文件中,术语“端子”意图包括任何适于提供或者接收电连接的导电部件,包括但不限于焊盘、导线、抽头(tap)等等。
显示面板200还包括覆晶薄膜组件(未标示)。覆晶薄膜组件可以包括覆晶薄膜202。覆晶薄膜组件可以还包括附接到覆晶薄膜202的集成电路芯片204。覆晶薄膜202可以设置于显示基板201的与第一面相反的一侧(即,第二面)上。集成电路芯片204可以附接到覆晶薄膜202的背离显示基板201的一侧。覆晶薄膜(相应地,覆晶薄膜组件)可以通过接合层203接合到所述显示基板的与第一面相反的第二面上。覆晶薄膜202可以具有第三连接端子208(如图3最佳地看到的)。对于覆晶薄膜202和集成电路芯片204的机械耦接和/或电连接的方式没有任何限制,本领域技术人员可以根据需要适当地应用相关领域中已知的或者将来开发的任何技术。
如图中所示,第一连接孔和第二连接孔可以被设置为其在显示基板上的正投影在所 述覆晶薄膜的外边缘在显示基板上的正投影内。在一些实施例中,覆晶薄膜可以是一体形成的。
根据这些实施例的方案,覆晶薄膜(COF)可以在显示基板的背面(也即,第二面)上基本上整面地制作,这样以适应双侧打孔。如此,COF可以制作得较大,给其上的布线提供了足够的空间,所以其上的布线可以进行单层制作。而现有技术中COF通常比较小,所以其上的布线通常需要制作成双层或更多层,工艺难度较大。因此,根据本公开的实施例,可以简化制造工艺,降低制造成本,还可以增加设计的灵活性。
根据不同的实施例,接合层203可以由不同材料形成。例如,接合层203可以是由绝缘材料(例如,绝缘性粘接材料)形成的绝缘接合层。替代地,接合层203可以由例如异方性导电胶形成。
在图2a和2b中所示的实施例中,在显示区的第一侧处和与第一侧相对的第二侧处,也即,在非显示区的第一部分和第二部分处,分别形成有至少贯穿显示基板201和接合层203的多个连接孔205。在连接孔205中填充有导电材料206以形成电连接件(也称作通孔(via)或通孔连接件,同样以206标示。在这样的实施例中,接合层203可以是绝缘接合层;或者,在替代实施例中,接合层203可以由异方性导电胶形成,例如,在某些情况下,可能会希望通过覆晶薄膜向显示基板的背面提供电连接。
位于第一侧处的连接端子211和位于第二侧处的连接端子213可以分别通过相应的导电材料(如,通孔连接件)206连接于设置在覆晶薄膜202的连接端子208。
由于在高分辨率的条件下,显示基板201上可能会设置数量众多的连接端子。在本公开实施例中,将连接端子207分为两部分,分别设置于显示基板的第一侧处和第二侧处(也即,设置于非显示区的第一部分和第二部分中)。并使位于第一侧处的连接端子211通过第一侧处的连接孔205(2051)内的导电材料206与覆晶薄膜202上的对应的连接端子208相连。使位于第二侧处的连接端子213通过第二侧处的连接孔205(2053)内的导电材料206与覆晶薄膜202上对应的连接端子208相连。从而,减少了第一侧处或第二侧处的连接孔205的数量,使得在显示面板的边缘部分处(可以对应于非显示区)的尺寸可以减小或者最小化,促进了显示面板的窄边框设计。因此,在保证高分辨率的同时,获得了具有较窄边框的显示面板。
在本公开的一些实施例中,如图2a和图2b所示,可以设置各连接孔205贯穿显示基板201和接合层203。连接端子208可以设置于覆晶薄膜202面向显示基板201的一侧。 利用这样的设置,在后续对各连接孔205填充导电材料来形成导电材料206之后,可以实现金属材料206与覆晶薄膜202之间的面接触,从而有效减小了接触电阻。
在本公开的另外一些实施例中,如图2c和图2d所示,还可以设置各连接孔205贯穿显示基板201、接合层203和覆晶薄膜202。连接端子208可以设置于覆晶薄膜202背离显示基板201的一侧。利用这样的设置,在实际操作时,可以在将覆晶薄膜202贴合到显示基板201的背离第一面的一侧(也即,第二面)后,将显示基板201一侧直接放置在设备平台上,从而可以从覆晶薄膜202一侧进行打孔,从而对显示面板进行打孔。如此,避免了对设备平台进行特殊处理。此外,根据该实施例,还可以提高制造的精度,从而可以提供可靠的电连接。
再如,在本公开的一些其他实施例中,还可以设置一部分连接孔205贯穿显示基板201和接合层203,与该部分连接孔205对应的连接端子可以分别通过该部分连接孔205内的导电材料206,而连接到设置在覆晶薄膜202面向显示基板201一侧的对应的连接端子208。还可以将其它的一部分连接孔205设置为贯穿显示基板201、接合层203和覆晶薄膜202,与该其他的部分连接孔对应的连接端子分别通过该部分连接孔205内的导电材料206,连接到设置在覆晶薄膜202的背离显示基板201一侧的对应的连接端子208。
在一个示例中,可以在第一侧处同时存在贯穿显示基板201和接合层203的连接孔,以及贯穿显示基板201、接合层203和覆晶薄膜202的连接孔。在第二侧处也可以同时存在贯穿显示基板201和接合层203的连接孔,以及贯穿显示基板201、接合层203和覆晶薄膜202的连接孔。显然,本公开不限于此。如此,可以增加设计(例如组件布局和布线)的灵活性。
在本公开的其他一些实施例中,如图2e和图2f所示,还可以使第一侧处仅存在贯穿显示基板201和接合层203的连接孔2051,并使第二侧处仅存在贯穿显示基板201、接合层203和覆晶薄膜202的连接孔2053。在其他实施例中,如图2g和图2h所示,使显示区的第一侧处仅存在贯穿显示基板201、接合层203和覆晶薄膜202的连接孔2051,并使显示区的第二侧处仅存在贯穿显示基板201和接合层203的连接孔2053。优选地,所述显示区的第一侧和第二侧处于第一面上的非显示区中。
需要说明的是,在实际应用时,优选将显示基板201上的全部连接孔205的深度设置为相同。例如,将第一侧处的各连接孔205和第二侧处的各连接孔205全部设置为贯穿显示基板201和接合层203;或者将第一侧处的各连接孔205和第二侧处的各连接孔205全 部设置为贯穿显示基板201、接合层203和覆晶薄膜202。这两种设置方式,均可以使得显示基板201上的全部连接孔205的深度相同。从而,可以仅设置一次工艺参数,形成全部的连接孔205,简化了制作工艺,提高了生产效率。
另外,在本公开的一些实施例中,如图4b所示,第一连接端子211可以与所述显示基板的显示区中的第一布线2071电连接,所述第二连接端子与所述显示基板的显示区中第二布线2072电连接。第一布线2071和第二布线2072可以交替设置。
通过这样设置,可以使第一侧处的连接端子的数量与第二侧处的连接端子的数量相同,从而使得第一侧处的连接孔205的数量与第二侧处的连接孔205的数量形同,进而使得第一侧和第二侧的宽度(w)相同。在将这种第一侧和第二侧宽度相同的显示面板应用到手表、手环之类的穿戴产品中时,更有利于提高手表、手环之类的穿戴产品的结构稳定性。
在本公开的一些实施例中,连接端子(如,第一侧处的连接端子211、第二侧处的连接端子213)可以用作时钟连接端子、数据(Data)连接端子、高电平(VDD)连接端子、低电平(VSS)连接端子中之一或多者。应理解,本公开并不限于此。
需要说明的是,在第一侧处的连接端子与第二侧处的连接端子同时包括高电平连接端子和低电平连接端子时,由于高电平连接端子和低电平连接端子在第一侧处和第二侧处同时走线,从而在一定程度上避免了高电平连接端子和低电平连接端子的电阻压降(IR drop)导致的显示面板上下亮度不均一的现象,进而可以实现亮度更均一的显示画面。
在一些更具体实施例中,连接孔205一般被设置为与对应的连接端子(例如,连接端子208和连接端子211或213)一一对应。
图3为本公开实施例的连接孔与连接端子的结构示意图。图4a和4b为本公开实施例的覆晶薄膜的连接端子以及显示基板的显示面上的连接端子与连接孔(电连接件)的连接关系的示意图。如图3和图4a、4b所示,连接端子208的尺寸a大于连接孔205的孔径d(也即,大于连接孔中的连接件的直径);对于连接端子211或213也可以如此。在一个实现方式中,连接端子被设置为其在显示基板201上的正投影覆盖对应的连接孔205,以提供可靠的电连接。连接端子208可以对应地分布在覆晶薄膜202的两端,且覆晶薄膜202的上述两端分别与显示基板201的第一侧和第二侧相对应。
需要说明的是,在本公开实施例提供的上述显示面板中,连接端子208/211/213可以为任意形状,例如三角形、方形或圆形等。当连接端子的形状为圆形时,连接端子的直径被设置为大于对应的连接孔205的孔径。当连接端子的形状为方形时,如图3所示,连 接端子的边长a大于连接孔205的孔径d。对于连接端子208/211/213都可以如此。
此外,在本公开一些实施例中,如图3所示,覆晶薄膜还可以包括与集成电路芯片204的管脚连接的端子(如图中阴影部分所示)。其中示出了通过导线与连接端子208相连的端子M(其可以与连接端子208同层设置);以及未与连接端子208相连的端子N(其可以与连接端子208同层设置,也可以与连接端子208异层设置)。
一般地,覆晶薄膜202的连接端子208可能会数量多、密度高。为了高效快速地制作与连接端子208一一对应的连接孔205,在本公开一些实施例中,可以采用激光打孔工艺。可以通过控制激光的直径和能量,获得具有所需孔径和孔深的连接孔205。当然,还可以通过本领域技术人员已知的其他工艺制作连接孔205。
在本公开一些实施例中,如图3所示,各连接孔205的孔径d被设置为大于或等于25μm,即各连接孔205的孔径d的最小值可以为25μm。可以将显示面板的第一面的两端(即,显示区的第一侧和第二侧)处各部件的尺寸都最小化,以进一步实现窄的边框。
在本公开一些实施例中,导电材料206可以由电阻率较小、导电性能较好的导电材料(例如,金属材料)形成。当然,导电材料206还可以为其他具有导电性能的材料,例如氧化铟锡、氧化铟锌或石墨烯。
在本公开一些实施例中,显示基板201可以为柔性显示基板或刚性显示基板。较佳地,显示基板201为柔性显示基板,例如有机发光二极管(Organic Light Emitting Diodes,OLED)显示基板,或量子点发光二极管(Quantum Dot Light Emitting Diodes,QLED)显示基板等。
在本公开一些实施例中,如图2b、图2d、图2f和图2h所示,显示面板还可以包括附接到所述覆晶薄膜的一部分的柔性电路板209。可以通过外接的柔性电路板(Flexible Printed Circuit,FPC)来提供显示面板中像素驱动所需要的电源、电荷以及控制信号等。例如,柔性电路板209可以接合到覆晶薄膜202的背离显示基板201一侧。例如,可以通过覆晶薄膜202和电连接件206传输电源和控制信号等至显示面板,例如至显示面板的端子211/213。在一些实施例中,还构思了可以通过前述的电连接件或者另外的电连接件来提供柔性电路板和显示基板之间的电连接。
在本公开一些实施例中,为了能使显示面板更好成像,如图2a、图2b、图2c、图2e和图2g所示,还可以包括:与显示基板201的第一面的显示区相关联地设置的偏光片(Polarizer,Pol)210。偏光片210可以采用本领域已知或者将来开发的任何适当偏光片, 并可以利用本领域已知或者将来开发的任何附接技术附接到显示区。这里,省略了对其进一步详细说明。
根据本公开一些实施例,还提供了显示面板的制作方法。图5a和图5b分别示出了根据本公开一些实施例的显示面板的制作方法的流程图。
下面结合图5a和图2a、2b说明根据本公开一些实施例的显示面板的制作方法。如图5a所示,在步骤S501,提供显示基板201。显示基板201可以具有第一面2011和相对的第二面2013。显示基板201可以具有显示区以及在显示区周围的非显示区。在所述显示基板的第一侧处(也即,在非显示区的在显示区的第一侧的部分(第一部分))形成有第一连接端子211以及至少贯穿所述显示基板的第一连接孔2051。在与所述第一侧相对的第二侧处(也即,在非显示区的在显示区的第二侧的部分(第二部分))形成有第二连接端子213以及至少贯穿所述显示基板的第二连接孔2053。
在步骤S502,将覆晶薄膜202接合到所述显示基板的与第一面相反的一侧(面2013),以将覆晶薄膜组件接合到所述显示基板。所述覆晶薄膜组件包括所述覆晶薄膜202。覆晶薄膜组件可以还包括集成电路芯片204。集成电路芯片204可以设置在所述覆晶薄膜的背离所述显示基板的一侧。所述覆晶薄膜可以具有第三连接端子208。
例如,可以通过接合层(例如,绝缘胶或异方性导电胶)203将覆晶薄膜附接到所述显示基板的与第一面2011相反的面2013上。这里所述接合层或其部分可以由异向性导电胶形成。这里,同样地,第一连接孔和第二连接孔可以被设置为其在显示基板上的正投影在所述覆晶薄膜的外边缘在显示基板上的正投影内。
在步骤S503,在所述第一连接孔和第二连接孔中形成(例如,填充)导电材料206(例如但不限于,导电胶),以形成相应的电连接件(同样以206标示)。所述第一连接端子211和所述第二连接端子213可以分别通过相应的电连接件电连接到所述覆晶薄膜的相应的第三连接端子208。如此,可以提供电连接件与对应端子之间的可靠电连接。
下面结合图5b和图2c、2e、2g说明根据本公开另外一些实施例的显示面板的制作方法。如图5b所示,在步骤S601,提供显示基板201。显示基板201可以具有第一面2011和相对的第二面2013。显示基板可以具有显示区以及非显示区。所述非显示区包括至少位于所述显示区相对的两侧的第一部分和第二部分。在所述显示区的第一侧处,也即,在非显示区的在显示区的第一侧的部分(第一部分),形成有第一连接端子211。在与所述第一 侧相对的第二侧处,也即,在非显示区的在显示区的第二侧的部分(第二部分),形成有第二连接端子213。
在步骤S602,在所述显示基板上设置覆晶薄膜组件。所述覆晶薄膜组件包括覆晶薄膜。在一些实现方式中,覆晶薄膜组件可以包括覆晶薄膜以及集成电路芯片。在一具体实现方式中,可以将覆晶薄膜202设置到所述显示基板的与第一面相反的面2013上。集成电路芯片204可以附接到所述覆晶薄膜的背离所述显示基板的一侧。例如,可以通过接合层(例如,异方性导电胶)203将覆晶薄膜附接到所述显示基板的与第一面相反的第二面2013上。
在步骤S603,形成第一连接孔。可以在非显示区的第一部分,形成至少贯穿所述显示基板的第一连接孔2051。
在步骤S604,形成第二连接孔。可以在非显示区的第二部分,形成至少贯穿所述显示基板的第二连接孔2053。步骤S603和S604(也即,第一连接孔和第二连接孔的形成)可以同时进行,也可以分别单独进行。根据不同的实施例,步骤S603和S604也可以在S602之前或之后进行。
在步骤S605,在所述第一连接孔和第二连接孔中形成导电材料206。从而,形成相应的电连接件。所述第一连接端子和所述第二连接端子分别通过相应的导电材料电连接到所述覆晶薄膜的相应的第三连接端子。这里,可以至少通过所述导电材料(以及上述的端子等)提供到所述显示基板的电连接,例如所述覆晶薄膜(或者其上的集成电路芯片)与所述显示基板之间的电连接。这里,同样地,第一连接孔和第二连接孔可以被设置为其在显示基板上的正投影在所述覆晶薄膜的外边缘在显示基板上的正投影内。
应理解,对于上面所说明的方法实施例的步骤的执行顺序没有限制,除非明确相反说明,或者其上下文暗示或者明示了特定的顺序。例如,根据不同的实施例,形成贯穿显示基板的连接孔的步骤,可以在贴合覆晶薄膜(或覆晶薄膜组件)之前或之后执行。又例如,在图5a所示的示例中,形成导电材料的步骤可以在可以在设置COF组件的步骤之前或之后进行。
在一个具体实现方式中,如前所述的,可以在显示基板上设置覆晶薄膜组件之后,执行所述形成第一连接孔和所述形成第二连接孔。在一些实现方式中,可以在形成所述第一连接孔和所述第二连接孔之后,执行所述在所述第一连接孔和所述第二连接孔中形成导电材料。
还应理解,将覆晶薄膜组件设置到所述显示基板的与第一面相反的面上可以包括多种实现方式。例如,可以在覆晶薄膜上设置集成电路芯片;之后,例如,通过导电胶将所述覆晶薄膜附接到所述显示基板的远离第一面的一侧(面)。然而将覆晶薄膜组件设置到显示基板的方式不限于此,只要最终形成了集成电路芯片附接到覆晶薄膜而覆晶薄膜附接到显示基板即可。
在本公开的其它实施例中,在第一面的第一侧处和与第一侧相对的第二侧处分别形成至少贯穿显示基板和接合层的多个连接孔,具体可以通过以下步骤实现:在第一面的第一侧处和与第一侧相对的第二侧处分别形成贯穿显示基板和接合层的多个连接孔,以使第一侧处的连接端子和第二侧处的连接端子分别通过导电材料连接于设置在覆晶薄膜面向显示基板的一侧的连接端子。
在本公开的其他实施例中,在第一面的第一侧处和与第一侧相对的第二侧处分别形成至少贯穿显示基板和接合层的多个连接孔,还可以通过以下步骤实现:在第一面的第一侧处和与第一侧相对的第二侧处分别形成贯穿显示基板、接合层和覆晶薄膜的多个连接孔,以使第一侧处的连接端子和第二侧处的连接端子分别通过导电材料连接于设置在覆晶薄膜背离显示基板的连接端子。
在本公开的其他实施例中,在第一面的第一侧处和与第一侧相对的第二侧处分别形成至少贯穿显示基板和接合层的多个连接孔,具体还可以通过以下步骤实现:
在第一面的第一侧处和与第一侧相对的第二侧处分别形成贯穿显示基板和接合层的部分连接孔,以使第一侧处的连接端子和第二侧处的连接端子分别通过该部分连接孔内的导电材料,连接于设置在覆晶薄膜面向显示基板一侧的连接端子;
在第一面的第一侧处和与第一侧相对的第二侧处分别形成贯穿显示基板、接合层和覆晶薄膜的其余部分连接孔,以使第一侧处的连接端子和第二侧处的连接端子分别通过该其余部分连接孔内的导电材料,连接于设置在覆晶薄膜背离显示基板一侧的连接端子。
在本公开的另外的实施例中,在第一面的第一侧处和与第一侧相对的第二侧处分别形成至少贯穿显示基板和接合层的多个连接孔,还可以通过以下步骤实现:
在第一面的第一侧处形成贯穿显示基板和接合层的多个连接孔,以使第一侧处的连接端子通过导电材料连接于设置在覆晶薄膜面向显示基板的连接端子;并在第一面的与第一侧相对的第二侧处形成贯穿显示基板、接合层和覆晶薄膜的多个连接孔,以使第二侧处的连接端子通过导电材料连接于设置在覆晶薄膜背离显示基板的连接端子;或者,
在第一面的第一侧处形成贯穿显示基板、接合层和覆晶薄膜的多个连接孔,以使第一侧处的连接端子通过导电材料连接于设置在覆晶薄膜背离显示基板的连接端子;并在第一面的与第一侧相对的第二侧处形成贯穿显示基板和接合层的多个连接孔,以使第二侧处的连接端子通过导电材料连接于设置在覆晶薄膜面向显示基板的连接端子。
根据本公开一些实施例,所述第一连接孔和第二连接孔中的至少一个连接孔以及与该至少一个连接孔对应的导电材料可以被配置为贯穿所述显示基板和所述接合层。与所述至少一个连接孔对应的第三连接端子可以设置于所述覆晶薄膜的面向所述显示基板的一侧。
根据本公开一些实施例,所述第一连接孔和第二连接孔中的至少一个连接孔以及与该至少一个连接孔对应的导电材料可以被配置为贯穿所述显示基板、所述接合层和所述覆晶薄膜。与所述至少一个连接孔对应的第三连接端子可以设置于所述覆晶薄膜的背离所述显示基板的一侧。
根据本公开一些实施例,所述第一连接孔可以与所述第一连接端子一一对应。所述第二连接孔可以与所述第二连接端子一一对应。第一和第二连接端子中每一个的尺寸可以大于对应的连接孔的孔径。所述第一和第二连接端子中的每一个在所述显示基板上的正投影可以被配置为覆盖对应的连接孔。
根据本公开一些实施例,还包括以下步骤:在覆晶薄膜设置有集成电路芯片的一侧将柔性电路板接合到所述覆晶薄膜。
为提高生产效率,可以在覆晶薄膜上设置集成电路芯片的同时,在覆晶薄膜设置有集成电路芯片的一侧绑定柔性电路板。当然,也可以在覆晶薄膜上设置集成电路芯片之前或之后,执行在覆晶薄膜设置有集成电路芯片的一侧绑定柔性电路板的步骤。
根据本公开一些实施例,可以通过接合层(例如,但不限于异方性导电胶),将覆晶薄膜接合到所述显示基板的第二面上。在一些实施例中,部分连接孔(例如,第一连接孔)和与其对应的电连接件可以被配置为贯穿显示基板和接合层。在这种情况下,与所述连接孔对应的第三连接端子可以设置于所述覆晶薄膜的面对所述显示基板的一侧。
在一些实施例中,部分连接孔(例如,第二连接孔)和与其对应的电连接件贯穿所述显示基板、所述接合层和所述覆晶薄膜。在这种情况下,与所述连接孔对应的第三连接端子可以设置于所述覆晶薄膜的背离所述显示基板的一侧。在一些实施例中,所述覆晶薄膜可以是一体的。
在一些实施例中,所述方法还可以包括:在所述覆晶薄膜的设置有所述集成电路芯片的一侧将柔性电路板接合到所述覆晶薄膜。
图6a至图6e分别示出了根据本公开一些实施例的显示面板的制作方法中的某些步骤对应的显示面板的结构示意图。图7为图6d中显示面板沿AA线的截面示意图。图8为图6e中显示面板沿BB线的截面示意图。下面结合图6a-6e、图7-8以及图2a-2d来说明根据本公开一些实施例的显示面板的制作方法。
如图6a所示,提供显示基板201。在显示基板201的显示区可以贴合有偏光片210。在所述第一面的第一侧处,也即,在非显示区的在显示区的第一侧的部分(第一部分),可以形成有第一连接端子。在与所述第一侧相对的第二侧处,也即,在非显示区的在显示区的第二侧的部分(第二部分),形成有第二连接端子。
如图6b所示,提供覆晶薄膜组件。覆晶薄膜组件可以包括覆晶薄膜202。在一些实例中,覆晶薄膜组件可以还包括集成电路芯片204。例如,可以在覆晶薄膜202上设置集成电路芯片204。可选地,还可以在覆晶薄膜202的设置有集成电路芯片204的一侧绑定(附接)柔性电路板209。覆晶薄膜202可以具有一个或多个连接端子208。连接端子208可以根据不同的需要而设置在覆晶薄膜202的不同表面或不同的层中。
如图6c所示,在显示基板201的背离第一面的一侧(即,第二面)贴合覆晶薄膜202,例如通过接合层203。集成电路芯片204可以设置于覆晶薄膜202的背离显示基板201的一侧。
如图6d和图7所示,可以例如采用激光打孔工艺,从显示基板201的第一面一侧来进行打孔,在第一面的第一侧处(也即,在非显示区的在显示区的第一侧的部分(第一部分))和与第一侧相对的第二侧处(也即,在非显示区的在显示区的第二侧的部分(第二部分))分别形成贯穿显示基板201和接合层203的多个连接孔2051和2053。图7中还示意性地示出了经过打孔之后残余的连接端子部分211/213以及覆晶薄膜上的连接端子208。
各连接孔可以被设置为其在显示基板上的正投影位于覆晶薄膜的外边缘在显示基板上的正投影内。各连接孔205可以与覆晶薄膜202面向显示基板201一侧的连接端子208一一对应,并与显示基板的第一面上的连接端子211/213分别对应。连接端子208/211/213的尺寸可以设置为大于连接孔205的孔径。连接端子208/211/213可以被设置为在显示基板201上的正投影覆盖对应的连接孔205。
之后,可以在各连接孔205内填充导电材料以形成导电材料206,以使位于第一侧处的连接端子211和位于第二侧处的连接端子213通过导电材料206连接到覆晶薄膜202上的连接端子208,如图2a和图2b所示。
至此,制作出了具有如图2a和图2b所示结构的显示面板。
制作如图2c和图2d所示的显示面板的详细过程与制作如图2a和图2b所示的显示面板的详细过程相似,区别主要在于形成连接孔205的步骤不同以及连接端子208的位置设置得不同。图6e和图8示出了作为图6d的连接孔形成步骤的替代实现方式的示意结构。图6e之前的步骤可以与图6a-c所示的基本相同。因此,在此仅对制作如图2c和图2d所示的显示面板与制作如图2a和图2b所示的显示面板的不同之处进行介绍,重复之处,不再赘述。
根据该替代实现方式,可以采用激光打孔工艺,从显示基板201的背离第一面的一侧,即从覆晶薄膜一侧,在显示区的第一侧处和与第一侧相对的第二侧处(也即,在非显示区的第一部分和第二部分)分别形成贯穿覆晶薄膜202、接合层203和显示基板201的多个连接孔205,如图6e和图8所示。
在一些实施例中,各连接孔205与覆晶薄膜20的背离显示基板201一侧的各连接端子208可以设置为一一对应。连接端子208的尺寸可以大于连接孔205的孔径。连接端子208在显示基板201上的正投影覆盖对应的连接孔205。类似地,对于连接端子211/213也可以如此配置。
之后,可以在各连接孔205内填充导电材料以形成导电材料206,以使位于第一侧处的连接端子211和位于第二侧处的连接端子213通过导电材料206连接到覆晶薄膜202上的连接端子208,如图2c和图2d所示。
根据本公开实施例的显示面板可以应用于多种多样的显示装置,包括但不限于:手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述显示面板的实施例,重复之处不再赘述。
根据本公开的实施例,省去了连接端子弯折工艺,以致在显示面板的边缘不会存在连接端子弯折区域,从而使得显示面板的边框更窄。
根据本公开实施例,减少了第一侧处或第二侧处的连接孔的数量,实现了显示面板的窄边框设计。因此,在保证高分辨率的同时,获得了具有较窄边框的显示面板。
根据本公开的实施例,可以提高基板利用效率,可以提高良品率,可以简化制造工艺,和/或可以降低制造成本。
显然,本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这里所公开的实施例的特征可以自由地适当组合,而不脱离本发明的精神和范围。因此,倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内,则本公开也意图包含这些改动和变型在内。本发明的范围由所附权利要求来限定。
Claims (20)
- 一种显示面板,包括:显示基板,具有第一面以及与所述第一面相对的第二面,所述显示基板包括显示区以及非显示区,所述非显示区包括至少位于所述显示区相对的两侧的第一部分和第二部分;第一连接端子,位于所述第一部分,且位于所述第一面上;第一连接孔,位于所述第一部分,且所述第一连接孔至少贯穿所述显示基板;第二连接端子,位于所述第二部分,且位于所述第一面上;第二连接孔,位于所述第二部分,且所述第二连接孔至少贯穿所述显示基板;覆晶薄膜,位于所述显示基板的第二面,所述覆晶薄膜包括第三连接端子;导电材料,所述导电材料分别设置在相应的第一连接孔和第二连接孔中;其中所述显示基板的第一连接端子和第二连接端子分别通过位于所述第一连接孔和所述第二连接孔中的导电材料与相应的第三连接端子电连接;其中,所述第一连接孔和第二连接孔在显示基板上的正投影位于所述覆晶薄膜的外边缘在显示基板上的正投影内。
- 如权利要求1所述的显示面板,还包括:接合层,设置在所述覆晶薄膜和所述显示基板的第二面之间。
- 如权利要求2所述的显示面板,其中所述第一连接孔和第二连接孔中的至少一个连接孔以及与该至少一个连接孔对应的导电材料贯穿所述显示基板和所述接合层;其中与所述至少一个连接孔对应的第三连接端子设置于所述覆晶薄膜的面向所述显示基板的一侧。
- 如权利要求2所述的显示面板,其中所述第一连接孔和第二连接孔中的至少一个连接孔以及与该至少一个连接孔对应的导电材料贯穿所述显示基板、所述接合层和所述覆晶薄膜;其中与所述至少一个连接孔对应的第三连接端子设置于所述覆晶薄膜的背离所述显示基板的一侧。
- 如权利要求1所述的显示面板,所述第一连接端子与所述显示基板的显示区域中的第一布线电连接,所述第二连接端子与所述显示基板的显示区域中第二布线电连接,第一布线和第二布线交替设置。
- 如权利要求1所述的显示面板,其中:所述第一连接孔与所述第一连接端子一一对应,所述第二连接孔与所述第二连接端子一一对应,所述第一连接端子和第二连接端子的尺寸大于对应的连接孔的孔径。
- 如权利要求1所述的显示面板,其中所述第一连接孔和第二连接孔的孔径大于或等于25μm;所述第一连接端子和第二连接端子在所述显示基板上的正投影覆盖对应的连接孔在所述显示基板上的正投影。
- 如权利要求1所述的显示面板,其中所述第一连接端子或所述第二连接端子适于作为下列中的一个或多个:时钟连接端子、数据连接端子、高电平连接端子、低电平连接端子。
- 如权利要求1所述的显示面板,还包括:集成电路芯片,位于所述覆晶薄膜背离所述显示基板的一侧;以及柔性电路板,在所述覆晶薄膜的背离所述显示基板的一侧接合到所述覆晶薄膜。
- 如权利要求1所述的显示面板,其中所述显示基板为柔性显示基板。
- 一种显示装置,包括如权利要求1-10中任一项所述的显示面板。
- 一种显示面板的制作方法,包括:提供显示基板,其具有第一面以及与所述第一面相对的第二面,所述显示基板包括显示区以及非显示区,所述非显示区包括至少位于所述显示区相对的两侧的第一部分和第二部分,在所述非显示区的第一部分且在所述第一面上形成有第一连接端子,以及在所述 非显示区的第二部分且在所述第一面上形成有第二连接端子;在所述显示基板上设置覆晶薄膜组件,其中所述覆晶薄膜组件包括覆晶薄膜,其中所述覆晶薄膜被接合到所述显示基板的第二面,所述覆晶薄膜具有第三连接端子;形成第一连接孔,所述第一连接孔在所述非显示区的第一部分,并至少贯穿所述显示基板;形成第二连接孔,所述第二连接孔在所述非显示区的第二部分,并至少贯穿所述显示基板;以及在所述第一连接孔和第二连接孔中形成导电材料,其中,所述第一连接端子和所述第二连接端子分别通过相应的导电材料电连接到所述覆晶薄膜的相应的第三连接端子,其中,所述第一连接孔和第二连接孔被设置为其在显示基板上的正投影在所述覆晶薄膜的外边缘在显示基板上的正投影内。
- 如权利要求12所述的制作方法,其中在所述显示基板上设置覆晶薄膜组件包括:通过接合层,将覆晶薄膜接合到所述显示基板的第二面上。
- 如权利要求13所述的制作方法,其中:所述第一连接孔和所述第二连接孔中的至少一个连接孔被形成为贯穿所述显示基板和所述接合层,与所述至少一个连接孔对应的导电材料也被形成为贯穿所述显示基板和所述接合层,并且与所述至少一个连接孔对应的第三连接端子设置于所述覆晶薄膜的面对所述显示基板的一侧。
- 如权利要求13所述的制作方法,其中:所述第一连接孔和所述第二连接孔中的至少一个连接孔被形成为贯穿所述显示基板、所述接合层和所述覆晶薄膜,与所述至少一个连接孔对应的导电材料贯穿所述显示基板、所述接合层和所述覆晶薄膜,并且与所述至少一个连接孔对应的第三连接端子设置于所述覆晶薄膜的背离所述显示基板的一侧。
- 如权利要求12所述的制作方法,其中:所述第一连接孔与所述第一连接端子一一对应,所述第二连接孔与所述第二连接端子一一对应,所述第一和第二连接端子中的每一个在所述显示基板上的正投影覆盖对应的连接孔。
- 如权利要求12所述的制作方法,其中形成第一连接孔和形成第二连接孔是通过激光打孔工艺进行的。
- 如权利要求12所述的制作方法,还包括:在所述覆晶薄膜的设置有所述集成电路芯片的一侧将柔性电路板接合到所述覆晶薄膜。
- 如权利要求12所述的制作方法,其中所述覆晶薄膜组件还包括设置在所述覆晶薄膜的背离所述显示基板一侧的集成电路芯片。
- 如权利要求12所述的制造方法,其中:在所述显示基板上设置覆晶薄膜组件之后,执行所述形成第一连接孔和所述形成第二连接孔;在形成所述第一连接孔和所述第二连接孔之后,执行所述在所述第一连接孔和所述第二连接孔中形成导电材料。
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