WO2018210329A1 - 像素驱动电路及其驱动方法、显示装置 - Google Patents

像素驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2018210329A1
WO2018210329A1 PCT/CN2018/087456 CN2018087456W WO2018210329A1 WO 2018210329 A1 WO2018210329 A1 WO 2018210329A1 CN 2018087456 W CN2018087456 W CN 2018087456W WO 2018210329 A1 WO2018210329 A1 WO 2018210329A1
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Prior art keywords
circuit
control
sub
transistor
reset
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PCT/CN2018/087456
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English (en)
French (fr)
Inventor
徐映嵩
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US16/330,529 priority Critical patent/US20200342812A1/en
Publication of WO2018210329A1 publication Critical patent/WO2018210329A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0686—Adjustment of display parameters with two or more screen areas displaying information with different brightness or colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel driving circuit, a driving method thereof, and a display device.
  • the AMOLED (Active Matrix Organic Light-Emitting Diode) display has many advantages such as self-luminous, ultra-thin, fast response, high contrast, wide viewing angle, and the like, and is a display device which has been widely concerned at present.
  • the AMOLED display includes a plurality of pixels arranged in a matrix, wherein driving and controlling each pixel for gray scale display depends on a pixel driving circuit inside the pixel.
  • the pixel driving circuit mainly includes: a switching transistor, a capacitor, an OLED (Organic Light-Emitting Diode) light emitting device, and a driving transistor.
  • the driving transistor in each pixel drives the corresponding OLED light emitting device to emit light to realize the self-luminous function of the AMOLED display.
  • each of the driving transistors included in the AMOLED display has a certain non-uniformity during fabrication, so that the threshold voltages of the driving transistors corresponding to different pixels in the AMOLED display are different. Therefore, when the same data voltage is input to the two driving transistors having different threshold voltages, the driving currents generated by the two driving transistors in the saturated state are different, so that the luminances of the OLED light-emitting devices corresponding to the driving thereof are different, thereby affecting Display brightness uniformity of AMOLED displays.
  • an aspect of the present disclosure provides a pixel driving circuit including: a driving transistor, an energy storage sub-circuit, a voltage maintaining sub-circuit, a data writing sub-circuit, a power control sub-circuit, and a reset compensation control sub-circuit.
  • a control electrode of the driving transistor is connected to the first node, a first electrode of the driving transistor is connected to the second node, a second electrode of the driving transistor is connected to the third node, and is configured to drive the illuminating sub-circuit to emit light.
  • a first end of the energy storage subcircuit is coupled to the first node, a second end of the energy storage subcircuit is coupled to the fourth node, and is configured to store a threshold voltage of the drive transistor.
  • a first end of the voltage maintaining subcircuit is coupled to the first level input, a second end of the voltage maintaining subcircuit is coupled to the fourth node, and is configured to maintain a potential of the second end of the energy storage subcircuit.
  • the data writing sub-circuit is connected to the scan signal input end, the data signal input end and the fourth node, and is configured to write the data signal provided by the data signal input end under the control of the scan signal provided by the scan signal input end The fourth node.
  • the power control sub-circuit is connected to the power control terminal, the power signal input end and the third node, and is configured to provide the power signal provided by the power signal input end to the third node under the control of the power control signal provided by the power control terminal .
  • the reset compensation control sub-circuit is connected to the reset compensation control terminal, the reference level input terminal and the first node, and is configured to enable the driving transistor and the storage in the reset phase under the control of the reset compensation control signal provided by the reset compensation control terminal.
  • the energy sub-circuit and the voltage maintaining sub-circuit are reset, and the threshold voltage compensation is performed on the driving transistor in the threshold compensation phase.
  • the reset compensation control sub-circuit includes a reset transistor and a compensation transistor
  • the reset compensation control terminal includes a reset control terminal and a compensation control terminal.
  • the control electrode of the reset transistor is connected to the reset control terminal, the first pole of the reset transistor is connected to the first node, and the second pole of the reset transistor is connected to the reference level input terminal.
  • the control electrode of the compensation transistor is connected to the compensation control terminal, the first pole of the compensation transistor is connected to the fourth node, and the second pole of the compensation transistor is connected to the third node.
  • the reset transistor and the compensation transistor are of the same type, and the reset control terminal and the compensation control terminal are connected to the same signal terminal.
  • the data writing sub-circuit includes a write control transistor, a gate of the write control transistor is connected to the scan signal input terminal, a first pole of the write control transistor is connected to the fourth node, and is written The second pole of the control transistor is coupled to the data signal input.
  • the power control sub-circuit includes a power control transistor, the control electrode of the power control transistor is connected to the power control terminal, the first pole of the power control transistor is connected to the third node, and the second pole of the power control transistor is The power signal input is connected.
  • the energy storage subcircuit includes a storage capacitor, the first end of the storage capacitor is coupled to the first node, and the second end of the storage capacitor is coupled to the fourth node.
  • the voltage maintaining subcircuit includes a voltage stabilizing capacitor, one end of the voltage stabilizing capacitor is connected to the first level input terminal, and the other end of the voltage stabilizing capacitor is connected to the fourth node.
  • the above pixel driving circuit further includes an emission control sub-circuit.
  • the illumination control sub-circuit is respectively connected to the illumination control terminal, the second node and the second level input terminal, and is configured to ensure that the illumination sub-circuit emits light only in the illumination phase under the control of the illumination control signal provided by the illumination control terminal.
  • the light emission control sub-circuit includes a light emission control transistor, a control electrode of the light emission control transistor is connected to the light emission control terminal, a first electrode of the light emission control transistor is connected to the second level input terminal, and the light emission control transistor is The second pole is coupled to the first pole of the drive transistor.
  • the illuminating sub-circuit includes a light emitting device, an anode of the light emitting device being coupled to the first pole of the driving transistor, and a cathode of the light emitting diode being coupled to the second level input.
  • Another aspect of the present disclosure provides a driving method of a pixel driving circuit applied to any of the above pixel driving circuits.
  • the driving method includes, during each display cycle:
  • the drive transistor In the threshold compensation phase, the drive transistor is discharged by the reset compensation sub-circuit, and the threshold voltage of the drive transistor is stored in the energy storage sub-circuit;
  • the data signal is written to the energy storage sub-circuit through the data writing sub-circuit;
  • the illuminating sub-circuit is driven to emit light by the driving transistor.
  • the driving method further includes: in at least one of a reset period, a threshold compensation period, and a data writing period, by the illumination control sub-circuit, Ensure that the illuminator circuit does not emit light.
  • the driving method further includes a first buffering phase between the threshold compensation phase and the data writing phase.
  • the driving method further includes a second buffering phase between the data writing phase and the lighting phase.
  • a further aspect of the present disclosure provides a display device comprising any of the above pixel drive circuits.
  • FIG. 1 is a block diagram of a pixel driving circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a circuit structural diagram of a pixel driving circuit provided by an embodiment of the present disclosure
  • FIG. 3 is a control timing diagram of a pixel driving circuit provided by an embodiment of the present disclosure.
  • 4a-4d are equivalent circuit diagrams of different stages of a pixel driving circuit in a driving cycle according to an embodiment of the present disclosure.
  • a pixel driving circuit provided by an embodiment of the present disclosure includes: a driving transistor Td, an energy storage sub-circuit 6, a voltage maintaining sub-circuit 1, a data writing sub-circuit 2, a power control sub-circuit 3, and a reset compensation controller. Circuit 5.
  • the control electrode of the driving transistor Td is connected to the first node A, the first electrode of the driving transistor Td is connected to the second node B, the second electrode of the driving transistor Td is connected to the third node C, and is configured to drive the illuminating sub-circuit 4 to emit light. .
  • the first end of the energy storage sub-circuit 6 is connected to the first node A
  • the second end of the energy storage sub-circuit 6 is connected to the fourth node D, and is configured to store the threshold voltage of the driving transistor Td.
  • the first end of the voltage maintaining sub-circuit 1 is connected to the first level input terminal VDD
  • the second end of the voltage maintaining sub-circuit 1 is connected to the fourth node D, and is configured to maintain the potential of the second end of the energy storage sub-circuit 6.
  • the data writing sub-circuit 2 is connected to the scanning signal input terminal Sc, the data signal input terminal Data and the fourth node D, and is configured to provide the data signal input terminal Data under the control of the scanning signal provided by the scanning signal input terminal Sc. The data signal is written to the fourth node D.
  • the power control sub-circuit 3 is connected to the power control terminal Sv, the power signal input terminal ELVDD and the third node C, and is configured to supply the power source signal input terminal ELVDD under the control of the power source control signal provided by the power source control terminal Sv.
  • the signal is provided to the third node C.
  • the reset compensation control sub-circuit 5 is connected to the reset compensation control terminal Srb, the reference level input terminal REF and the first node A, and is configured to be under the control of the reset compensation control signal provided by the reset compensation control terminal Srb in the reset phase.
  • the driving transistor Td, the energy storage sub-circuit 6 and the voltage maintaining sub-circuit 1 are reset, and the threshold voltage compensation is performed on the driving transistor Td in the threshold compensation phase.
  • the driving current of the illuminating sub-circuit can be made only
  • the supply voltage is related to the data voltage and has no relationship to the threshold voltage of the drive transistor. Therefore, when the same data voltage is input to the plurality of driving transistors having different threshold voltages, the driving currents generated by the respective driving transistors having different threshold voltages in the saturated state are the same, so that the respective light emitting luminances of the respective light emitting sub-circuits are the same. Thereby, the problem of uneven illumination of the respective illuminating sub-circuits due to the threshold voltage drift is avoided.
  • the above pixel driving circuit may further include an emission control sub-circuit 7.
  • the illumination control sub-circuit 7 is respectively connected to the illumination control terminal Sn, the second node B and the second level input terminal VSS, and is configured to ensure that the illumination sub-circuit 4 is only under the control of the illumination control signal provided by the illumination control terminal Sn. Illuminates in the illuminating phase.
  • FIG. 2 illustrates a circuit configuration diagram of a pixel driving circuit provided by an embodiment of the present disclosure.
  • the reset compensation control sub-circuit 5 includes a reset transistor Tr and a compensation transistor Tb, and the reset compensation control terminal Srb includes a reset control terminal Sr and a compensation control terminal Sb.
  • the gate of the reset transistor Tr is connected to the reset control terminal Sr, the first electrode of the reset transistor Tr is connected to the first node A, and the second electrode of the reset transistor Tr is connected to the reference level input terminal REF.
  • the control electrode of the compensation transistor Tb is connected to the compensation control terminal Sb, the first pole of the compensation transistor Tb is connected to the fourth node D, and the second pole of the compensation transistor Tb is connected to the third node C.
  • the control signals provided by the reset control terminal Sr and the compensation control terminal Sb may be The same control signal, that is, in this case, the reset control terminal Sr and the compensation control terminal Sb are connected to the same signal terminal, thereby effectively reducing circuit traces and reducing circuit complexity.
  • the data writing sub-circuit 2 includes a write control transistor Tc.
  • the control electrode of the write control transistor Tc is connected to the scan signal input terminal Sc
  • the first electrode of the write control transistor Tc is connected to the fourth node D
  • the second electrode of the write control transistor Tc is connected to the data signal input terminal Data.
  • the power control sub-circuit 3 includes a power control transistor Tv, and the control electrode of the power control transistor Tv is connected to the power control terminal Sv, and the first and third nodes of the power control transistor Tv C is connected, and the second electrode of the power control transistor Tv is connected to the power signal input terminal ELVDD.
  • the energy storage sub-circuit 6 includes a storage capacitor C1, the first end of the storage capacitor C1 is connected to the first node A, and the second end of the storage capacitor C1 is Four-node D connection.
  • the voltage maintaining sub-circuit 1 includes a voltage stabilizing capacitor C2, one end of the voltage stabilizing capacitor C2 is connected to the first level input terminal VDD, and the other end of the voltage stabilizing capacitor C2 is Four-node D connection.
  • the light emission controlling sub circuit 7 includes the light emission controlling transistor Tn.
  • the control electrode of the light emission control transistor Tn is connected to the light emission control terminal Sn
  • the first electrode of the light emission control transistor Tn is connected to the second level input terminal VSS
  • the second electrode of the light emission control transistor Tn is connected to the first electrode of the driving transistor Td.
  • the illuminating sub-circuit 4 includes a light emitting device D.
  • the anode of the light emitting device D (for example, an organic light emitting diode) is connected to the first electrode of the driving transistor Td, and the cathode of the light emitting diode is connected to the second level input terminal VSS.
  • FIG. 3 illustrates a control timing chart of the pixel driving circuit shown in FIG. 1.
  • the power supply control terminal Sv supplies a power supply control signal having an active level
  • the reset compensation control terminal Srb provides a reset compensation control signal having an active level
  • the scan signal input terminal Sc provides a scan signal having an inactive level.
  • the power supply sub-circuit 3 supplies the power supply signal supplied from the power supply signal input terminal ELVDD to the second electrode of the drive transistor Td under the control of the power supply control signal.
  • the reset compensation control sub-circuit 5 supplies the reference level Vref supplied from the reference level input terminal REF to the control electrode of the driving transistor Td under the control of the reset compensation control signal to turn on the driving transistor Td for the subsequent threshold Prepare for the compensation phase.
  • the reset compensation control sub-circuit 5 also releases the residual charge in the energy storage sub-circuit 6 and the voltage maintenance sub-circuit 1 under the control of the reset compensation signal, so that the energy storage sub-circuit 6 and the voltage maintenance sub-circuit 1 are reset, thereby realizing the pair of pixels. Initialization of the drive circuit.
  • the term "active level” refers to a level that causes a respective transistor to turn on or cause a corresponding sub-circuit to operate. For example, for an N-type transistor, the active level is high. For P-type transistors, the active level is low. Accordingly, the term “invalid level” refers to a level at which the corresponding transistor is turned off or the corresponding sub-circuit is not operated. For example, for an N-type transistor, the inactive level is low. For P-type transistors, the inactive level is high.
  • the power supply control terminal Sv provides a power supply control signal having an inactive level
  • the reset compensation control terminal Srb provides a reset compensation control signal having an active level
  • the scan signal input terminal Sc provides a scan signal having an inactive level .
  • the reset compensation control sub-circuit 5 supplies the reference level Vref supplied from the reference level input terminal REF to the control electrode of the driving transistor Td under the control of the reset compensation control signal, so that the driving transistor Td continues to be turned on. Since the power supply control signal has an inactive level, the power supply control sub-circuit 3 does not supply the first level Vdd to the driving transistor Td, so that the driving transistor Td undergoes a discharging process and becomes turned off by conduction.
  • the potential of the second electrode of the driving transistor Td is changed from Vdd to Vref - Vth, where Vth is the threshold voltage of the driving transistor Td.
  • the reset compensation control sub-circuit 5 connects the second electrode of the driving transistor Td to the second end of the energy storage sub-circuit 6 under the control of the reset compensation signal, so that the potential of the second end of the energy storage sub-circuit 6 follows the driving transistor Td.
  • the potential of the second pole also becomes Vref-Vth.
  • the driving transistor Td undergoes the discharging process, the potential of the second electrode of the driving transistor Td starts to decrease from Vdd until the falling to Vref-Vth, and the conduction condition of the driving transistor Td is not satisfied, so that the driving transistor Td cutoff.
  • the power supply control terminal Sv supplies a power supply control signal having an inactive level
  • the reset compensation control terminal Srb provides a reset compensation control signal having an inactive level
  • the scan signal input terminal Sc provides a scan with an active level signal.
  • the data writing sub-circuit 2 writes the data signal Vdata provided by the data signal input terminal Data to the second end of the energy storage sub-circuit 6 under the control of the scanning signal, so that the potential of the second end of the energy storage sub-circuit 6 is Vref-Vth becomes Vdata.
  • the potential of the first end of the energy storage sub-circuit 6 is changed from Vref-Vth to Vdata, and from Vref to Vdata+Vth in response to the potential of the second end of the energy storage sub-circuit 6. Specifically, when the potential of the second end of the energy storage sub-circuit 6 is changed from Vref - Vth to Vdata, the amount of change in the potential of the second end of the energy storage sub-circuit 6 is Vdata - (Vref - Vth).
  • the potential of the first end of the energy storage sub-circuit 6 should also be changed by the same amount, so that the potential of the control electrode of the drive transistor Td becomes Vref + Vdata - (Vref - Vth), that is, Vdata + Vth.
  • the power supply control terminal Sv supplies a power supply control signal having an active level
  • the reset compensation control terminal Srb provides a reset compensation control signal having an inactive level
  • the scan signal input terminal Sc supplies a scan signal having an inactive level.
  • the power supply control sub-circuit 3 supplies the power supply signal supplied from the power supply signal input terminal ELVDD to the second electrode of the drive transistor Td under the control of the power supply control signal, so that the potential of the second pole of the drive transistor Td is changed from Vref-Vth to Vdd. .
  • the energy storage sub-circuit 6 maintains the potential of the second terminal at Vdata, and further maintains the potential of the control electrode of the driving transistor Td by Vdata+Vth under the action of the energy storage sub-circuit 6.
  • the driving transistor Td is turned on under the common control of its control electrode potential Vdata+Vth and its second terminal potential Vdd, and generates a driving signal for driving the light-emitting sub-circuit 4 to emit light, thereby realizing driving of the light-emitting sub-circuit 4 to emit light.
  • the driving transistor Td in the reset phase P1, the residual charge in the energy storage sub-circuit 6 and the voltage maintaining sub-circuit 1 is released, and The driving transistor Td is turned on; in the threshold compensation phase P2, the driving transistor Td is subjected to a discharging process by controlling the potential of the second electrode of the driving transistor Td until the driving transistor Td is turned off, and the threshold voltage of the driving transistor Td is stored in In the energy storage sub-circuit 6; in the data writing phase P3, the data signal is written to the second end of the energy storage sub-circuit 6, so that the potential of the second end of the energy storage sub-circuit 6 is changed from Vref-Vth to Vdata.
  • the control potential of the driving transistor Td is jumped to Vdata+Vth; in the light-emitting phase P4, under the action of the voltage maintaining sub-circuit 1, the potential of the control electrode of the driving transistor Td Vdata+Vth is maintained, and the potential of the second pole of the driving transistor Td becomes the power supply voltage Vdd, so that the driving transistor Td is turned on.
  • the voltage Vgs between the control electrode of the driving transistor Td and the second electrode of the driving transistor Td is:
  • Vgs Vdata+Vth-Vdd, Equation 1
  • the driving current I generated when the driving transistor Td is turned on and operates in a saturated state is:
  • the drive current I is only related to the power supply voltage Vdd and the data voltage Vdata, and has no relationship with the threshold voltage Vth of the drive transistor Td. Therefore, when the same data voltage is input to the plurality of driving transistors Td having different threshold voltages Vth, the driving currents generated when the driving transistors Td having different threshold voltages Vth are in the saturated state are the same. Therefore, when the corresponding light-emitting sub-circuit 4 is driven by the driving transistor Td having different threshold voltages Vth, the light-emitting luminance of the light-emitting sub-circuit 4 is the same, thereby avoiding the driving of the light-emitting sub-circuit 4 by the driving transistor Td having different threshold voltages Vth. The problem that the illuminating sub-circuit 4 emits unevenly due to the threshold voltage drift.
  • 4a to 4d illustrate equivalent circuit diagrams of the pixel driving circuit shown in Fig. 2 in various stages.
  • the reset switch transistor Tr is turned on under the control of the reset control signal supplied from the reset control terminal Sr, so that the control electrode of the drive transistor Td is connected to the reference level input terminal REF.
  • the compensation transistor Tb is turned on under the control of the compensation control signal supplied from the compensation control terminal Sb such that the second electrode of the driving transistor Td is connected to the second terminal of the storage capacitor C1.
  • the write control transistor Tc is turned off under the control of the scan signal supplied from the scan signal input terminal Sc, so that the second end of the storage capacitor C1 is disconnected from the data signal input terminal Data.
  • the power control transistor Tv is turned on under the control of the power supply control signal supplied from the power supply control terminal Sv such that the second electrode of the driving transistor Td is connected to the power supply signal input terminal ELVDD.
  • the voltage stabilizing capacitor C2 regulates the first end of the storage capacitor C1 and regulates the control electrode of the driving transistor Td through the storage capacitor C1, thereby avoiding display abnormality caused by external disturbance.
  • the reset transistor Tr is turned on under the control of the reset control signal supplied from the reset control terminal Sr, so that the gate electrode of the drive transistor Td is connected to the reference level input terminal REF.
  • the compensation transistor Tb is turned on under the control of the compensation control signal supplied from the compensation control terminal Sb such that the second electrode of the driving transistor Td is connected to the second terminal of the storage capacitor C1.
  • the write control transistor Tc is turned off under the control of the scan signal supplied from the scan signal input terminal Sc, so that the second end of the storage capacitor C1 is disconnected from the data signal input terminal Data.
  • the power control transistor Tv is turned off under the control of the power supply control signal supplied from the power supply control terminal Sv, so that the second electrode of the driving transistor Td is disconnected from the power supply signal input terminal ELVDD.
  • the voltage stabilizing capacitor C2 regulates the first end of the storage capacitor C1 and regulates the control electrode of the driving transistor Td through the storage capacitor C1, thereby avoiding display abnormality caused by external disturbance.
  • the reset transistor Tr is turned off under the control of the reset control signal supplied from the reset control terminal Sr, so that the gate electrode of the driving transistor Td is disconnected from the reference level input terminal REF.
  • the compensation transistor Tb is turned off under the control of the compensation control signal supplied from the compensation control terminal Sb, so that the second electrode of the driving transistor Td is disconnected from the second end of the storage capacitor C1.
  • the write control transistor Tc is turned on under the control of the scan signal supplied from the scan signal input terminal Sc such that the second end of the storage capacitor C1 is connected to the data signal input terminal Data.
  • the power control transistor Tv is turned off under the control of the power supply control signal supplied from the power supply control terminal Sv, so that the second electrode of the driving transistor Td is disconnected from the power supply signal input terminal ELVDD.
  • the voltage stabilizing capacitor C2 regulates the first end of the storage capacitor C1 and regulates the control electrode of the driving transistor Td through the storage capacitor C1, thereby avoiding display abnormality caused by external disturbance.
  • the reset transistor Tr is turned off under the control of the reset control signal supplied from the reset control terminal Sr, so that the gate electrode of the drive transistor Td is disconnected from the reference level input terminal REF.
  • the compensation transistor Tb is turned off under the control of the compensation control signal supplied from the compensation control terminal Sb, so that the second electrode of the driving transistor Td is disconnected from the second end of the storage capacitor C1.
  • the write control transistor Tc is turned off under the control of the scan signal supplied from the scan signal input terminal Sc, so that the second end of the storage capacitor C1 is disconnected from the data signal input terminal Data.
  • the power control transistor Tv is turned on under the control of the power supply control terminal Sv such that the second electrode of the driving transistor Td is connected to the power supply signal input terminal ELVDD. Since the second end of the storage capacitor C1 is in a floating state, the second end of the storage capacitor C1 is connected to the voltage stabilizing capacitor C2, and the other end of the voltage stabilizing capacitor C2 is connected to the first level input terminal VDD, thereby realizing energy storage. The holding of the potential of the second end of the capacitor C1. The first end of the storage capacitor C1 is in turn connected to the control electrode of the driving transistor Td, thereby ensuring that the control electrode of the driving transistor Td is not in a floating state.
  • the pixel driving circuit includes the light emission control sub-circuit 7
  • the light emission control sub-circuit 7 includes the light emission control transistor Tn
  • the reset phase P1 the threshold compensation phase P2, and the data writing phase P3
  • the light emission control transistor Tn is at the light emission control terminal Sn
  • the control of the provided light-emission control signal is turned on, so that the first electrode of the driving transistor Td is connected to the second level input terminal VSS, thereby short-circuiting the light-emitting device D.
  • the illuminating control transistor Tn is turned off under the control of the illuminating control signal provided by the illuminating control terminal Sn, causing the first pole of the driving transistor Td to be disconnected from the second level input terminal VSS, thereby causing the light emitting device D It is possible to normally emit light under the driving of the driving transistor Td.
  • the cathode of the light emitting device D and the first pole of the light emission controlling transistor Tn may not be connected to the same end (the second level input terminal VSS), and only need to satisfy the light emitting function of the light emitting device D and the short circuit of the light emitting control transistor Tn.
  • the function is OK.
  • the above-mentioned light-emitting control terminal Sn can be provided with the reset control terminal Sr.
  • the same control signal as the compensation control terminal Sb is used to ensure that in the reset phase P1 and the threshold compensation phase P2, the illumination control terminal Sn can control the illumination control transistor Tn to be turned on, thereby enabling the illumination sub-circuit 4 to be compensated in the reset phase P1 and threshold. No light is emitted in phase P2.
  • the illumination control terminal Sn and the reset control terminal Sr and the compensation control terminal Sb can be connected to the same control signal output terminal, thereby effectively reducing Circuit routing.
  • the potential of the control electrode of the driving transistor Td is Vdata+Vth
  • the potential of the second electrode of the driving transistor Td is Vref-Vth.
  • the condition that the driving transistor Td does not satisfy the conduction can be controlled such that: (Vdata+Vth)-(Vref-Vth) is smaller than the threshold voltage Vth of the driving transistor Td. Therefore, a suitable reference voltage Vref can be set as required so that the illuminating sub-circuit 4 is not illuminated in the data writing phase P3.
  • the first level provided by the first level input terminal VDD may be a stable potential.
  • the first level provided by the first level input terminal VDD may be the power supply voltage Vdd.
  • the first level input terminal can be directly connected to the power signal input terminal ELVDD, thereby avoiding introducing an additional circuit for providing the first level, reducing the area occupied by the pixel driving circuit, and further facilitating the display device.
  • the number of pixels increases the display effect of the display device.
  • the first level input terminal can also be connected to the reference voltage input terminal REF or the low level output terminal VSS, but is not limited thereto. It should be noted that the working process of the provided pixel driving circuit is only described by taking the specific circuit structure shown in FIG. 2 as an example.
  • the illumination control sub-circuits 7 can also each be implemented in other configurations and will not be described in detail herein.
  • the number of devices used in the pixel driving circuit is small, so the area occupied by the pixel driving circuit is small, which is more advantageous for increasing the number of pixels of the display device and improving the display effect of the display device.
  • each of the above transistors may use a thin film transistor, a field effect transistor or other devices having the same characteristics.
  • first pole in order to distinguish the two poles of the transistor except the control pole, one of the poles is referred to as a first pole, and the other pole is referred to as a second pole.
  • first pole may be a drain
  • second pole may be a source
  • first pole may be a source
  • second pole may be a drain
  • each transistor is a P-type transistor, and the first extremely drain and the second source are described as an example.
  • One or more of the above transistors may also be N-type transistors without departing from the scope of the present disclosure.
  • the control signal provided by the power control terminal Sv, the illumination control terminal Sn, the reset control terminal Sr and the compensation control terminal Sb, the scan signal provided by the scan signal input terminal Sc, and the data signal provided by the data signal input terminal Data may be Both are pulse signals.
  • the signals can all be DC signals.
  • the embodiment of the present disclosure further provides a driving method of a pixel driving circuit, which is applied to the above pixel driving circuit. Specifically, in each display cycle, the driving method includes:
  • the drive transistor In the threshold compensation phase, the drive transistor is discharged by the reset compensation sub-circuit, and the threshold voltage of the drive transistor is stored in the energy storage sub-circuit;
  • the data signal is written to the energy storage sub-circuit through the data writing sub-circuit;
  • the illuminating sub-circuit is driven to emit light by the driving transistor.
  • the power supply control terminal Sv provides a power supply control signal having an active level
  • the reset compensation control terminal Srb provides a reset compensation control signal having an active level
  • the scan signal input terminal Sc provides an inactive level Scan the signal.
  • the power supply sub-circuit 3 supplies the power supply signal supplied from the power supply signal input terminal ELVDD to the second electrode of the drive transistor Td under the control of the power supply control signal.
  • the reset compensation control sub-circuit 5 supplies the reference level Vref supplied from the reference level input terminal REF to the control electrode of the driving transistor Td under the control of the reset compensation control signal to turn on the driving transistor Td for the subsequent threshold Prepare for the compensation phase.
  • the reset compensation control sub-circuit 5 also releases the residual charge in the energy storage sub-circuit 6 and the voltage maintenance sub-circuit 1 under the control of the reset compensation signal, so that the energy storage sub-circuit 6 and the voltage maintenance sub-circuit 1 are reset, thereby realizing the pair of pixels. Initialization of the drive circuit.
  • the power supply control terminal Sv provides a power supply control signal having an inactive level
  • the reset compensation control terminal Srb provides a reset compensation control signal having an active level
  • the scan signal input terminal Sc provides a scan signal having an inactive level .
  • the reset compensation control sub-circuit 5 supplies the reference level Vref supplied from the reference level input terminal REF to the control electrode of the driving transistor Td under the control of the reset compensation control signal, so that the driving transistor Td continues to be turned on. Since the power supply control signal has an inactive level, the power supply control sub-circuit 3 does not supply the first level Vdd to the driving transistor Td, so that the driving transistor Td undergoes a discharging process and becomes turned off by conduction.
  • the potential of the second electrode of the driving transistor Td is changed from Vdd to Vref - Vth, where Vth is the threshold voltage of the driving transistor Td.
  • the reset compensation control sub-circuit 5 connects the second electrode of the driving transistor Td to the second end of the energy storage sub-circuit 6 under the control of the reset compensation signal, so that the potential of the second end of the energy storage sub-circuit 6 follows the driving transistor Td.
  • the potential of the second pole also becomes Vref-Vth.
  • the driving transistor Td undergoes the discharging process, the potential of the second electrode of the driving transistor Td starts to decrease from Vdd until the falling to Vref-Vth, and the conduction condition of the driving transistor Td is not satisfied, so that the driving transistor Td cutoff.
  • the power supply control terminal Sv supplies a power supply control signal having an inactive level
  • the reset compensation control terminal Srb provides a reset compensation control signal having an inactive level
  • the scan signal input terminal Sc provides a scan with an active level signal.
  • the data writing sub-circuit 2 writes the data signal Vdata provided by the data signal input terminal Data to the second end of the energy storage sub-circuit 6 under the control of the scanning signal, so that the potential of the second end of the energy storage sub-circuit 6 is Vref-Vth becomes Vdata.
  • the potential of the first end of the energy storage sub-circuit 6 is changed from Vref-Vth to Vdata, and from Vref to Vdata+Vth in response to the potential of the second end of the energy storage sub-circuit 6. Specifically, when the potential of the second end of the energy storage sub-circuit 6 is changed from Vref - Vth to Vdata, the amount of change in the potential of the second end of the energy storage sub-circuit 6 is Vdata - (Vref - Vth).
  • the potential of the first end of the energy storage sub-circuit 6 should also be changed by the same amount, so that the potential of the control electrode of the drive transistor Td becomes Vref + Vdata - (Vref - Vth), that is, Vdata + Vth.
  • the power supply control terminal Sv supplies a power supply control signal having an active level
  • the reset compensation control terminal Srb provides a reset compensation control signal having an inactive level
  • the scan signal input terminal Sc provides a scan signal having an inactive level.
  • the power supply control sub-circuit 3 supplies the power supply signal supplied from the power supply signal input terminal ELVDD to the second electrode of the drive transistor Td under the control of the power supply control signal, so that the potential of the second pole of the drive transistor Td is changed from Vref-Vth to Vdd. .
  • the energy storage sub-circuit 6 maintains the potential of the second terminal at Vdata, and further maintains the potential of the control electrode of the driving transistor Td by Vdata+Vth under the action of the energy storage sub-circuit 6.
  • the driving transistor Td is turned on under the common control of its control electrode potential Vdata+Vth and its second terminal potential Vdd, and generates a driving signal for driving the light-emitting sub-circuit 4 to emit light, thereby realizing driving of the light-emitting sub-circuit 4 to emit light.
  • the driving transistor Td in the reset phase P1, the residual charge in the energy storage sub-circuit 6 and the voltage maintaining sub-circuit 1 is released, and the driving transistor Td is turned on; In the phase P2, the driving transistor Td is subjected to a discharging process by controlling the potential of the second electrode of the driving transistor Td until the driving transistor Td is turned off, and the threshold voltage of the driving transistor Td is stored in the energy storage sub-circuit 6; In the in-stage P3, the data signal is written to the second end of the energy storage sub-circuit 6, so that the potential of the second end of the energy storage sub-circuit 6 is changed from Vref-Vth to Vdata, and under the action of the energy storage sub-circuit 6.
  • the drive current I generated by the drive transistor Td is only related to the power supply voltage Vdd and the data voltage Vdata, and has no relationship with the threshold voltage Vth of the drive transistor Td. Therefore, when the same data voltage is input to the plurality of driving transistors Td having different threshold voltages Vth, the driving currents generated when the driving transistors Td having different threshold voltages Vth are in the saturated state are the same. Therefore, when the corresponding light-emitting sub-circuit 4 is driven by the driving transistor Td having different threshold voltages Vth, the light-emitting luminance of the light-emitting sub-circuit 4 is the same, thereby avoiding the driving of the light-emitting sub-circuit 4 by the driving transistor Td having different threshold voltages Vth. The problem that the illuminating sub-circuit 4 emits unevenly due to the threshold voltage drift.
  • a first buffering phase P5 may be introduced between the threshold compensation phase P2 and the data writing phase P3, ie such that after the threshold compensation phase P2 When the reset compensation control signal changes from the second level to the first level, the process proceeds to the first buffer stage P5.
  • the data writing phase P3 is entered, at which time the control scan signal is changed from the first level to the second level. This not only ensures the working process of the pixel driving circuit, but also avoids the signal crosstalk caused by the simultaneous jump of different signals.
  • a second buffering phase P6 may be introduced between the data writing phase P3 and the lighting phase P4, ie such that after the data writing phase P3, When the scan signal changes from the second level to the first level, it proceeds to the second buffer stage P6. At the end of the second buffering phase P6, the light emission phase P4 is entered. At this time, the control power control signal is changed from the first level to the second level, which not only ensures the working process of the pixel driving circuit, but also avoids signal crosstalk caused by simultaneous hopping of different signals.
  • the driving method of the pixel driving circuit further includes: during the reset period P1, the threshold compensation period P2, and/or data writing In the period P3, the light-emitting sub-circuit 4 is ensured not to emit light by the light-emission control sub-circuit.
  • Embodiments of the present disclosure also provide a display device including the above pixel driving circuit.
  • the display device when the same data voltage is input to the plurality of driving transistors Td having different threshold voltages Vth, the driving currents generated when the driving transistors Td having different threshold voltages Vth are in the saturated state are the same. Therefore, when the corresponding light-emitting sub-circuit 4 is driven by the driving transistor Td having different threshold voltages Vth, the light-emitting luminance of the light-emitting sub-circuit 4 is the same, thereby avoiding the driving of the light-emitting sub-circuit 4 by the driving transistor Td having different threshold voltages Vth.
  • the problem of uneven illumination of the illuminating sub-circuit 4 due to the threshold voltage drift ensures the display quality of the display device.
  • the display device provided in this embodiment may be an OLED (Organic Light-Emitting Diode) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like, or any display product. component.
  • OLED Organic Light-Emitting Diode

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Abstract

一种像素驱动电路及其驱动方法、显示装置。像素驱动电路包括：驱动晶体管(Td)、储能子电路(6)、电压维持子电路(1)、数据写入子电路(2)、电源控制子电路(3)和复位补偿控制子电路(5)。储能子电路(6)配置成存储驱动晶体管(Td)的阈值电压。复位补偿控制子电路(5)配置成在复位补偿控制端(Srb)所提供的复位补偿控制信号的控制下，在复位阶段(P1)中使驱动晶体管(Td)、储能子电路(6)和电压维持子电路(1)复位，并且在阈值补偿阶段(P2)中对驱动晶体管(Td)进行阈值电压补偿。

Description

像素驱动电路及其驱动方法、显示装置
相关申请
本申请要求享有2017年5月18日提交的中国专利申请No.201710352258.1的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路及其驱动方法、显示装置。
背景技术
AMOLED(Active Matrix Organic Light-Emitting Diode，有源矩阵有机发光二极管)显示器具有自发光、超薄、反应速度快、对比度高、视角广等诸多优点，是目前受到广泛关注的一种显示器件。
AMOLED显示器包括矩阵式排布的多个像素，其中驱动和控制每个像素进行灰阶显示依赖于像素内部的像素驱动电路。该像素驱动电路主要包括：开关晶体管、电容器、OLED(Organic Light-Emitting Diode，有机发光二极管)发光器件，以及驱动晶体管。在工作时，各像素中的驱动晶体管驱动对应的OLED发光器件发光，以实现AMOLED显示器的自发光功能。
但是，AMOLED显示器中包括的各驱动晶体管在制作时存在一定的不均匀性，使得AMOLED显示器中不同像素对应的驱动晶体管的阈值电压不同。因此，在向阈值电压不同的两个驱动晶体管输入相同的数据电压时，这两个驱动晶体管在饱和状态下所产生的驱动电流不同，致使它们对应驱动的OLED发光器件的发光亮度不同，从而影响AMOLED显示器的显示亮度均匀性。
发明内容
鉴于以上，本公开的一个方面提供了一种像素驱动电路，包括：驱动晶体管、储能子电路、电压维持子电路、数据写入子电路、电源控制子电路和复位补偿控制子电路。驱动晶体管的控制极与第一节点连接，驱动晶体管的第一极与第二节点连接，驱动晶体管的第二极与 第三节点连接，并且配置成驱动发光子电路发光。储能子电路的第一端与第一节点连接，储能子电路的第二端与第四节点连接，并且配置成存储驱动晶体管的阈值电压。电压维持子电路的第一端与第一电平输入端连接，电压维持子电路的第二端与第四节点连接，并且配置成维持储能子电路的第二端的电位。数据写入子电路与扫描信号输入端、数据信号输入端和第四节点连接，并且配置成在扫描信号输入端所提供的扫描信号的控制下将数据信号输入端所提供的数据信号写入到第四节点。电源控制子电路与电源控制端、电源信号输入端和第三节点连接，并且配置成在电源控制端所提供的电源控制信号的控制下将电源信号输入端所提供的电源信号提供到第三节点。复位补偿控制子电路与复位补偿控制端、参考电平输入端和第一节点连接，并且配置成在复位补偿控制端所提供的复位补偿控制信号的控制下，在复位阶段中使驱动晶体管、储能子电路和电压维持子电路复位，并且在阈值补偿阶段中对驱动晶体管进行阈值电压补偿。
根据本公开的一些实施例，复位补偿控制子电路包括复位晶体管和补偿晶体管，复位补偿控制端包括复位控制端和补偿控制端。复位晶体管的控制极与复位控制端连接，复位晶体管的第一极与第一节点连接，并且复位晶体管的第二极与参考电平输入端连接。补偿晶体管的控制极与补偿控制端连接，补偿晶体管的第一极与第四节点连接，并且补偿晶体管的第二极与第三节点连接。
根据本公开的一些实施例，复位晶体管和补偿晶体管的类型相同，并且复位控制端和补偿控制端连接到相同信号端。
根据本公开的一些实施例，数据写入子电路包括写入控制晶体管，写入控制晶体管的控制极与扫描信号输入端连接，写入控制晶体管的第一极与第四节点连接，并且写入控制晶体管的第二极与数据信号输入端连接。
根据本公开的一些实施例，电源控制子电路包括电源控制晶体管，电源控制晶体管的控制极与电源控制端连接，电源控制晶体管的第一极与第三节点连接，电源控制晶体管的第二极与电源信号输入端连接。
根据本公开的一些实施例，储能子电路包括储能电容器，储能电容器的第一端与第一节点连接，并且储能电容器的第二端与第四节点连接。
根据本公开的一些实施例，电压维持子电路包括稳压电容器，稳压电容器的一端与第一电平输入端连接，并且稳压电容器的另一端与第四节点连接。
根据本公开的一些实施例，上述像素驱动电路还包括发光控制子电路。发光控制子电路分别与发光控制端、第二节点和第二电平输入端连接，并且配置成在发光控制端所提供的发光控制信号的控制下，保证发光子电路仅在发光阶段中发光。
根据本公开的一些实施例，发光控制子电路包括发光控制晶体管，发光控制晶体管的控制极与发光控制端连接，发光控制晶体管的第一极与第二电平输入端连接，并且发光控制晶体管的第二极与驱动晶体管的第一极连接。
根据本公开的一些实施例，发光子电路包括发光器件，发光器件的阳极与驱动晶体管的第一极连接，并且发光二极管的阴极与第二电平输入端连接。
本公开的另一方面提供了一种像素驱动电路的驱动方法，应用于上述任一种像素驱动电路。该驱动方法包括，在每一显示周期：
在复位阶段中，通过复位补偿控制子电路释放储能子电路和电压维持子电路中残留的电荷，并使驱动晶体管导通；
在阈值补偿阶段中，通过复位补偿子电路，对驱动晶体管进行放电，并且将驱动晶体管的阈值电压存储在储能子电路中；
在数据写入阶段中，通过数据写入子电路将数据信号写入到储能子电路；
在发光阶段中，通过驱动晶体管驱动发光子电路发光。
根据本公开的一些实施例，当像素驱动电路还包括发光控制子电路时，该驱动方法还包括：在复位时段、阈值补偿时段和数据写入时段中的至少一个中，通过发光控制子电路，保证发光子电路不发光。
根据本公开的一些实施例，该驱动方法还包括阈值补偿阶段与数据写入阶段之间的第一缓冲阶段。
根据本公开的一些实施例，该驱动方法还包括数据写入阶段与发光阶段之间的第二缓冲阶段。
本公开另外的方面提供了一种显示装置，包括上述任一种像素驱动电路。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分。本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为由本公开实施例提供的像素驱动电路的框图；
图2为由本公开实施例提供的像素驱动电路的电路结构图；
图3为由本公开实施例提供的像素驱动电路的控制时序图；以及
图4a～4d为本公开实施例所提供的像素驱动电路在一个驱动周期内的不同阶段的等效电路图。
具体实施方式
为了进一步说明本公开实施例提供的像素驱动电路及其驱动方法、显示装置，下面结合说明书附图进行详细描述。
如图1所示，本公开实施例提供的像素驱动电路包括：驱动晶体管Td、储能子电路6、电压维持子电路1、数据写入子电路2、电源控制子电路3和复位补偿控制子电路5。驱动晶体管Td的控制极与第一节点A连接，驱动晶体管Td的第一极与第二节点B连接，驱动晶体管Td的第二极与第三节点C连接，并且配置成驱动发光子电路4发光。储能子电路6的第一端与第一节点A连接，储能子电路6的第二端与第四节点D连接，并且配置成存储驱动晶体管Td的阈值电压。电压维持子电路1的第一端与第一电平输入端VDD连接，电压维持子电路1的第二端与第四节点D连接，并且配置成维持储能子电路6的第二端的电位。数据写入子电路2与扫描信号输入端Sc、数据信号输入端Data和第四节点D连接，并且配置成在扫描信号输入端Sc所提供的扫描信号的控制下将数据信号输入端Data所提供的数据信号写入到第四节点D。电源控制子电路3与电源控制端Sv、电源信号输入端ELVDD和第三节点C连接，并且配置成在电源控制端Sv所提供的电源控制信号的控制下将电源信号输入端ELVDD所提供的电源信号提供到第三节点C。复位补偿控制子电路5与复位补偿控制端Srb、参考电平输入端REF和第一节点A连接，并且配置成在复位补偿控制端Srb所提供的复位补偿控制信号的控制下，在复位阶段中使驱动晶体管Td、储能子电路 6和电压维持子电路1复位，并且在阈值补偿阶段中对驱动晶体管Td进行阈值电压补偿。
在上述像素驱动电路中，通过利用储能子电路存储驱动晶体管的阈值电压，并且利用复位补偿控制子电路在阈值补偿阶段中对驱动晶体管进行阈值电压补偿，可以使得发光子电路的驱动电流只与电源电压和数据电压有关，而与驱动晶体管的阈值电压没有关系。因此，在向阈值电压不同的多个驱动晶体管输入相同的数据电压时，阈值电压不同的各个驱动晶体管在饱和状态时所产生的驱动电流相同，从而使相应的各个发光子电路的发光亮度相同，从而避免了由于阈值电压漂移而导致的各个发光子电路发光不均匀的问题。
在示例实施例中，如图1所示，上述像素驱动电路还可以包括发光控制子电路7。发光控制子电路7分别与发光控制端Sn、第二节点B和第二电平输入端VSS连接，并且配置成在发光控制端Sn所提供的发光控制信号的控制下，保证发光子电路4仅在发光阶段中发光。
图2图示了由本公开实施例提供的像素驱动电路的电路结构图。如图2所示，在示例性实施例中，复位补偿控制子电路5包括复位晶体管Tr和补偿晶体管Tb，并且复位补偿控制端Srb包括复位控制端Sr和补偿控制端Sb。复位晶体管Tr的控制极与复位控制端Sr连接，复位晶体管Tr的第一极与第一节点A连接，并且复位晶体管Tr的第二极与参考电平输入端REF连接。补偿晶体管Tb的控制极与补偿控制端Sb连接，补偿晶体管Tb的第一极与第四节点D连接，并且补偿晶体管Tb的第二极与第三节点C连接。
特别地，当复位晶体管Tr和补偿晶体管Tb采用相同类型的晶体管时(例如同为P型晶体管或同为N型晶体管)，由上述复位控制端Sr和补偿控制端Sb所提供的控制信号可以为同一控制信号，也就是说，在这种情况下，复位控制端Sr和补偿控制端Sb连接到相同信号端，从而有效减少电路走线，降低电路的复杂度。
在示例性实施例中，如图2所示，数据写入子电路2包括写入控制晶体管Tc。写入控制晶体管Tc的控制极与扫描信号输入端Sc连接，写入控制晶体管Tc的第一极与第四节点D连接，并且写入控制晶体管Tc的第二极与数据信号输入端Data连接。
在示例性实施例中，如图2所示，电源控制子电路3包括电源控 制晶体管Tv，电源控制晶体管Tv的控制极与电源控制端Sv连接，电源控制晶体管Tv的第一极与第三节点C连接，电源控制晶体管Tv的第二极与电源信号输入端ELVDD连接。
在示例性实施例中，如图2所示，储能子电路6包括储能电容器C1，储能电容器C1的第一端与第一节点A连接，并且储能电容器C1的第二端与第四节点D连接。
在示例性实施例中，如图2所示，电压维持子电路1包括稳压电容器C2，稳压电容器C2的一端与第一电平输入端VDD连接，并且稳压电容器C2的另一端与第四节点D连接。
在示例性实施例中，如图2所示，当像素驱动电路包括发光控制子电路7时，发光控制子电路7包括发光控制晶体管Tn。发光控制晶体管Tn的控制极与发光控制端Sn连接，发光控制晶体管Tn的第一极与第二电平输入端VSS连接，并且发光控制晶体管Tn的第二极与驱动晶体管Td的第一极连接。
在示例性实施例中，如图2所示，发光子电路4包括发光器件D。发光器件D(例如，有机发光二极管)的阳极与驱动晶体管Td的第一极连接，并且发光二极管的阴极与第二电平输入端VSS连接。
图3图示了如图1所示的像素驱动电路的控制时序图。
在复位阶段P1中，电源控制端Sv提供具有有效电平的电源控制信号，复位补偿控制端Srb提供具有有效电平的复位补偿控制信号，扫描信号输入端Sc提供具有无效电平的扫描信号。此时，电源控制子电路3在电源控制信号的控制下，将电源信号输入端ELVDD所提供的电源信号提供到驱动晶体管Td的第二极。复位补偿控制子电路5在复位补偿控制信号的控制下，将参考电平输入端REF所提供的参考电平Vref提供到驱动晶体管Td的控制极，使驱动晶体管Td导通，以便为随后的阈值补偿阶段作准备。复位补偿控制子电路5在复位补偿信号的控制下，还释放储能子电路6和电压维持子电路1中的残留电荷，使得储能子电路6和电压维持子电路1复位，从而实现对像素驱动电路的初始化。
如本文所使用的，术语“有效电平”是指使得相应的晶体管导通或使得相应的子电路进行动作的电平。例如，对于N型晶体管而言，有效电平为高电平。对于P型晶体管而言，有效电平为低电平。相应 地，术语“无效电平”是指使得相应的晶体管关断或使得相应的子电路不进行动作的电平。例如，对于N型晶体管而言，无效电平为低电平。对于P型晶体管而言，无效电平为高电平。
在阈值补偿阶段P2中，电源控制端Sv提供具有无效电平的电源控制信号，复位补偿控制端Srb提供具有有效电平的复位补偿控制信号，扫描信号输入端Sc提供具有无效电平的扫描信号。复位补偿控制子电路5在复位补偿控制信号的控制下，将参考电平输入端REF所提供的参考电平Vref提供到驱动晶体管Td的控制极，使驱动晶体管Td继续导通。由于电源控制信号具有无效电平，因此电源控制子电路3不向驱动晶体管Td提供第一电平Vdd，使得驱动晶体管Td经历放电过程，并且由导通变为截止。在截止时，驱动晶体管Td的第二极的电位由Vdd变为Vref-Vth，其中Vth为驱动晶体管Td的阈值电压。复位补偿控制子电路5在复位补偿信号的控制下，将驱动晶体管Td的第二极与储能子电路6的第二端连接，使储能子电路6的第二端的电位跟随驱动晶体管Td的第二极的电位也变为Vref-Vth。需要说明的是，驱动晶体管Td在经历放电过程时，驱动晶体管Td的第二极的电位由Vdd开始下降，直至下降为Vref-Vth时，不满足驱动晶体管Td的导通条件，使得驱动晶体管Td截止。
在数据写入阶段P3中，电源控制端Sv提供具有无效电平的电源控制信号，复位补偿控制端Srb提供具有无效电平的复位补偿控制信号，扫描信号输入端Sc提供具有有效电平的扫描信号。数据写入子电路2在扫描信号的控制下，将数据信号输入端Data所提供的数据信号Vdata写入到储能子电路6的第二端，使得储能子电路6的第二端的电位由Vref-Vth变为Vdata。储能子电路6的第一端的电位响应于储能子电路6的第二端的电位由Vref-Vth变为Vdata，由Vref变为Vdata+Vth。具体地，当储能子电路6的第二端的电位由Vref-Vth变为Vdata时，储能子电路6的第二端的电位的变化量为Vdata-(Vref-Vth)。根据电荷守恒定理，储能子电路6的第一端的电位也应当变化相同的量，使得驱动晶体管Td的控制极的电位变为Vref+Vdata-(Vref-Vth)，即为Vdata+Vth。
在发光时段P4中，电源控制端Sv提供具有有效电平的电源控制信号，复位补偿控制端Srb提供具有无效电平的复位补偿控制信号，扫 描信号输入端Sc提供具有无效电平的扫描信号。电源控制子电路3在电源控制信号的控制下，将由电源信号输入端ELVDD提供的电源信号提供到驱动晶体管Td的第二极，使驱动晶体管Td的第二极的电位由Vref-Vth变为Vdd。储能子电路6在电压维持子电路1的控制下，其第二端的电位保持Vdata，进而在储能子电路6的作用下，使驱动晶体管Td的控制极的电位保持Vdata+Vth。这样驱动晶体管Td在其控制极电位Vdata+Vth和其第二端电位Vdd的共同控制下导通，并生成用于驱动发光子电路4发光的驱动信号，从而实现驱动发光子电路4发光。
根据上述像素驱动电路在一个驱动周期的工作过程可知，在本公开实施例提供的像素驱动电路中，在复位阶段P1中，释放储能子电路6和电压维持子电路1中残留的电荷，并使驱动晶体管Td导通；在阈值补偿阶段P2中，通过控制驱动晶体管Td的第二极的电位，使驱动晶体管Td经历放电过程，直至驱动晶体管Td截止，并且将驱动晶体管Td的阈值电压存储在储能子电路6中；在数据写入阶段P3中，将数据信号写入到储能子电路6的第二端，使储能子电路6的第二端的电位由Vref-Vth变为Vdata，并且在储能子电路6的作用下，使得驱动晶体管Td的控制极电位跳变为Vdata+Vth；在发光阶段P4中，在电压维持子电路1的作用下，驱动晶体管Td的控制极的电位保持Vdata+Vth，而驱动晶体管Td的第二极的电位变为电源电压Vdd，使得驱动晶体管Td导通。此时，驱动晶体管Td的控制极和驱动晶体管Td的第二极之间的电压Vgs为：
Vgs＝Vdata+Vth-Vdd，  公式一
驱动晶体管Td导通并工作在饱和状态时产生的驱动电流I为：
I＝k(Vgs-Vth) 2  公式二
将公式一代入公式二得到：
I＝k(Vdata+Vth-Vdd-Vth) 2＝k(Vdata-Vdd) 2  公式三
其中，k为常数。
由公式三可知驱动电流I只与电源电压Vdd和数据电压Vdata有关，而与驱动晶体管Td的阈值电压Vth没有关系。因此，在向阈值电压Vth不同的多个驱动晶体管Td输入相同的数据电压时，阈值电压Vth不同的驱动晶体管Td在饱和状态时所产生的驱动电流相同。因此，在由阈值电压Vth不同的驱动晶体管Td驱动对应的发光子电路4发光 时，发光子电路4的发光亮度相同，因而避免了采用阈值电压Vth不同的驱动晶体管Td驱动发光子电路4发光时，由于阈值电压漂移而导致的发光子电路4发光不均匀的问题。
图4a～4d图示了如图2所示的像素驱动电路在各个阶段中的等效电路图。
如图4a所示，在复位阶段P1中，复位开关管Tr在复位控制端Sr所提供的复位控制信号的控制下导通，使得驱动晶体管Td的控制极与参考电平输入端REF连接。补偿晶体管Tb在补偿控制端Sb所提供的补偿控制信号的控制下导通，使得驱动晶体管Td的第二极与储能电容器C1的第二端连接。写入控制晶体管Tc在扫描信号输入端Sc所提供的扫描信号的控制下截止，使得储能电容器C1的第二端与数据信号输入端Data断开。电源控制晶体管Tv在电源控制端Sv所提供的电源控制信号的控制下导通，使得驱动晶体管Td的第二极与电源信号输入端ELVDD连接。稳压电容器C2对储能电容器C1的第一端起到稳压作用，并通过储能电容器C1对驱动晶体管Td的控制极起到稳压作用，从而避免由于外部扰动而引起的显示异常。
如图4b所示，在阈值补偿阶段P2中，复位晶体管Tr在复位控制端Sr所提供的复位控制信号的控制下导通，使得驱动晶体管Td的控制极与参考电平输入端REF连接。补偿晶体管Tb在补偿控制端Sb所提供的补偿控制信号的控制下导通，使得驱动晶体管Td的第二极与储能电容器C1的第二端连接。写入控制晶体管Tc在扫描信号输入端Sc所提供的扫描信号的控制下截止，使得储能电容器C1的第二端与数据信号输入端Data断开。电源控制晶体管Tv在电源控制端Sv所提供的电源控制信号的控制下截止，使得驱动晶体管Td的第二极与电源信号输入端ELVDD断开。稳压电容器C2对储能电容器C1的第一端起到稳压作用，并通过储能电容器C1对驱动晶体管Td的控制极起到稳压作用，从而避免由于外部扰动而引起的显示异常。
如图4c所示，在数据写入阶段P3中，复位晶体管Tr在复位控制端Sr所提供的复位控制信号的控制下截止，使得驱动晶体管Td的控制极与参考电平输入端REF断开。补偿晶体管Tb在补偿控制端Sb所提供的补偿控制信号的控制下截止，使得驱动晶体管Td的第二极与储能电容器C1的第二端断开。写入控制晶体管Tc在扫描信号输入端Sc 所提供的扫描信号的控制下导通，使得储能电容器C1的第二端与数据信号输入端Data连接。电源控制晶体管Tv在电源控制端Sv所提供的电源控制信号的控制下截止，使得驱动晶体管Td的第二极与电源信号输入端ELVDD断开。稳压电容器C2对储能电容器C1的第一端起到稳压作用，并通过储能电容器C1对驱动晶体管Td的控制极起到稳压作用，从而避免由于外部扰动而引起的显示异常。
如图4d所示，在发光阶段P4中，复位晶体管Tr在复位控制端Sr所提供的复位控制信号的控制下截止，使得驱动晶体管Td的控制极与参考电平输入端REF断开。补偿晶体管Tb在补偿控制端Sb所提供的补偿控制信号的控制下截止，使得驱动晶体管Td的第二极与储能电容器C1的第二端断开。写入控制晶体管Tc在扫描信号输入端Sc所提供的扫描信号的控制下截止，使得储能电容器C1的第二端与数据信号输入端Data断开。电源控制晶体管Tv在电源控制端Sv的控制下导通，使得驱动晶体管Td的第二极与电源信号输入端ELVDD连接。由于储能电容器C1的第二端处于悬空状态，储能电容器C1的第二端与稳压电容器C2连接，稳压电容器C2的另一端与第一电平输入端VDD连接，因此实现对储能电容器C1的第二端的电位的保持。储能电容器C1的第一端又与驱动晶体管Td的控制极连接，从而保证了驱动晶体管Td的控制极没有处于悬空状态。
当像素驱动电路包括发光控制子电路7，并且发光控制子电路7包括发光控制晶体管Tn时，在复位阶段P1、阈值补偿阶段P2和数据写入阶段P3中，发光控制晶体管Tn在发光控制端Sn所提供的发光控制信号的控制下导通，使驱动晶体管Td的第一极与第二电平输入端VSS连接，从而将发光器件D短路。在发光阶段P4中，发光控制晶体管Tn在发光控制端Sn所提供的发光控制信号的控制下截止，使驱动晶体管Td的第一极与第二电平输入端VSS断开，从而使得发光器件D能够在驱动晶体管Td的驱动下正常发光。
可替换地，发光器件D的阴极和发光控制晶体管Tn的第一极可以不连接到同一端(第二电平输入端VSS)，只需满足发光器件D的发光功能和发光控制晶体管Tn的短路功能即可。
应当指出的是，当发光控制晶体管Tn、复位晶体管Tr和补偿晶体管Tb采用相同类型的晶体管时(同为P型晶体管或同为N型晶体管)， 上述发光控制端Sn可以提供与复位控制端Sr和补偿控制端Sb相同的控制信号，以保证在复位阶段P1和阈值补偿阶段P2中，发光控制端Sn能够控制发光控制晶体管Tn导通，从而使得发光子电路4能够在复位阶段P1和阈值补偿阶段P2中不发光。而且，使发光控制端Sn和复位控制端Sr以及补偿控制端Sb提供相同的控制信号，可以将发光控制端Sn、复位控制端Sr和补偿控制端Sb连接到同一控制信号输出端，从而有效减少电路走线。
在数据写入阶段P3中，驱动晶体管Td的控制极的电位为Vdata+Vth，驱动晶体管Td的第二极的电位为Vref-Vth。为了保证发光子电路4在此阶段不发光，可以控制驱动晶体管Td不满足导通的条件，即使得：(Vdata+Vth)-(Vref-Vth)小于驱动晶体管Td的阈值电压Vth。因此，可以根据要求设置合适的参考电压Vref，以使得在数据写入阶段P3中保证发光子电路4不发光。
需要说明的是，上述第一电平输入端VDD所提供的第一电平只要为稳定的电位即可。可选地，第一电平输入端VDD所提供的第一电平可以为电源电压Vdd。这样第一电平输入端就可以直接与电源信号输入端ELVDD连接，从而避免了引入额外的用于提供第一电平的电路，减少了像素驱动电路所占的面积，更有利于增加显示装置的像素数量，提高显示装置的显示效果。当然，第一电平输入端也可以与参考电压输入端REF或低电平输出端VSS连接，但不仅限于此。值得注意的是，本实施例仅以如图2所示的具体的电路结构为例对所提供的像素驱动电路的工作过程进行介绍。在本公开的其它实施例中，像素驱动电路的电压维持子电路1、数据写入子电路2、电源控制子电路3、发光子电路4、复位补偿控制子电路5、储能子电路6和发光控制子电路7还可各自采用其它的结构实现，在此不再详述。此外，上述像素驱动电路所采用的器件数量较少，因此该像素驱动电路所占的面积较小，更有利于增加显示装置的像素数量，提高显示装置的显示效果。此外，以上的各个晶体管均可以采用薄膜晶体管、场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，将另一极称为第二极。在实际操作时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
在本实施例中，以各个晶体管均为P型晶体管，且第一极为漏极，第二极为源极为例进行说明。上述晶体管中的一个或多个也可以为N型晶体管，而不脱离本公开的范围。另外，由电源控制端Sv、发光控制端Sn、复位控制端Sr和补偿控制端Sb提供的控制信号、由扫描信号输入端Sc提供的扫描信号，以及由数据信号输入端Data提供的数据信号可以均为脉冲信号。由电源信号输入端ELVDD提供的电源信号、由第二电平输入端VSS(可以与电源负极连接，但不仅限于此)提供的第二电平信号，以及由参考电平输入端REF提供的参考信号可以均为直流信号。
本公开实施例还提供了一种像素驱动电路的驱动方法，应用于上述像素驱动电路。具体地，在每一显示周期，该驱动方法包括：
在复位阶段中，通过复位补偿控制子电路释放储能子电路和电压维持子电路中残留的电荷，并使驱动晶体管导通；
在阈值补偿阶段中，通过复位补偿子电路，对驱动晶体管进行放电，并且将驱动晶体管的阈值电压存储在储能子电路中；
在数据写入阶段中，通过数据写入子电路将数据信号写入到储能子电路；
在发光阶段中，通过驱动晶体管驱动发光子电路发光。
具体地，在复位阶段P1中，电源控制端Sv提供具有有效电平的电源控制信号，复位补偿控制端Srb提供具有有效电平的复位补偿控制信号，扫描信号输入端Sc提供具有无效电平的扫描信号。此时，电源控制子电路3在电源控制信号的控制下，将电源信号输入端ELVDD所提供的电源信号提供到驱动晶体管Td的第二极。复位补偿控制子电路5在复位补偿控制信号的控制下，将参考电平输入端REF所提供的参考电平Vref提供到驱动晶体管Td的控制极，使驱动晶体管Td导通，以便为随后的阈值补偿阶段作准备。复位补偿控制子电路5在复位补偿信号的控制下，还释放储能子电路6和电压维持子电路1中的残留电荷，使得储能子电路6和电压维持子电路1复位，从而实现对像素驱动电路的初始化。
在阈值补偿阶段P2中，电源控制端Sv提供具有无效电平的电源控制信号，复位补偿控制端Srb提供具有有效电平的复位补偿控制信号，扫描信号输入端Sc提供具有无效电平的扫描信号。复位补偿控制 子电路5在复位补偿控制信号的控制下，将参考电平输入端REF所提供的参考电平Vref提供到驱动晶体管Td的控制极，使驱动晶体管Td继续导通。由于电源控制信号具有无效电平，因此电源控制子电路3不向驱动晶体管Td提供第一电平Vdd，使得驱动晶体管Td经历放电过程，并且由导通变为截止。在截止时，驱动晶体管Td的第二极的电位由Vdd变为Vref-Vth，其中Vth为驱动晶体管Td的阈值电压。复位补偿控制子电路5在复位补偿信号的控制下，将驱动晶体管Td的第二极与储能子电路6的第二端连接，使储能子电路6的第二端的电位跟随驱动晶体管Td的第二极的电位也变为Vref-Vth。需要说明的是，驱动晶体管Td在经历放电过程时，驱动晶体管Td的第二极的电位由Vdd开始下降，直至下降为Vref-Vth时，不满足驱动晶体管Td的导通条件，使得驱动晶体管Td截止。
在数据写入阶段P3中，电源控制端Sv提供具有无效电平的电源控制信号，复位补偿控制端Srb提供具有无效电平的复位补偿控制信号，扫描信号输入端Sc提供具有有效电平的扫描信号。数据写入子电路2在扫描信号的控制下，将数据信号输入端Data所提供的数据信号Vdata写入到储能子电路6的第二端，使得储能子电路6的第二端的电位由Vref-Vth变为Vdata。储能子电路6的第一端的电位响应于储能子电路6的第二端的电位由Vref-Vth变为Vdata，由Vref变为Vdata+Vth。具体地，当储能子电路6的第二端的电位由Vref-Vth变为Vdata时，储能子电路6的第二端的电位的变化量为Vdata-(Vref-Vth)。根据电荷守恒定理，储能子电路6的第一端的电位也应当变化相同的量，使得驱动晶体管Td的控制极的电位变为Vref+Vdata-(Vref-Vth)，即为Vdata+Vth。
在发光时段P4中，电源控制端Sv提供具有有效电平的电源控制信号，复位补偿控制端Srb提供具有无效电平的复位补偿控制信号，扫描信号输入端Sc提供具有无效电平的扫描信号。电源控制子电路3在电源控制信号的控制下，将由电源信号输入端ELVDD提供的电源信号提供到驱动晶体管Td的第二极，使驱动晶体管Td的第二极的电位由Vref-Vth变为Vdd。储能子电路6在电压维持子电路1的控制下，其第二端的电位保持Vdata，进而在储能子电路6的作用下，使驱动晶体管Td的控制极的电位保持Vdata+Vth。这样驱动晶体管Td在其控制极电 位Vdata+Vth和其第二端电位Vdd的共同控制下导通，并生成用于驱动发光子电路4发光的驱动信号，从而实现驱动发光子电路4发光。
在本公开实施例提供的上述像素驱动电路的驱动方法中，在复位阶段P1中，释放储能子电路6和电压维持子电路1中残留的电荷，并使驱动晶体管Td导通；在阈值补偿阶段P2中，通过控制驱动晶体管Td的第二极的电位，使驱动晶体管Td经历放电过程，直至驱动晶体管Td截止，并且将驱动晶体管Td的阈值电压存储在储能子电路6中；在数据写入阶段P3中，将数据信号写入到储能子电路6的第二端，使储能子电路6的第二端的电位由Vref-Vth变为Vdata，并且在储能子电路6的作用下，使得驱动晶体管Td的控制极电位跳变为Vdata+Vth；在发光阶段P4中，在电压维持子电路1的作用下，驱动晶体管Td的控制极的电位保持Vdata+Vth，而驱动晶体管Td的第二极的电位变为电源电压Vdd，使得驱动晶体管Td导通。此时，驱动晶体管Td工作在饱和状态时产生的驱动电流I为：I＝k(Vgs-Vth) 2，k为常数。
因此，由驱动晶体管Td产生的驱动电流I只与电源电压Vdd和数据电压Vdata有关，而与驱动晶体管Td的阈值电压Vth没有关系。因此，在向阈值电压Vth不同的多个驱动晶体管Td输入相同的数据电压时，阈值电压Vth不同的驱动晶体管Td在饱和状态时所产生的驱动电流相同。因此，在由阈值电压Vth不同的驱动晶体管Td驱动对应的发光子电路4发光时，发光子电路4的发光亮度相同，因而避免了采用阈值电压Vth不同的驱动晶体管Td驱动发光子电路4发光时，由于阈值电压漂移而导致的发光子电路4发光不均匀的问题。
在由阈值补偿阶段P2进入到数据写入阶段P3时，由复位补偿控制端Srb(包括复位控制端Sr和补偿控制端Sb)提供的控制信号发生跳变(如图3中，由第二电平变为第一电平)，且同时由扫描信号输入端Sc提供的扫描信号也发生跳变(如图3中，由第一电平变为第二电平)。为了避免这两个信号同时跳变而产生串扰，在示例性实施例中，可以在阈值补偿阶段P2和数据写入阶段P3之间引入第一缓冲阶段P5，即，使得在阈值补偿阶段P2之后，复位补偿控制信号由第二电平变为第一电平时，进入到第一缓冲阶段P5。在第一缓冲阶段P5结束时，进入到数据写入阶段P3，此时再控制扫描信号由第一电平变为第二电平。这样既保证了像素驱动电路的工作过程，又避免了由于不同 的信号同时跳变导致的信号串扰现象。
类似地，在数据写入阶段P3进入到发光阶段P4时，由扫描信号输入端Sc提供的扫描信号发生跳变(如图3中，由第二电平变为第一电平)，且同时由电源控制端Sv提供的电源控制信号发生跳变(如图3中，由第一电平变为第二电平)。为了避免这两个信号同时跳变产生串扰，在示例性实施例中，可以在数据写入阶段P3和发光阶段P4之间引入第二缓冲阶段P6，即，使得在数据写入阶段P3之后，扫描信号由第二电平变为第一电平时，进入到第二缓冲阶段P6。在第二缓冲阶段P6结束时，进入到发光阶段P4。此时控制电源控制信号由第一电平变为第二电平，这样既保证了像素驱动电路的工作过程，又避免了由于不同的信号同时跳变导致的信号串扰现象。
在示例性实施例中，当上述实施例提供的像素驱动电路还包括发光控制子电路7时，上述像素驱动电路的驱动方法还包括：在复位时段P1、阈值补偿时段P2和/或数据写入时段P3，通过发光控制子电路保证发光子电路4不发光。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
本公开实施例还提供了一种显示装置，包括上述像素驱动电路。在该显示装置中，在向阈值电压Vth不同的多个驱动晶体管Td输入相同的数据电压时，阈值电压Vth不同的驱动晶体管Td在饱和状态时所产生的驱动电流相同。因此，在由阈值电压Vth不同的驱动晶体管Td驱动对应的发光子电路4发光时，发光子电路4的发光亮度相同，因而避免了采用阈值电压Vth不同的驱动晶体管Td驱动发光子电路4发光时，由于阈值电压漂移而导致的发光子电路4发光不均匀的问题，保证了显示装置的显示质量。
本实施例所提供的显示装置可以为OLED(Organic Light-Emitting Diode，有机发光二极管)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种像素驱动电路，包括：驱动晶体管、储能子电路、电压维持子电路、数据写入子电路、电源控制子电路和复位补偿控制子电路，其中
    驱动晶体管的控制极与第一节点连接，驱动晶体管的第一极与第二节点连接，驱动晶体管的第二极与第三节点连接，并且配置成驱动发光子电路发光；
    储能子电路的第一端与第一节点连接，储能子电路的第二端与第四节点连接，并且配置成存储驱动晶体管的阈值电压；
    电压维持子电路的第一端与第一电平输入端连接，电压维持子电路的第二端与第四节点连接，并且配置成维持储能子电路的第二端的电位；
    数据写入子电路与扫描信号输入端、数据信号输入端和第四节点连接，并且配置成在扫描信号输入端所提供的扫描信号的控制下将数据信号输入端所提供的数据信号写入到第四节点；
    电源控制子电路与电源控制端、电源信号输入端和第三节点连接，并且配置成在电源控制端所提供的电源控制信号的控制下将电源信号输入端所提供的电源信号提供到第三节点；
    复位补偿控制子电路与复位补偿控制端、参考电平输入端和第一节点连接，并且配置成在复位补偿控制端所提供的复位补偿控制信号的控制下，在复位阶段中使驱动晶体管、储能子电路和电压维持子电路复位，并且在阈值补偿阶段中对驱动晶体管进行阈值电压补偿。
  2. 根据权利要求1所述的像素驱动电路，其中，所述复位补偿控制子电路包括复位晶体管和补偿晶体管，所述复位补偿控制端包括复位控制端和补偿控制端，其中，
    复位晶体管的控制极与复位控制端连接，复位晶体管的第一极与第一节点连接，并且复位晶体管的第二极与参考电平输入端连接；
    补偿晶体管的控制极与补偿控制端连接，补偿晶体管的第一极与第四节点连接，并且补偿晶体管的第二极与第三节点连接。
  3. 根据权利要求2所述的像素驱动电路，其中，所述复位晶体管和补偿晶体管的类型相同，并且所述复位控制端和补偿控制端连接到 相同信号端。
  4. 根据权利要求1所述的像素驱动电路，其中，所述数据写入子电路包括写入控制晶体管，写入控制晶体管的控制极与扫描信号输入端连接，写入控制晶体管的第一极与第四节点连接，并且写入控制晶体管的第二极与数据信号输入端连接。
  5. 根据权利要求1所述的像素驱动电路，其中，所述电源控制子电路包括电源控制晶体管，电源控制晶体管的控制极与电源控制端连接，电源控制晶体管的第一极与第三节点连接，电源控制晶体管的第二极与电源信号输入端连接。
  6. 根据权利要求1所述的像素驱动电路，其中，所述储能子电路包括储能电容器，储能电容器的第一端与第一节点连接，并且储能电容器的第二端与第四节点连接。
  7. 根据权利要求1所述的像素驱动电路，其中，所述电压维持子电路包括稳压电容器，稳压电容器的一端与第一电平输入端连接，并且稳压电容器的另一端与第四节点连接。
  8. 根据权利要求1～7任一项所述的像素驱动电路，还包括：
    发光控制子电路，所述发光控制子电路分别与发光控制端、第二节点和第二电平输入端连接，并且配置成在发光控制端所提供的发光控制信号的控制下，保证发光子电路仅在发光阶段中发光。
  9. 根据权利要求8所述的像素驱动电路，其中，所述发光控制子电路包括发光控制晶体管，发光控制晶体管的控制极与发光控制端连接，发光控制晶体管的第一极与第二电平输入端连接，并且发光控制晶体管的第二极与驱动晶体管的第一极连接。
  10. 根据权利要求1～9任一项所述的像素驱动电路，其中，所述发光子电路包括发光器件，发光器件的阳极与驱动晶体管的第一极连接，并且发光二极管的阴极与第二电平输入端连接。
  11. 一种像素驱动电路的驱动方法，应用于如权利要求1～10任一项所述的像素驱动电路，所述驱动方法包括：在每一显示周期，
    在复位阶段中，通过复位补偿控制子电路释放储能子电路和电压维持子电路中残留的电荷，并使驱动晶体管导通；
    在阈值补偿阶段中，通过复位补偿子电路，对驱动晶体管进行放电，并且将驱动晶体管的阈值电压存储在储能子电路中；
    在数据写入阶段中，通过数据写入子电路将数据信号写入到储能子电路；
    在发光阶段中，通过驱动晶体管驱动发光子电路发光。
  12. 根据权利要求11所述的像素驱动电路的驱动方法，其中，所述像素驱动电路还包括发光控制子电路，所述发光控制子电路分别与发光控制端、第二节点和第二电平输入端连接，并且配置成在发光控制端所提供的发光控制信号的控制下，保证发光子电路仅在发光阶段中发光，
    所述驱动方法还包括：在所述复位时段、所述阈值补偿时段和所述数据写入时段中的至少一个中，通过所述发光控制子电路，保证发光子电路不发光。
  13. 根据权利要求11或12所述的像素驱动电路的驱动方法，还包括阈值补偿阶段与数据写入阶段之间的第一缓冲阶段。
  14. 根据权利要求11～13任一项所述的像素驱动电路的驱动方法，还包括数据写入阶段与发光阶段之间的第二缓冲阶段。
  15. 一种显示装置，包括权利要求1～10任一项所述的像素驱动电路。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11094253B2 (en) * 2019-09-10 2021-08-17 Hefei Boe Joint Technology Co., Ltd. Pixel driving circuit, method for driving the same, array substrate and display device

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106952615B (zh) * 2017-05-18 2019-02-01 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置
CN107256694B (zh) * 2017-07-31 2019-11-05 武汉华星光电半导体显示技术有限公司 显示装置、像素驱动方法及像素驱动电路
CN108986747B (zh) * 2018-07-25 2020-07-28 京东方科技集团股份有限公司 一种阵列基板、有机电致发光显示面板及显示装置
CN109545138A (zh) * 2019-01-10 2019-03-29 云谷（固安）科技有限公司 一种像素电路、显示面板和像素电路驱动方法
CN110675815A (zh) * 2019-09-26 2020-01-10 武汉天马微电子有限公司 像素驱动电路及其驱动方法、显示装置
CN111063304B (zh) * 2020-01-02 2023-02-03 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、阵列基板、显示装置
WO2022110247A1 (zh) * 2020-11-30 2022-06-02 京东方科技集团股份有限公司 驱动电路、其驱动方法及显示装置
CN115101011A (zh) * 2021-07-21 2022-09-23 武汉天马微电子有限公司 配置成控制发光元件的像素电路
CN114023253B (zh) * 2021-11-16 2022-09-27 武汉华星光电半导体显示技术有限公司 像素电路及显示装置
CN114822409A (zh) * 2022-06-24 2022-07-29 惠科股份有限公司 像素驱动电路、显示面板及显示装置
WO2024065614A1 (zh) * 2022-09-30 2024-04-04 京东方科技集团股份有限公司 像素驱动电路、驱动方法及其显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1815538A (zh) * 2005-02-02 2006-08-09 索尼株式会社 像素电路、显示屏及其驱动方法
US20130057532A1 (en) * 2011-09-05 2013-03-07 Young-Hak Lee Pixel circuit of organic light emitting diode display device
CN104867456A (zh) * 2015-06-19 2015-08-26 合肥鑫晟光电科技有限公司 像素电路及其驱动方法、显示装置
CN204808833U (zh) * 2015-07-15 2015-11-25 京东方科技集团股份有限公司 一种像素电路、显示面板和显示装置
CN205282057U (zh) * 2016-01-04 2016-06-01 京东方科技集团股份有限公司 像素驱动电路、显示面板和显示装置
CN106952615A (zh) * 2017-05-18 2017-07-14 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005099715A (ja) * 2003-08-29 2005-04-14 Seiko Epson Corp 電子回路の駆動方法、電子回路、電子装置、電気光学装置、電子機器および電子装置の駆動方法
KR101549284B1 (ko) * 2011-11-08 2015-09-02 엘지디스플레이 주식회사 유기발광다이오드 표시장치
CN104064160B (zh) * 2014-07-17 2016-06-15 深圳市华星光电技术有限公司 具有自我补偿功能的栅极驱动电路
CN104200771B (zh) * 2014-09-12 2017-03-01 上海天马有机发光显示技术有限公司 像素电路、阵列基板及显示装置
CN104700778B (zh) * 2015-03-27 2017-06-27 深圳市华星光电技术有限公司 Amoled像素驱动电路及像素驱动方法
CN104992663B (zh) * 2015-08-05 2017-09-22 京东方科技集团股份有限公司 一种移位寄存器单元及栅极驱动电路、显示面板
CN105427803B (zh) * 2016-01-04 2018-01-02 京东方科技集团股份有限公司 像素驱动电路、方法、显示面板和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1815538A (zh) * 2005-02-02 2006-08-09 索尼株式会社 像素电路、显示屏及其驱动方法
US20130057532A1 (en) * 2011-09-05 2013-03-07 Young-Hak Lee Pixel circuit of organic light emitting diode display device
CN104867456A (zh) * 2015-06-19 2015-08-26 合肥鑫晟光电科技有限公司 像素电路及其驱动方法、显示装置
CN204808833U (zh) * 2015-07-15 2015-11-25 京东方科技集团股份有限公司 一种像素电路、显示面板和显示装置
CN205282057U (zh) * 2016-01-04 2016-06-01 京东方科技集团股份有限公司 像素驱动电路、显示面板和显示装置
CN106952615A (zh) * 2017-05-18 2017-07-14 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11094253B2 (en) * 2019-09-10 2021-08-17 Hefei Boe Joint Technology Co., Ltd. Pixel driving circuit, method for driving the same, array substrate and display device

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