WO2018152883A1 - 阵列基板以及具有该阵列基板的液晶面板 - Google Patents

阵列基板以及具有该阵列基板的液晶面板 Download PDF

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WO2018152883A1
WO2018152883A1 PCT/CN2017/076554 CN2017076554W WO2018152883A1 WO 2018152883 A1 WO2018152883 A1 WO 2018152883A1 CN 2017076554 W CN2017076554 W CN 2017076554W WO 2018152883 A1 WO2018152883 A1 WO 2018152883A1
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region
dummy pixel
polysilicon
gate line
array substrate
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PCT/CN2017/076554
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English (en)
French (fr)
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虞晓江
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武汉华星光电技术有限公司
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Priority to US15/522,563 priority Critical patent/US20180292719A1/en
Publication of WO2018152883A1 publication Critical patent/WO2018152883A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/22—Antistatic materials or arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to the field of electrical protection, and in particular to an array substrate capable of effectively discharging an electrostatic voltage and a liquid crystal panel having the array substrate.
  • the liquid crystal panel device When the liquid crystal panel device is in the manufacturing process or when it is within a certain range of voltage, current and power consumption, a large amount of static charge will generate a high-voltage discharge when the conditions are suitable, and an electrostatic discharge (ESD, Elctro-Static Discharge) is passed through the circuit.
  • ESD electrostatic discharge
  • the high-voltage transient transmission of the device leads may cause breakdown of the insulating layer of the circuit device, resulting in loss of function of the circuit device.
  • LTPS low temperature polysilicon
  • the digital signal is operated at a higher frequency due to the introduction of the TFT module, which increases the probability that an electrostatic discharge event occurs on the circuit device.
  • the driving circuit region which can provide the gate driving signal for the display region often contains a large area of metal, which is easily affected by the electrostatic discharge event and generates a large electrostatic voltage.
  • the electrostatic voltage of the driving circuit region can be transmitted to the display area along the gate line, causing damage to the pixel of the display area edge adjacent to the driving circuit area.
  • the purpose of electrostatic protection is generally achieved by a method of setting a dummy pixel region at the edge of the display region.
  • the principle of the method is to enable the electrostatic voltage to be fully released in the virtual pixel area, to prevent the high voltage of static electricity from continuing to enter the display area and causing the pixels of the display area to be injured.
  • FIG. 1 it is a partial schematic view of an existing array substrate.
  • the array substrate mainly includes: a dummy pixel region 1', a source line 2', a gate line 3', a polysilicon trace 4', a pixel ITO trace 5', a display region 6', and a driving circuit region 7'.
  • the virtual pixel area 1' is located at the edge of the display area 6'. That is, between the display area 6' and the drive circuit area 7'.
  • the source line 2' is perpendicular to the gate line 3', the polysilicon trace 4' intersects the gate line 3', and the polysilicon trace 4' and the source line 2' pass through the via (not shown) )connection.
  • the ESD high voltage generated by the driving circuit region 7' is passed to the display region 6' along the gate line 3', since the gate line 3' only goes with the polysilicon in the dummy pixel region 1'.
  • the line 4' is overlapped twice, (between the gate line 3' and the polysilicon trace 4' is only separated by a gate insulating layer of about 100 nm thick, between the gate line 3' and the polysilicon trace 4'.
  • the high voltage difference easily causes the gate insulating layer to be broken down, and the overlap area is very limited. Therefore, there is often an unreleased ESD high voltage that continues to be transmitted to the display area 6', causing the pixel of the display area 6' to be injured.
  • the edge of the display area 6' causes an abnormal bright spot or dark spot.
  • the inventors of the present application have found that the area of the polysilicon trace 4' in the dummy pixel region 1' overlapping the gate line 3' is equal to or smaller than the polysilicon trace 4' and the gate in the display region 6'.
  • the electrostatic voltage cannot be effectively released. Therefore, when the electrostatic voltage is too large, the virtual pixel area cannot be fully released, so that the electrostatic voltage continues to enter the display area along the gate line, thereby destroying the pixel function of the display area.
  • An object of the present invention is to provide an array substrate and a liquid crystal panel having the same, which can effectively discharge an electrostatic voltage, greatly weaken an electrostatic voltage that may continue to enter the display area along the gate line, and avoid damaging the pixel function of the display area.
  • the present invention provides an array substrate including: a dummy pixel region, a display region, and a driving circuit region, the dummy pixel region being located between the display region and the driving circuit region, the display region and the dummy pixel region
  • Each of the polysilicon traces and gate lines are arranged with different faces;
  • the area in which the polysilicon traces in the dummy pixel region overlap with the gate lines is larger than the area in which the polysilicon traces in the display region overlap with the gate lines.
  • the polysilicon traces intersect the gate lines at least three times.
  • the polysilicon trace intersects the gate line seven times.
  • the polysilicon traces crossing the gate line are connected in parallel.
  • the polysilicon traces crossing the gate line are connected in series.
  • the line width of the polysilicon trace in the dummy pixel region is larger than the line width of the polysilicon trace in the display region.
  • a line width of a gate line in the dummy pixel region is larger than a line width of a gate line in the display region.
  • a transition region is further disposed between the dummy pixel region and the display region, and an overlap area between the polysilicon trace and the gate line in the transition region is less than or equal to polysilicon in the dummy pixel region
  • An overlapping area between the trace and the gate line, and an overlap area between the polysilicon trace and the gate line in the transition region is greater than or equal to an overlap area between the polysilicon trace and the gate line in the display region .
  • the array substrate wherein the transition region is a virtual pixel region or a display region.
  • the present invention also provides a liquid crystal panel comprising the above array substrate.
  • the virtual pixel region can effectively release the electrostatic voltage and avoid the display region. The pixels are injured, which can improve the yield of the display panel.
  • the transition region may be a virtual pixel region or a display region, and an overlap between the polysilicon traces and the gate lines in the transition region
  • the area may be less than or equal to the overlap area between the polysilicon trace and the gate line in the dummy pixel region, and the overlap area between the polysilicon trace and the gate line in the transition region may be greater than or equal to that in the display region
  • the overlapping area between the polysilicon trace and the gate line realizes further release of the electrostatic voltage and improves the electrostatic protection of the display area.
  • 1 is a partial schematic view of a conventional array substrate
  • FIG. 2 is a partial schematic view of a preferred embodiment of an array substrate in accordance with the present invention.
  • FIG. 3 is a partial schematic view of another preferred embodiment of an array substrate in accordance with the present invention.
  • the array substrate mainly includes: a dummy pixel region 1, a source line 2, a gate line 3, a polysilicon trace 4, a pixel ITO trace 5, a display region 6, and a driving circuit region 7.
  • the virtual pixel area 1 is located at the edge of the display area 6, that is, between the display area 6 and the driving circuit area 7.
  • the display region 6 and the dummy pixel region 1 are respectively provided with a source line 2, a gate line 3, a polysilicon trace 4, and a pixel ITO trace 5.
  • the source line 2 and the gate line 3 are perpendicular to each other, and the polysilicon is removed.
  • the line 4 intersects the gate line 3 on a different side, and the polysilicon trace 4 and the source line 2 are connected by a via (not shown).
  • the improvement of the present invention is that the area of the polysilicon trace 4 in the dummy pixel region 1 overlapping with the gate line 3 is larger than the area of the polysilicon trace 4 in the display region 6 overlapping with the gate line 3, thereby effectively The electrostatic voltage is released to prevent the pixels of the display area 6 from being damaged, thereby improving the yield of the display panel.
  • the polysilicon trace 4 may intersect the gate line 3 at least three times, so that the area of the polysilicon trace 4 in the dummy pixel region 1 overlapping with the gate line 3 is larger than the display area.
  • the area of the polysilicon trace 4 in the region 6 overlaps with the gate line 3 by 50%, thereby increasing the capacitance between the polysilicon trace 4 and the gate line 3, so that the dummy pixel region 1 can discharge the electrostatic voltage to the display. 6 Perform electrostatic protection.
  • the polysilicon trace 4 shown in FIG. 2 intersects the gate line 3 seven times, which makes the area of the polysilicon trace 4 and the gate line 3 in the dummy pixel region 1 overlap by more than the surface.
  • the area of the polysilicon trace 4 in the display area 6 overlapping with the gate line 3 is three times as large as that, and the electrostatic voltage can be completely released to prevent the pixel of the display area 6 from being damaged.
  • the number of times the polysilicon trace 4 and the gate line 3 intersect each other is not limited to the above embodiment, and may be four times, five times, six times, eight times, or the like.
  • the polysilicon traces 4 crossing the gate line 3 are connected in parallel, which is convenient for processing, and the production cost can be effectively controlled.
  • the polysilicon traces 4 crossing the gate line 3 may also be connected in series.
  • the present invention does not intend to limit the shape and connection manner of the polysilicon trace 4, and may be any regular shape or irregular shape as long as the polysilicon trace 4 and the gate line 3 in the dummy pixel region 1 are ensured.
  • the area overlapped by the different faces may be larger than the area in which the polysilicon traces 4 in the display region 6 overlap the different faces of the gate lines 3.
  • the portion of the polysilicon trace 4 that overlaps the surface of the gate line 3 is a thick design, and the gate line 3 may be thickened at a portion where the opposite sides overlap, in other words,
  • the line width of the polysilicon trace 4 in the dummy pixel region 1 is larger than the line width of the polysilicon trace in the display region 6, and/or is virtual
  • the line width of the gate line 3 in the pseudo pixel region 1 is larger than the line width of the polysilicon trace in the display region 6, thereby increasing the overlapping area of the polysilicon trace 4 and the gate line 3 in the dummy pixel region 1, increasing both The capacitance between them effectively releases the static voltage.
  • the polysilicon trace 4 is formed by patterning with a polysilicon layer. Compared with manufacturing the existing polysilicon trace, the polysilicon trace 4 is not increased, and the static protection of the display region can be realized without increasing the cost. Specifically, the polysilicon trace unit 1 can be fabricated by thin film deposition, exposure, and etching, but is not limited to this method.
  • FIG. 3 it is a partial schematic view of another preferred embodiment of the array substrate according to the present invention.
  • a transition region 8 is further disposed between the virtual pixel region 1 and the display region 6, and the transition region 8 may be a virtual pixel region or a display region.
  • the overlapping area between the polysilicon trace 4 and the gate line 3 in the transition region 8 may be less than or equal to the overlap area between the polysilicon trace 4 and the gate line 3 in the dummy pixel region 1, and the transition
  • the overlap area between the polysilicon trace 4 and the gate line 3 in the region 8 may be greater than or equal to the overlap area between the polysilicon trace 4 and the gate line 3 in the display region 6.
  • transition region 8 is a virtual pixel region
  • the first column of virtual pixel regions in FIG. 3 (labeled as "1" in the figure) still fails to sufficiently discharge the electrostatic voltage
  • the second column of virtual pixel regions ( The figure is labeled "8") to continue to discharge the electrostatic voltage, thereby ensuring that the gate insulating layer in the display region is not broken down when the voltage continues to be loaded in the display region 6.
  • transition region 8 is the display region
  • the edge position as the display region (marked as "8” in the figure)
  • the electrostatic voltage will continue to be released, thereby ensuring that the gate insulating layer in the display region is not broken down when the voltage continues to be applied to the gradually near middle position of the display region 6.
  • the purpose of this design is to consider that the electrostatic voltage generated during the use of the display area should be released by the electrostatic protection device; on the other hand, it is transmitted from the driving circuit area to the display area in consideration of the electrostatic voltage generated during the production process of the liquid crystal panel.
  • the voltage of the process is gradually consumed, that is, the voltage at the edge of the display area is relatively large, and the electrostatic voltage near the center of the display area is small.
  • the polysilicon trace unit in the pixel at the edge of the display area is displayed.
  • the number of gate polysilicon traces is greater than or equal to the number of gate polysilicon traces of the polysilicon trace unit in the pixel near the center of the display region. It should be noted that since the transition region 8 is located at the edge position of the display region, it does not have any negative influence on the imaging effect of the display region 6.
  • the dummy pixel region 1 and the transition region 8 are respectively designed as one column, and the display region is an innumerable column, in actual production, according to the structural requirements and production conditions of the produced liquid crystal panel, Design the virtual pixel area, the transition area, and the number of columns of pixels in the display area. Under certain production processes, tooling conditions and liquid crystal panel use conditions, the best polysilicon trace structure in different parts is obtained.
  • the present invention also provides a liquid crystal panel having the array substrate of any of the above structures.
  • the virtual pixel region can effectively release the electrostatic voltage and avoid the display region. The pixels are injured, which can improve the yield of the display panel.
  • the transition region may be a virtual pixel region or a display region, and an overlap between the polysilicon traces and the gate lines in the transition region
  • the area may be less than or equal to the overlap area between the polysilicon trace and the gate line in the dummy pixel region, and the overlap area between the polysilicon trace and the gate line in the transition region may be greater than or equal to that in the display region
  • the overlapping area between the polysilicon trace and the gate line realizes further release of the electrostatic voltage and improves the electrostatic protection of the display area.

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  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Crystallography & Structural Chemistry (AREA)
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  • Chemical & Material Sciences (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

阵列基板以及具有阵列基板的液晶面板，其中，阵列基板包括：虚拟像素区(1)、显示区(6)以及驱动电路区(7)，虚拟像素区(1)位于显示区(6)与驱动电路区(7)之间，显示区(6)和虚拟像素区(1)内均设置有异面交叉的多晶硅走线(4)和栅极线(3)；其中，虚拟像素区(1)内的多晶硅走线(4)与栅极线(3)异面重叠的面积大于显示区(6)内的多晶硅走线(4)与栅极线(3)异面重叠的面积。能够有效释放静电电压，大大削弱可能会继续沿栅极线(3)传入显示区(6)的静电电压，避免破坏显示区(6)像素功能。

Description

阵列基板以及具有该阵列基板的液晶面板
相关申请的交叉引用
本申请要求享有于2017年2月24日提交的名称为“阵列基板以及具有该阵列基板的液晶面板”的中国专利申请CN2017101023803的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明属于电气保护领域，特别涉及一种能够有效释放静电电压的阵列基板以及具有该阵列基板的液晶面板。
背景技术
液晶面板器件在生产制造过程中或工作在一定的电压、电流和功耗限定范围内时，大量聚集的静电荷在条件适宜时会产生高压放电，静电放电(ESD，Elctro-Static Discharge)通过电路器件引线的高压瞬时传送，可能会使电路器件的绝缘层击穿，造成电路器件的功能丧失。低温多晶硅(LTPS，Low Temperature Poly-Silicon)技术应用在显示面板上时，由于TFT模块的引入，数字信号要在更高的频率上工作，则增加了静电放电事件在电路器件上发生的概率。且低温多晶硅阵列基板(Array)结构设计中，可以为显示区提供栅极驱动信号的驱动电路区(GOA)往往含有较大面积的金属，容易受静电放电事件影响，产生较大的静电电压。驱动电路区的静电电压可沿栅极线传入显示区，造成与驱动电路区相邻的显示区边缘像素损坏。
现有技术中，通常通过在显示区边缘设置虚拟像素区(Dummy Pixel)的方法来达到静电保护的目的。该方法的原理是使静电电压在虚拟像素区充分释放，避免静电的高电压继续传入显示区而造成显示区的像素被击伤。
例如，如图1所示，其为现有的阵列基板的局部示意图。所述阵列基板主要包括：虚拟像素区1’、源极线2’、栅极线3’、多晶硅走线4’、像素ITO走线5’、显示区6’以及驱动电路区7’。其中，所述虚拟像素区1’位于显示区6’的边缘， 即显示区6’与驱动电路区7’之间。源极线2’与栅极线3’异面垂直，多晶硅走线4’与栅极线3’异面交叉，且多晶硅走线4’与源极线2’通过过孔(图中未标示)连接。在阵列基板的制造过程中，驱动电路区7’产生的ESD高电压在沿栅极线3’传入显示区6’前，由于栅极线3’仅和虚拟像素区1’中的多晶硅走线4’异面重叠二次，(栅极线3’和多晶硅走线4’之间仅隔着约100纳米厚的栅极绝缘层，栅极线3’和多晶硅走线4’之间的高电压差容易造成栅极绝缘层被击穿)，重叠面积非常有限，因此常常有未被释放掉的ESD高电压继续传入显示区6’而造成显示区6’的像素被击伤，在显示区6’边缘造成异常亮点或暗点。
换言之，本申请的发明人发现，当虚拟像素区1’内的多晶硅走线4’与栅极线3’异面重叠的面积等于或小于显示区6’内的多晶硅走线4’与栅极线3’异面重叠的面积时，无法有效释放掉静电电压。因此在静电电压过大时，虚拟像素区无法对其进行充分释放，致使静电电压继续沿栅极线传入显示区，破坏显示区像素功能。
发明内容
本发明目的在于提供一种阵列基板以及具有该阵列基板的液晶面板，其能够有效释放静电电压，大大削弱可能会继续沿栅极线传入显示区的静电电压，避免破坏显示区像素功能。
为达上述目的，本发明提供一种阵列基板，其包括：虚拟像素区、显示区以及驱动电路区，所述虚拟像素区位于显示区与驱动电路区之间，所述显示区和虚拟像素区内均设置有异面交叉的多晶硅走线和栅极线；
其中，所述虚拟像素区内的多晶硅走线与栅极线异面重叠的面积大于显示区内的多晶硅走线与栅极线异面重叠的面积。
所述的阵列基板，其中，在虚拟像素区内，多晶硅走线与栅极线异面交叉至少三次。
所述的阵列基板，其中，在虚拟像素区内，多晶硅走线与栅极线异面交叉七次。
所述的阵列基板，其中，在虚拟像素区内，与栅极线异面交叉的多晶硅走线为并联连接。
所述的阵列基板，其中，在虚拟像素区内，与栅极线异面交叉的多晶硅走线为串联连接。
所述的阵列基板，其中，在虚拟像素区内，虚拟像素区内的多晶硅走线的线宽大于显示区内的多晶硅走线的线宽。
所述的阵列基板，其中，在虚拟像素区内，虚拟像素区内的栅极线的线宽大于显示区内的栅极线的线宽。
所述的阵列基板，其中，在虚拟像素区与显示区之间还设置有过渡区，所述过渡区内的多晶硅走线与栅极线之间的重叠面积小于或等于虚拟像素区内的多晶硅走线与栅极线之间的重叠面积，并且所述过渡区内的多晶硅走线与栅极线之间的重叠面积大于或等于显示区内的多晶硅走线与栅极线之间的重叠面积。
所述的阵列基板，其中，所述过渡区为虚拟像素区或显示区。
本发明还提供一种液晶面板，其包括上述的阵列基板。
综上所述，本发明的有益效果是：
1、通过使虚拟像素区内的多晶硅走线与栅极线的重叠面积大于显示区内的多晶硅走线与栅极线的重叠面积，使得虚拟像素区能够从而有效释放掉静电电压，避免显示区的像素被击伤，因此能提升显示面板制造的良率。
2、通过在虚拟像素区与显示区之间设置过渡区，所述过渡区可以是虚拟像素区，也可以是显示区，并且所述过渡区内的多晶硅走线与栅极线之间的重叠面积可以小于或等于虚拟像素区内的多晶硅走线与栅极线之间的重叠面积，并且所述过渡区内的多晶硅走线与栅极线之间的重叠面积可以大于或等于显示区内的多晶硅走线与栅极线之间的重叠面积，实现进一步释放掉静电电压，提高对显示区的静电保护。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中：
图1是现有的阵列基板的局部示意图；
图2是根据本发明的阵列基板的一个优选实施例的局部示意图；
图3是根据本发明的阵列基板的另一优选实施例的局部示意图。
在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例。
具体实施方式
下面将结合附图对本发明作进一步说明。
如图2所示，其为根据本发明的阵列基板的一个优选实施例的局部示意图。所述阵列基板主要包括：虚拟像素区1、源极线2、栅极线3、多晶硅走线4、像素ITO走线5、显示区6以及驱动电路区7。其中，所述虚拟像素区1位于显示区6的边缘，即显示区6与驱动电路区7之间。所述显示区6和虚拟像素区1内均设置有源极线2、栅极线3、多晶硅走线4以及像素ITO走线5，源极线2与栅极线3异面垂直，多晶硅走线4与栅极线3异面交叉，且多晶硅走线4与源极线2通过过孔(图中未标示)连接。
本发明的改进在于，使得虚拟像素区1内的多晶硅走线4与栅极线3异面重叠的面积大于显示区6内的多晶硅走线4与栅极线3异面重叠的面积，从而有效释放掉静电电压，避免显示区6的像素被击伤，因此能提升显示面板制造的良率。
具体地，在虚拟像素区内1，多晶硅走线4可以与栅极线3异面交叉至少三次，从而使得虚拟像素区1内的多晶硅走线4与栅极线3异面重叠的面积大于显示区6内的多晶硅走线4与栅极线3异面重叠的面积50％，由此增加多晶硅走向4与栅极线3之间的电容，使得虚拟像素区1能够释放掉静电电压，对显示器6进行静电保护。
更具体地，图2中所示的多晶硅走线4与栅极线3异面交叉了七次，这使得虚拟像素区1内的多晶硅走线4与栅极线3异面重叠的面积明显大于显示区6内的多晶硅走线4与栅极线3异面重叠的面积三倍之多，完全可以释放掉静电电压，避免显示区6的像素被击伤。需要说明的是，多晶硅走线4与栅极线3异面交叉的次数并不以上述实施例为限，也可以是四次、五次、六次、八次等等。
优选地，在虚拟像素区内1，与栅极线3异面交叉的多晶硅走线4为并联连接，便于加工，生产成本可以得到有效控制。当然，与栅极线3异面交叉的多晶硅走线4也可以为串联连接。
当然，本发明并不希望对多晶硅走线4的形状及连接方式做任何限定，其可以是任何的规则形状或不规则形状，只要保证虚拟像素区1内的多晶硅走线4与栅极线3异面重叠的面积大于显示区6内的多晶硅走线4与栅极线3异面重叠的面积即可。
例如，在虚拟像素区1内，多晶硅走线4在与栅极线3异面重叠的部分为加粗设计，而栅极线3也可以在异面重叠的部分进行加粗设计，换言之，使虚拟像素区1内的多晶硅走线4的线宽大于显示区6内的多晶硅走线的线宽，和/或使虚 拟像素区1内的栅极线3的线宽大于显示区6内的多晶硅走线的线宽，从而在虚拟像素区1内增加多晶硅走线4与栅极线3的重叠面积，增加二者之间的电容，从而有效释放掉静电电压。
所述多晶硅走线4是利用多晶硅层图案化后制得的，其相比于制造现有的多晶硅走线并没有增加工序，在不增加成本的前提下可以实现对显示区的静电保护。具体地，所述多晶硅走线单元1可通过薄膜沉积及曝光、蚀刻的方法制得，但不仅限于此方法。
再如图3所示，其为根据本发明的阵列基板的另一优选实施例的局部示意图。该实施例与上一实施例的区别在于，在虚拟像素区1与显示区6之间还设置有过渡区8，所述过渡区8可以是虚拟像素区，也可以是显示区。
所述过渡区8内的多晶硅走线4与栅极线3之间的重叠面积可以小于或等于虚拟像素区1内的多晶硅走线4与栅极线3之间的重叠面积，并且所述过渡区8内的多晶硅走线4与栅极线3之间的重叠面积可以大于或等于显示区6内的多晶硅走线4与栅极线3之间的重叠面积。
如此一来，当过渡区8为虚拟像素区时，如果图3中的第一列虚拟像素区(图中标记为“1”)仍未能充分释放静电电压时，第二列虚拟像素区(图中标记为“8”)继续释放静电电压，从而确保当电压继续加载在显示区6时，不会出现显示区内的栅极绝缘层被击穿的情况。
当过渡区8为显示区时，如果图3中的虚拟像素区(图中标记为“1”)仍未能充分释放静电电压时，那么作为显示区的边缘位置(图中标记为“8”)将继续释放静电电压，从而确保当电压继续加载在显示区6的逐渐靠近中部位置时，不会出现显示区内的栅极绝缘层被击穿的情况。
这样设计的目的一方面是考虑到显示区使用时产生的静电电压应该有静电保护装置进行释放；另一方面是考虑到液晶面板生产过程中产生的静电电压时有由驱动电路区向显示区传递的，该过程电压逐渐被消耗，也就说显示区边缘部位电压较大，靠近显示区中心部位的静电电压较小，则设计液晶面板结构时将显示区边缘部位的像素中多晶硅走线单元的栅形部多晶硅走线数量大于等于靠近显示区中心部的像素中多晶硅走线单元的栅形部多晶硅走线数量。需要说明的是，由于过渡区8位于显示区的边缘位置，因此不会对显示区6的成像效果有任何的负面影响。
此外，虽然在图3中，虚拟像素区1和过渡区8分别设计为一列，显示区为无数列，然而在实际生产过程中，可根据所生产的液晶面板的结构需要和生产条件需要，来设计虚拟像素区、过渡区与显示区内像素的列数。在一定生产工艺、工装条件及液晶面板使用条件下，获得不同部位最佳多晶硅走线结构。
本发明还提供一种液晶面板，其具有上述任一种结构形式的阵列基板。
综上所述，本发明的有益效果是：
1、通过使虚拟像素区内的多晶硅走线与栅极线的重叠面积大于显示区内的多晶硅走线与栅极线的重叠面积，使得虚拟像素区能够从而有效释放掉静电电压，避免显示区的像素被击伤，因此能提升显示面板制造的良率。
2、通过在虚拟像素区与显示区之间设置过渡区，所述过渡区可以是虚拟像素区，也可以是显示区，并且所述过渡区内的多晶硅走线与栅极线之间的重叠面积可以小于或等于虚拟像素区内的多晶硅走线与栅极线之间的重叠面积，并且所述过渡区内的多晶硅走线与栅极线之间的重叠面积可以大于或等于显示区内的多晶硅走线与栅极线之间的重叠面积，实现进一步释放掉静电电压，提高对显示区的静电保护。
虽然已经参考优选实施例对本发明进行了描述，但在不脱离本发明的范围的情况下，可以对其进行各种改进并且可以用等效物替换其中的部件。尤其是，只要不存在结构冲突，各个实施例中所提到的各项技术特征均可以任意方式组合起来。本发明并不局限于文中公开的特定实施例，而是包括落入权利要求的范围内的所有技术方案。

Claims (20)

  1. 一种阵列基板，其中，包括：虚拟像素区、显示区以及驱动电路区，所述虚拟像素区位于显示区与驱动电路区之间，所述显示区和虚拟像素区内均设置有异面交叉的多晶硅走线和栅极线；
    其中，所述虚拟像素区内的多晶硅走线与栅极线异面重叠的面积大于显示区内的多晶硅走线与栅极线异面重叠的面积。
  2. 根据权利要求1所述的阵列基板，其中，在虚拟像素区内，多晶硅走线与栅极线异面交叉至少三次。
  3. 根据权利要求1所述的阵列基板，其中，在虚拟像素区内，多晶硅走线与栅极线异面交叉七次。
  4. 根据权利要求1所述的阵列基板，其中，在虚拟像素区内，与栅极线异面交叉的多晶硅走线为并联连接。
  5. 根据权利要求1所述的阵列基板，其中，在虚拟像素区内，与栅极线异面交叉的多晶硅走线为串联连接。
  6. 根据权利要求1所述的阵列基板，其中，在虚拟像素区内，虚拟像素区内的多晶硅走线的线宽大于显示区内的多晶硅走线的线宽。
  7. 根据权利要求1所述的阵列基板，其中，在虚拟像素区内，虚拟像素区内的栅极线的线宽大于显示区内的栅极线的线宽。
  8. 根据权利要求1所述的阵列基板，其中，在虚拟像素区与显示区之间还设置有过渡区，所述过渡区内的多晶硅走线与栅极线之间的重叠面积小于或等于虚拟像素区内的多晶硅走线与栅极线之间的重叠面积，并且所述过渡区内的多晶硅走线与栅极线之间的重叠面积大于或等于显示区内的多晶硅走线与栅极线之间的重叠面积。
  9. 根据权利要求2所述的阵列基板，其中，在虚拟像素区与显示区之间还设置有过渡区，所述过渡区内的多晶硅走线与栅极线之间的重叠面积小于或等于虚拟像素区内的多晶硅走线与栅极线之间的重叠面积，并且所述过渡区内的多晶硅走线与栅极线之间的重叠面积大于或等于显示区内的多晶硅走线与栅极线之间的重叠面积。
  10. 根据权利要求3所述的阵列基板，其中，在虚拟像素区与显示区之间还 设置有过渡区，所述过渡区内的多晶硅走线与栅极线之间的重叠面积小于或等于虚拟像素区内的多晶硅走线与栅极线之间的重叠面积，并且所述过渡区内的多晶硅走线与栅极线之间的重叠面积大于或等于显示区内的多晶硅走线与栅极线之间的重叠面积。
  11. 根据权利要求4所述的阵列基板，其中，在虚拟像素区与显示区之间还设置有过渡区，所述过渡区内的多晶硅走线与栅极线之间的重叠面积小于或等于虚拟像素区内的多晶硅走线与栅极线之间的重叠面积，并且所述过渡区内的多晶硅走线与栅极线之间的重叠面积大于或等于显示区内的多晶硅走线与栅极线之间的重叠面积。
  12. 根据权利要求5所述的阵列基板，其中，在虚拟像素区与显示区之间还设置有过渡区，所述过渡区内的多晶硅走线与栅极线之间的重叠面积小于或等于虚拟像素区内的多晶硅走线与栅极线之间的重叠面积，并且所述过渡区内的多晶硅走线与栅极线之间的重叠面积大于或等于显示区内的多晶硅走线与栅极线之间的重叠面积。
  13. 根据权利要求6所述的阵列基板，其中，在虚拟像素区与显示区之间还设置有过渡区，所述过渡区内的多晶硅走线与栅极线之间的重叠面积小于或等于虚拟像素区内的多晶硅走线与栅极线之间的重叠面积，并且所述过渡区内的多晶硅走线与栅极线之间的重叠面积大于或等于显示区内的多晶硅走线与栅极线之间的重叠面积。
  14. 根据权利要求7所述的阵列基板，其中，在虚拟像素区与显示区之间还设置有过渡区，所述过渡区内的多晶硅走线与栅极线之间的重叠面积小于或等于虚拟像素区内的多晶硅走线与栅极线之间的重叠面积，并且所述过渡区内的多晶硅走线与栅极线之间的重叠面积大于或等于显示区内的多晶硅走线与栅极线之间的重叠面积。
  15. 根据权利要求8所述的阵列基板，其中，所述过渡区为虚拟像素区或显示区。
  16. 根据权利要求9所述的阵列基板，其中，所述过渡区为虚拟像素区或显示区。
  17. 根据权利要求10所述的阵列基板，其中，所述过渡区为虚拟像素区或显示区。
  18. 根据权利要求11所述的阵列基板，其中，所述过渡区为虚拟像素区或显示区。
  19. 根据权利要求12所述的阵列基板，其中，所述过渡区为虚拟像素区或显示区。
  20. 一种液晶面板，其中，包括根据权利要求1所述的阵列基板。
PCT/CN2017/076554 2017-02-24 2017-03-14 阵列基板以及具有该阵列基板的液晶面板 WO2018152883A1 (zh)

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