CN106783845A - 阵列基板以及具有该阵列基板的液晶面板 - Google Patents

阵列基板以及具有该阵列基板的液晶面板 Download PDF

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CN106783845A
CN106783845A CN201710102380.3A CN201710102380A CN106783845A CN 106783845 A CN106783845 A CN 106783845A CN 201710102380 A CN201710102380 A CN 201710102380A CN 106783845 A CN106783845 A CN 106783845A
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虞晓江
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to PCT/CN2017/076554 priority patent/WO2018152883A1/zh
Priority to US15/522,563 priority patent/US20180292719A1/en
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Abstract

本发明提供一种阵列基板以及具有该阵列基板的液晶面板，所述阵列基板包括：虚拟像素区、显示区以及驱动电路区，所述虚拟像素区位于显示区与驱动电路区之间，所述显示区和虚拟像素区内均设置有异面交叉的多晶硅走线和栅极线；其中，所述虚拟像素区内的多晶硅走线与栅极线异面重叠的面积大于显示区内的多晶硅走线与栅极线异面重叠的面积。本发明的阵列基板能够有效释放静电电压，大大削弱可能会继续沿栅极线传入显示区的静电电压，避免破坏显示区像素功能。

Description

阵列基板以及具有该阵列基板的液晶面板
技术领域
本发明属于电气保护领域，特别涉及一种能够有效释放静电电压的阵列基板以及具有该阵列基板的液晶面板。
背景技术
液晶面板器件在生产制造过程中或工作在一定的电压、电流和功耗限定范围内时，大量聚集的静电荷在条件适宜时会产生高压放电，静电放电(ESD，Elctro-StaticDischarge)通过电路器件引线的高压瞬时传送，可能会使电路器件的绝缘层击穿，造成电路器件的功能丧失。低温多晶硅(LTPS，Low Temperature Poly-Silicon)技术应用在显示面板上时，由于TFT模块的引入，数字信号要在更高的频率上工作，则增加了静电放电事件在电路器件上发生的概率。且低温多晶硅阵列基板(Array)结构设计中，可以为显示区提供栅极驱动信号的驱动电路区(GOA)往往含有较大面积的金属，容易受静电放电事件影响，产生较大的静电电压。驱动电路区的静电电压可沿栅极线传入显示区，造成与驱动电路区相邻的显示区边缘像素损坏。
现有技术中，通常通过在显示区边缘设置虚拟像素区(Dummy Pixel)的方法来达到静电保护的目的。该方法的原理是使静电电压在虚拟像素区充分释放，避免静电的高电压继续传入显示区而造成显示区的像素被击伤。
例如，如图1所示，其为现有的阵列基板的局部示意图。所述阵列基板主要包括：虚拟像素区1’、源极线2’、栅极线3’、多晶硅走线4’、像素ITO走线5’、显示区6’以及驱动电路区7’。其中，所述虚拟像素区1’位于显示区6’的边缘，即显示区6’与驱动电路区7’之间。源极线2’与栅极线3’异面垂直，多晶硅走线4’与栅极线3’异面交叉，且多晶硅走线4’与源极线2’通过过孔(图中未标示)连接。在阵列基板的制造过程中，驱动电路区7’产生的ESD高电压在沿栅极线3’传入显示区6’前，由于栅极线3’仅和虚拟像素区1’中的多晶硅走线4’异面重叠二次，(栅极线3’和多晶硅走线4’之间仅隔着约100纳米厚的栅极绝缘层，栅极线3’和多晶硅走线4’之间的高电压差容易造成栅极绝缘层被击穿)，重叠面积非常有限，因此常常有未被释放掉的ESD高电压继续传入显示区6’而造成显示区6’的像素被击伤，在显示区6’边缘造成异常亮点或暗点。
换言之，本申请的发明人发现，当虚拟像素区1’内的多晶硅走线4’与栅极线3’异面重叠的面积等于或小于显示区6’内的多晶硅走线4’与栅极线3’异面重叠的面积时，无法有效释放掉静电电压。因此在静电电压过大时，虚拟像素区无法对其进行充分释放，致使静电电压继续沿栅极线传入显示区，破坏显示区像素功能。
发明内容
本发明目的在于提供一种阵列基板以及具有该阵列基板的液晶面板，其能够有效释放静电电压，大大削弱可能会继续沿栅极线传入显示区的静电电压，避免破坏显示区像素功能。
为达上述目的，本发明提供一种阵列基板，其包括：虚拟像素区、显示区以及驱动电路区，所述虚拟像素区位于显示区与驱动电路区之间，所述显示区和虚拟像素区内均设置有异面交叉的多晶硅走线和栅极线；
其中，所述虚拟像素区内的多晶硅走线与栅极线异面重叠的面积大于显示区内的多晶硅走线与栅极线异面重叠的面积。
所述的阵列基板，其中，在虚拟像素区内，多晶硅走线与栅极线异面交叉至少三次。
所述的阵列基板，其中，在虚拟像素区内，多晶硅走线与栅极线异面交叉七次。
所述的阵列基板，其中，在虚拟像素区内，与栅极线异面交叉的多晶硅走线为并联连接。
所述的阵列基板，其中，在虚拟像素区内，与栅极线异面交叉的多晶硅走线为串联连接。
所述的阵列基板，其中，在虚拟像素区内，虚拟像素区内的多晶硅走线的线宽大于显示区内的多晶硅走线的线宽。
所述的阵列基板，其中，在虚拟像素区内，虚拟像素区内的栅极线的线宽大于显示区内的栅极线的线宽。
所述的阵列基板，其中，在虚拟像素区与显示区之间还设置有过渡区，所述过渡区内的多晶硅走线与栅极线之间的重叠面积小于或等于虚拟像素区内的多晶硅走线与栅极线之间的重叠面积，并且所述过渡区内的多晶硅走线与栅极线之间的重叠面积大于或等于显示区内的多晶硅走线与栅极线之间的重叠面积。
所述的阵列基板，其中，所述过渡区为虚拟像素区或显示区。
本发明还提供一种液晶面板，其包括上述的阵列基板。
综上所述，本发明的有益效果是：
1、通过使虚拟像素区内的多晶硅走线与栅极线的重叠面积大于显示区内的多晶硅走线与栅极线的重叠面积，使得虚拟像素区能够从而有效释放掉静电电压，避免显示区的像素被击伤，因此能提升显示面板制造的良率。
2、通过在虚拟像素区与显示区之间设置过渡区，所述过渡区可以是虚拟像素区，也可以是显示区，并且所述过渡区内的多晶硅走线与栅极线之间的重叠面积可以小于或等于虚拟像素区内的多晶硅走线与栅极线之间的重叠面积，并且所述过渡区内的多晶硅走线与栅极线之间的重叠面积可以大于或等于显示区内的多晶硅走线与栅极线之间的重叠面积，实现进一步释放掉静电电压，提高对显示区的静电保护。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中：
图1是现有的阵列基板的局部示意图；
图2是根据本发明的阵列基板的一个优选实施例的局部示意图；
图3是根据本发明的阵列基板的另一优选实施例的局部示意图。
在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例。
具体实施方式
下面将结合附图对本发明作进一步说明。
如图2所示，其为根据本发明的阵列基板的一个优选实施例的局部示意图。所述阵列基板主要包括：虚拟像素区1、源极线2、栅极线3、多晶硅走线4、像素ITO走线5、显示区6以及驱动电路区7。其中，所述虚拟像素区1位于显示区6的边缘，即显示区6与驱动电路区7之间。所述显示区6和虚拟像素区1内均设置有源极线2、栅极线3、多晶硅走线4以及像素ITO走线5，源极线2与栅极线3异面垂直，多晶硅走线4与栅极线3异面交叉，且多晶硅走线4与源极线2通过过孔(图中未标示)连接。
本发明的改进在于，使得虚拟像素区1内的多晶硅走线4与栅极线3异面重叠的面积大于显示区6内的多晶硅走线4与栅极线3异面重叠的面积，从而有效释放掉静电电压，避免显示区6的像素被击伤，因此能提升显示面板制造的良率。
具体地，在虚拟像素区内1，多晶硅走线4可以与栅极线3异面交叉至少三次，从而使得虚拟像素区1内的多晶硅走线4与栅极线3异面重叠的面积大于显示区6内的多晶硅走线4与栅极线3异面重叠的面积50％，由此增加多晶硅走向4与栅极线3之间的电容，使得虚拟像素区1能够释放掉静电电压，对显示器6进行静电保护。
更具体地，图2中所示的多晶硅走线4与栅极线3异面交叉了七次，这使得虚拟像素区1内的多晶硅走线4与栅极线3异面重叠的面积明显大于显示区6内的多晶硅走线4与栅极线3异面重叠的面积三倍之多，完全可以释放掉静电电压，避免显示区6的像素被击伤。需要说明的是，多晶硅走线4与栅极线3异面交叉的次数并不以上述实施例为限，也可以是四次、五次、六次、八次等等。
优选地，在虚拟像素区内1，与栅极线3异面交叉的多晶硅走线4为并联连接，便于加工，生产成本可以得到有效控制。当然，与栅极线3异面交叉的多晶硅走线4也可以为串联连接。
当然，本发明并不希望对多晶硅走线4的形状及连接方式做任何限定，其可以是任何的规则形状或不规则形状，只要保证虚拟像素区1内的多晶硅走线4与栅极线3异面重叠的面积大于显示区6内的多晶硅走线4与栅极线3异面重叠的面积即可。
例如，在虚拟像素区1内，多晶硅走线4在与栅极线3异面重叠的部分为加粗设计，而栅极线3也可以在异面重叠的部分进行加粗设计，换言之，使虚拟像素区1内的多晶硅走线4的线宽大于显示区6内的多晶硅走线的线宽，和/或使虚拟像素区1内的栅极线3的线宽大于显示区6内的多晶硅走线的线宽，从而在虚拟像素区1内增加多晶硅走线4与栅极线3的重叠面积，增加二者之间的电容，从而有效释放掉静电电压。
所述多晶硅走线4是利用多晶硅层图案化后制得的，其相比于制造现有的多晶硅走线并没有增加工序，在不增加成本的前提下可以实现对显示区的静电保护。具体地，所述多晶硅走线单元1可通过薄膜沉积及曝光、蚀刻的方法制得，但不仅限于此方法。
再如图3所示，其为根据本发明的阵列基板的另一优选实施例的局部示意图。该实施例与上一实施例的区别在于，在虚拟像素区1与显示区6之间还设置有过渡区8，所述过渡区8可以是虚拟像素区，也可以是显示区。
所述过渡区8内的多晶硅走线4与栅极线3之间的重叠面积可以小于或等于虚拟像素区1内的多晶硅走线4与栅极线3之间的重叠面积，并且所述过渡区8内的多晶硅走线4与栅极线3之间的重叠面积可以大于或等于显示区6内的多晶硅走线4与栅极线3之间的重叠面积。
如此一来，当过渡区8为虚拟像素区时，如果图3中的第一列虚拟像素区(图中标记为“1”)仍未能充分释放静电电压时，第二列虚拟像素区(图中标记为“8”)继续释放静电电压，从而确保当电压继续加载在显示区6时，不会出现显示区内的栅极绝缘层被击穿的情况。
当过渡区8为显示区时，如果图3中的虚拟像素区(图中标记为“1”)仍未能充分释放静电电压时，那么作为显示区的边缘位置(图中标记为“8”)将继续释放静电电压，从而确保当电压继续加载在显示区6的逐渐靠近中部位置时，不会出现显示区内的栅极绝缘层被击穿的情况。
这样设计的目的一方面是考虑到显示区使用时产生的静电电压应该有静电保护装置进行释放；另一方面是考虑到液晶面板生产过程中产生的静电电压时有由驱动电路区向显示区传递的，该过程电压逐渐被消耗，也就说显示区边缘部位电压较大，靠近显示区中心部位的静电电压较小，则设计液晶面板结构时将显示区边缘部位的像素中多晶硅走线单元的栅形部多晶硅走线数量大于等于靠近显示区中心部的像素中多晶硅走线单元的栅形部多晶硅走线数量。需要说明的是，由于过渡区8位于显示区的边缘位置，因此不会对显示区6的成像效果有任何的负面影响。
此外，虽然在图3中，虚拟像素区1和过渡区8分别设计为一列，显示区为无数列，然而在实际生产过程中，可根据所生产的液晶面板的结构需要和生产条件需要，来设计虚拟像素区、过渡区与显示区内像素的列数。在一定生产工艺、工装条件及液晶面板使用条件下，获得不同部位最佳多晶硅走线结构。
本发明还提供一种液晶面板，其具有上述任一种结构形式的阵列基板。
综上所述，本发明的有益效果是：
1、通过使虚拟像素区内的多晶硅走线与栅极线的重叠面积大于显示区内的多晶硅走线与栅极线的重叠面积，使得虚拟像素区能够从而有效释放掉静电电压，避免显示区的像素被击伤，因此能提升显示面板制造的良率。
2、通过在虚拟像素区与显示区之间设置过渡区，所述过渡区可以是虚拟像素区，也可以是显示区，并且所述过渡区内的多晶硅走线与栅极线之间的重叠面积可以小于或等于虚拟像素区内的多晶硅走线与栅极线之间的重叠面积，并且所述过渡区内的多晶硅走线与栅极线之间的重叠面积可以大于或等于显示区内的多晶硅走线与栅极线之间的重叠面积，实现进一步释放掉静电电压，提高对显示区的静电保护。
虽然已经参考优选实施例对本发明进行了描述，但在不脱离本发明的范围的情况下，可以对其进行各种改进并且可以用等效物替换其中的部件。尤其是，只要不存在结构冲突，各个实施例中所提到的各项技术特征均可以任意方式组合起来。本发明并不局限于文中公开的特定实施例，而是包括落入权利要求的范围内的所有技术方案。

Claims (10)

1.一种阵列基板，其特征在于，包括：虚拟像素区、显示区以及驱动电路区，所述虚拟像素区位于显示区与驱动电路区之间，所述显示区和虚拟像素区内均设置有异面交叉的多晶硅走线和栅极线；
其中，所述虚拟像素区内的多晶硅走线与栅极线异面重叠的面积大于显示区内的多晶硅走线与栅极线异面重叠的面积。
2.根据权利要求1所述的阵列基板，其特征在于，在虚拟像素区内，多晶硅走线与栅极线异面交叉至少三次。
3.根据权利要求1所述的阵列基板，其特征在于，在虚拟像素区内，多晶硅走线与栅极线异面交叉七次。
4.根据权利要求1所述的阵列基板，其特征在于，在虚拟像素区内，与栅极线异面交叉的多晶硅走线为并联连接。
5.根据权利要求1所述的阵列基板，其特征在于，在虚拟像素区内，与栅极线异面交叉的多晶硅走线为串联连接。
6.根据权利要求1所述的阵列基板，其特征在于，在虚拟像素区内，虚拟像素区内的多晶硅走线的线宽大于显示区内的多晶硅走线的线宽。
7.根据权利要求1所述的阵列基板，其特征在于，在虚拟像素区内，虚拟像素区内的栅极线的线宽大于显示区内的栅极线的线宽。
8.根据权利要求1至7中任一项所述的阵列基板，其特征在于，在虚拟像素区与显示区之间还设置有过渡区，所述过渡区内的多晶硅走线与栅极线之间的重叠面积小于或等于虚拟像素区内的多晶硅走线与栅极线之间的重叠面积，并且所述过渡区内的多晶硅走线与栅极线之间的重叠面积大于或等于显示区内的多晶硅走线与栅极线之间的重叠面积。
9.根据权利要求8所述的阵列基板，其特征在于，所述过渡区为虚拟像素区或显示区。
10.一种液晶面板，其特征在于，包括根据权利要求1至9中任一项所述的阵列基板。
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