WO2018095233A1 - Semiconductor structure and forming method therefor, and packaging structure and forming method therefor - Google Patents
Semiconductor structure and forming method therefor, and packaging structure and forming method therefor Download PDFInfo
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- WO2018095233A1 WO2018095233A1 PCT/CN2017/110641 CN2017110641W WO2018095233A1 WO 2018095233 A1 WO2018095233 A1 WO 2018095233A1 CN 2017110641 W CN2017110641 W CN 2017110641W WO 2018095233 A1 WO2018095233 A1 WO 2018095233A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Definitions
- the present invention relates to the field of packaging technologies, and in particular, to a semiconductor structure, a method of forming the same, a package structure, and a method of forming the same.
- SIP System In a Package
- Existing multifunctional SIP packaged chips include one or more chips attached to the surface of the substrate. With the high integration of packaged chips, the power of packaged chips is getting larger and larger, so chip heat dissipation has become a problem that must be considered in the packaging process. The heat generated by the chip itself, except for a small part of the heat dissipation through the bottom substrate and the pad, the main heat is dissipated through the surface of the chip. Therefore, the existing chip package design generally adds a heat dissipation cover on the chip, and the heat dissipation cover is pasted on the chip and the substrate through a heat conductive material to form a sealed package structure.
- the problem to be solved by the present invention is to provide a semiconductor structure, a method for forming the same, a package structure, and a method for forming the same, which effectively reduces heat inside and around the chip and prevents the chip from overheating.
- the present invention provides a semiconductor structure including: a substrate, the base a solder ball is disposed on the board; a chip disposed on the substrate, and the chip and the solder ball are disposed on a same side of the substrate, the chip having opposite first and second sides, the first One side is opposite to the substrate, and the second surface has a heat conducting layer.
- the heat conducting layer is located on the entire second surface.
- the second surface has a circuit layer; the heat conductive layer is located on a portion of the second surface and is electrically insulated from the circuit layer.
- the material of the heat conductive layer is a heat conductive resin material or a metal material.
- the material of the heat conductive layer is one or more of copper, gold, tungsten or tin.
- a distance between the top of the solder ball and the substrate is greater than a distance between a top of the heat conductive layer and the substrate.
- a distance between the top of the solder ball and the substrate is equal to a distance between a top of the heat conductive layer and the substrate.
- the semiconductor structure further includes: a plurality of spaced-apart conductive layers between the substrate and the first surface of the chip, the conductive layer is used to implement electricity between the chip and the substrate connection.
- the semiconductor structure further includes: an underfill filled between the substrate and the chip.
- the chip is an image sensing chip, and the chip has an image sensing area.
- the substrate has an opening penetrating the substrate, and the image sensing area is located above the opening;
- the semiconductor structure further includes: a transparent cover plate covering the opening, and the The transparent cover plate and the chip are respectively located on opposite sides of the substrate.
- the substrate is a light transmissive substrate.
- the semiconductor structure further includes: a sealant on the substrate and covering the sidewall of the chip.
- the sealant has thermal conductivity.
- the present invention also provides a package structure comprising: the foregoing semiconductor structure; a circuit board having a circuit board functional surface, the solder ball and the functional surface of the circuit board being electrically connected, and the heat conductive layer It is in contact with the functional surface of the circuit board.
- the functional surface of the circuit board has spaced apart functional electrical connection layers and a heat dissipation electrical connection layer; wherein the solder balls are electrically connected to the functional electrical connection layer, and the thermal conduction layer and the heat dissipation electrical connection layer Contact.
- the top of the functional electrical connection layer is flush with the top of the heat dissipation electrical connection layer.
- the material of the functional electrical connection layer is the same as the material of the heat dissipation electrical connection layer.
- the material of the heat dissipation electrical connection layer is one or more of gold, tungsten or solder paste.
- the present invention also provides a method of forming the foregoing semiconductor structure, comprising: providing a substrate on which a solder ball is disposed; providing a chip, the chip having opposite first and second faces, the second face Having a thermally conductive layer; the chip is disposed on the substrate, and the chip and the solder ball are disposed on a same side of the substrate, and the first surface is opposite to the substrate.
- the thermally conductive layer is formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
- a part of the second surface is disposed with the heat conductive layer; and the step of forming the heat conductive layer includes: forming a heat conductive film completely covering the second surface on the second surface; The heat conductive film forms the heat conductive layer on a part of the second surface.
- the chip is disposed on the substrate by a solder bonding process.
- a plurality of pads are formed on the substrate, and the pads are in one-to-one correspondence with the conductive layer; the pads are soldered to the conductive layer by a solder bonding process.
- the solder ball is formed on the substrate before the chip is disposed on the substrate; or, after the chip is disposed on the substrate, a substrate is formed on the substrate Said solder balls.
- the process step of forming the chip includes: providing a wafer; forming a heat conductive film on the wafer; cutting the wafer and the heat conductive film to form a plurality of spaced-apart chips And the heat conducting layer.
- the present invention also provides a method of forming the foregoing package structure, comprising: providing the foregoing semiconductor structure; providing a circuit board having a functional surface of the circuit board; and disposing the semiconductor structure on the functional surface of the circuit board such that the soldering The ball is electrically connected to the functional surface of the circuit board, and the heat conducting layer is in contact with the functional surface of the circuit board.
- the functional surface of the circuit board has spaced apart functional electrical connection layers and a heat dissipation electrical connection layer; wherein the solder balls are electrically connected to the functional electrical connection layer, and the thermal conduction layer and the heat dissipation electrical connection layer Contacting; using a solder bonding process, the solder balls are electrically connected to the functional electrical connection layer, and the heat conductive layer is bonded to the heat dissipation electrical connection layer.
- the material of the heat conductive layer is a metal material, and the material of the heat dissipation electrical connection layer is a solder paste; and the heat conductive layer is bonded to the heat dissipation electrical connection layer by a eutectic bonding process.
- the chip is disposed on the substrate, the first surface of the chip is opposite to the substrate, and the second surface of the chip has a heat conducting layer, and the chip can be used by the heat conducting layer
- the heat inside is transmitted to the external environment or components, thereby effectively reducing the heat inside the chip; in addition, the invention avoids the problem that the heat sink collects the heat generated by the chip, so that the heat generated by the chip can be effectively and timely Export to prevent the chip from overheating.
- the semiconductor structure provided by the present invention is small in size.
- the circuit board not only has the function of electrically connecting the substrate and the chip, but also has a heat generated inside the conductive chip due to the contact of the circuit board with the heat conductive layer. Function to prevent overheating inside the chip.
- the solder ball and the chip are disposed on the same side of the substrate, so the thickness of the package structure provided by the present invention is significantly reduced, and the package structure has a smaller volume.
- FIG. 1 is a schematic cross-sectional structural view of a package structure
- FIG. 2 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
- FIG. 3 to FIG. 5 are schematic cross-sectional structural views showing a process of forming a semiconductor structure according to an embodiment of the present invention.
- FIG. 6 is a schematic structural diagram of a package structure according to an embodiment of the present invention.
- FIG. 7 is a schematic structural diagram of a process of forming a package structure according to an embodiment of the present invention.
- the heat dissipation effect of the package structure provided by the prior art is limited, and the package structure is bulky.
- Figure 1 is a schematic cross-sectional structure of the package structure.
- the package structure includes a substrate 101 having opposite front and back surfaces, and a plurality of solder balls 102 disposed on a back surface of the substrate 101.
- the plurality of solder balls 102 may be BGAs (Ball Grid Array) a ball 103 disposed on a front surface of the substrate 101, the chip 103 having opposite functional and non-functional surfaces, wherein the functional surface is opposite to a front surface of the substrate 101, and the substrate 101 and the substrate An electrical connection is made between the chips 103 through the conductive layer 104; a heat dissipation cover 105 located on the front surface of the substrate 101 and surrounding the chip 103, the chip 103 is located in the heat dissipation cover 105, and the chip 103 is non-functional
- the heat sink cover 105 is next to the heat sink.
- the heat dissipation effect of the above package structure is poor, and the reason for the analysis is mainly that since the chip 103 is surrounded by the heat dissipation cover 105, the chip 103 is in a sealed environment; the heat dissipation cover 105 not only has a heat dissipation effect, The heat dissipation cover 105 also has the function of collecting the heat generated by the chip 103. The heat that is not transmitted to the outside by the heat dissipation cover 105 is concentrated in the sealed environment surrounded by the heat dissipation cover 105, resulting in a high temperature around the chip 103. , affect the performance of the chip.
- the thickness of the package structure is: the sum of the thickness of the BAG ball, the thickness of the substrate 101, and the height of the heat dissipation cover 105, and the height of the heat dissipation cover 105 is greater than the thickness of the chip 103, so the above The thickness of the package structure is thick.
- the heat dissipation cover 105 It is disposed on the substrate 101, so the substrate 101 also needs to reserve a space position for the heat dissipation cover 105. Therefore, the package structure provided above has a large volume, which is disadvantageous for the miniaturization of the chip and the miniaturization toward miniaturization.
- the present invention provides a semiconductor structure that timely and effectively transfers heat generated by the chip, prevents excessive temperature inside and around the chip, ensures efficient operation of the chip, and reduces the volume of the semiconductor structure.
- FIG. 2 is a schematic view showing the structure of a semiconductor structure provided by the embodiment.
- the semiconductor structure includes:
- the substrate 201 is provided with solder balls 202;
- the chip 203 has opposite first faces (not labeled) and second A face (not shown), the first face is opposite the substrate 201, and the second face has a thermally conductive layer 204.
- the substrate 201 is used to fix the chip 203 and electrically connect the chip 203 with other devices or circuits.
- the substrate 201 is a rigid substrate or a flexible substrate; the substrate 201 may also be a transparent substrate, such as an inorganic glass substrate, an organic glass substrate or a filter glass substrate.
- the substrate 201 is a rigid substrate
- the rigid substrate is a PCB substrate, a glass substrate, a metal substrate, a semiconductor substrate, or a polymer substrate.
- the substrate 201 may further have a plurality of pads (not shown) thereon, and the pads and the solder balls 202 are located on the same side of the substrate 201.
- the pads are for electrical connection with the chip 203.
- the first surface of the chip 203 has a plurality of mutually discrete conductive layers 205, that is, the conductive layers 205 are spaced apart, and the pads are used for electrical connection with the conductive layer 205.
- the location and number of pads can be determined based on the number and location of conductive layers 205 in chip 203.
- the substrate 201 may further have a circuit layer (not shown), and the chip 203 is electrically connected to the circuit layer.
- the cross-sectional shape of the substrate 201 is a square, a circle, a triangle, a regular polygon, or an irregular shape in a direction parallel to the surface of the substrate 201.
- the cross-sectional shape of the substrate 201 is a square.
- the solder balls 202 are used to electrically connect the substrate 201 and other devices or external circuits. For example, electrical connection between the substrate 201 and the circuit board can be achieved by the solder balls 202.
- the cross-sectional shape of the solder ball 202 is spherical. In other embodiments, the cross-sectional shape of the solder ball may also be square.
- solder balls 202 are distributed on the substrate 201 on the periphery of the chip 203, and the solder balls 202 are symmetrically distributed on the substrate 201.
- the chip 203 is a functional chip, such as an image sensing chip.
- the chip 203 and the solder ball 202 are disposed on the same surface of the substrate 201.
- the chip 203 is located in the area of the substrate 201 surrounded by the solder ball 202.
- the chip 203 when the chip 203 is an image sensing chip, the chip 203 has an image sensing area (not shown).
- the substrate 201 has an opening penetrating through the substrate 201 (not shown). And the image sensing area is located above the opening, so that external light can be transmitted to the image sensing area via the opening.
- the semiconductor structure further includes: a transparent cover plate covering the opening, and the transparent cover plate and the chip 203 They are respectively located on opposite sides of the substrate 201.
- the substrate 201 may also be a transparent substrate, and the corresponding substrate 201 does not need to be disposed through the substrate. The opening of 201.
- the first surface of the chip 203 is opposite to the substrate 201, and the first surface of the chip 203 is fixed to the substrate 201.
- the semiconductor structure further includes: a plurality of separate conductive layers 205 between the substrate 202 and the first side of the chip 203, the conductive layer 205 is used to achieve electrical connection between the chip 203 and the substrate 201, and through the conductive The layer 205 fixes the chip 203 and the substrate 201 to each other.
- the position and number of the conductive layer 205 are determined according to the position and number of electrical connections that need to be made on the first side of the chip 203.
- the material of the conductive layer 205 is one or more of copper, aluminum, tungsten or tin. In this embodiment, the material of the conductive layer 205 is copper.
- the second surface of the chip 203 has a heat conductive layer 204.
- the heat conducting layer 204 can conduct heat inside the chip 203 to the external environment or other devices, so that the heat inside the chip 203 is reduced, and the chip 203 is prevented from being overheated. The problem.
- the material of the heat conductive layer 204 is a heat conductive resin material or a metal material.
- the material of the heat conductive layer 204 is a metal material, and the material of the heat conductive layer 204 is one or more of copper, tungsten or tin.
- the thickness of the heat conducting layer 204 should not be too thin, and should not be too thick. If the thickness of the heat conducting layer 204 is too thin, the heat conducting layer 204 has a limited heat conduction capability, and the heat conducting layer 204 is susceptible to deformation under the heat generated by the chip 203; if the thickness of the heat conducting layer 204 is excessive If the thickness is thick, the overall thickness of the semiconductor structure is also relatively thick, which is disadvantageous for satisfying the development trend of miniaturization and miniaturization of the semiconductor structure.
- the heat conductive layer 204 has a thickness of 3 micrometers to 8 micrometers, for example, 3 micrometers, 5 micrometers, and 8 micrometers.
- the heat conducting layer 204 is located on the entire second surface of the chip 203. Because the area of the heat conducting layer 204 is large, the heat conducting capability of the heat conducting layer 204 is strong, so that the heat of the chip 203 is highly extracted, effectively avoiding the problem of overheating of the chip 203, and ensuring that the chip 203 is stable and reliable. work.
- the thermal conductive layer may also be located in the second part of the chip in consideration of circuit layout on the second surface of the chip. And electrically insulated from the circuit layer to avoid the heat conductive layer and the chip Unnecessary electrical connections occur between them.
- the material of the heat conductive layer may also be a heat conductive resin material. Since the heat conductive resin material is an insulating material, unnecessary occurrence of unnecessary heat conduction between the heat conductive layer and the chip is avoided. The problem of electrical connection.
- the heat conducting layer 204 has limited ability to conduct heat inside the chip 203 to the external environment. When the heat conducting layer 204 is bonded to other components that absorb heat, the heat conducting layer 204 conducts heat to In the component, the energy of the heat conduction layer 204 to conduct heat inside the chip 203 is significantly improved, and the temperature around the chip 203 is effectively reduced.
- the component is also a component that is electrically connected to the solder ball 202, so that the chip 203, the substrate 201 and the component are electrically connected through the solder ball 202; therefore, the semiconductor structure is further improved.
- the electrical connection between the semiconductor structure and the component can be realized, and a more complicated package structure can be formed.
- the component can be a circuit board.
- the heat conducting layer 204 should be in contact with the circuit board, and the solder balls 202 and the circuit board are electrically connected. In the process of electrically connecting the solder ball 202 and the circuit board, the thickness of the solder ball 202 may be reduced; in order to ensure that the solder ball 202 is electrically connected to the circuit board, The heat conducting layer 204 is in contact with the circuit board, and a distance L1 between the top of the solder ball 202 and the substrate 201 is greater than or equal to a distance L2 between the top of the heat conductive layer 204 and the substrate 201.
- a distance L1 between the top of the solder ball 202 and the substrate 201 is greater than a distance L2 between the top of the heat conductive layer 204 and the substrate 201. If the distance (L1-L2) between the top of the solder ball 202 and the top of the heat conductive layer 204 is too large, when the solder ball 202 is electrically connected to the circuit board, the heat conductive layer 204 is not connected to the circuit board. Contact, therefore, the distance between the top of the solder ball 202 and the top of the thermally conductive layer 204 should not be too large. In this embodiment, the distance between the top of the solder ball 202 and the top of the heat conductive layer 204 may satisfy that the heat conductive layer 204 can be eutectic bonded to the heat dissipation electrical connection layer in other components.
- the thickness of the solder ball 202 can be adjusted according to the thickness of the chip 203, the thickness of the conductive layer 205, and the thickness of the heat conductive layer 204, so that the heat conductive layer 204 can be electrically connected to other components.
- the layers achieve eutectic bonding.
- the conductive layer 205 has a thickness of 10 micrometers to 20 micrometers
- the chip 203 has a thickness of 150 micrometers
- the thermally conductive layer 204 has a thickness of 5 micrometers
- the solder balls 202 have a thickness of 200 micrometers. .
- the distance between the top of the solder ball and the substrate may also be equal to the distance between the top of the thermally conductive layer and the substrate.
- the distance between the top of the solder ball and the substrate may be smaller than the distance between the top of the heat conductive layer and the substrate. The solder ball is ensured to be electrically connected to the circuit board, and the heat conductive layer is in contact with the circuit board.
- the semiconductor structure may further include: an under-fill filled between the substrate 201 and the chip 203.
- the underfill may have thermal conductivity, so the underfill can not only improve the stability between the chip 203 and the substrate 201, but also generate the inside of the chip 203 because the underfill has a heat dissipation function. The heat can be transferred to the external environment via the underfill, thereby reducing the heat accumulated inside the chip 203 and avoiding the problem of overheating of the chip 203.
- the underfill may not be disposed in the semiconductor structure, and in order to improve the chip 203 and
- the bonding property between the substrates 201 further includes: a sealant (not shown) on the substrate 201 and covering the sidewalls of the chip 203. Also, the sealant has thermal conductivity, so that the sealant can not only improve the sealing performance of the chip 203, but also facilitate heat dissipation.
- the chip 203 is disposed on the substrate 201, the first surface of the chip 203 is opposite to the substrate 201, and the second surface of the chip 203 has a heat conductive layer 204 through the heat conduction.
- the layer 204 can conduct heat inside the chip 203 to the external environment or components, thereby effectively reducing the heat inside the chip 203; in addition, the embodiment avoids the problem that the heat sink collects the heat generated by the chip 203, so that The heat generated by the chip 203 can be efficiently and timely released to prevent the chip 203 from overheating.
- the chip 203 and the solder ball 202 are disposed on the same surface of the substrate 201, it is not necessary to set a large volume.
- the heat shield, so the semiconductor structure provided by the embodiment is small in size.
- the present invention also provides a method of forming the above semiconductor structure, comprising: providing a substrate on which a solder ball is disposed; providing a chip having opposite first and second faces, the second face Having a thermally conductive layer; the chip is disposed on the substrate, and the chip and the solder ball are disposed on a same side of the substrate, and the first surface is opposite to the substrate.
- the semiconductor structure formed by the invention has good heat dissipation effect on the chip, and the semiconductor structure has a small volume.
- FIG. 3 to FIG. 5 are schematic diagrams showing the structure of a semiconductor structure forming process according to an embodiment of the present invention.
- a substrate 201 is provided on which a solder ball 202 is disposed.
- the number and position of the solder balls 202 can be determined according to the substrate 201 and the subsequently provided chip 203.
- the solder balls 202 are symmetrically disposed on the substrate 201 such that the subsequently provided chips are located in the area surrounded by the solder balls 202.
- the solder ball 202 has a spherical shape in cross section, and a solder ball 202 is formed on the substrate 201 by a ball bonding process.
- the solder balls may also be formed using a screen printing process and a reflow process.
- the solder ball may be formed on the substrate after the chip is subsequently disposed on the substrate.
- a chip 203 is provided having opposing first and second faces, the second face having a thermally conductive layer 204.
- the material of the heat conductive layer 204 is a heat conductive resin material or a metal material.
- the material of the heat conductive layer 204 is a metal material, such as one or more of copper, gold, tungsten or tin.
- the heat conducting layer 204 is located on the entire second surface of the chip 203.
- the thermally conductive layer 204 may be formed using a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
- the thermally conductive layer may also be located on a portion of the second side of the chip; the step of forming the thermally conductive layer includes: forming a thermally conductive film over the entire second side of the chip; The heat conductive film forms a heat conductive layer on the second surface of the chip portion.
- a conductive layer 205 is also formed on the first surface of the chip 203, and the conductive layer 205 is used to realize electrical connection between the chip 203 and the substrate 201.
- the conductive layer 205 is formed by a screen printing process. In other embodiments, the conductive layer may also be formed using a deposition process and an etching process.
- the process step of forming the chip 203 includes: providing a wafer; forming a heat conductive film on the wafer, and forming a heat conductive film on the wafer by using a sputtering process; The wafer and the heat conductive film form a plurality of discrete chips 203 and the heat conductive layer 204.
- the chip 203 is disposed on the substrate 201, and the chip 203 and the solder ball 202 are disposed on the same surface of the upper substrate 201, and the first surface is opposite to the substrate 201. .
- the chip 203 is placed on the substrate 201 by a solder bonding process, and the chip 203 is fixedly bonded to the substrate 201.
- the substrate 201 is connected to the conductive layer 205 such that the chip 203 is disposed on the substrate 201.
- Pads (not shown) are formed on the substrate 201, and each pad corresponds to a discrete conductive layer 205. The pads are solder bonded to the conductive layer 205 using a solder bonding process.
- the solder bonding process is eutectic bonding, ultrasonic hot pressing, hot press welding, ultrasonic pressure welding, or the like.
- the solder bonding process is ultrasonic hot pressing; when the material of the conductive layer 205 is Au, The material of the pad on the substrate 201 is Sn, and the solder bonding process is a eutectic bonding method.
- the chip 203 is located in a region surrounded by the solder ball 202.
- the top of the solder ball 202 and the top of the heat conductive layer 204 reference may be made to the corresponding description in the foregoing embodiments, and details are not described herein again.
- a step of forming a heat dissipating gel covering the sidewall of the chip 203 on the substrate 201 may also be included.
- the heat dissipating glue may be formed by a dispensing process or a plastic sealing process.
- the heat dissipating adhesive not only functions to further fix the chip 203 and the substrate 201, but also functions as a heat sink to further reduce heat inside the chip 203.
- FIG. 6 shows a schematic structural view of a package structure provided by an embodiment of the present invention.
- the package structure includes:
- the semiconductor structure provided by the foregoing embodiment includes: a substrate 201 on which a solder ball 202 is disposed; a chip 203 disposed on the substrate 201, and the chip 203 and the solder ball 202 are disposed on the substrate On the same side of 201, the chip 203 has opposite first and second faces, the first face is opposite to the substrate 201, the second face has a heat conducting layer 204;
- the circuit board 301 has a functional surface, and the solder ball 202 is electrically connected to the functional surface of the circuit board 301, and the heat conductive layer 204 is in contact with the functional surface of the circuit board 301.
- the circuit board 301 is a PCB board.
- the function board 301 has a functional electrical connection layer 311 and a heat dissipation electrical connection layer 312 which are separated from each other.
- the functional electrical connection layer 311 and the heat dissipation electrical connection layer 312 are spaced apart from each other on the functional surface of the circuit board 301.
- the solder ball 202 is electrically connected to the functional electrical connection layer 311, and the heat conductive layer 204 is in contact with the heat dissipation electrical connection layer 312.
- the solder ball 202 realizes electrical connection between the circuit board 301 and the substrate 201 and the chip 203 through the functional electrical connection layer 311.
- the heat conducting layer 204 is in contact with the heat dissipation electrical connection layer 312
- heat generated inside the chip 203 is transferred to the heat dissipation electrical connection layer 312 via the heat conduction layer 204, so that the chip 203 is internally generated.
- the heat can be dissipated via the circuit board 301.
- the heat dissipation effect of the circuit board 301 is good, so that the heat inside the chip 203 is conducted in time and effectively, and the chip 203 is effectively operated.
- the top of the functional electrical connection layer 311 is flush with the top of the heat dissipation electrical connection layer 312.
- the top of the functional electrical connection layer may also be lower than the top of the heat dissipation electrical connection layer, or the top of the functional electrical connection layer is flush with the top of the heat dissipation electrical connection layer to ensure the solder ball
- the electrical connection layer is electrically connected to the functional electrical connection layer, and the thermal conductive layer is in contact with the heat dissipation electrical connection.
- the heat conductive layer 204 and the heat dissipation electrical connection layer 312 are bonded to each other.
- the material of the heat dissipation electrical connection layer 312 is one or more of gold, tungsten or solder paste.
- the material of the heat dissipation electrical connection layer 312 is solder paste, and the heat conduction layer 204 is in contact with the heat dissipation electrical connection layer 312 by eutectic bonding.
- the material of the functional electrical connection layer 311 is the same as the material of the heat dissipation electrical connection layer 312. In other embodiments, the material of the functional electrical connection layer may also be different from the material of the heat dissipation electrical connection layer.
- the circuit board 301 not only has the function of electrically connecting the substrate 201 and the chip 203, but also has the function of generating heat inside the conductive chip 203 to prevent overheating of the chip 203.
- the package structure has a smaller volume.
- the embodiment of the present invention further provides a method for forming the above package structure, comprising: providing the foregoing semiconductor structure; providing a circuit board having a functional surface; and disposing the semiconductor structure on the functional surface of the circuit board, so that the soldering The ball is electrically connected to the functional surface of the circuit board, and the thermally conductive layer is in contact with the function of the circuit board.
- the circuit board can realize the electrical connection with the substrate and the chip, and also can contact the heat conductive layer to timely and effectively transfer the heat generated by the chip, thereby improving the heat dissipation effect of the package structure. And reduce the volume of the package structure.
- FIG. 7 is a schematic structural diagram of a process of forming a package structure according to an embodiment of the present invention.
- the semiconductor structure includes a substrate 201 on which a solder ball 202 is disposed, a chip 203 disposed on the substrate 201, and the chip 203 and the solder ball 202 are disposed on the same side of the substrate 201.
- the chip 203 has opposite first and second faces, the first face being opposite to the substrate 201, and the second face having a heat conductive layer 204.
- the first surface and the substrate 201 further have a plurality of conductive layers 205 separated from each other.
- circuit board 301 having a functional surface is provided.
- the circuit board 301 is a PCB board.
- the functional surface is a surface that is subsequently bonded to the semiconductor structure.
- the circuit board 301 has functional electrical connection layers 311 and heat dissipation electrical connection layers 312 separated from each other.
- the functional electrical connection layer 311 and the heat dissipation electrical connection layer 312 may be formed on the circuit board 301 by a printing process.
- the top of the functional electrical connection layer 311 is flush with the top of the heat dissipation electrical connection layer 312.
- the top of the functional electrical connection layer may also be lower than the top of the heat dissipation electrical connection layer, or the top of the functional electrical connection layer may be flush with the top of the heat dissipation electrical connection layer.
- the material of the heat dissipation electrical connection layer 312 is one or more of tin, gold or tungsten. In this embodiment, the material of the heat dissipation electrical connection layer 312 is tin.
- the material of the heat dissipation electrical connection layer 312 is the same as the material of the functional electrical connection layer 311.
- the semiconductor structure is disposed on a functional surface of the circuit board 301 such that the solder ball 202 is electrically connected to a functional surface of the circuit board 301, and the heat conductive layer 204 and the circuit board are The 301 functional surface is in contact.
- solder ball 202 is bonded to the functional electrical connection layer 311 by a solder bonding process such that the heat conductive layer 204 is bonded to the heat dissipation electrical connection layer 312.
- the material of the heat dissipation electrical connection layer 312 is a solder paste, and the material of the heat conduction layer 204 is a metal material; the eutectic bonding process is used to make the heat conduction layer 204 and the heat dissipation electrical connection layer 312 Bond.
- the bonding interface between the heat conducting layer 204 and the heat dissipating electrical connection layer 312 is such that the heat conducting layer 204 and the heat dissipating electrical connection layer 312 are eutectic bonded. Has excellent thermal conductivity.
- the thermal conductive layer may be bonded to the functional surface of the circuit board by ultrasonic hot pressing, thermocompression bonding or ultrasonic pressure welding, etc., so that the thermal conductive layer and the thermal conductive layer The heat-dissipating electrical connection layers are in contact.
- the top of the functional electrical connection layer 311 is flush with the top of the heat dissipation electrical connection layer 312, and the top of the solder ball 202 is higher than the top of the thermal conductive layer 204.
- the thickness of the solder ball 202 may be reduced, so when the solder ball 202 and the function
- the electrical connection layer 311 is electrically connected, the heat conduction layer 204 and the heat dissipation electrical connection layer 312 can be bonded to each other, that is, the heat conduction layer 204 is in contact with the functional surface of the circuit board 301.
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Abstract
A semiconductor structure and a forming method therefor, and a packaging structure and a forming method therefor. The semiconductor structure comprises a substrate (201) and a chip (203). Welding balls (202) are disposed on the substrate (201). The chip (203) is disposed on the substrate (201), and the chip (203) and the welding balls (202) are disposed on a same surface of the substrate (201). The chip (203) is provided with a first surface and a second surface that are opposite to each other. The first surface is opposite to the substrate (201), and the second surface is provided with a heat conducting layer (204). Heat dissipation effects of the semiconductor structure and the packaging structure are improved, and temperatures in and around the chip are prevented from being excessively high, thereby ensuring reliable and effective operation of the chip.
Description
本申请要求于2016年11月24日提交中国专利局、申请号为201611045346.9、发明名称为“半导体结构及其形成方法、封装结构及其形成方法”的中国专利申请的优先权,和于2016年11月24日提交中国专利局、申请号为201621266619.8、发明名称为“半导体结构以及封装结构”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。This application claims priority to Chinese Patent Application No. 201611045346.9, entitled "Semiconductor Structure and Its Forming Method, Package Structure and Method of Forming It", filed on November 24, 2016, and in 2016 Priority is filed on Nov. 24, the entire disclosure of which is hereby incorporated by reference in its entirety in its entirety in the the the the the the the the the the
本发明涉及封装技术领域,特别涉及一种半导体结构及其形成方法、封装结构及其形成方法。The present invention relates to the field of packaging technologies, and in particular, to a semiconductor structure, a method of forming the same, a package structure, and a method of forming the same.
随着无线通信、汽车电子和其他消费类电子产品的快速发展,微电子封装技术向着多功能、小型化、便携式、高速度、低功耗和高可靠性的方向发展。其中,***级封装(SIP,System In a Package)是一种新型的封装技术,能够有效减小封装面积。With the rapid development of wireless communications, automotive electronics and other consumer electronics, microelectronic packaging technology is moving toward versatility, miniaturization, portability, high speed, low power consumption and high reliability. Among them, System In a Package (SIP) is a new type of packaging technology that can effectively reduce the package area.
现有的多功能SIP封装芯片包括在基板的表面贴合一个或多个芯片。随着封装芯片的高度集成,封装芯片的功率越来越大,因此芯片散热成为封装过程中一个必须考虑的问题。芯片本身产生的热量,除了少部分通过底部基板以及焊垫向外散热外,其主要热量是通过芯片表面进行散热的。因此,现有的芯片封装设计一般在芯片上加散热罩,将散热罩通过导热材料粘贴在芯片和基板上,形成密封封装结构。Existing multifunctional SIP packaged chips include one or more chips attached to the surface of the substrate. With the high integration of packaged chips, the power of packaged chips is getting larger and larger, so chip heat dissipation has become a problem that must be considered in the packaging process. The heat generated by the chip itself, except for a small part of the heat dissipation through the bottom substrate and the pad, the main heat is dissipated through the surface of the chip. Therefore, the existing chip package design generally adds a heat dissipation cover on the chip, and the heat dissipation cover is pasted on the chip and the substrate through a heat conductive material to form a sealed package structure.
然而,现有技术提供的封装结构的散热效果有待提高,且具有散热功能的封装结构体积大。However, the heat dissipation effect of the package structure provided by the prior art needs to be improved, and the package structure having the heat dissipation function is bulky.
发明内容Summary of the invention
本发明解决的问题是提供一种半导体结构及其形成方法、封装结构及其形成方法,有效的降低芯片内部以及周围热量,防止芯片过热。The problem to be solved by the present invention is to provide a semiconductor structure, a method for forming the same, a package structure, and a method for forming the same, which effectively reduces heat inside and around the chip and prevents the chip from overheating.
为解决上述问题,本发明提供一种半导体结构,包括:基板,所述基
板上设置有焊球;设置在所述基板上的芯片,且所述芯片与所述焊球设置在基板的同一面上,所述芯片具有相对的第一面与第二面,所述第一面与所述基板相对,所述第二面上具有导热层。In order to solve the above problems, the present invention provides a semiconductor structure including: a substrate, the base
a solder ball is disposed on the board; a chip disposed on the substrate, and the chip and the solder ball are disposed on a same side of the substrate, the chip having opposite first and second sides, the first One side is opposite to the substrate, and the second surface has a heat conducting layer.
可选的,所述导热层位于整个所述第二面上。Optionally, the heat conducting layer is located on the entire second surface.
可选的,所述第二面具有线路层;所述导热层位于部分所述第二面上,且与所述线路层之间电绝缘。Optionally, the second surface has a circuit layer; the heat conductive layer is located on a portion of the second surface and is electrically insulated from the circuit layer.
可选的,所述导热层的材料为导热树脂材料或者金属材料。Optionally, the material of the heat conductive layer is a heat conductive resin material or a metal material.
可选的,所述导热层的材料为铜、金、钨或锡中的一种或多种。Optionally, the material of the heat conductive layer is one or more of copper, gold, tungsten or tin.
可选的,所述焊球顶部与所述基板之间的距离大于所述导热层顶部与所述基板之间的距离。Optionally, a distance between the top of the solder ball and the substrate is greater than a distance between a top of the heat conductive layer and the substrate.
可选的,所述焊球顶部与所述基板之间的距离等于所述导热层顶部与所述基板之间的距离。Optionally, a distance between the top of the solder ball and the substrate is equal to a distance between a top of the heat conductive layer and the substrate.
可选的,所述半导体结构还包括:位于所述基板与所述芯片第一面之间的若干间隔分布的导电层,所述导电层用于实现所述芯片与所述基板之间的电连接。Optionally, the semiconductor structure further includes: a plurality of spaced-apart conductive layers between the substrate and the first surface of the chip, the conductive layer is used to implement electricity between the chip and the substrate connection.
可选的,所述半导体结构还包括:填充于所述基板与所述芯片之间的底部填充胶。Optionally, the semiconductor structure further includes: an underfill filled between the substrate and the chip.
可选的,所述芯片为影像传感芯片,且所述芯片具有影像感应区。Optionally, the chip is an image sensing chip, and the chip has an image sensing area.
可选的,所述基板内具有贯穿所述基板的开口,且所述影像感应区位于所述开口上方;所述半导体结构还包括:覆盖在所述开口上的透光盖板,且所述透光盖板与所述芯片分别位于所述基板相对的两侧。Optionally, the substrate has an opening penetrating the substrate, and the image sensing area is located above the opening; the semiconductor structure further includes: a transparent cover plate covering the opening, and the The transparent cover plate and the chip are respectively located on opposite sides of the substrate.
可选的,所述基板为透光基板。Optionally, the substrate is a light transmissive substrate.
可选的,所述半导体结构还包括:位于所述基板上且覆盖所述芯片侧壁的密封胶。Optionally, the semiconductor structure further includes: a sealant on the substrate and covering the sidewall of the chip.
可选的,所述密封胶具有导热性能。
Optionally, the sealant has thermal conductivity.
本发明还提供一种封装结构,包括:前述的半导体结构;电路板,所述电路板具有电路板功能面,所述焊球与所述电路板功能面之间电连接,且所述导热层与所述电路板功能面相接触。The present invention also provides a package structure comprising: the foregoing semiconductor structure; a circuit board having a circuit board functional surface, the solder ball and the functional surface of the circuit board being electrically connected, and the heat conductive layer It is in contact with the functional surface of the circuit board.
可选的,所述电路板功能面上具有间隔设置的功能电连接层以及散热电连接层;其中,所述焊球与所述功能电连接层电连接,所述导热层与散热电连接层相接触。Optionally, the functional surface of the circuit board has spaced apart functional electrical connection layers and a heat dissipation electrical connection layer; wherein the solder balls are electrically connected to the functional electrical connection layer, and the thermal conduction layer and the heat dissipation electrical connection layer Contact.
可选的,所述功能电连接层顶部与所述散热电连接层顶部齐平。Optionally, the top of the functional electrical connection layer is flush with the top of the heat dissipation electrical connection layer.
可选的,所述功能电连接层的材料与所述散热电连接层的材料相同。Optionally, the material of the functional electrical connection layer is the same as the material of the heat dissipation electrical connection layer.
可选的,所述散热电连接层的材料为金、钨或锡膏中的一种或多种。Optionally, the material of the heat dissipation electrical connection layer is one or more of gold, tungsten or solder paste.
本发明还提供一种前述半导体结构的形成方法,包括:提供基板,所述基板上设置有焊球;提供芯片,所述芯片具有相对的第一面与第二面,所述第二面上具有导热层;将所述芯片设置在所述基板上,且所述芯片与所述焊球设置在基板的同一面上,所述第一面与所述基板相对。The present invention also provides a method of forming the foregoing semiconductor structure, comprising: providing a substrate on which a solder ball is disposed; providing a chip, the chip having opposite first and second faces, the second face Having a thermally conductive layer; the chip is disposed on the substrate, and the chip and the solder ball are disposed on a same side of the substrate, and the first surface is opposite to the substrate.
可选的,采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺,形成所述导热层。Optionally, the thermally conductive layer is formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
可选的,部分所述第二面设置有所述导热层;形成所述导热层的工艺步骤包括:在所述第二面上形成完全覆盖所述第二面的导热膜;图形化所述导热膜,在部分所述第二面上形成所述导热层。Optionally, a part of the second surface is disposed with the heat conductive layer; and the step of forming the heat conductive layer includes: forming a heat conductive film completely covering the second surface on the second surface; The heat conductive film forms the heat conductive layer on a part of the second surface.
可选的,通过焊接键合工艺,将所述芯片设置在所述基板上。Optionally, the chip is disposed on the substrate by a solder bonding process.
可选的,所述基板上形成有若干焊盘,且所述焊盘与所述导电层一一对应;采用焊接键合工艺,将所述焊盘与所述导电层焊接结合。Optionally, a plurality of pads are formed on the substrate, and the pads are in one-to-one correspondence with the conductive layer; the pads are soldered to the conductive layer by a solder bonding process.
可选的,在将所述芯片设置在所述基板上之前,在所述基板上形成所述焊球;或者,在将所述芯片设置在所述基板上之后,在所述基板上形成所述焊球。Optionally, the solder ball is formed on the substrate before the chip is disposed on the substrate; or, after the chip is disposed on the substrate, a substrate is formed on the substrate Said solder balls.
可选的,形成所述芯片的工艺步骤包括:提供晶圆;在所述晶圆上形成导热膜;切割所述晶圆以及导热膜,形成若干个间隔分布的所述芯片以
及所述导热层。Optionally, the process step of forming the chip includes: providing a wafer; forming a heat conductive film on the wafer; cutting the wafer and the heat conductive film to form a plurality of spaced-apart chips
And the heat conducting layer.
本发明还提供一种前述封装结构的形成方法,包括:提供前述的半导体结构;提供具有电路板功能面的电路板;将所述半导体结构设置在所述电路板功能面上,使得所述焊球与所述电路板功能面之间电连接,且所述导热层与所述电路板功能面相接触。The present invention also provides a method of forming the foregoing package structure, comprising: providing the foregoing semiconductor structure; providing a circuit board having a functional surface of the circuit board; and disposing the semiconductor structure on the functional surface of the circuit board such that the soldering The ball is electrically connected to the functional surface of the circuit board, and the heat conducting layer is in contact with the functional surface of the circuit board.
可选的,所述电路板功能面上具有间隔设置的功能电连接层以及散热电连接层;其中,所述焊球与所述功能电连接层电连接,所述导热层与散热电连接层相接触;采用焊接键合工艺,使得所述焊球与所述功能电连接层电连接,且所述导热层与所述散热电连接层相键合。Optionally, the functional surface of the circuit board has spaced apart functional electrical connection layers and a heat dissipation electrical connection layer; wherein the solder balls are electrically connected to the functional electrical connection layer, and the thermal conduction layer and the heat dissipation electrical connection layer Contacting; using a solder bonding process, the solder balls are electrically connected to the functional electrical connection layer, and the heat conductive layer is bonded to the heat dissipation electrical connection layer.
可选的,所述导热层的材料为金属材料,所述散热电连接层的材料为锡膏;采用共晶结合工艺,使得所述导热层与所述散热电连接层相键合。Optionally, the material of the heat conductive layer is a metal material, and the material of the heat dissipation electrical connection layer is a solder paste; and the heat conductive layer is bonded to the heat dissipation electrical connection layer by a eutectic bonding process.
与现有技术相比,本发明的技术方案具有以下优点:Compared with the prior art, the technical solution of the present invention has the following advantages:
本发明提供的半导体结构的技术方案中,所述芯片设置在所述基板上,所述芯片第一面与基板相对,所述芯片第二面上具有导热层,通过所述导热层可以将芯片内部的热量传导至外界环境或部件中,从而有效的降低了芯片内部热量;此外,本发明避免了散热罩将所述芯片产生的热量聚集起来的问题,使得芯片产生的热量可以及时有效的被导出,防止芯片过热的问题。同时由于芯片与焊球设置在所述基板的同一面上,且无需设置占据体积较大的散热罩,因此本发明提供的半导体结构体积小。In the technical solution of the semiconductor structure provided by the present invention, the chip is disposed on the substrate, the first surface of the chip is opposite to the substrate, and the second surface of the chip has a heat conducting layer, and the chip can be used by the heat conducting layer The heat inside is transmitted to the external environment or components, thereby effectively reducing the heat inside the chip; in addition, the invention avoids the problem that the heat sink collects the heat generated by the chip, so that the heat generated by the chip can be effectively and timely Export to prevent the chip from overheating. At the same time, since the chip and the solder ball are disposed on the same surface of the substrate, and it is not necessary to provide a heat dissipation cover that occupies a large volume, the semiconductor structure provided by the present invention is small in size.
本发明提供的封装结构的技术方案中,所述电路板不仅具有电连接所述基板以及芯片的功能,且由于电路板与导热层相接触,使得所述电路板还具有传导芯片内部产生热量的作用,防止芯片内部过热。此外,所述焊球与芯片设置在所述基板同一面上,因此本发明提供的封装结构的厚度明显减小,封装结构具有更小的体积。In the technical solution of the package structure provided by the present invention, the circuit board not only has the function of electrically connecting the substrate and the chip, but also has a heat generated inside the conductive chip due to the contact of the circuit board with the heat conductive layer. Function to prevent overheating inside the chip. In addition, the solder ball and the chip are disposed on the same side of the substrate, so the thickness of the package structure provided by the present invention is significantly reduced, and the package structure has a smaller volume.
图1为一种封装结构的剖面结构示意图;
1 is a schematic cross-sectional structural view of a package structure;
图2为本发明实施例提供的半导体结构的结构示意图;2 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention;
图3至图5为本发明实施例提供的半导体结构形成过程的剖面结构示意图;3 to FIG. 5 are schematic cross-sectional structural views showing a process of forming a semiconductor structure according to an embodiment of the present invention;
图6为本发明实施例提供的封装结构的结构示意图;FIG. 6 is a schematic structural diagram of a package structure according to an embodiment of the present invention;
图7为本发明实施例提供的封装结构形成过程的结构示意图。FIG. 7 is a schematic structural diagram of a process of forming a package structure according to an embodiment of the present invention.
根据背景技术,现有技术提供的封装结构的散热效果有限,且封装结构的体积大。According to the background art, the heat dissipation effect of the package structure provided by the prior art is limited, and the package structure is bulky.
现结合一种封装结构进行分析,图1为封装结构的剖面结构示意图。Now combined with a package structure for analysis, Figure 1 is a schematic cross-sectional structure of the package structure.
参考图1,所述封装结构包括:基板101,所述基板101具有相对的正面与背面,所述基板101背面上设置有若干焊球102,所述若干焊球102可以为BGA(Ball Grid Array)球;设置在所述基板101正面的芯片103,所述芯片103具有相对的功能面与非功能面,其中,所述功能面与所述基板101的正面相对,且所述基板101与所述芯片103之间通过导电层104实现电连接;位于所述基板101正面且包围所述芯片103的散热罩105,所述芯片103位于所述散热罩105内,且所述芯片103非功能面紧挨所述散热罩105。Referring to FIG. 1, the package structure includes a substrate 101 having opposite front and back surfaces, and a plurality of solder balls 102 disposed on a back surface of the substrate 101. The plurality of solder balls 102 may be BGAs (Ball Grid Array) a ball 103 disposed on a front surface of the substrate 101, the chip 103 having opposite functional and non-functional surfaces, wherein the functional surface is opposite to a front surface of the substrate 101, and the substrate 101 and the substrate An electrical connection is made between the chips 103 through the conductive layer 104; a heat dissipation cover 105 located on the front surface of the substrate 101 and surrounding the chip 103, the chip 103 is located in the heat dissipation cover 105, and the chip 103 is non-functional The heat sink cover 105 is next to the heat sink.
上述封装结构中,芯片103产生的部分热量经由散热罩105传递至外界中。然而,上述封装结构的散热效果差,分析其原因主要为:由于所述芯片103被所述散热罩105包围,因此所述芯片103处于密封环境中;所述散热罩105不仅具有散热的作用,所述散热罩105还具有聚集所述芯片103产生的热量的作用,未被散热罩105传递至外界的热量集中在所述散热罩105包围的密封环境中,造成芯片103周围具有较高的温度,影响芯片的工作性能。In the above package structure, part of the heat generated by the chip 103 is transmitted to the outside through the heat dissipation cover 105. However, the heat dissipation effect of the above package structure is poor, and the reason for the analysis is mainly that since the chip 103 is surrounded by the heat dissipation cover 105, the chip 103 is in a sealed environment; the heat dissipation cover 105 not only has a heat dissipation effect, The heat dissipation cover 105 also has the function of collecting the heat generated by the chip 103. The heat that is not transmitted to the outside by the heat dissipation cover 105 is concentrated in the sealed environment surrounded by the heat dissipation cover 105, resulting in a high temperature around the chip 103. , affect the performance of the chip.
此外,上述封装结构中,所述封装结构的厚度为:BAG球的厚度、基板101厚度以及散热罩105的高度之和,且所述散热罩105的高度大于所述芯片103的厚度,因此上述封装结构的厚度较厚。并且,所述散热罩105
设置在所述基板101上,因此所述基板101还需要为所述散热罩105预留空间位置。因此,上述提供的封装结构的体积较大,不利于芯片小型化、微型化向小型化微型化的趋势发展。In addition, in the above package structure, the thickness of the package structure is: the sum of the thickness of the BAG ball, the thickness of the substrate 101, and the height of the heat dissipation cover 105, and the height of the heat dissipation cover 105 is greater than the thickness of the chip 103, so the above The thickness of the package structure is thick. And, the heat dissipation cover 105
It is disposed on the substrate 101, so the substrate 101 also needs to reserve a space position for the heat dissipation cover 105. Therefore, the package structure provided above has a large volume, which is disadvantageous for the miniaturization of the chip and the miniaturization toward miniaturization.
为解决上述问题,本发明提供一种半导体结构,及时有效的将芯片产生的热量传递出去,防止芯片内部以及周围温度过高,保证芯片有效运行,且还降低了半导体结构的体积。In order to solve the above problems, the present invention provides a semiconductor structure that timely and effectively transfers heat generated by the chip, prevents excessive temperature inside and around the chip, ensures efficient operation of the chip, and reduces the volume of the semiconductor structure.
为使本发明的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。The above described objects, features, and advantages of the present invention will be more apparent from the aspects of the invention.
图2示出了本实施例提供的半导体结构的结构示意图。参考图2,所述半导体结构包括:FIG. 2 is a schematic view showing the structure of a semiconductor structure provided by the embodiment. Referring to FIG. 2, the semiconductor structure includes:
基板201,所述基板201上设置有焊球202;a substrate 201, the substrate 201 is provided with solder balls 202;
设置在所述基板201上方的芯片203,且所述芯片203与所述焊球202设置在所述基板201的同一面上,所述芯片203具有相对的第一面(未标示)与第二面(未标示),所述第一面与所述基板201相对,所述第二面上具有导热层204。a chip 203 disposed above the substrate 201, and the chip 203 and the solder ball 202 are disposed on the same side of the substrate 201. The chip 203 has opposite first faces (not labeled) and second A face (not shown), the first face is opposite the substrate 201, and the second face has a thermally conductive layer 204.
以下将结合附图对本实施例提供的半导体结构进行详细说明。The semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings.
所述基板201用于固定所述芯片203,并使所述芯片203与其他器件或者电路电连接。所述基板201为硬性基板或软性基板;所述基板201还可以为透光基板,例如为无机玻璃基板、有机玻璃基板或者滤光玻璃基板。The substrate 201 is used to fix the chip 203 and electrically connect the chip 203 with other devices or circuits. The substrate 201 is a rigid substrate or a flexible substrate; the substrate 201 may also be a transparent substrate, such as an inorganic glass substrate, an organic glass substrate or a filter glass substrate.
本实施例中,所述基板201为硬性基板,所述硬性基板为PCB基板、玻璃基板、金属基板、半导体基板或聚合物基板。In this embodiment, the substrate 201 is a rigid substrate, and the rigid substrate is a PCB substrate, a glass substrate, a metal substrate, a semiconductor substrate, or a polymer substrate.
所述基板201上还可以具有若干焊盘(未图示),且所述焊盘与所述焊球202位于基板201的同一面上。所述焊盘用于与芯片203电连接。具体地,所述芯片203的第一面上具有若干相互分立的导电层205,即各导电层205间隔分布,所述焊盘用于与所述导电层205电连接。所述焊盘的位置和数量可以根据芯片203中的导电层205的数量和位置确定。
The substrate 201 may further have a plurality of pads (not shown) thereon, and the pads and the solder balls 202 are located on the same side of the substrate 201. The pads are for electrical connection with the chip 203. Specifically, the first surface of the chip 203 has a plurality of mutually discrete conductive layers 205, that is, the conductive layers 205 are spaced apart, and the pads are used for electrical connection with the conductive layer 205. The location and number of pads can be determined based on the number and location of conductive layers 205 in chip 203.
所述基板201内还可以具有电路层(未图示),所述芯片203与所述电路层电连接。The substrate 201 may further have a circuit layer (not shown), and the chip 203 is electrically connected to the circuit layer.
在平行于所述基板201表面方向上,所述基板201的剖面形状为方形、圆形、三角形、规则多边形或者不规则形状。本实施例中,以所述基板201的剖面形状为方形为例。The cross-sectional shape of the substrate 201 is a square, a circle, a triangle, a regular polygon, or an irregular shape in a direction parallel to the surface of the substrate 201. In the present embodiment, the cross-sectional shape of the substrate 201 is a square.
所述焊球202用于电连接所述基板201以及其他器件或者外部电路,例如,通过所述焊球202可以实现所述基板201与电路板之间的电连接。The solder balls 202 are used to electrically connect the substrate 201 and other devices or external circuits. For example, electrical connection between the substrate 201 and the circuit board can be achieved by the solder balls 202.
本实施例中,所述焊球202的剖面形状为球状。在其他实施例中,所述焊球的剖面形状还可以为方形。In this embodiment, the cross-sectional shape of the solder ball 202 is spherical. In other embodiments, the cross-sectional shape of the solder ball may also be square.
为了节约空间,可以对所述焊球202位于基板201上的位置进行合理布局。本实施例中,所述焊球202分布在所述芯片203***的基板201上,且所述焊球202在所述基板201上对称分布。In order to save space, a reasonable layout of the position of the solder ball 202 on the substrate 201 can be made. In this embodiment, the solder balls 202 are distributed on the substrate 201 on the periphery of the chip 203, and the solder balls 202 are symmetrically distributed on the substrate 201.
所述芯片203为功能芯片,例如为影像传感芯片。且所述芯片203与所述焊球202设置在所述基板201的同一面上;本实施例中,所述芯片203位于所述焊球202包围的基板201区域内。The chip 203 is a functional chip, such as an image sensing chip. The chip 203 and the solder ball 202 are disposed on the same surface of the substrate 201. In this embodiment, the chip 203 is located in the area of the substrate 201 surrounded by the solder ball 202.
需要说明的是,所述芯片203为影像传感芯片时,所述芯片203具有影像感应区(未图示);相应的,所述基板201内具有贯穿所述基板201的开口(未图示),且所述影像感应区位于所述开口上方,使得外界光线可以经由所述开口传递至所述影像感应区内。并且,为了保护所述影像感应区,避免所述影像感应区受到污染,所述半导体结构还包括:覆盖在所述开口上的透光盖板,且所述透光盖板与所述芯片203分别位于所述基板201相对的两侧。It should be noted that when the chip 203 is an image sensing chip, the chip 203 has an image sensing area (not shown). Correspondingly, the substrate 201 has an opening penetrating through the substrate 201 (not shown). And the image sensing area is located above the opening, so that external light can be transmitted to the image sensing area via the opening. In addition, in order to protect the image sensing area from being contaminated, the semiconductor structure further includes: a transparent cover plate covering the opening, and the transparent cover plate and the chip 203 They are respectively located on opposite sides of the substrate 201.
还需要说明的是,所述芯片203为影像传感芯片,所述芯片203具有影像感应区时,所述基板201还可以为透光基板,相应的所述基板201内无需设置贯穿所述基板201的开口。It should be noted that, when the chip 203 is an image sensing chip, and the chip 203 has an image sensing area, the substrate 201 may also be a transparent substrate, and the corresponding substrate 201 does not need to be disposed through the substrate. The opening of 201.
所述芯片203的第一面与基板201相对,所述芯片203的第一面与所述基板201相固定。具体地,本实施例中,所述半导体结构还包括:位于
所述基板202与所述芯片203第一面之间的若干分离的导电层205,所述导电层205用于实现所述芯片203与所述基板201之间的电连接,且通过所述导电层205使所述芯片203与所述基板201之间相互固定。The first surface of the chip 203 is opposite to the substrate 201, and the first surface of the chip 203 is fixed to the substrate 201. Specifically, in this embodiment, the semiconductor structure further includes:
a plurality of separate conductive layers 205 between the substrate 202 and the first side of the chip 203, the conductive layer 205 is used to achieve electrical connection between the chip 203 and the substrate 201, and through the conductive The layer 205 fixes the chip 203 and the substrate 201 to each other.
根据所述芯片203第一面上需要进行电连接的位置和数量,确定所述导电层205的位置和数量。所述导电层205的材料为铜、铝、钨或锡中的一种或多种。本实施例中,所述导电层205的材料为铜。The position and number of the conductive layer 205 are determined according to the position and number of electrical connections that need to be made on the first side of the chip 203. The material of the conductive layer 205 is one or more of copper, aluminum, tungsten or tin. In this embodiment, the material of the conductive layer 205 is copper.
所述芯片203的第二面上具有导热层204。当所述芯片203工作造成芯片203内部产生热量时,所述导热层204可以将所述芯片203内部热量传导至外界环境或者其他器件中,从而使得芯片203内部热量减小,避免出现芯片203过热的问题。The second surface of the chip 203 has a heat conductive layer 204. When the chip 203 works to generate heat inside the chip 203, the heat conducting layer 204 can conduct heat inside the chip 203 to the external environment or other devices, so that the heat inside the chip 203 is reduced, and the chip 203 is prevented from being overheated. The problem.
所述导热层204的材料为导热树脂材料或者金属材料。本实施例中,所述导热层204的材料为金属材料,所述导热层204的材料为铜、钨或锡中的一种或多种。The material of the heat conductive layer 204 is a heat conductive resin material or a metal material. In this embodiment, the material of the heat conductive layer 204 is a metal material, and the material of the heat conductive layer 204 is one or more of copper, tungsten or tin.
所述导热层204的厚度不宜过薄,也不宜过厚。如果所述导热层204的厚度过薄,则所述导热层204具有的热传导能力有限,且所述导热层204在芯片203产生的热量作用下易发生形变;如果所述导热层204的厚度过厚,则所述半导体结构的整体厚度也相应偏厚,不利于满足半导体结构小型化微型化的发展趋势。The thickness of the heat conducting layer 204 should not be too thin, and should not be too thick. If the thickness of the heat conducting layer 204 is too thin, the heat conducting layer 204 has a limited heat conduction capability, and the heat conducting layer 204 is susceptible to deformation under the heat generated by the chip 203; if the thickness of the heat conducting layer 204 is excessive If the thickness is thick, the overall thickness of the semiconductor structure is also relatively thick, which is disadvantageous for satisfying the development trend of miniaturization and miniaturization of the semiconductor structure.
为此,本实施例中,所述导热层204的厚度为3微米~8微米,例如3微米、5微米、8微米。To this end, in the embodiment, the heat conductive layer 204 has a thickness of 3 micrometers to 8 micrometers, for example, 3 micrometers, 5 micrometers, and 8 micrometers.
本实施例中,所述导热层204位于所述芯片203的整个第二面上。由于所述导热层204的面积大,因此所述导热层204的热传导能力强,使得所述芯片203内部热量被导出的效率高,有效的避免芯片203过热的问题,保证所述芯片203稳定可靠的工作。In this embodiment, the heat conducting layer 204 is located on the entire second surface of the chip 203. Because the area of the heat conducting layer 204 is large, the heat conducting capability of the heat conducting layer 204 is strong, so that the heat of the chip 203 is highly extracted, effectively avoiding the problem of overheating of the chip 203, and ensuring that the chip 203 is stable and reliable. work.
需要说明的是,在其他实施例中,所述芯片第二面具有线路层时,考虑到所述芯片第二面上的电路布局情况,所述导热层还可以位于所述芯片的部分第二面上,且与所述线路层之间电绝缘,避免导热层与所述芯片之
间发生不必要的电连接。It should be noted that, in other embodiments, when the second side of the chip has a circuit layer, the thermal conductive layer may also be located in the second part of the chip in consideration of circuit layout on the second surface of the chip. And electrically insulated from the circuit layer to avoid the heat conductive layer and the chip
Unnecessary electrical connections occur between them.
需要说明的是,在其他实施例中,所述导热层的材料还可以为导热树脂材料,由于所述导热树脂材料为绝缘材料,因此避免了可能出现的导热层与芯片之间发生不必要的电连接的问题。It should be noted that, in other embodiments, the material of the heat conductive layer may also be a heat conductive resin material. Since the heat conductive resin material is an insulating material, unnecessary occurrence of unnecessary heat conduction between the heat conductive layer and the chip is avoided. The problem of electrical connection.
所述导热层204将所述芯片203内部热量传导至外界环境中的能力有限,当所述导热层204与其他吸收热量能力强的部件相键合时,则所述导热层204将热量传导至所述部件中,使得导热层204传导芯片203内部热量的能量得到显著的提高,有效的降低芯片203周围的温度。The heat conducting layer 204 has limited ability to conduct heat inside the chip 203 to the external environment. When the heat conducting layer 204 is bonded to other components that absorb heat, the heat conducting layer 204 conducts heat to In the component, the energy of the heat conduction layer 204 to conduct heat inside the chip 203 is significantly improved, and the temperature around the chip 203 is effectively reduced.
此外,为了降低半导体结构复杂性,所述部件还为与焊球202电连接的部件,从而使得芯片203、基板201与所述部件通过焊球202实现电连接;因此,在进一步改善半导体结构的散热能量的同时,还能够实现半导体结构与所述部件的电连接,形成功能更为复杂的封装结构。In addition, in order to reduce the complexity of the semiconductor structure, the component is also a component that is electrically connected to the solder ball 202, so that the chip 203, the substrate 201 and the component are electrically connected through the solder ball 202; therefore, the semiconductor structure is further improved. At the same time as the heat dissipating energy, the electrical connection between the semiconductor structure and the component can be realized, and a more complicated package structure can be formed.
具体地,所述部件可以为电路板。为实现上述目的,所述导热层204应与所述电路板相接触,且所述焊球202与所述电路板之间电连接。在使所述焊球202与所述电路板之间电连接的过程中,所述焊球202的厚度会有所减小;为了保证所述焊球202与所述电路板电连接,且所述导热层204与所述电路板相接触,所述焊球202顶部与所述基板201之间的距离L1大于或等于所述导热层204顶部与所述基板201之间的距离L2。In particular, the component can be a circuit board. To achieve the above object, the heat conducting layer 204 should be in contact with the circuit board, and the solder balls 202 and the circuit board are electrically connected. In the process of electrically connecting the solder ball 202 and the circuit board, the thickness of the solder ball 202 may be reduced; in order to ensure that the solder ball 202 is electrically connected to the circuit board, The heat conducting layer 204 is in contact with the circuit board, and a distance L1 between the top of the solder ball 202 and the substrate 201 is greater than or equal to a distance L2 between the top of the heat conductive layer 204 and the substrate 201.
本实施例中,所述焊球202顶部与所述基板201之间的距离L1大于所述导热层204顶部与所述基板201之间的距离L2。若所述焊球202顶部与所述导热层204顶部之间的距离(L1-L2)过大,则当焊球202与电路板之间电连接时,所述导热层204未与电路板相接触,因此,所述焊球202顶部与所述导热层204顶部之间的距离不宜过大。本实施例中,所述焊球202顶部与所述导热层204顶部之间的距离可以满足所述导热层204能够与其他部件中的散热电连接层实现共晶结合即可。In this embodiment, a distance L1 between the top of the solder ball 202 and the substrate 201 is greater than a distance L2 between the top of the heat conductive layer 204 and the substrate 201. If the distance (L1-L2) between the top of the solder ball 202 and the top of the heat conductive layer 204 is too large, when the solder ball 202 is electrically connected to the circuit board, the heat conductive layer 204 is not connected to the circuit board. Contact, therefore, the distance between the top of the solder ball 202 and the top of the thermally conductive layer 204 should not be too large. In this embodiment, the distance between the top of the solder ball 202 and the top of the heat conductive layer 204 may satisfy that the heat conductive layer 204 can be eutectic bonded to the heat dissipation electrical connection layer in other components.
综合上述分析可知,所述焊球202的厚度可以根据芯片203的厚度、导电层205的厚度以及导热层204的厚度进行相应的调整,保证所述导热层204可以与其他部件中的散热电连接层实现共晶键合。
According to the above analysis, the thickness of the solder ball 202 can be adjusted according to the thickness of the chip 203, the thickness of the conductive layer 205, and the thickness of the heat conductive layer 204, so that the heat conductive layer 204 can be electrically connected to other components. The layers achieve eutectic bonding.
在一个具体实施例中,所述导电层205的厚度为10微米~20微米,所述芯片203的厚度为150微米,所述导热层204的厚度为5微米,焊球202的厚度为200微米。In one embodiment, the conductive layer 205 has a thickness of 10 micrometers to 20 micrometers, the chip 203 has a thickness of 150 micrometers, the thermally conductive layer 204 has a thickness of 5 micrometers, and the solder balls 202 have a thickness of 200 micrometers. .
在其他实施例中,所述焊球顶部与所述基板之间的距离还可以等于所述导热层顶部与所述基板之间的距离。此外,还需要说明的是,当提供的电路板表面并非为平坦表面时,所述焊球顶部与所述基板之间的距离还可以小于所述导热层顶部与所述基板之间的距离,保证所述焊球与所述电路板电连接、且所述导热层与所述电路板相接触即可。In other embodiments, the distance between the top of the solder ball and the substrate may also be equal to the distance between the top of the thermally conductive layer and the substrate. In addition, it should be noted that when the surface of the provided circuit board is not a flat surface, the distance between the top of the solder ball and the substrate may be smaller than the distance between the top of the heat conductive layer and the substrate. The solder ball is ensured to be electrically connected to the circuit board, and the heat conductive layer is in contact with the circuit board.
为了进一步的提高所述芯片203与所述基板201之间的结合稳定性,所述半导体结构还可以包括:填充于所述基板201与芯片203之间的底部填充胶(under-fill)。所述底部填充胶可以具有导热性能,因此所述底部填充胶不仅可以使芯片203与基板201之间的稳定性提高,并且,由于所述底部填充胶具有散热功能,使得所述芯片203内部产生的热量可以经由所述底部填充胶传递至外界环境中,从而减小所述芯片203内部聚集的热量,避免芯片203出现过热问题。In order to further improve the bonding stability between the chip 203 and the substrate 201, the semiconductor structure may further include: an under-fill filled between the substrate 201 and the chip 203. The underfill may have thermal conductivity, so the underfill can not only improve the stability between the chip 203 and the substrate 201, but also generate the inside of the chip 203 because the underfill has a heat dissipation function. The heat can be transferred to the external environment via the underfill, thereby reducing the heat accumulated inside the chip 203 and avoiding the problem of overheating of the chip 203.
还需要说明的是,当所述芯片203为影像传感芯片时,为了避免底部填充胶对影像感应区造成污染,所述半导体结构中可以不设置所述底部填充胶,且为了提高芯片203与基板201之间的结合性能,所述半导体结构还包括:位于所述基板201上且覆盖所述芯片203侧壁的密封胶(未图示)。同样的,所述密封胶具有导热性能,使得所述密封胶不仅可以提高芯片203的密封性能,且还有利于散热。It should be noted that, when the chip 203 is an image sensing chip, in order to prevent the underfill from contaminating the image sensing area, the underfill may not be disposed in the semiconductor structure, and in order to improve the chip 203 and The bonding property between the substrates 201 further includes: a sealant (not shown) on the substrate 201 and covering the sidewalls of the chip 203. Also, the sealant has thermal conductivity, so that the sealant can not only improve the sealing performance of the chip 203, but also facilitate heat dissipation.
本实施例提供的半导体结构中,所述芯片203设置在所述基板201上,所述芯片203第一面与基板201相对,所述芯片203第二面上具有导热层204,通过所述导热层204可以将芯片203内部的热量传导至外界环境或部件中,从而有效的降低了芯片203内部热量;此外,本实施例避免了散热罩将所述芯片203产生的热量聚集起来的问题,使得芯片203产生的热量可以及时有效的被导出,防止芯片203过热的问题。同时由于芯片203与焊球202设置在所述基板201的同一面上,且无需设置占据体积较大的散
热罩,因此本实施例提供的半导体结构体积小。In the semiconductor structure provided by the embodiment, the chip 203 is disposed on the substrate 201, the first surface of the chip 203 is opposite to the substrate 201, and the second surface of the chip 203 has a heat conductive layer 204 through the heat conduction. The layer 204 can conduct heat inside the chip 203 to the external environment or components, thereby effectively reducing the heat inside the chip 203; in addition, the embodiment avoids the problem that the heat sink collects the heat generated by the chip 203, so that The heat generated by the chip 203 can be efficiently and timely released to prevent the chip 203 from overheating. At the same time, since the chip 203 and the solder ball 202 are disposed on the same surface of the substrate 201, it is not necessary to set a large volume.
The heat shield, so the semiconductor structure provided by the embodiment is small in size.
本发明还提供一种上述半导体结构的形成方法,包括:提供基板,所述基板上设置有焊球;提供芯片,所述芯片具有相对的第一面与第二面,所述第二面上具有导热层;将所述芯片设置在所述基板上,且所述芯片与所述焊球设置在基板的同一面上,所述第一面与所述基板相对。本发明形成的半导体结构对芯片的散热效果好,且半导体结构的体积小。The present invention also provides a method of forming the above semiconductor structure, comprising: providing a substrate on which a solder ball is disposed; providing a chip having opposite first and second faces, the second face Having a thermally conductive layer; the chip is disposed on the substrate, and the chip and the solder ball are disposed on a same side of the substrate, and the first surface is opposite to the substrate. The semiconductor structure formed by the invention has good heat dissipation effect on the chip, and the semiconductor structure has a small volume.
图3至图5为本发明实施例提供的半导体结构形成过程的结构示意图。FIG. 3 to FIG. 5 are schematic diagrams showing the structure of a semiconductor structure forming process according to an embodiment of the present invention.
参考图3,提供基板201,所述基板201上设置有焊球202。Referring to FIG. 3, a substrate 201 is provided on which a solder ball 202 is disposed.
有关所述基板201以及焊球202的相应描述可参考前述实施例的说明。For a description of the substrate 201 and the solder balls 202, reference may be made to the description of the foregoing embodiments.
所述焊球202的数量和位置可以根据所述基板201以及后续提供的芯片203进行确定。本实施例中,为了节约空间减小形成的半导体结构的体积,所述焊球202对称的设置于所述基板201上,使得后续提供的芯片位于所述焊球202包围的区域内。The number and position of the solder balls 202 can be determined according to the substrate 201 and the subsequently provided chip 203. In this embodiment, in order to save space and reduce the volume of the formed semiconductor structure, the solder balls 202 are symmetrically disposed on the substrate 201 such that the subsequently provided chips are located in the area surrounded by the solder balls 202.
本实施例中,所述焊球202的剖面形状为球状,采用植球工艺,在所述基板201上形成焊球202。在其他实施例中,还可以采用网板印刷工艺以及回流工艺,形成所述焊球。In this embodiment, the solder ball 202 has a spherical shape in cross section, and a solder ball 202 is formed on the substrate 201 by a ball bonding process. In other embodiments, the solder balls may also be formed using a screen printing process and a reflow process.
需要说明的是,在其他实施例中,还可以在后续将芯片设置在所述基板上之后,在所述基板上形成所述焊球。It should be noted that, in other embodiments, the solder ball may be formed on the substrate after the chip is subsequently disposed on the substrate.
参考图4,提供芯片203,所述芯片203具有相对的第一面与第二面,所述第二面上具有导热层204。Referring to FIG. 4, a chip 203 is provided having opposing first and second faces, the second face having a thermally conductive layer 204.
所述导热层204的材料为导热树脂材料或者金属材料。The material of the heat conductive layer 204 is a heat conductive resin material or a metal material.
本实施例中,所述导热层204的材料为金属材料,例如为铜、金、钨或锡中的一种或多种。In this embodiment, the material of the heat conductive layer 204 is a metal material, such as one or more of copper, gold, tungsten or tin.
所述导热层204位于所述芯片203的整个第二面上。可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺,形成所述导热层204。
The heat conducting layer 204 is located on the entire second surface of the chip 203. The thermally conductive layer 204 may be formed using a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
在其他实施例中,所述导热层还可以位于所述芯片的部分第二面上;形成所述导热层的工艺步骤包括:在所述芯片整个第二面上形成导热膜;图形化所述导热膜,在所述芯片部分第二面上形成导热层。In other embodiments, the thermally conductive layer may also be located on a portion of the second side of the chip; the step of forming the thermally conductive layer includes: forming a thermally conductive film over the entire second side of the chip; The heat conductive film forms a heat conductive layer on the second surface of the chip portion.
本实施例中,还在所述芯片203的第一面上形成导电层205,所述导电层205用于实现芯片203与基板201之间的电连接。本实施例中,采用网板印刷工艺,形成所述导电层205。在其他实施例中,还可以采用沉积工艺以及刻蚀工艺,形成所述导电层。In this embodiment, a conductive layer 205 is also formed on the first surface of the chip 203, and the conductive layer 205 is used to realize electrical connection between the chip 203 and the substrate 201. In this embodiment, the conductive layer 205 is formed by a screen printing process. In other embodiments, the conductive layer may also be formed using a deposition process and an etching process.
需要说明的是,本实施例中,形成所述芯片203的工艺步骤包括:提供晶圆;在所述晶圆上形成导热膜,可以采用溅射工艺在所述晶圆上形成导热膜;切割所述晶圆以及导热膜,形成若干个分立的所述芯片203以及所述导热层204。It should be noted that, in this embodiment, the process step of forming the chip 203 includes: providing a wafer; forming a heat conductive film on the wafer, and forming a heat conductive film on the wafer by using a sputtering process; The wafer and the heat conductive film form a plurality of discrete chips 203 and the heat conductive layer 204.
参考图5,将所述芯片203设置在所述基板201上,且所述芯片203与所述焊球202设置在所上基板201的同一面上,所述第一面与所述基板201相对。Referring to FIG. 5, the chip 203 is disposed on the substrate 201, and the chip 203 and the solder ball 202 are disposed on the same surface of the upper substrate 201, and the first surface is opposite to the substrate 201. .
通过焊接键合工艺,将所述芯片203设置在所述基板201上,使所述芯片203与所述基板201固定接合。The chip 203 is placed on the substrate 201 by a solder bonding process, and the chip 203 is fixedly bonded to the substrate 201.
具体地,通过所述基板201与所述导电层205相连接,使得所述芯片203设置于所述基板201上。所述基板201上形成有焊盘(未图示),且每一个焊盘对应于一个分立的导电层205。采用焊接键合工艺将焊盘与导电层205焊接结合。Specifically, the substrate 201 is connected to the conductive layer 205 such that the chip 203 is disposed on the substrate 201. Pads (not shown) are formed on the substrate 201, and each pad corresponds to a discrete conductive layer 205. The pads are solder bonded to the conductive layer 205 using a solder bonding process.
所述焊接键合工艺为共晶键合、超声热压、热压焊接、超声波压焊等。例如,当所述导电层205的材料为Al时,所述基板201上焊盘的材料为Au,所述焊接键合工艺为超声热压方式;当所述导电层205的材料为Au,所述基板201上焊盘的材料为Sn,所述焊接键合工艺为共晶键合方式。The solder bonding process is eutectic bonding, ultrasonic hot pressing, hot press welding, ultrasonic pressure welding, or the like. For example, when the material of the conductive layer 205 is Al, the material of the pad on the substrate 201 is Au, the solder bonding process is ultrasonic hot pressing; when the material of the conductive layer 205 is Au, The material of the pad on the substrate 201 is Sn, and the solder bonding process is a eutectic bonding method.
本实施例中,所述芯片203位于所述焊球202包围的区域内。有关所述焊球202顶部、导热层204顶部之间的位置关系,可参考前述实施例中的相应描述,在此不再赘述。
In this embodiment, the chip 203 is located in a region surrounded by the solder ball 202. For the positional relationship between the top of the solder ball 202 and the top of the heat conductive layer 204, reference may be made to the corresponding description in the foregoing embodiments, and details are not described herein again.
还可以包括步骤:在所述基板201上形成覆盖所述芯片203侧壁的散热胶。可以采用点胶工艺或者塑封工艺,形成所述散热胶。所述散热胶不仅可以起到进一步的固定所述芯片203与基板201的作用,且还可以起到散热作用,进一步的减小所述芯片203内部热量。A step of forming a heat dissipating gel covering the sidewall of the chip 203 on the substrate 201 may also be included. The heat dissipating glue may be formed by a dispensing process or a plastic sealing process. The heat dissipating adhesive not only functions to further fix the chip 203 and the substrate 201, but also functions as a heat sink to further reduce heat inside the chip 203.
本发明实施例还提供一种封装结构,图6示出了本发明实施例提供的封装结构的结构示意图。The embodiment of the present invention further provides a package structure, and FIG. 6 shows a schematic structural view of a package structure provided by an embodiment of the present invention.
参考图6,所述封装结构包括:Referring to FIG. 6, the package structure includes:
如前述实施例提供的半导体结构,包括:基板201,所述基板201上设置有焊球202;设置在所述基板201上的芯片203,且所述芯片203与所述焊球202设置在基板201的同一面上,所述芯片203具有相对的第一面与第二面,所述第一面与所述基板201相对,所述第二面上具有导热层204;The semiconductor structure provided by the foregoing embodiment includes: a substrate 201 on which a solder ball 202 is disposed; a chip 203 disposed on the substrate 201, and the chip 203 and the solder ball 202 are disposed on the substrate On the same side of 201, the chip 203 has opposite first and second faces, the first face is opposite to the substrate 201, the second face has a heat conducting layer 204;
具有功能面的电路板301,所述焊球202与所述电路板301功能面之间电连接,且所述导热层204与所述电路板301功能面相接触。The circuit board 301 has a functional surface, and the solder ball 202 is electrically connected to the functional surface of the circuit board 301, and the heat conductive layer 204 is in contact with the functional surface of the circuit board 301.
以下将结合附图对本实施例提供的封装结构进行详细说明。The package structure provided in this embodiment will be described in detail below with reference to the accompanying drawings.
有关所述半导体结构的描述可参考前述实施例的相应描述,在此不再赘述。For a description of the semiconductor structure, reference may be made to the corresponding description of the foregoing embodiments, and details are not described herein again.
本实施例中,所述电路板301为PCB板。所述电路板301功能面上具有相互分立的功能电连接层311以及散热电连接层312,即功能电连接层311与散热电连接层312相互间隔布置于电路板301的功能面上。其中,所述焊球202与所述功能电连接层311电连接,所述导热层204与所述散热电连接层312相接触。In this embodiment, the circuit board 301 is a PCB board. The function board 301 has a functional electrical connection layer 311 and a heat dissipation electrical connection layer 312 which are separated from each other. The functional electrical connection layer 311 and the heat dissipation electrical connection layer 312 are spaced apart from each other on the functional surface of the circuit board 301. The solder ball 202 is electrically connected to the functional electrical connection layer 311, and the heat conductive layer 204 is in contact with the heat dissipation electrical connection layer 312.
其中,所述焊球202通过所述功能电连接层311实现电路板301与基板201以及芯片203之间的电连接。同时,由于所述导热层204与所述散热电连接层312相接触,所述芯片203内部产生的热量经由所述导热层204传递至散热电连接层312内,因此所述芯片203内部产生的热量可以经由电路板301进行散热,所述电路板301的散热效果好,从而保证芯片203内部的热量及时有效的被传导出去,保证芯片203有效的运行。
The solder ball 202 realizes electrical connection between the circuit board 301 and the substrate 201 and the chip 203 through the functional electrical connection layer 311. At the same time, since the heat conducting layer 204 is in contact with the heat dissipation electrical connection layer 312, heat generated inside the chip 203 is transferred to the heat dissipation electrical connection layer 312 via the heat conduction layer 204, so that the chip 203 is internally generated. The heat can be dissipated via the circuit board 301. The heat dissipation effect of the circuit board 301 is good, so that the heat inside the chip 203 is conducted in time and effectively, and the chip 203 is effectively operated.
本实施例中,所述功能电连接层311顶部与所述散热电连接层312顶部齐平。在其他实施例中,所述功能电连接层顶部还可以低于所述散热电连接层顶部,或者,所述功能电连接层顶部与所述散热电连接层顶部齐平,保证所述焊球与所述功能电连接层电连接,且所述导热层与所述散热电连接相接触即可。In this embodiment, the top of the functional electrical connection layer 311 is flush with the top of the heat dissipation electrical connection layer 312. In other embodiments, the top of the functional electrical connection layer may also be lower than the top of the heat dissipation electrical connection layer, or the top of the functional electrical connection layer is flush with the top of the heat dissipation electrical connection layer to ensure the solder ball The electrical connection layer is electrically connected to the functional electrical connection layer, and the thermal conductive layer is in contact with the heat dissipation electrical connection.
所述导热层204与所述散热电连接层312相互键合。所述散热电连接层312的材料为金、钨或锡膏中的一种或多种。本实施例中,所述散热电连接层312的材料为锡膏,所述导热层204与所述散热电连接层312通过共晶结合的方式相接触。The heat conductive layer 204 and the heat dissipation electrical connection layer 312 are bonded to each other. The material of the heat dissipation electrical connection layer 312 is one or more of gold, tungsten or solder paste. In this embodiment, the material of the heat dissipation electrical connection layer 312 is solder paste, and the heat conduction layer 204 is in contact with the heat dissipation electrical connection layer 312 by eutectic bonding.
本实施例中,所述功能电连接层311的材料与所述散热电连接层312的材料相同。在其他实施例中,所述功能电连接层的材料还可以与所述散热电连接层的材料不同。In this embodiment, the material of the functional electrical connection layer 311 is the same as the material of the heat dissipation electrical connection layer 312. In other embodiments, the material of the functional electrical connection layer may also be different from the material of the heat dissipation electrical connection layer.
本实施例提供的封装结构中,所述电路板301不仅具有电连接所述基板201以及芯片203的功能,且还具有传导芯片203内部产生热量的作用,防止芯片203内部过热。In the package structure provided by the embodiment, the circuit board 301 not only has the function of electrically connecting the substrate 201 and the chip 203, but also has the function of generating heat inside the conductive chip 203 to prevent overheating of the chip 203.
且由于所述焊球202与芯片203设置在所述基板201同一面上,与所述焊与芯片设置在基板相对的两个面上的技术方案相比,本实施例提供的封装结构的厚度明显减小了,封装结构具有更小的体积。And because the solder ball 202 and the chip 203 are disposed on the same surface of the substrate 201, compared with the technical solution that the solder and the chip are disposed on opposite sides of the substrate, the thickness of the package structure provided by the embodiment Significantly reduced, the package structure has a smaller volume.
本发明实施例还提供一种上述封装结构的形成方法,包括:提供前述的半导体结构;提供具有功能面的电路板;将所述半导体结构设置在所述电路板功能面上,使得所述焊球与所述电路板功能面之间电连接,且所述导热层与所述电路板功能相接触。本发明形成的封装结构中,电路板既能实现与基板以及芯片之间的电连接,且还通过与导热层相接触从而及时有效的将芯片产生的热量传递出去,改善封装结构的散热效果,且减小封装结构的体积。The embodiment of the present invention further provides a method for forming the above package structure, comprising: providing the foregoing semiconductor structure; providing a circuit board having a functional surface; and disposing the semiconductor structure on the functional surface of the circuit board, so that the soldering The ball is electrically connected to the functional surface of the circuit board, and the thermally conductive layer is in contact with the function of the circuit board. In the package structure formed by the invention, the circuit board can realize the electrical connection with the substrate and the chip, and also can contact the heat conductive layer to timely and effectively transfer the heat generated by the chip, thereby improving the heat dissipation effect of the package structure. And reduce the volume of the package structure.
图7为本发明实施例提供的封装结构形成过程的结构示意图。FIG. 7 is a schematic structural diagram of a process of forming a package structure according to an embodiment of the present invention.
参考图2,提供半导体结构。
Referring to Figure 2, a semiconductor structure is provided.
所述半导体结构包括:基板201,所述基板201上设置有焊球202;设置在所述基板201上的芯片203,且所述芯片203与所述焊球202设置在基板201的同一面上,所述芯片203具有相对的第一面与第二面,所述第一面与所述基板201相对,所述第二面上具有导热层204。其中,所述第一面与所述基板201之间还具有若干相互分离的导电层205。The semiconductor structure includes a substrate 201 on which a solder ball 202 is disposed, a chip 203 disposed on the substrate 201, and the chip 203 and the solder ball 202 are disposed on the same side of the substrate 201. The chip 203 has opposite first and second faces, the first face being opposite to the substrate 201, and the second face having a heat conductive layer 204. The first surface and the substrate 201 further have a plurality of conductive layers 205 separated from each other.
参考图7,提供具有功能面的电路板301。Referring to Figure 7, a circuit board 301 having a functional surface is provided.
本实施例中,所述电路板301为PCB板。所述功能面为后续与前述半导体结构相键合的面。In this embodiment, the circuit board 301 is a PCB board. The functional surface is a surface that is subsequently bonded to the semiconductor structure.
所述电路板301上具有相互分离的功能电连接层311以及散热电连接层312。可以采用印刷工艺,在所述电路板301上形成所述功能电连层311以及散热电连接层312。The circuit board 301 has functional electrical connection layers 311 and heat dissipation electrical connection layers 312 separated from each other. The functional electrical connection layer 311 and the heat dissipation electrical connection layer 312 may be formed on the circuit board 301 by a printing process.
本实施例中,所述功能电连接层311顶部与所述散热电连接层312顶部齐平。在其他实施例中,所述功能电连接层顶部还可以低于所述散热电连接层顶部,或者,所述功能电连接层顶部与所述散热电连接层顶部齐平。In this embodiment, the top of the functional electrical connection layer 311 is flush with the top of the heat dissipation electrical connection layer 312. In other embodiments, the top of the functional electrical connection layer may also be lower than the top of the heat dissipation electrical connection layer, or the top of the functional electrical connection layer may be flush with the top of the heat dissipation electrical connection layer.
所述散热电连接层312的材料为锡、金或钨中的一种或多种。本实施例中,所述散热电连接层312的材料为锡。The material of the heat dissipation electrical connection layer 312 is one or more of tin, gold or tungsten. In this embodiment, the material of the heat dissipation electrical connection layer 312 is tin.
本实施例中,所述散热电连接层312的材料与所述功能电连接层311的材料相同。In this embodiment, the material of the heat dissipation electrical connection layer 312 is the same as the material of the functional electrical connection layer 311.
参考图6,将所述半导体结构设置在所述电路板301功能面上,使得所述焊球202与所述电路板301功能面之间电连接,且所述导热层204与所述电路板301功能面相接触。Referring to FIG. 6, the semiconductor structure is disposed on a functional surface of the circuit board 301 such that the solder ball 202 is electrically connected to a functional surface of the circuit board 301, and the heat conductive layer 204 and the circuit board are The 301 functional surface is in contact.
具体地,通过焊接键合工艺,使得所述焊球202与所述功能电连接层311相键合,使得所述导热层204与所述散热电连接层312相键合。Specifically, the solder ball 202 is bonded to the functional electrical connection layer 311 by a solder bonding process such that the heat conductive layer 204 is bonded to the heat dissipation electrical connection layer 312.
本实施例中,所述散热电连接层312的材料为锡膏,所述导热层204的材料为金属材料;采用共晶结合工艺,使得所述导热层204与所述散热电连接层312相键合。由于所述导热层204与所述散热电连接层312为共晶结合,使得所述导热层204与所述散热电连接层312之间的键合界面具
有优良的导热性能。In this embodiment, the material of the heat dissipation electrical connection layer 312 is a solder paste, and the material of the heat conduction layer 204 is a metal material; the eutectic bonding process is used to make the heat conduction layer 204 and the heat dissipation electrical connection layer 312 Bond. The bonding interface between the heat conducting layer 204 and the heat dissipating electrical connection layer 312 is such that the heat conducting layer 204 and the heat dissipating electrical connection layer 312 are eutectic bonded.
Has excellent thermal conductivity.
需要说明的是,在其他实施例中,还可以采用超声热压、热压焊接或超声波压焊等方法,实现所述导热层与所述电路板功能面相键合,使得所述导热层与所述散热电连接层相接触。It should be noted that, in other embodiments, the thermal conductive layer may be bonded to the functional surface of the circuit board by ultrasonic hot pressing, thermocompression bonding or ultrasonic pressure welding, etc., so that the thermal conductive layer and the thermal conductive layer The heat-dissipating electrical connection layers are in contact.
本实施例中,在进行所述焊接键合工艺之前,所述功能电连接层311顶部与所述散热电连接层312顶部齐平,且所述焊球202顶部高于所述导热层204顶部;在通过焊接键合工艺使所述焊球202与所述功能电连接层311相键合的过程中,所述焊球202的厚度会减小,因此当所述焊球202与所述功能电连接层311电连接时,可以实现所述导热层204与所述散热电连接层312之间相键合,即,所述导热层204与所述电路板301功能面相接触。In this embodiment, before the solder bonding process is performed, the top of the functional electrical connection layer 311 is flush with the top of the heat dissipation electrical connection layer 312, and the top of the solder ball 202 is higher than the top of the thermal conductive layer 204. In the process of bonding the solder ball 202 to the functional electrical connection layer 311 by a solder bonding process, the thickness of the solder ball 202 may be reduced, so when the solder ball 202 and the function When the electrical connection layer 311 is electrically connected, the heat conduction layer 204 and the heat dissipation electrical connection layer 312 can be bonded to each other, that is, the heat conduction layer 204 is in contact with the functional surface of the circuit board 301.
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。
Although the present invention has been disclosed above, the present invention is not limited thereto. Any changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be determined by the scope defined by the appended claims.
Claims (29)
- 一种半导体结构,其特征在于,包括:A semiconductor structure, comprising:基板,所述基板上设置有焊球;a substrate on which a solder ball is disposed;设置在所述基板上的芯片,且所述芯片与所述焊球设置在基板的同一面上,所述芯片具有相对的第一面与第二面,所述第一面与所述基板相对,所述第二面上具有导热层。a chip disposed on the substrate, wherein the chip and the solder ball are disposed on a same side of the substrate, the chip having opposite first and second faces, the first face being opposite to the substrate The second surface has a heat conducting layer.
- 如权利要求1所述的半导体结构,其特征在于,所述导热层位于整个所述第二面上。The semiconductor structure of claim 1 wherein said thermally conductive layer is located throughout said second side.
- 如权利要求1所述的半导体结构,其特征在于,所述第二面具有线路层;所述导热层位于部分所述第二面上,且与所述线路层之间电绝缘。The semiconductor structure of claim 1 wherein said second side has a wiring layer; said thermally conductive layer being located on said portion of said second side and electrically insulated from said wiring layer.
- 如权利要求1所述的半导体结构,其特征在于,所述导热层的材料为导热树脂材料或者金属材料。The semiconductor structure according to claim 1, wherein the material of the heat conductive layer is a thermally conductive resin material or a metal material.
- 如权利要求1或4所述的半导体结构,其特征在于,所述导热层的材料为铜、金、钨或锡中的一种或多种。The semiconductor structure according to claim 1 or 4, wherein the material of the heat conductive layer is one or more of copper, gold, tungsten or tin.
- 如权利要求1所述的半导体结构,其特征在于,所述焊球顶部与所述基板之间的距离大于所述导热层顶部与所述基板之间的距离。The semiconductor structure of claim 1 wherein a distance between said solder ball top and said substrate is greater than a distance between said top of said thermally conductive layer and said substrate.
- 如权利要求1所述的半导体结构,其特征在于,所述焊球顶部与所述基板之间的距离等于所述导热层顶部与所述基板之间的距离。The semiconductor structure of claim 1 wherein a distance between said solder ball top and said substrate is equal to a distance between said top of said thermally conductive layer and said substrate.
- 如权利要求1所述的半导体结构,其特征在于,所述半导体结构还包括:位于所述基板与所述第一面之间的若干间隔分布的导电层,所述导电层用于实现所述芯片与所述基板之间的电连接。The semiconductor structure of claim 1 further comprising: a plurality of spaced apart conductive layers between said substrate and said first side, said conductive layer for achieving said An electrical connection between the chip and the substrate.
- 如权利要求1所述的半导体结构,其特征在于,所述半导体结构还包括:填充于所述基板与所述芯片之间的底部填充胶。The semiconductor structure of claim 1 further comprising: an underfill filled between said substrate and said chip.
- 如权利要求1所述的半导体结构,其特征在于,所述芯片为影像传感芯片,且所述芯片具有影像感应区。 The semiconductor structure of claim 1 wherein said chip is an image sensing chip and said chip has an image sensing area.
- 如权利要求10所述的半导体结构,其特征在于,所述基板内具有贯穿所述基板的开口,且所述影像感应区位于所述开口上方;所述半导体结构还包括:覆盖在所述开口上的透光盖板,且所述透光盖板与所述芯片分别位于所述基板相对的两侧。The semiconductor structure of claim 10, wherein the substrate has an opening through the substrate, and the image sensing region is located above the opening; the semiconductor structure further comprises: covering the opening a transparent cover plate, and the transparent cover plate and the chip are respectively located on opposite sides of the substrate.
- 如权利要求10所述的半导体结构,其特征在于,所述基板为透光基板。The semiconductor structure of claim 10 wherein said substrate is a light transmissive substrate.
- 如权利要求10所述的半导体结构,其特征在于,所述半导体结构还包括:位于所述基板上且覆盖所述芯片侧壁的密封胶。The semiconductor structure of claim 10 wherein said semiconductor structure further comprises: a sealant on said substrate and covering said sidewalls of said chip.
- 如权利要求13所述的半导体结构,其特征在于,所述密封胶具有导热性能。The semiconductor structure of claim 13 wherein said sealant has thermal conductivity.
- 一种封装结构,其特征在于,包括:A package structure, comprising:如权利要求1至14任一项所述的半导体结构;A semiconductor structure according to any one of claims 1 to 14;电路板,所述电路板具有电路板功能面,所述焊球与所述电路板功能面之间电连接,且所述导热层与所述电路板功能面相接触。a circuit board having a circuit board functional surface, the solder ball being electrically connected to the circuit board functional surface, and the heat conductive layer being in contact with the circuit board functional surface.
- 如权利要求15所述的封装结构,其特征在于,所述电路板功能面上具有间隔设置的功能电连接层以及散热电连接层;其中,所述焊球与所述功能电连接层电连接,所述导热层与散热电连接层相接触。The package structure as claimed in claim 15 , wherein the functional surface of the circuit board has spaced apart functional electrical connection layers and heat dissipation electrical connection layers; wherein the solder balls are electrically connected to the functional electrical connection layer The heat conductive layer is in contact with the heat dissipation electrical connection layer.
- 如权利要求16所述的封装结构,其特征在于,所述功能电连接层顶部与所述散热电连接层顶部齐平。The package structure of claim 16 wherein the top of the functional electrical connection layer is flush with the top of the heat dissipation electrical connection layer.
- 如权利要求16所述的封装结构,其特征在于,所述功能电连接层的材料与所述散热电连接层的材料相同。The package structure according to claim 16, wherein the material of the functional electrical connection layer is the same as the material of the heat dissipation electrical connection layer.
- 如权利要求16所述的封装结构,其特征在于,所述散热电连接层的材料为金、钨或锡膏中的一种或多种。The package structure according to claim 16, wherein the material of the heat dissipation electrical connection layer is one or more of gold, tungsten or solder paste.
- 一种如权利要求1至14任一项所述的半导体结构的形成方法,其特征在于,包括:A method of forming a semiconductor structure according to any one of claims 1 to 14, comprising:提供基板,所述基板上设置有焊球; Providing a substrate on which a solder ball is disposed;提供芯片,所述芯片具有相对的第一面与第二面,所述第二面上具有导热层;Providing a chip having opposite first and second faces, the second face having a thermally conductive layer;将所述芯片设置在所述基板上,且所述芯片与所述焊球设置在基板的同一面上,所述第一面与所述基板相对。The chip is disposed on the substrate, and the chip and the solder ball are disposed on a same side of the substrate, and the first surface is opposite to the substrate.
- 如权利要求20所述的半导体结构的形成方法,其特征在于,采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺,形成所述导热层。The method of forming a semiconductor structure according to claim 20, wherein the thermally conductive layer is formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
- 如权利要求20所述的半导体结构的形成方法,其特征在于,部分所述第二面设置有所述导热层;形成所述导热层的工艺步骤包括:在所述第二面上形成完全覆盖所述第二面的导热膜;图形化所述导热膜,在部分所述第二面上形成所述导热层。A method of forming a semiconductor structure according to claim 20, wherein a part of said second surface is provided with said heat conducting layer; and said forming step of said heat conducting layer comprises: forming a complete covering on said second surface a heat conductive film on the second surface; the heat conductive film is patterned to form the heat conductive layer on a portion of the second surface.
- 如权利要求20所述的半导体结构的形成方法,其特征在于,通过焊接键合工艺,将所述芯片设置在所述基板上。A method of forming a semiconductor structure according to claim 20, wherein said chip is disposed on said substrate by a solder bonding process.
- 如权利要求23所述的半导体结构的形成方法,其特征在于,所述基板上形成有若干焊盘,且所述焊盘与所述导电层一一对应;采用焊接键合工艺,将所述焊盘与所述导电层焊接结合。The method of forming a semiconductor structure according to claim 23, wherein a plurality of pads are formed on the substrate, and the pads are in one-to-one correspondence with the conductive layer; A pad is solder bonded to the conductive layer.
- 如权利要求20所述的半导体结构的形成方法,其特征在于,在将所述芯片设置在所述基板上之前,在所述基板上形成所述焊球;或者,在将所述芯片设置在所述基板上之后,在所述基板上形成所述焊球。A method of forming a semiconductor structure according to claim 20, wherein said solder ball is formed on said substrate before said chip is disposed on said substrate; or After the substrate is on, the solder balls are formed on the substrate.
- 如权利要求20所述的半导体结构的形成方法,其特征在于,形成所述芯片的工艺步骤包括:提供晶圆;在所述晶圆上形成导热膜;切割所述晶圆以及导热膜,形成若干个间隔分布的所述芯片以及所述导热层。The method of forming a semiconductor structure according to claim 20, wherein the step of forming the chip comprises: providing a wafer; forming a heat conductive film on the wafer; cutting the wafer and a heat conductive film to form A plurality of spaced apart said chips and said thermally conductive layer.
- 一种如权利要求15至19任一项所述的封装结构的形成方法,其特征在于,包括:A method of forming a package structure according to any one of claims 15 to 19, comprising:提供如权利要求1至14任一项所述的半导体结构;Providing the semiconductor structure of any one of claims 1 to 14;提供具有电路板功能面的电路板; Providing a circuit board having a functional surface of the circuit board;将所述半导体结构设置在所述电路板功能面上,使得所述焊球与所述电路板功能面之间电连接,且所述导热层与所述电路板功能面相接触。The semiconductor structure is disposed on the functional surface of the circuit board such that the solder ball is electrically connected to the functional surface of the circuit board, and the heat conductive layer is in contact with the functional surface of the circuit board.
- 如权利要求27所述的封装结构的形成方法,其特征在于,所述电路板功能面上具有间隔设置的功能电连接层以及散热电连接层;其中,所述焊球与所述功能电连接层电连接,所述导热层与散热电连接层相接触;采用焊接键合工艺,使得所述焊球与所述功能电连接层电连接,且所述导热层与所述散热电连接层相键合。The method of forming a package structure according to claim 27, wherein the functional surface of the circuit board has spaced apart functional electrical connection layers and a heat dissipation electrical connection layer; wherein the solder balls are electrically connected to the function The layer is electrically connected, the heat conducting layer is in contact with the heat dissipating electrical connection layer; the solder ball is electrically connected to the functional electrical connection layer by a solder bonding process, and the heat conducting layer and the heat dissipating electrical connection layer are Bond.
- 如权利要求28所述的封装结构的形成方法,其特征在于,所述导热层的材料为金属材料,所述散热电连接层的材料为锡膏;采用共晶结合工艺,使得所述导热层与所述散热电连接层相键合。 The method of forming a package structure according to claim 28, wherein the material of the heat conductive layer is a metal material, the material of the heat dissipation electrical connection layer is a solder paste; and the heat conductive layer is formed by a eutectic bonding process. Bonding to the heat dissipation electrical connection layer.
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CN201611045346.9A CN106449551B (en) | 2016-11-24 | 2016-11-24 | Semiconductor structure and forming method thereof, packaging structure and forming method thereof |
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