CN206259339U - Semiconductor structure and encapsulating structure - Google Patents
Semiconductor structure and encapsulating structure Download PDFInfo
- Publication number
- CN206259339U CN206259339U CN201621266619.8U CN201621266619U CN206259339U CN 206259339 U CN206259339 U CN 206259339U CN 201621266619 U CN201621266619 U CN 201621266619U CN 206259339 U CN206259339 U CN 206259339U
- Authority
- CN
- China
- Prior art keywords
- substrate
- chip
- heat
- semiconductor structure
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
A kind of semiconductor structure and encapsulating structure, semiconductor structure include：Substrate, soldered ball is provided with the substrate；Chip on the substrate is set, and the chip is arranged on the same face of substrate with the soldered ball, the chip has the first relative face and the second face, and first face is relative with the substrate, has heat-conducting layer on second face.The utility model improves the radiating effect in semiconductor structure and encapsulating structure, prevents the temperature of chip internal and surrounding too high, it is ensured that the reliable and effective operation of chip.
Description
Technical field
The utility model is related to encapsulation technology field, more particularly to a kind of semiconductor structure and encapsulating structure.
Background technology
With the fast development of radio communication, automotive electronics and other consumer electronics products, microelectronic packaging technology to
The direction for multi-functional, miniaturization, portable, high speed, low-power consumption and high reliability is developed.Wherein, system in package (SIP,
System In a Package) it is a kind of new encapsulation technology, package area can be effectively reduced.
The surface that existing multi-functional SIP encapsulation chip is included in substrate is fitted one or more chips.With encapsulation core
Piece it is highly integrated, the power for encapsulating chip is increasing, therefore chip cooling turns into encapsulation process one and must take into consideration
Problem.The heat that chip is produced in itself, in addition at least partially through bottom substrate and weld pad outwards radiating, its major heat is
Radiated by chip surface.Therefore, existing chip package designs are general adds heat dissipating housing on chip, and heat dissipating housing is led to
Cross Heat Conduction Material to be pasted onto on chip and substrate, form encapsulation structure.
However, the radiating effect of the encapsulating structure of prior art offer has much room for improvement, and the encapsulation knot with heat sinking function
Structure volume is big.
Utility model content
The problem that the utility model is solved is to provide a kind of semiconductor structure and encapsulating structure, effectively reduces in chip
Portion and ambient heat, prevent chip overheating.
To solve the above problems, the utility model provides a kind of semiconductor structure, including：Substrate, is set on the substrate
There is soldered ball；Chip on the substrate is set, and the chip is arranged on the same face of substrate with the soldered ball, the core
Piece has the first relative face and the second face, and first face is relative with the substrate, has heat-conducting layer on second face.
Optionally, the heat-conducting layer is located on whole second face.
Optionally, the face of the chip second has line layer；The heat-conducting layer be located at part second face on, and with institute
State electric insulation between line layer.
Optionally, the material of the heat-conducting layer is heat-conducting resin material or metal material.
Optionally, the material of the heat-conducting layer is one or more in copper, gold, tungsten or tin.
Optionally, the distance between soldered ball top and described substrate more than heat-conducting layer top and the substrate it
Between distance.
Optionally, the distance between soldered ball top and described substrate be equal to heat-conducting layer top and the substrate it
Between distance.
Optionally, the semiconductor structure also includes：Some points between the substrate and the chip first side
From conductive layer, the conductive layer is used for the electrical connection for realizing between the chip and the substrate.
Optionally, the semiconductor structure also includes：It is filled in the underfill between the substrate and the chip.
Optionally, the chip is image sensing chip, and the chip has video sensing area.
Optionally, have through the opening of the substrate in the substrate, and the video sensing area is located at the opening
Top；The semiconductor structure also includes：Covering euphotic cover plate over said opening, and the euphotic cover plate and the chip
The relative both sides of the substrate are located at respectively.
Optionally, the substrate is transparent substrates.
Optionally, the semiconductor structure also includes：On the substrate and cover the fluid sealant of the chip side wall.
Optionally, the fluid sealant has heat conductivility.
The utility model also provides a kind of encapsulating structure, including：Foregoing semiconductor structure；Circuit with functional surfaces
Plate, electrically connects between the soldered ball and the circuit board functional surfaces, and the heat-conducting layer is in contact with the circuit board functional surfaces.
Optionally, there is the function electric connection layer and radiating electric connection layer being separated from each other on the circuit board functional surfaces；
Wherein, the soldered ball is electrically connected with the function electric connection layer, and the heat-conducting layer is in contact with radiating electric connection layer.
Optionally, the function electric connection layer top flushes with the radiating electric connection layer top.
Optionally, the material of the function electric connection layer is identical with the material of the radiating electric connection layer.
Optionally, the material of the radiating electric connection layer is one or more in gold, tungsten or tin cream.
Compared with prior art, the technical solution of the utility model has advantages below：
In the technical scheme of the semiconductor structure that the utility model is provided, the chip is set on the substrate, described
Chip first side is relative with substrate, has heat-conducting layer on the face of the chip second, can be by chip internal by the heat-conducting layer
Heat conduct into external environment or part, so as to effectively reduce chip internal heat；Additionally, the utility model is avoided
The problem that heat dissipating housing gathers together the heat that the chip is produced so that the heat that chip is produced can timely and effectively by
Derive, prevent the problem of chip overheating.Simultaneously because chip is arranged on the same face of the substrate with soldered ball, and without setting
The larger heat dissipating housing of volume is occupied, therefore the semiconductor structure volume that the utility model is provided is small.
In the technical scheme of the encapsulating structure that the utility model is provided, the circuit board not only has the electrical connection substrate
And the function of chip, and because circuit board is in contact with heat-conducting layer so that also there is the circuit board conduction chip internal to produce
The effect of heat amount, prevents chip internal from overheating.Additionally, the soldered ball is arranged on the substrate the same face with chip, therefore
The thickness of the encapsulating structure that the utility model is provided is obviously reduced, and encapsulating structure has smaller volume.
Brief description of the drawings
Fig. 1 is a kind of cross-sectional view of encapsulating structure；
The structural representation of the semiconductor structure that Fig. 2 is provided for the utility model embodiment；
The cross-sectional view of the semiconductor structure formation process that Fig. 3 to Fig. 5 is provided for the utility model embodiment；
The structural representation of the encapsulating structure that Fig. 6 is provided for the utility model embodiment；
The structural representation of the encapsulating structure forming process that Fig. 7 is provided for the utility model embodiment.
Specific embodiment
The radiating effect of the encapsulating structure provided according to background technology, prior art is limited, and the volume of encapsulating structure is big.
It is analyzed in conjunction with a kind of encapsulating structure, Fig. 1 is the cross-sectional view of encapsulating structure.
With reference to Fig. 1, the encapsulating structure includes：Substrate 101, the substrate 101 has relative front and the back side, described
Some soldered balls 102 are provided with the back side of substrate 101, some soldered balls 102 can be BGA (Ball Grid Array) ball；If
Put in the positive chip 103 of the substrate 101, the chip 103 has relative functional surfaces nand function face, wherein, it is described
Functional surfaces are relative with the front of the substrate 101, and realized by conductive layer 104 between the substrate 101 and the chip 103
Electrical connection；Positioned at the front of the substrate 101 and the heat dissipating housing 105 of the encirclement chip 103, the chip 103 is located at described dissipating
In heat cover 105, and the adjacent heat dissipating housing 105 in the non-functional face of the chip 103.
In above-mentioned encapsulating structure, the partial heat that chip 103 is produced is transferred in the external world via heat dissipating housing 105.However, on
The radiating effect for stating encapsulating structure is poor, analyzes its reason and is mainly：Because the chip 103 is surrounded by the heat dissipating housing 105, because
This described chip 103 is in sealed environment；The heat dissipating housing 105 not only has the effect of radiating, and the heat dissipating housing 105 also has
There is the heat that the aggregation chip 103 is produced, the radiating is not concentrated on by the heat that heat dissipating housing 105 is transferred to the external world
In the sealed environment that cover 105 is surrounded, cause that there is temperature higher around chip 103, influence the service behaviour of chip.
Additionally, in above-mentioned encapsulating structure, the thickness of the encapsulating structure is：The thickness of BAG balls, the thickness of substrate 101 and
The height sum of heat dissipating housing 105, and the heat dissipating housing 105 thickness of the height more than the chip 103, therefore above-mentioned encapsulation knot
The thickness of structure is thicker.Also, the heat dissipating housing 105 is arranged on the substrate 101, therefore the substrate 101 also needs to be institute
State the headspace position of heat dissipating housing 105.Therefore, the volume of the encapsulating structure of above-mentioned offer is larger, be unfavorable for chip miniaturization, it is micro-
The trend development that type is miniaturized to miniaturization.
To solve the above problems, the utility model provides a kind of semiconductor structure, the heat for timely and effectively producing chip
Amount is passed, and prevents chip internal and environment temperature too high, it is ensured that chip effectively runs, and also reduces semiconductor structure
Volume.
It is understandable to enable above-mentioned purpose of the present utility model, feature and advantage to become apparent, below in conjunction with the accompanying drawings to this
The specific embodiment of utility model is described in detail.
Fig. 2 shows the structural representation of the semiconductor structure that the present embodiment is provided.With reference to Fig. 2, the semiconductor structure
Including：
Substrate 201, is provided with soldered ball 202 on the substrate 201；
The chip 203 of the top of the substrate 201 is arranged on, and the chip 203 is arranged on the base with the soldered ball 202
On the same face of plate 201, the chip 203 has relative the first face (sign) and the second face (sign), described first
Face is relative with the substrate 201, has heat-conducting layer 204 on second face.
The semiconductor structure that the present embodiment is provided is described in detail below with reference to accompanying drawing.
The substrate 201 is used to fix the chip 203, and the chip 203 is electrically connected with other devices or circuit
Connect.The substrate 201 is rigid substrate or flexible base plate；The substrate 201 can also be transparent substrates, for example, unorganic glass
Substrate, pmma substrate or filter glass substrate.
In the present embodiment, the substrate 201 is rigid substrate, and the rigid substrate is PCB substrate, glass substrate, metal
Substrate, semiconductor substrate or polymeric substrates.
There can also be some pads (not shown) on the substrate 201, and the pad is located at base with the soldered ball 202
On the same face of plate 201.The pad is used to be electrically connected with chip 203.Specifically, have on the first face of the chip 203
Some mutually discrete conductive layers 205, the pad is used to be electrically connected with the conductive layer 205.The position sum of the pad
The quantity and position for measuring conductive layer 205 that can be in chip 203 determine.
There can also be circuit layer (not shown) in the substrate 201, the chip 203 is electrically connected with the circuit layer.
On parallel to the surface direction of the substrate 201, the section shape of the substrate 201 is square, circular, triangle
Shape, regular polygon or irregular shape.In the present embodiment, so that the section shape of the substrate 201 is square as an example.
The soldered ball 202 is used to electrically connect the substrate 201 and other devices or external circuit, for example, passing through institute
State the electrical connection that soldered ball 202 can be realized between the substrate 201 and circuit board.
In the present embodiment, the section shape of the soldered ball 202 is spherical.In other embodiments, the section shape of the soldered ball
Shape can also be square.
In order to save space, rational deployment can be carried out to the position that the soldered ball 202 is located on substrate 201.This implementation
In example, the soldered ball 202 is distributed on the substrate 201 of the periphery of the chip 203, and the soldered ball 202 is on the substrate 201
It is symmetrical.
The chip 203 is functional chip, for example, image sensing chip.And the chip 203 sets with the soldered ball 202
Put on the same face of the substrate 201；In the present embodiment, the chip 203 is located at the substrate 201 that the soldered ball 202 is surrounded
In region.
It should be noted that when the chip 203 is image sensing chip, the chip 203 has video sensing area (not
Diagram)；Accordingly, have through the opening (not shown) of the substrate 201 in the substrate 201, and the video sensing area
Positioned at the overthe openings so that ambient can be transferred in the video sensing area via the opening.Also, in order to
Protect the video sensing area, it is to avoid the video sensing area is contaminated, and the semiconductor structure also includes：It is covered in described
Euphotic cover plate on opening, and the euphotic cover plate is located at the relative both sides of the substrate 201 with the chip 203 respectively.
Also, it should be noted that the chip 203 is image sensing chip, when the chip 203 has video sensing area,
The substrate 201 can also be transparent substrates, without setting through the opening of the substrate 201 in the corresponding substrate 201.
First face of the chip 203 is relative with substrate 201, and the first face of the chip 203 is mutually solid with the substrate 201
It is fixed.Specifically, in the present embodiment, the semiconductor structure also includes：Positioned at the substrate 202 and the face of the chip 203 first
Between some separation conductive layer 205, the conductive layer 205 be used for realize between the chip 203 and the substrate 201
Electrical connection, and make to be interfixed between the chip 203 and the substrate 201 by the conductive layer 205.
According to the position and the quantity that need to be electrically connected on the face of the chip 203 first, the conductive layer 205 is determined
Position and quantity.The material of the conductive layer 205 is one or more in copper, aluminium, tungsten or tin.It is described to lead in the present embodiment
The material of electric layer 205 is copper.
There is heat-conducting layer 204 on second face of the chip 203.When the work of the chip 203 causes the inside of chip 203 to produce
During heat amount, the heat-conducting layer 204 can be conducted into external environment or other devices the internal heat of the chip 203,
So that the internal heat of chip 203 reduces, it is to avoid the problem of the overheat of chip 203 occur.
The material of the heat-conducting layer 204 is heat-conducting resin material or metal material.In the present embodiment, the heat-conducting layer
204 material is metal material, and the material of the heat-conducting layer 204 is one or more in copper, tungsten or tin.
The thickness of the heat-conducting layer 204 is unsuitable excessively thin, also unsuitable blocked up.If the thickness of the heat-conducting layer 204 is excessively thin,
The capacity of heat transmission that the heat-conducting layer 204 has is limited, and the heat-conducting layer 204 is easy under the heat effect that chip 203 is produced
Deform upon；If the thickness of the heat-conducting layer 204 is blocked up, the integral thickness of the semiconductor structure is also corresponding partially thick, no
Beneficial to the development trend for meeting semiconductor structure miniaturization miniaturization.
Therefore, in the present embodiment, the thickness of the heat-conducting layer 204 is 3 microns~8 microns, such as 3 microns, 5 microns, it is 8 micro-
Rice.
In the present embodiment, the heat-conducting layer 204 is located on whole second face of the chip 203.Due to the heat-conducting layer
204 area is big, therefore the capacity of heat transmission of the heat-conducting layer 204 is strong so that the effect that the internal heat of the chip 203 is exported
Rate is high, the problem for effectively avoiding chip 203 from overheating, it is ensured that the reliable and stable work of the chip 203.
It should be noted that in other embodiments, when the face of the chip second has line layer, it is contemplated that the chip
Circuit layout situation on second face, the heat-conducting layer may be located on the face of part second of the chip, and with the line
It is electrically insulated between the floor of road, it is to avoid unnecessary electrical connection occurs between heat-conducting layer and the chip.
It should be noted that in other embodiments, the material of the heat-conducting layer can also be heat-conducting resin material, due to
The heat-conducting resin material is insulating materials, therefore avoids between the heat-conducting layer and chip being likely to occur unnecessary electricity occurs
The problem of connection.
The internal heat of the chip 203 is conducted limited in one's ability into external environment by the heat-conducting layer 204, is led when described
When the part strong with other absorption heat abilities of thermosphere 204 is mutually bonded, then the heat-conducting layer 204 conducts heat to the part
In so that the energy of the conduction internal heat of chip 203 of heat-conducting layer 204 is significantly improved, and effectively reduces around chip 203
Temperature.
Additionally, in order to reduce semiconductor structure complexity, the part is also the part electrically connected with soldered ball 202, so that
So that chip 203, substrate 201 are realized electrically connecting with the part by soldered ball 202；Therefore, semiconductor junction is further being improved
While the radiated energy of structure, additionally it is possible to realize the electrical connection of semiconductor structure and the part, function is formed increasingly complex
Encapsulating structure.
Specifically, the part can be circuit board.To achieve the above object, the heat-conducting layer 204 should be with the circuit
Plate is in contact, and is electrically connected between the soldered ball 202 and the circuit board.Make between the soldered ball 202 and the circuit board
During electrical connection, the thickness of the soldered ball 202 can reduce；In order to ensure the soldered ball 202 with circuit board electricity
The distance between connection, and the heat-conducting layer 204 is in contact with the circuit board, the top of the soldered ball 202 and described substrate 201
L1 is more than or equal to the distance between the top of the heat-conducting layer 204 and the substrate 201 L2.
In the present embodiment, the distance between the top of the soldered ball 202 and described substrate 201 L1 are more than the heat-conducting layer 204
The distance between top and the substrate 201 L2.If the distance between the top of the soldered ball 202 and the top of the heat-conducting layer 204
(L1-L2) excessive, then when being electrically connected between soldered ball 202 and circuit board, the heat-conducting layer 204 is not in contact with circuit board, because
This, the top of the soldered ball 202 is unsuitable with the distance between the top of the heat-conducting layer 204 excessive.In the present embodiment, the soldered ball
The distance between 202 tops and the top of the heat-conducting layer 204 can meet the heat-conducting layer 204 can with miscellaneous part in dissipate
Thermoelectricity articulamentum realizes eutectic bond.
The above analysis understands that the thickness of the soldered ball 202 can be according to the thickness of chip 203, the thickness of conductive layer 205
The thickness of degree and heat-conducting layer 204 is adjusted correspondingly, it is ensured that the heat-conducting layer 204 can be with the electricity of the radiating in miscellaneous part
Articulamentum realizes eutectic bonding.
In a specific embodiment, the thickness of the conductive layer 205 is 10 microns~20 microns, the chip 203
Thickness is 150 microns, and the thickness of the heat-conducting layer 204 is 5 microns, and the thickness of soldered ball 202 is 200 microns.
In other embodiments, the distance between soldered ball top and described substrate can also be equal to the heat-conducting layer top
The distance between portion and described substrate.In addition it is also necessary to explanation, when the circuit board surface for providing is not flat surfaces
When, the distance between soldered ball top and the substrate be also less than between the heat-conducting layer top and the substrate away from
From, it is ensured that the soldered ball is electrically connected with the circuit board and the heat-conducting layer is in contact with the circuit board.
In order to further improve the combination stability between the chip 203 and the substrate 201, the semiconductor junction
Structure can also include：It is filled in the underfill (under-fill) between the substrate 201 and chip 203.The bottom
Filling glue can have heat conductivility, therefore the underfill can not only make the stabilization between chip 203 and substrate 201
Property improve, also, because the underfill has heat sinking function so that the heat that the inside of the chip 203 produces can be with
It is transferred in external environment via the underfill, so as to reduce the heat of the inside of the chip 203 aggregation, it is to avoid chip
203 there is problems of excessive heat.
Also, it should be noted that when the chip 203 is image sensing chip, in order to avoid underfill is to image
Induction zone is polluted, and the underfill can be not provided with the semiconductor structure, and in order to improve chip 203 and base
Binding ability between plate 201, the semiconductor structure also includes：On the substrate 201 and cover the side of chip 203
The fluid sealant (not shown) of wall.Likewise, the fluid sealant has heat conductivility so that the fluid sealant can not only improve core
The sealing property of piece 203, and also help radiating.
In the semiconductor structure that the present embodiment is provided, the chip 203 is arranged on the substrate 201, the chip 203
First face is relative with substrate 201, has heat-conducting layer 204 on the face of the chip 203 second, can be by by the heat-conducting layer 204
Heat inside chip 203 is conducted into external environment or part, so as to effectively reduce the internal heat of chip 203；Additionally,
This embodiment avoids the problem that heat dissipating housing gathers together the heat that the chip 203 is produced so that the heat that chip 203 is produced
Amount can timely and effectively be exported, the problem for preventing chip 203 from overheating.Simultaneously because chip 203 is arranged on institute with soldered ball 202
State on the same face of substrate 201, and the larger heat dissipating housing of volume is occupied without setting, therefore the semiconductor junction that the present embodiment is provided
Structure small volume.
The utility model also provides a kind of forming method of above-mentioned semiconductor structure, including：Substrate is provided, on the substrate
It is provided with soldered ball；Chip is provided, the chip has the first relative face and the second face, has heat-conducting layer on second face；
The chip is set on the substrate, and the chip is arranged on the same face of substrate with the soldered ball, described first
Face is relative with the substrate.The semiconductor structure that the utility model is formed is to the good heat dissipation effect of chip, and semiconductor structure
Small volume.
The structural representation of the semiconductor structure formation process that Fig. 3 to Fig. 5 is provided for the utility model embodiment.
With reference to Fig. 3, there is provided substrate 201, soldered ball 202 is provided with the substrate 201.
Corresponding description about the substrate 201 and soldered ball 202 refers to the explanation of previous embodiment.
The quantity of the soldered ball 202 and position can be carried out really according to the substrate 201 and the follow-up chip 203 for providing
It is fixed.In the present embodiment, in order to save the volume that space reduces the semiconductor structure to be formed, the soldered ball 202 is symmetrical to be arranged at
On the substrate 201 so that the follow-up chip for providing is located in the region that the soldered ball 202 is surrounded.
In the present embodiment, the section shape of the soldered ball 202 is spherical, using plant ball technique, the shape on the substrate 201
Into soldered ball 202.In other embodiments, screen printing technique and reflux technique can also be used, the soldered ball is formed.
It should be noted that in other embodiments, can also after subsequently chip is set on the substrate,
The soldered ball is formed on the substrate.
With reference to Fig. 4, there is provided chip 203, the chip 203 has the first relative face and the second face, on second face
With heat-conducting layer 204.
The material of the heat-conducting layer 204 is heat-conducting resin material or metal material.
In the present embodiment, the material of the heat-conducting layer 204 is metal material, for example, the one kind in copper, gold, tungsten or tin or
It is various.
The heat-conducting layer 204 is located on whole second face of the chip 203.Can using chemical vapor deposition method,
Physical gas-phase deposition or atom layer deposition process, form the heat-conducting layer 204.
In other embodiments, the heat-conducting layer may be located on the face of part second of the chip；Led described in being formed
The processing step of thermosphere includes：Heat conducting film is formed on whole second face of the chip；The graphical heat conducting film, in the core
Piece part second forms heat-conducting layer on face.
In the present embodiment, conductive layer 205 is formed also on the first face of the chip 203, the conductive layer 205 is used for real
Existing electrical connection between chip 203 and substrate 201.In the present embodiment, using screen printing technique, the conductive layer 205 is formed.
In other embodiments, depositing operation and etching technics can also be used, the conductive layer is formed.
It should be noted that in the present embodiment, the processing step for forming the chip 203 includes：Wafer is provided；Described
Heat conducting film is formed on wafer, heat conducting film can be formed on the wafer using sputtering technology；Cut the wafer and heat conduction
Film, forms several discrete chips 203 and the heat-conducting layer 204.
With reference to Fig. 5, the chip 203 is arranged on the substrate 201, and the chip 203 sets with the soldered ball 202
Put on the same face of institute's upper substrate 201, first face is relative with the substrate 201.
By solder bonds technique, the chip 203 is arranged on the substrate 201, make the chip 203 with it is described
The fixed engagement of substrate 201.
Specifically, it is connected with the conductive layer 205 by the substrate 201 so that the chip 203 is arranged at described
On substrate 201.Pad (not shown) is formed with the substrate 201, and each pad corresponds to a discrete conductive layer
205.Using solder bonds technique by pad and the solder bond of conductive layer 205.
The solder bonds technique is eutectic bonding, ultrasonic thermocompression, thermal compression welding, ultrasonic wire bonding etc..For example, when described
When the material of conductive layer 205 is Al, the material of pad is Au on the substrate 201, and the solder bonds technique is ultrasonic thermocompression
Mode；When the material of the conductive layer 205 is Au, the material of pad is Sn on the substrate 201, and the solder bonds technique is
Eutectic bonding mode.
In the present embodiment, the chip 203 is located in the region that the soldered ball 202 is surrounded.The relevant soldered ball 202 is pushed up
Position relationship between portion, the top of heat-conducting layer 204, refers to the corresponding description in previous embodiment, will not be repeated here.
Step can also be included：The thermal paste of the covering side wall of chip 203 is formed on the substrate 201.Can adopt
With gluing process or plastic package process, the thermal paste is formed.The thermal paste can not only play further fixed described
The effect of chip 203 and substrate 201, and thermolysis is may also operate as, further reduce the internal heat of the chip 203.
The utility model embodiment also provides a kind of encapsulating structure, and Fig. 6 shows the envelope that the utility model embodiment is provided
The structural representation of assembling structure.
With reference to Fig. 6, the encapsulating structure includes：
The semiconductor structure that such as previous embodiment is provided, including：Substrate 201, is provided with soldered ball 202 on the substrate 201；
The chip 203 on the substrate 201 is arranged on, and the chip 203 is arranged on the same face of substrate 201 with the soldered ball 202
On, the chip 203 has the first relative face and the second face, and first face is relative with the substrate 201, second face
It is upper that there is heat-conducting layer 204；
Circuit board 301 with functional surfaces, electrically connects between the soldered ball 202 and the functional surfaces of the circuit board 301, and institute
Heat-conducting layer 204 is stated to be in contact with the functional surfaces of the circuit board 301.
The encapsulating structure that the present embodiment is provided is described in detail below with reference to accompanying drawing.
Description about the semiconductor structure refers to the corresponding description of previous embodiment, will not be repeated here.
In the present embodiment, the circuit board 301 is pcb board.There is mutually discrete work(on the functional surfaces of the circuit board 301
Energy electric connection layer 311 and radiating electric connection layer 312, wherein, the soldered ball 202 is electrically connected with the function electric connection layer 311,
The heat-conducting layer 204 is in contact with the radiating electric connection layer 312.
Wherein, the soldered ball 202 realizes circuit board 301 and substrate 201 and chip by the function electric connection layer 311
Electrical connection between 203.Simultaneously as the heat-conducting layer 204 is in contact with the radiating electric connection layer 312, the chip 203
The heat that inside produces is transferred in radiating electric connection layer 312 via the heat-conducting layer 204, therefore is produced from the inside of the chip 203
Raw heat can be radiated via circuit board 301, the good heat dissipation effect of the circuit board 301, so as to ensure in chip 203
The heat in portion is timely and effectively conducted, it is ensured that chip 203 effectively runs.
In the present embodiment, the top of the function electric connection layer 311 flushes with the top of radiating electric connection layer 312.At it
In his embodiment, the function electric connection layer top may also be below the radiating electric connection layer top, or, the function electricity
Articulamentum top is flushed with the radiating electric connection layer top, it is ensured that the soldered ball is electrically connected with the function electric connection layer, and
The heat-conducting layer is in contact with the radiating electrical connection.
The heat-conducting layer 204 is mutually bonded with the radiating electric connection layer 312.The material of the radiating electric connection layer 312
It is one or more in gold, tungsten or tin cream.In the present embodiment, the material of the radiating electric connection layer 312 is tin cream, described to lead
Thermosphere 204 is in contact with the radiating electric connection layer 312 by way of eutectic bond.
In the present embodiment, the material of the function electric connection layer 311 is identical with the material of the radiating electric connection layer 312.
In other embodiments, the material of the function electric connection layer can also be different from the material of the radiating electric connection layer.
In the encapsulating structure that the present embodiment is provided, the circuit board 301 not only has the electrical connection substrate 201 and core
The function of piece 203, and also there is the inside of conduction chip 203 to produce the effect of heat, prevent the over-heat inside of chip 203.
And because the soldered ball 202 and chip 203 are arranged on the same face of the substrate 201, set with chip with the weldering
The technical scheme put on two relative faces of substrate is compared, and the thickness of the encapsulating structure that the present embodiment is provided is substantially reduced,
Encapsulating structure has smaller volume.
The utility model embodiment also provides a kind of forming method of above-mentioned encapsulating structure, including：Offer is foregoing partly to be led
Body structure；Circuit board with functional surfaces is provided；The semiconductor structure is arranged on the circuit board functional surfaces so that institute
State and electrically connected between soldered ball and the circuit board functional surfaces, and the heat-conducting layer is in contact with the circuit board function.This practicality
In the encapsulating structure of new formation, circuit board can realize the electrical connection and substrate and chip between, and also by with heat conduction
Layer is in contact so as to timely and effectively the heat transfer that chip is produced be gone out, and improves the radiating effect of encapsulating structure, and reduce
The volume of encapsulating structure.
The structural representation of the encapsulating structure forming process that Fig. 7 is provided for the utility model embodiment.
With reference to Fig. 2, there is provided semiconductor structure.
The semiconductor structure includes：Substrate 201, is provided with soldered ball 202 on the substrate 201；It is arranged on the substrate
Chip 203 on 201, and the chip 203 is arranged on the same face of substrate 201 with the soldered ball 202, the chip 203
With the first relative face and the second face, first face is relative with the substrate 201, has heat-conducting layer on second face
204.Wherein, also there are some conductive layers 205 being separated from each other between first face and the substrate 201.
With reference to Fig. 7, there is provided the circuit board 301 with functional surfaces.
In the present embodiment, the circuit board 301 is pcb board.The functional surfaces for subsequently with aforesaid semiconductor structure phase key
The face of conjunction.
There is the function electric connection layer 311 and radiating electric connection layer 312 being separated from each other on the circuit board 301.Can be with
Using typography, formed on the circuit board 301 function be electrically connected layer 311 and radiating electric connection layer 312.
In the present embodiment, the top of the function electric connection layer 311 flushes with the top of radiating electric connection layer 312.At it
In his embodiment, the function electric connection layer top may also be below the radiating electric connection layer top, or, the function electricity
Articulamentum top flushes with the radiating electric connection layer top.
The material of the radiating electric connection layer 312 is one or more in tin, gold or tungsten.It is described to dissipate in the present embodiment
The material of thermoelectricity articulamentum 312 is tin.
In the present embodiment, the material of the radiating electric connection layer 312 is identical with the material of the function electric connection layer 311.
With reference to Fig. 6, the semiconductor structure is arranged on the functional surfaces of the circuit board 301 so that the soldered ball 202 with
Electrically connected between the functional surfaces of the circuit board 301, and the heat-conducting layer 204 is in contact with the functional surfaces of the circuit board 301.
Specifically, by solder bonds technique so that the soldered ball 202 is mutually bonded with the function electric connection layer 311, makes
The heat-conducting layer 204 is obtained mutually to be bonded with the radiating electric connection layer 312.
In the present embodiment, the material of the radiating electric connection layer 312 is tin cream, and the material of the heat-conducting layer 204 is metal
Material；Using eutectic bond technique so that the heat-conducting layer 204 is mutually bonded with the radiating electric connection layer 312.Led due to described
Thermosphere 204 is eutectic bond with the radiating electric connection layer 312 so that the heat-conducting layer 204 and the radiating electric connection layer 312
Between bonded interface there is excellent heat conductivility.
It should be noted that in other embodiments, can also be using ultrasonic thermocompression, thermal compression welding or ultrasonic wire bonding etc.
Method, realizes that the heat-conducting layer is mutually bonded with the circuit board functional surfaces so that the heat-conducting layer and the radiating electric connection layer
It is in contact.
In the present embodiment, before the solder bonds technique is carried out, the top of the function electric connection layer 311 dissipates with described
The top of thermoelectricity articulamentum 312 flushes, and the top of the soldered ball 202 is higher than the top of the heat-conducting layer 204；By solder bonds work
During skill makes the soldered ball 202 be mutually bonded with the function electric connection layer 311, the thickness of the soldered ball 202 can reduce, because
This is when the soldered ball 202 is electrically connected with the function electric connection layer 311, it is possible to achieve the heat-conducting layer 204 and the radiating
Mutually it is bonded between electric connection layer 312, i.e. the heat-conducting layer 204 is in contact with the functional surfaces of the circuit board 301.
Although the utility model is disclosed as above, the utility model is not limited to this.Any those skilled in the art,
Do not depart from spirit and scope of the present utility model, can make various changes or modifications, therefore protection domain of the present utility model
Should be defined by claim limited range.
Claims (19)
1. a kind of semiconductor structure, it is characterised in that including：
Substrate, soldered ball is provided with the substrate；
Chip on the substrate is set, and the chip is arranged on the same face of substrate with the soldered ball, the chip
With the first relative face and the second face, first face is relative with the substrate, has heat-conducting layer on second face.
2. semiconductor structure as claimed in claim 1, it is characterised in that the heat-conducting layer is located on whole second face.
3. semiconductor structure as claimed in claim 1, it is characterised in that the face of the chip second has line layer；It is described to lead
Thermosphere is located on second face of part, and is electrically insulated between the line layer.
4. semiconductor structure as claimed in claim 1, it is characterised in that the material of the heat-conducting layer be heat-conducting resin material or
Person's metal material.
5. the semiconductor structure as described in claim 1 or 4, it is characterised in that the material of the heat-conducting layer be copper, gold, tungsten or
One or more in tin.
6. semiconductor structure as claimed in claim 1, it is characterised in that the distance between the soldered ball top and described substrate
More than heat-conducting layer top the distance between with the substrate.
7. semiconductor structure as claimed in claim 1, it is characterised in that the distance between the soldered ball top and described substrate
Equal to heat-conducting layer top the distance between with the substrate.
8. semiconductor structure as claimed in claim 1, it is characterised in that the semiconductor structure also includes：Positioned at the base
Some separate conductive layers between plate and the chip first side, the conductive layer is used to realize the chip with the substrate
Between electrical connection.
9. semiconductor structure as claimed in claim 1, it is characterised in that the semiconductor structure also includes：It is filled in described
Underfill between substrate and the chip.
10. semiconductor structure as claimed in claim 1, it is characterised in that the chip is image sensing chip, and the core
Piece has video sensing area.
11. semiconductor structures as claimed in claim 10, it is characterised in that there is opening through the substrate in the substrate
Mouthful, and the video sensing area is located at the overthe openings；The semiconductor structure also includes：Covering over said opening saturating
Light cover plate, and the euphotic cover plate is located at the relative both sides of the substrate with the chip respectively.
12. semiconductor structures as claimed in claim 10, it is characterised in that the substrate is transparent substrates.
13. semiconductor structures as claimed in claim 10, it is characterised in that the semiconductor structure also includes：Positioned at described
On substrate and cover the fluid sealant of the chip side wall.
14. semiconductor structures as claimed in claim 13, it is characterised in that the fluid sealant has heat conductivility.
A kind of 15. encapsulating structures, it is characterised in that including：
Semiconductor structure as described in any one of claim 1 to 14；
Circuit board with functional surfaces, electrically connects between the soldered ball and the circuit board functional surfaces, and the heat-conducting layer and institute
Circuit board functional surfaces are stated to be in contact.
16. encapsulating structures as claimed in claim 15, it is characterised in that have what is be separated from each other on the circuit board functional surfaces
Function electric connection layer and radiating electric connection layer；Wherein, the soldered ball is electrically connected with the function electric connection layer, the heat-conducting layer
It is in contact with radiating electric connection layer.
17. encapsulating structures as claimed in claim 16, it is characterised in that the function electric connection layer top and the radiating electricity
Articulamentum top flushes.
18. encapsulating structures as claimed in claim 16, it is characterised in that the material of the function electric connection layer and the radiating
The material of electric connection layer is identical.
19. encapsulating structures as claimed in claim 16, it is characterised in that the material of the radiating electric connection layer for gold, tungsten or
One or more in tin cream.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621266619.8U CN206259339U (en) | 2016-11-24 | 2016-11-24 | Semiconductor structure and encapsulating structure |
| PCT/CN2017/110641 WO2018095233A1 (en) | 2016-11-24 | 2017-11-13 | Semiconductor structure and forming method therefor, and packaging structure and forming method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621266619.8U CN206259339U (en) | 2016-11-24 | 2016-11-24 | Semiconductor structure and encapsulating structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206259339U true CN206259339U (en) | 2017-06-16 |
Family
ID=59026110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621266619.8U Active CN206259339U (en) | 2016-11-24 | 2016-11-24 | Semiconductor structure and encapsulating structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206259339U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449551A (en) * | 2016-11-24 | 2017-02-22 | 苏州晶方半导体科技股份有限公司 | Semiconductor structure and forming method thereof, as well as packaging structure and forming method thereof |
| WO2018095233A1 (en) * | 2016-11-24 | 2018-05-31 | 苏州晶方半导体科技股份有限公司 | Semiconductor structure and forming method therefor, and packaging structure and forming method therefor |
-
2016
- 2016-11-24 CN CN201621266619.8U patent/CN206259339U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449551A (en) * | 2016-11-24 | 2017-02-22 | 苏州晶方半导体科技股份有限公司 | Semiconductor structure and forming method thereof, as well as packaging structure and forming method thereof |
| WO2018095233A1 (en) * | 2016-11-24 | 2018-05-31 | 苏州晶方半导体科技股份有限公司 | Semiconductor structure and forming method therefor, and packaging structure and forming method therefor |
| CN106449551B (en) * | 2016-11-24 | 2020-06-19 | 苏州晶方半导体科技股份有限公司 | Semiconductor structure and forming method thereof, packaging structure and forming method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7928590B2 (en) | Integrated circuit package with a heat dissipation device | |
| US7838334B2 (en) | Package-on-package device, semiconductor package and method for manufacturing the same | |
| TWI529878B (en) | Hybrid thermal interface material for ic packages with integrated heat spreader | |
| TWI508255B (en) | Thermally dissipating flip-chip package | |
| EP1524690B1 (en) | Semiconductor package with heat spreader | |
| JP4332567B2 (en) | Manufacturing method and mounting method of semiconductor device | |
| TWI235469B (en) | Thermally enhanced semiconductor package with EMI shielding | |
| US7498203B2 (en) | Thermally enhanced BGA package with ground ring | |
| CN107978566A (en) | The manufacture method of stack package structure | |
| US20080093733A1 (en) | Chip package and manufacturing method thereof | |
| JP2001077301A (en) | Semiconductor package and its manufacturing method | |
| JP2013077691A (en) | Component built-in substrate package, manufacturing method thereof and component built-in substrate | |
| TWI650816B (en) | Semiconductor device and method of manufacturing same | |
| CN208111434U (en) | Power module | |
| CN206259339U (en) | Semiconductor structure and encapsulating structure | |
| CN106449551A (en) | Semiconductor structure and forming method thereof, as well as packaging structure and forming method thereof | |
| CN201946588U (en) | Packaging structure for power semiconductors | |
| US20040217451A1 (en) | Semiconductor packaging structure | |
| WO2018095233A1 (en) | Semiconductor structure and forming method therefor, and packaging structure and forming method therefor | |
| TWI282159B (en) | Thermally enhanced thin flip-chip package | |
| JPH09199629A (en) | Semiconductor device | |
| KR20130038581A (en) | Semiconductor package | |
| TW201220444A (en) | Semiconductor package device with a heat dissipation structure and the packaging method thereof | |
| CN200976345Y (en) | Chip packaging structure | |
| CN103050454A (en) | Package on package structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant |