CN103050454A - Package on package structure - Google Patents
Package on package structure Download PDFInfo
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- CN103050454A CN103050454A CN2012105170495A CN201210517049A CN103050454A CN 103050454 A CN103050454 A CN 103050454A CN 2012105170495 A CN2012105170495 A CN 2012105170495A CN 201210517049 A CN201210517049 A CN 201210517049A CN 103050454 A CN103050454 A CN 103050454A
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- packaging structure
- upper substrate
- thermal conductivity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a package on package structure, which comprises an upper package body, a lower package body and a heat conducting interface layer, wherein the upper package body comprises an upper substrate and an upper wafer, the upper substrate comprises a first patterning metal layer, the first patterning metal layer comprises a first heat conducting area, the upper wafer is arranged on the upper substrate and is electrically connected with the upper substrate, the lower package body comprises a lower substrate, a plurality of electric connecting elements and a lower wafer, the lower substrate is electrically connected with the upper substrate by the electric connecting elements, the lower wafer is arranged on the lower substrate and is electrically connected with the lower substrate, and the heat conducting interface layer is bonded between the first heat conducting area of the upper substrate and the lower wafer. Through the first heat conducting area and the heat conducting interface layer in the package structure, the heat conduction is favorably realized, the heat exchange area is increased, and the heat radiating efficiency of the wafers is further improved.
Description
Technical field
The invention relates to a kind of packaging structure that stacks, particularly relevant for a kind of packaging structure that stacks that improves radiating efficiency.
Background technology
Now, along with such as electronic installations such as portable type PC, wisdom mobile phone and digital cameras, microminiaturization, multifunction and high performance, less and the function that semiconductor device must design is more, thereby makes semiconductor packaging structure (semiconductor package) more and more general in the use of many electronic installations.For example, stacking type packaging structure (Package on Package, PoP) be a kind of very typical three-dimensional packaging structure, the packaging body that two individual packages are finished, stacked and formed single packaging structure, in order to increase the electrical functionality of single packaging structure, and the usage space when carrying out surface adhering technical (SMT) on the saving tellite, in addition, the stacking type packaging structure coincides in the bonding mode in surface after packaging and testing by two packaging bodies independently again, not only can reduce the manufacturing risk, improves product yield, more can shorten the line length between encapsulating structure, to reduce signal delay and access time.
Yet wafer can produce high temperature when running, so its surperficial need to heat radiation by other joint one fin (heat sink), and common fixing cooling fins is to use heat-conducting glue in the method for wafer.And stacking type encapsulation structure produces high temperature especially easily, reason is that stacking type encapsulation structure can be designed with the wafer more than two, the wafer of upper substrate (for example: memory chip, Memory Die) with the wafer of lower substrate (for example: the logic wafer, Logic Die) high temperature that produces, general only can be by the metallic conduction material of between the wafer with fin of upper substrate and upper substrate and lower substrate, using as electrically connect, for example be positioned at soldered ball around the wafer or the binding of conductive projection, because the common metal electric conducting material has higher thermal conductive property simultaneously, therefore can transfer heat to substrate dispels the heat, but the heat radiation interface of aforesaid way is few and as the heat dissipation path length that electrically connect is used inner high temperature can't effectively be left, and then the whole radiating efficiency of impact.In recent years, the stacking type packaging structure is widely used in the portable electronic product, in order to meet the day by day trend of compactization of portable electronic product, the stacking type packaging structure also needs further slimming, yet the stacking type packaging structure of slimming is difficult to provide sufficient space between upper and lower packaging body heat dissipation metal plate to be set, thereby so that whole radiating efficiency becomes low.
So, be necessary to provide a kind of packaging structure that stacks, to solve the existing problem of prior art.
Summary of the invention
In view of this, the invention provides a kind of packaging structure that stacks, to solve the not good problem of the existing radiating efficiency of prior art.
Main purpose of the present invention is to provide a kind of packaging structure that stacks, and it can help the area of heat conduction and increase heat exchange by thermal conductivity region and the heat conduction interface layer in the packaging structure, and then improves the radiating efficiency of wafer.
Another object of the present invention is to provide a kind of packaging structure that stacks, it can help by the heat conductive pad in the packaging structure heat conduction, and increases the area of heat exchange, and then improves the radiating efficiency of wafer.
For reaching aforementioned purpose of the present invention, one embodiment of the invention provides a kind of packaging structure that stacks, the wherein said packaging structure that stacks comprises: packaging body on, once packaging body and a heat conduction interface layer, described upper packaging body comprises wafer on a upper substrate and, described upper substrate comprises a upper surface, one lower surface and back to described upper surface is arranged on the first patterned metal layer of described lower surface, described patterned metal layer comprises the first thermal conductivity region, described upper wafer is arranged on the upper surface of described upper substrate and is electrically connected described upper substrate, described lower packaging body comprises an infrabasal plate, several are electrically connected element and a lower wafer, described infrabasal plate is electrically connected described upper substrate by described electric connection element, described lower wafer comprises first surface and back to the second surface of first surface, described lower wafer is arranged on the described infrabasal plate and the first surface of described lower wafer and the electric connection of described infrabasal plate.Described heat conduction interface layer is combined between the second surface of the first thermal conductivity region of described upper substrate and described lower wafer.
Moreover, another embodiment of the present invention provides another kind to stack packaging structure, the wherein said packaging structure that stacks comprises: packaging body on, one heat conductive pad reaches packaging body, described upper packaging body comprises wafer on a upper substrate and, described upper substrate has a upper surface and a lower surface back to described upper surface, described heat conductive pad is arranged at the upper surface of described upper substrate, described upper wafer is arranged on the described heat conductive pad and is electrically connected described upper substrate, described lower packaging body comprises an infrabasal plate, several are electrically connected element and a lower wafer, described infrabasal plate is electrically connected described upper substrate by described electric connection element, described lower wafer comprises a first surface and back to the second surface of first surface, described lower wafer is arranged on the described infrabasal plate and the first surface of described lower wafer and the electric connection of described infrabasal plate.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
Fig. 1 is the schematic diagram that one embodiment of the invention stacks packaging structure.
Fig. 2 is the schematic diagram that another embodiment of the present invention stacks packaging structure.
Fig. 3 is the schematic diagram that further embodiment of this invention stacks packaging structure.
Fig. 4 is the schematic diagram that yet another embodiment of the invention stacks packaging structure.
Fig. 5 is the assembling schematic diagram that Fig. 1 embodiment of the present invention stacks packaging structure.
Fig. 6 is the assembling schematic diagram that Fig. 3 embodiment of the present invention stacks packaging structure.
Embodiment
Below the explanation of each embodiment be with reference to additional graphic, can be in order to the specific embodiment of implementing in order to illustration the present invention.Moreover, the direction term that the present invention mentions, such as upper and lower, top, the end, front, rear, left and right, inside and outside, side, on every side, central authorities, level, laterally, vertically, vertically, axially, radially, the superiors or orlop etc., only be the direction with reference to annexed drawings.Therefore, the direction term of use is in order to explanation and understands the present invention, but not in order to limit the present invention.
Please refer to shown in Figure 1ly, the packaging structure 100 that stacks of one embodiment of the invention is made and is mainly comprised packaging body 1 on, once packaging body 2 and a heat conduction interface layer 3.Described upper packaging body 1 comprises on the upper substrate 11, a packaging adhesive material 15 on the wafer 14 and, described lower packaging body 2 comprises an infrabasal plate 21, several are electrically connected elements 22, a lower wafer 23 and packaging adhesive material 24 once, and the present invention will be in the detail structure, assembled relation and the operation principles thereof that hereinafter describe one by one above-mentioned each element of present embodiment in detail.
Please refer to shown in Figure 1, in the present embodiment, described upper substrate 11 and infrabasal plate 21 for example are selected from the organic printed circuit board (PCB) of encapsulation grade (printed circuit board, PCB) of rigid (rigid) or bendable (flexible), but the present invention is not limited thereto.Described upper substrate 11 and infrabasal plate 21 are mainly alternately stacked by several metal levels (being line layer) and insulating resin layer and form.
Please refer to shown in Figure 1, described upper substrate 11 comprises a upper surface (not indicating), one lower surface back to described upper surface (not indicating), one is arranged on the first patterned metal layer 111 of lower surface, one the second patterned metal layer 112 and that is arranged on upper surface covers, the solder mask 113 of lower surface, described the first patterned metal layer 111 comprises one first thermal conductivity region 1111 and one first circuit region 1112, described solder mask 113 exposes described the first thermal conductivity region 1111 at lower surface with a recess 110, and described heat conduction interface layer 3 can be embedded in the described recess 110.Moreover, described solder mask 113 also optionally exposes described the second thermal conductivity region 1121 with another recess 110 ' at the second patterned metal layer 112 of upper surface, one back side of described upper wafer 14 is arranged on described the second thermal conductivity region 1121 down, and an active surface of described upper wafer 14 up and be electrically connected the second circuit zone 1122 of described upper substrate 11, and wherein said the second thermal conductivity region 1121 is corresponding with described the first thermal conductivity region 1111.
In more detail; in the present embodiment; and described the first thermal conductivity region 1111 and the second thermal conductivity region 1121 are metal material (for example copper); namely by the some of described the first patterned metal layer 111 and the second patterned metal layer 112 directly as described the first thermal conductivity region 1111 and the second thermal conductivity region 1121; described solder mask 113 is anti-welding green lacquer (solder mask); it is covered on described the first patterned metal layer 111 and the second patterned metal layer 112 and exposed some; avoid causing weak point because of scratch to protect described the first patterned metal layer 111 and the second patterned metal layer 112; breaking phenomena; wherein said exposed second circuit zone 1122 can be as several weld pads, and its upper wafer 14 that can pass through bonding wire (indicating) and described routing type is electrically connected.In addition, described upper wafer 14 also can directly be arranged on several weld pads of the upper surface of described upper substrate 11 in the mode of flip chip, and described the second thermal conductivity region 1121 is not set this moment, therefore is not limited with present embodiment.Moreover described upper packaging adhesive material 15 for example is the mixture of epoxy resin and insulated particle (such as aluminium oxide or silicon dioxide), and described upper packaging adhesive material 15 is in order to coat the upper surface of protection described upper wafer 14, bonding wire and described upper substrate 11.
Described infrabasal plate 21 is electrically connected described upper substrate 11 by described electric connection element 22, described lower wafer 23 comprises the second surface 232 that first surface 231 reaches back to first surface 231, described electric connection element 22 can be selected from Metal Ball or columnar metal thing, for example is the tin ball.Described lower wafer 23 is arranged on the described infrabasal plate 21 and the first surface 231 of described lower wafer passes through several projections (indicating) and described infrabasal plate 21 electric connections in the mode of flip chip.Described lower packaging adhesive material 24 for example is the mixture of epoxy resin and insulated particle (such as aluminium oxide or silicon dioxide); described lower packaging adhesive material 24 is protected described lower wafer 23, projection, the upper surface of described infrabasal plate 21 and the some of described electric connection element 22 in order to coat, and exposes the back side of the first half and the described lower wafer 23 of described electric connection element 22.Moreover, described heat conduction interface layer 3 is combined between the second surface 232 of described the first thermal conductivity region 1111 and described lower wafer 23, according to one embodiment of the invention, the ratio of the area of the area of wherein said the first thermal conductivity region 1111 and lower wafer 23 is between 1 to 1.3, if ratio is on the low side less than 1 radiating effect, if ratio is greater than 1.3 demands that are difficult for satisfying the encapsulating structure miniaturization, described the second thermal conductivity region 1121 can be identical or different with the area of the first thermal conductivity region 1111.According to one embodiment of the invention, the area of the second thermal conductivity region 1121 and the first thermal conductivity region 1111 is close, can so that the thermal coefficient of expansion (CTE) of the first patterned metal layer 111 and the second patterned metal layer 112 approaches, can reduce because the problem of the warpage (warpage) that variations in temperature produces.
In the present embodiment, described heat conduction interface layer 3 comprises at least one deck heat-conducting glue or also comprises at least one layer graphene layer or metal heat-conducting material layer or alloy thermal conductive material layer, and the thickness of its use is for example between 50 to 100 microns; Described metal heat-conducting material layer for example is the composite bed of indium, indium alloy or indium and other metals, and the thickness of its use is for example between 150 to 250 microns.When heat conduction interface layer 3 of the present invention was selected the metal heat-conducting material layer, a back of the body metal level (not illustrating) can be selected to make in advance in the back side of described lower wafer 23, with the engage character of increase with described metal heat-conducting material layer.
According to present embodiment, described upper substrate 11 is by the described heat conduction interface layer 3 of described the first thermal conductivity region 1111 hot connections, can increase the thermocontact area of described upper packaging body 1 and lower packaging body 2 and shorten thermally conductive pathways, described upper wafer 14 belows connect described the second thermal conductivity region 1121 simultaneously, described lower wafer 23 tops connect described heat conduction interface layer 3, the heat energy remittance abroad that can rapidly two plates be produced is to described upper substrate 11, and then the radiating efficiency of raising two plates, in addition, see through the design that substrate imports thermal conductivity region and can improve the radiating efficiency that stacks packaging structure again not increasing under the integral thickness that stacks packaging structure.
Please refer to shown in Figure 2, another embodiment of the present invention stack packaging structure similar in appearance to Fig. 1 embodiment of the present invention, and roughly continue to use similar elements title and figure number, but the difference characteristic of present embodiment is: described heat conduction interface layer 3 is sandwich construction, further comprise graphene layer, or be the combination of copper layer and graphene layer, Graphene in the above-mentioned graphene layer (Graphene) is a kind ofly to form the flat film that hexangle type is the honeycomb lattice by carbon atom with the sp2 hybridized orbit, the two-dimensional material of only having a carbon atom thickness, described solder mask 113 form one first thermal conductivity region 1111 at lower surface with a recess 110 equally.The advantage that above-mentioned material is selected is: because the conduction of the heat of Graphene has anisotropy, the heat conduction of its z direction is 15W/mK, the heat conduction on its x-y plane is up to 5300W/mK, therefore, the heat energy along continuous straight runs that described heat conduction interface layer 3 can be produced described lower wafer 23 rapidly conducts towards each side with radial, again with the uniform remittance abroad of heat energy to described upper substrate 11, not only increase the even conduction of heat energy, also promoted the effective area of heat exchange, and then the heat sink of raising two plates goes out usefulness.
Please refer to shown in Figure 3, further embodiment of this invention stack packaging structure similar in appearance to Fig. 1 embodiment of the present invention, and roughly continue to use similar elements title and figure number, but the difference characteristic of present embodiment is: the described packaging structure 100 that stacks comprises: packaging body 1 reaches packaging body 2 on one, described upper packaging body 1 comprises a upper substrate 11, wafer 14 on one, packaging adhesive material 15 and a heat conductive pad 16 on one, described upper substrate 11 has a upper surface (not indicating) and a lower surface back to described upper surface (not indicating), wherein said heat conductive pad 16 is arranged at the upper surface of described upper substrate 11, and described upper wafer 14 is arranged on the described heat conductive pad 16 and is electrically connected one second patterned metal layer 112 of described upper substrate 11.Described lower packaging body 2 comprises an infrabasal plate 21, several are electrically connected elements 22, a lower wafer 23 and packaging adhesive material 24 once, described infrabasal plate 21 is electrically connected described upper substrate 11 by described electric connection element 22, described lower wafer 23 is arranged on the described infrabasal plate 21 and with described infrabasal plate 21 and is electrically connected, in the present embodiment, described heat conductive pad 16 is graphene layer.
According to present embodiment, by described heat conductive pad 16 being arranged at the upper surface of described upper substrate 11, help the thermal transpiration of described heat conductive pad 16 horizontal conductive to described upper packaging adhesive material 15 or bonding wire, and increase effective area of dissipation, and then improve the effect of wafer heat radiation.
Please refer to shown in Figure 4, yet another embodiment of the invention stack packaging structure similar in appearance to Fig. 3 embodiment of the present invention, and roughly continue to use similar elements title and figure number, but the difference characteristic of present embodiment is: the described packaging structure 100 that stacks comprises: packaging body 1 on, once packaging body 2, an and heat conduction ring 4, wherein said upper substrate 11 arranges a heat conductive pad 16 equally at upper surface, and described upper wafer 14 peripheries are provided with described heat conduction ring 4 on described upper heat conductive pad 16.In the present embodiment, described heat conductive pad 16 is graphene layer with heat conduction ring 4.
According to present embodiment, by described heat conductive pad 16 being arranged at the upper surface of described upper substrate 11, simultaneously described heat conduction ring 4 is centered around outside the described upper wafer 14, can increase the speed of thermal energy conduction, and improve radiating effect.
Please refer to Fig. 5 and cooperate Fig. 1, it shows the assembling schematic diagram that stacks packaging structure according to Fig. 1 embodiment of the present invention.The number of assembling steps that stacks packaging structure of present embodiment:
At first, purchase a upper substrate 11, the upper and lower surface of wherein said upper substrate 11 respectively has one first patterned metal layer 111 and one second patterned metal layer 112, and with the some of described the first patterned metal layer 111 and the second patterned metal layer 112 as one first thermal conductivity region 1111 and one second thermal conductivity region 1121, then again at upper and lower surface coverage one solder mask 113, described solder mask 113 respectively has a recess 110,110 ' in upper and lower surface, to expose described the first thermal conductivity region 1111 and the second thermal conductivity region 1121.Subsequently, again that wafer on a dozen line styles 14 is overlapped on the second thermal conductivity region 1121 of described upper substrate 11 upper surfaces, and described upper wafer 14 is electrically connected a second circuit zone 1122 of described the second patterned metal layer 112, and encapsulate with packaging adhesive material 15 on, to form packaging body 1 on.
Then, purchase an infrabasal plate 21, described infrabasal plate 21 arranges several and is electrically connected element 22, and the first surface 231 that a lower wafer 23 is had is arranged on the described infrabasal plate 21 by several projections and is electrically connected described infrabasal plate 21.Then; utilizing, packaging adhesive material 24 coats the described lower wafer 23 of protection, projection, the upper surface of described infrabasal plate 21 and the some of described electric connection element 22; and expose the first half of described electric connection element 22 and a second surface 232 of described lower wafer 23, to form packaging body 2.
At last, one heat conduction interface layer 3 is pasted second surface 232 at described lower wafer 23, the described upper packaging body 1 of recombinant and lower packaging body 2 to be electrically connected described upper and lower substrate 11,21 by described electric connection element 22, stack packaging structure 100 to form one.Wherein, before described upper packaging body 1 and 2 combinations of lower packaging body, described heat conduction interface layer 3 can be covered on first on described the first thermal conductivity region 1111 or be covered on the second surface 232 of described lower wafer 23, and the compound mode of described heat conduction interface layer 3 is not limited to present embodiment.
Please refer to Fig. 6 and cooperate Fig. 3, it shows the assembling schematic diagram that stacks packaging structure according to Fig. 3 embodiment of the present invention.The assembling following steps that stack packaging structure of present embodiment:
At first, purchase a upper substrate 11, the upper and lower surface of wherein said upper substrate 11 respectively has one first patterned metal layer 111 and one second patterned metal layer 112, and with graphene layer as a heat conductive pad 16, one solder mask 113 then is set again, described solder mask 113 has a recess 110 ' in upper surface, to expose described heat conductive pad 16.Subsequently, wafer on a dozen line styles 14 is overlapped on the heat conductive pad 16 of described upper substrate 11 upper surfaces, utilize that packaging adhesive material 15 encapsulates on one, to form packaging body 1 on.
Then, purchase an infrabasal plate 21, described infrabasal plate 21 arranges several and is electrically connected element 22, is arranged on described infrabasal plate 21 on by several projections a lower wafer 23 and is electrically connected described infrabasal plate 21.Then; utilizing, packaging adhesive material 24 coats the described lower wafer 23 of protection, projection, the upper surface of described infrabasal plate 21 and the some of described electric connection element 22; and expose the first half of described electric connection element 22 and the second surface 232 that described lower wafer 23 has, to form packaging body 2.
At last, make up described upper packaging body 1 and lower packaging body 2, to be electrically connected described upper and lower substrate 11,21 by described electric connection element 22, stack packaging structure 100 to form one.
The present invention is described by above-mentioned related embodiment, yet above-described embodiment is only for implementing example of the present invention.Must be pointed out that published embodiment does not limit the scope of the invention.On the contrary, being contained in the spirit of claims and modification and impartial setting of scope is included in the scope of the present invention.
Claims (12)
1. one kind stacks packaging structure, it is characterized in that: the described packaging structure that stacks comprises:
Packaging body on one, comprise wafer on a upper substrate and, described upper substrate comprises the first patterned metal layer that a upper surface, a lower surface and back to described upper surface are arranged on described lower surface, described patterned metal layer comprises the first thermal conductivity region, and described upper wafer is arranged on the upper surface of described upper substrate and is electrically connected described upper substrate;
Packaging body once, comprise an infrabasal plate, several electric connection element and lower wafers, described infrabasal plate is electrically connected described upper substrate by described electric connection element, described lower wafer comprises first surface and back to the second surface of first surface, described lower wafer is arranged on the described infrabasal plate and the first surface of described lower wafer and the electric connection of described infrabasal plate; And
One heat conduction interface layer is combined between the second surface of the first thermal conductivity region of described upper substrate and described lower wafer.
2. stack as claimed in claim 1 packaging structure, it is characterized in that: described the first thermal conductivity region is metal material.
3. stack as claimed in claim 1 packaging structure, it is characterized in that: the ratio of the area of described the first thermal conductivity region and the area of lower wafer is between 1 to 1.3.
4. stack as claimed in claim 1 packaging structure, it is characterized in that: described upper substrate also comprises second patterned metal layer that is arranged on described upper surface, described the second patterned metal layer comprises one second thermal conductivity region, described the second thermal conductivity region is corresponding with described the first thermal conductivity region, and described upper wafer is arranged on described the second thermal conductivity region.
5. stack as claimed in claim 4 packaging structure, it is characterized in that: described the second thermal conductivity region is identical with the material of described the first thermal conductivity region.
6. stack as claimed in claim 1 packaging structure, it is characterized in that: described heat conduction interface layer comprises at least one deck heat-conducting glue.
7. stack as claimed in claim 6 packaging structure, it is characterized in that: described heat conduction interface layer also comprises at least one layer graphene layer or metal heat-conducting material layer or alloy thermal conductive material layer.
8. stack as claimed in claim 1 packaging structure, it is characterized in that: described upper substrate also has a solder mask that is positioned at described lower surface, and described solder mask is with exposed described the first thermal conductivity region of a recess, and described heat conduction interface layer is positioned at described recess.
9. one kind stacks packaging structure, it is characterized in that: the described packaging structure that stacks comprises:
Packaging body on one comprises wafer on a upper substrate and, and described upper substrate has a upper surface and a lower surface back to described upper surface;
One heat conductive pad is arranged at the upper surface of described upper substrate, and described upper wafer is arranged on the described heat conductive pad and is electrically connected described upper substrate; And
Packaging body once, comprise an infrabasal plate, several electric connection element and lower wafers, described infrabasal plate is electrically connected described upper substrate by described electric connection element, described lower wafer comprises a first surface and back to the second surface of first surface, described lower wafer is arranged on the described infrabasal plate and the first surface of described lower wafer and the electric connection of described infrabasal plate.
10. stack as claimed in claim 9 packaging structure, it is characterized in that: the described packaging structure that stacks also comprises a heat conduction ring, and described heat conduction ring is arranged on the described heat conductive pad, and is looped around described upper wafer perimeter.
11. stack as claimed in claim 9 packaging structure, it is characterized in that: described heat conductive pad is graphene layer.
12. stack as claimed in claim 9 packaging structure, it is characterized in that: described heat conduction ring is graphene layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105170495A CN103050454A (en) | 2012-12-06 | 2012-12-06 | Package on package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105170495A CN103050454A (en) | 2012-12-06 | 2012-12-06 | Package on package structure |
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| CN103050454A true CN103050454A (en) | 2013-04-17 |
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| CN2012105170495A Pending CN103050454A (en) | 2012-12-06 | 2012-12-06 | Package on package structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105453255A (en) * | 2013-08-12 | 2016-03-30 | 三星电子株式会社 | Thermal interface material layer and package-on-package device comprising thermal interface material layer |
| US10431522B2 (en) | 2013-08-12 | 2019-10-01 | Samsung Electronics Co., Ltd. | Thermal interface material layer and package-on-package device including the same |
| US10950521B2 (en) | 2013-08-12 | 2021-03-16 | Samsung Electronics Co., Ltd. | Thermal interface material layer and package-on-package device including the same |
| CN106449551A (en) * | 2016-11-24 | 2017-02-22 | 苏州晶方半导体科技股份有限公司 | Semiconductor structure and forming method thereof, as well as packaging structure and forming method thereof |
| CN106449551B (en) * | 2016-11-24 | 2020-06-19 | 苏州晶方半导体科技股份有限公司 | Semiconductor structure and forming method thereof, packaging structure and forming method thereof |
| CN112992805A (en) * | 2021-01-28 | 2021-06-18 | 日月光半导体制造股份有限公司 | Semiconductor package device and method of manufacturing the same |
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